git.oblomov.eu Git - linux-2.6/blob - drivers/char/agp/efficeon-agp.c

   1 /*
   2  * Transmeta's Efficeon AGPGART driver.
   3  *
   4  * Based upon a diff by Linus around November '02.
   5  *
   6  * Ported to the 2.6 kernel by Carlos Puchol <cpglinux@puchol.com>
   7  * and H. Peter Anvin <hpa@transmeta.com>.
   8  */
   9
  10 /*
  11  * NOTE-cpg-040217:
  12  *
  13  *   - when compiled as a module, after loading the module,
  14  *     it will refuse to unload, indicating it is in use,
  15  *     when it is not.
  16  *   - no s3 (suspend to ram) testing.
  17  *   - tested on the efficeon integrated nothbridge for tens
  18  *     of iterations of starting x and glxgears.
  19  *   - tested with radeon 9000 and radeon mobility m9 cards
  20  *   - tested with c3/c4 enabled (with the mobility m9 card)
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/init.h>
  26 #include <linux/agp_backend.h>
  27 #include <linux/gfp.h>
  28 #include <linux/page-flags.h>
  29 #include <linux/mm.h>
  30 #include "agp.h"
  31
  32 /*
  33  * The real differences to the generic AGP code is
  34  * in the GART mappings - a two-level setup with the
  35  * first level being an on-chip 64-entry table.
  36  *
  37  * The page array is filled through the ATTPAGE register
  38  * (Aperture Translation Table Page Register) at 0xB8. Bits:
  39  *  31:20: physical page address
  40  *   11:9: Page Attribute Table Index (PATI)
  41  *         must match the PAT index for the
  42  *         mapped pages (the 2nd level page table pages
  43  *         themselves should be just regular WB-cacheable,
  44  *         so this is normally zero.)
  45  *      8: Present
  46  *    7:6: reserved, write as zero
  47  *    5:0: GATT directory index: which 1st-level entry
  48  *
  49  * The Efficeon AGP spec requires pages to be WB-cacheable
  50  * but to be explicitly CLFLUSH'd after any changes.
  51  */
  52 #define EFFICEON_ATTPAGE        0xb8
  53 #define EFFICEON_L1_SIZE        64      /* Number of PDE pages */
  54
  55 #define EFFICEON_PATI           (0 << 9)
  56 #define EFFICEON_PRESENT        (1 << 8)
  57
  58 static struct _efficeon_private {
  59         unsigned long l1_table[EFFICEON_L1_SIZE];
  60 } efficeon_private;
  61
  62 static const struct gatt_mask efficeon_generic_masks[] =
  63 {
  64         {.mask = 0x00000001, .type = 0}
  65 };
  66
  67 /* This function does the same thing as mask_memory() for this chipset... */
  68 static inline unsigned long efficeon_mask_memory(unsigned long addr)
  69 {
  70         return addr | 0x00000001;
  71 }
  72
  73 static const struct aper_size_info_lvl2 efficeon_generic_sizes[4] =
  74 {
  75         {256, 65536, 0},
  76         {128, 32768, 32},
  77         {64, 16384, 48},
  78         {32, 8192, 56}
  79 };
  80
  81 /*
  82  * Control interfaces are largely identical to
  83  * the legacy Intel 440BX..
  84  */
  85
  86 static int efficeon_fetch_size(void)
  87 {
  88         int i;
  89         u16 temp;
  90         struct aper_size_info_lvl2 *values;
  91
  92         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
  93         values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
  94
  95         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
  96                 if (temp == values[i].size_value) {
  97                         agp_bridge->previous_size =
  98                             agp_bridge->current_size = (void *) (values + i);
  99                         agp_bridge->aperture_size_idx = i;
 100                         return values[i].size;
 101                 }
 102         }
 103
 104         return 0;
 105 }
 106
 107 static void efficeon_tlbflush(struct agp_memory * mem)
 108 {
 109         printk(KERN_DEBUG PFX "efficeon_tlbflush()\n");
 110         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
 111         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
 112 }
 113
 114 static void efficeon_cleanup(void)
 115 {
 116         u16 temp;
 117         struct aper_size_info_lvl2 *previous_size;
 118
 119         printk(KERN_DEBUG PFX "efficeon_cleanup()\n");
 120         previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
 121         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
 122         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
 123         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE,
 124                               previous_size->size_value);
 125 }
 126
 127 static int efficeon_configure(void)
 128 {
 129         u32 temp;
 130         u16 temp2;
 131         struct aper_size_info_lvl2 *current_size;
 132
 133         printk(KERN_DEBUG PFX "efficeon_configure()\n");
 134
 135         current_size = A_SIZE_LVL2(agp_bridge->current_size);
 136
 137         /* aperture size */
 138         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE,
 139                               current_size->size_value);
 140
 141         /* address to map to */
 142         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
 143         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 144
 145         /* agpctrl */
 146         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
 147
 148         /* paccfg/nbxcfg */
 149         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
 150         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
 151                               (temp2 & ~(1 << 10)) | (1 << 9) | (1 << 11));
 152         /* clear any possible error conditions */
 153         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
 154         return 0;
 155 }
 156
 157 static int efficeon_free_gatt_table(struct agp_bridge_data *bridge)
 158 {
 159         int index, freed = 0;
 160
 161         for (index = 0; index < EFFICEON_L1_SIZE; index++) {
 162                 unsigned long page = efficeon_private.l1_table[index];
 163                 if (page) {
 164                         efficeon_private.l1_table[index] = 0;
 165                         ClearPageReserved(virt_to_page((char *)page));
 166                         free_page(page);
 167                         freed++;
 168                 }
 169                 printk(KERN_DEBUG PFX "efficeon_free_gatt_table(%p, %02x, %08x)\n",
 170                         agp_bridge->dev, EFFICEON_ATTPAGE, index);
 171                 pci_write_config_dword(agp_bridge->dev,
 172                         EFFICEON_ATTPAGE, index);
 173         }
 174         printk(KERN_DEBUG PFX "efficeon_free_gatt_table() freed %d pages\n", freed);
 175         return 0;
 176 }
 177
 178
 179 /*
 180  * Since we don't need contiguous memory we just try
 181  * to get the gatt table once
 182  */
 183
 184 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
 185 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
 186         GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
 187 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
 188 #undef  GET_GATT
 189 #define GET_GATT(addr) (efficeon_private.gatt_pages[\
 190         GET_PAGE_DIR_IDX(addr)]->remapped)
 191
 192 static int efficeon_create_gatt_table(struct agp_bridge_data *bridge)
 193 {
 194         int index;
 195         const int pati    = EFFICEON_PATI;
 196         const int present = EFFICEON_PRESENT;
 197         const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3;
 198         int num_entries, l1_pages;
 199
 200         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 201
 202         printk(KERN_DEBUG PFX "efficeon_create_gatt_table(%d)\n", num_entries);
 203
 204         /* There are 2^10 PTE pages per PDE page */
 205         BUG_ON(num_entries & 0x3ff);
 206         l1_pages = num_entries >> 10;
 207
 208         for (index = 0 ; index < l1_pages ; index++) {
 209                 int offset;
 210                 unsigned long page;
 211                 unsigned long value;
 212
 213                 page = efficeon_private.l1_table[index];
 214                 BUG_ON(page);
 215
 216                 page = get_zeroed_page(GFP_KERNEL);
 217                 if (!page) {
 218                         efficeon_free_gatt_table(agp_bridge);
 219                         return -ENOMEM;
 220                 }
 221                 SetPageReserved(virt_to_page((char *)page));
 222
 223                 for (offset = 0; offset < PAGE_SIZE; offset += clflush_chunk)
 224                         asm volatile("clflush %0" : : "m" (*(char *)(page+offset)));
 225
 226                 efficeon_private.l1_table[index] = page;
 227
 228                 value = virt_to_gart((unsigned long *)page) | pati | present | index;
 229
 230                 pci_write_config_dword(agp_bridge->dev,
 231                         EFFICEON_ATTPAGE, value);
 232         }
 233
 234         return 0;
 235 }
 236
 237 static int efficeon_insert_memory(struct agp_memory * mem, off_t pg_start, int type)
 238 {
 239         int i, count = mem->page_count, num_entries;
 240         unsigned int *page, *last_page;
 241         const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3;
 242         const unsigned long clflush_mask = ~(clflush_chunk-1);
 243
 244         printk(KERN_DEBUG PFX "efficeon_insert_memory(%lx, %d)\n", pg_start, count);
 245
 246         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 247         if ((pg_start + mem->page_count) > num_entries)
 248                 return -EINVAL;
 249         if (type != 0 || mem->type != 0)
 250                 return -EINVAL;
 251
 252         if (mem->is_flushed == FALSE) {
 253                 global_cache_flush();
 254                 mem->is_flushed = TRUE;
 255         }
 256
 257         last_page = NULL;
 258         for (i = 0; i < count; i++) {
 259                 int index = pg_start + i;
 260                 unsigned long insert = efficeon_mask_memory(mem->memory[i]);
 261
 262                 page = (unsigned int *) efficeon_private.l1_table[index >> 10];
 263
 264                 if (!page)
 265                         continue;
 266
 267                 page += (index & 0x3ff);
 268                 *page = insert;
 269
 270                 /* clflush is slow, so don't clflush until we have to */
 271                 if ( last_page &&
 272                      ((unsigned long)page^(unsigned long)last_page) & clflush_mask )
 273                     asm volatile("clflush %0" : : "m" (*last_page));
 274
 275                 last_page = page;
 276         }
 277
 278         if ( last_page )
 279                 asm volatile("clflush %0" : : "m" (*last_page));
 280
 281         agp_bridge->driver->tlb_flush(mem);
 282         return 0;
 283 }
 284
 285 static int efficeon_remove_memory(struct agp_memory * mem, off_t pg_start, int type)
 286 {
 287         int i, count = mem->page_count, num_entries;
 288
 289         printk(KERN_DEBUG PFX "efficeon_remove_memory(%lx, %d)\n", pg_start, count);
 290
 291         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 292
 293         if ((pg_start + mem->page_count) > num_entries)
 294                 return -EINVAL;
 295         if (type != 0 || mem->type != 0)
 296                 return -EINVAL;
 297
 298         for (i = 0; i < count; i++) {
 299                 int index = pg_start + i;
 300                 unsigned int *page = (unsigned int *) efficeon_private.l1_table[index >> 10];
 301
 302                 if (!page)
 303                         continue;
 304                 page += (index & 0x3ff);
 305                 *page = 0;
 306         }
 307         agp_bridge->driver->tlb_flush(mem);
 308         return 0;
 309 }
 310
 311
 312 static const struct agp_bridge_driver efficeon_driver = {
 313         .owner                  = THIS_MODULE,
 314         .aperture_sizes         = efficeon_generic_sizes,
 315         .size_type              = LVL2_APER_SIZE,
 316         .num_aperture_sizes     = 4,
 317         .configure              = efficeon_configure,
 318         .fetch_size             = efficeon_fetch_size,
 319         .cleanup                = efficeon_cleanup,
 320         .tlb_flush              = efficeon_tlbflush,
 321         .mask_memory            = agp_generic_mask_memory,
 322         .masks                  = efficeon_generic_masks,
 323         .agp_enable             = agp_generic_enable,
 324         .cache_flush            = global_cache_flush,
 325
 326         // Efficeon-specific GATT table setup / populate / teardown
 327         .create_gatt_table      = efficeon_create_gatt_table,
 328         .free_gatt_table        = efficeon_free_gatt_table,
 329         .insert_memory          = efficeon_insert_memory,
 330         .remove_memory          = efficeon_remove_memory,
 331         .cant_use_aperture      = 0,    // 1 might be faster?
 332
 333         // Generic
 334         .alloc_by_type          = agp_generic_alloc_by_type,
 335         .free_by_type           = agp_generic_free_by_type,
 336         .agp_alloc_page         = agp_generic_alloc_page,
 337         .agp_destroy_page       = agp_generic_destroy_page,
 338         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 339 };
 340
 341 static int __devinit agp_efficeon_probe(struct pci_dev *pdev,
 342                                      const struct pci_device_id *ent)
 343 {
 344         struct agp_bridge_data *bridge;
 345         u8 cap_ptr;
 346         struct resource *r;
 347
 348         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 349         if (!cap_ptr)
 350                 return -ENODEV;
 351
 352         /* Probe for Efficeon controller */
 353         if (pdev->device != PCI_DEVICE_ID_EFFICEON) {
 354                 printk(KERN_ERR PFX "Unsupported Efficeon chipset (device id: %04x)\n",
 355                     pdev->device);
 356                 return -ENODEV;
 357         }
 358
 359         printk(KERN_INFO PFX "Detected Transmeta Efficeon TM8000 series chipset\n");
 360
 361         bridge = agp_alloc_bridge();
 362         if (!bridge)
 363                 return -ENOMEM;
 364
 365         bridge->driver = &efficeon_driver;
 366         bridge->dev = pdev;
 367         bridge->capndx = cap_ptr;
 368
 369         /*
 370         * The following fixes the case where the BIOS has "forgotten" to
 371         * provide an address range for the GART.
 372         * 20030610 - hamish@zot.org
 373         */
 374         r = &pdev->resource[0];
 375         if (!r->start && r->end) {
 376                 if (pci_assign_resource(pdev, 0)) {
 377                         printk(KERN_ERR PFX "could not assign resource 0\n");
 378                         agp_put_bridge(bridge);
 379                         return -ENODEV;
 380                 }
 381         }
 382
 383         /*
 384         * If the device has not been properly setup, the following will catch
 385         * the problem and should stop the system from crashing.
 386         * 20030610 - hamish@zot.org
 387         */
 388         if (pci_enable_device(pdev)) {
 389                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
 390                 agp_put_bridge(bridge);
 391                 return -ENODEV;
 392         }
 393
 394         /* Fill in the mode register */
 395         if (cap_ptr) {
 396                 pci_read_config_dword(pdev,
 397                                 bridge->capndx+PCI_AGP_STATUS,
 398                                 &bridge->mode);
 399         }
 400
 401         pci_set_drvdata(pdev, bridge);
 402         return agp_add_bridge(bridge);
 403 }
 404
 405 static void __devexit agp_efficeon_remove(struct pci_dev *pdev)
 406 {
 407         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 408
 409         agp_remove_bridge(bridge);
 410         agp_put_bridge(bridge);
 411 }
 412
 413 #ifdef CONFIG_PM
 414 static int agp_efficeon_suspend(struct pci_dev *dev, pm_message_t state)
 415 {
 416         return 0;
 417 }
 418
 419 static int agp_efficeon_resume(struct pci_dev *pdev)
 420 {
 421         printk(KERN_DEBUG PFX "agp_efficeon_resume()\n");
 422         return efficeon_configure();
 423 }
 424 #endif
 425
 426 static struct pci_device_id agp_efficeon_pci_table[] = {
 427         {
 428         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 429         .class_mask     = ~0,
 430         .vendor         = PCI_VENDOR_ID_TRANSMETA,
 431         .device         = PCI_ANY_ID,
 432         .subvendor      = PCI_ANY_ID,
 433         .subdevice      = PCI_ANY_ID,
 434         },
 435         { }
 436 };
 437
 438 MODULE_DEVICE_TABLE(pci, agp_efficeon_pci_table);
 439
 440 static struct pci_driver agp_efficeon_pci_driver = {
 441         .name           = "agpgart-efficeon",
 442         .id_table       = agp_efficeon_pci_table,
 443         .probe          = agp_efficeon_probe,
 444         .remove         = agp_efficeon_remove,
 445 #ifdef CONFIG_PM
 446         .suspend        = agp_efficeon_suspend,
 447         .resume         = agp_efficeon_resume,
 448 #endif
 449 };
 450
 451 static int __init agp_efficeon_init(void)
 452 {
 453         static int agp_initialised=0;
 454
 455         if (agp_off)
 456                 return -EINVAL;
 457
 458         if (agp_initialised == 1)
 459                 return 0;
 460         agp_initialised=1;
 461
 462         return pci_register_driver(&agp_efficeon_pci_driver);
 463 }
 464
 465 static void __exit agp_efficeon_cleanup(void)
 466 {
 467         pci_unregister_driver(&agp_efficeon_pci_driver);
 468 }
 469
 470 module_init(agp_efficeon_init);
 471 module_exit(agp_efficeon_cleanup);
 472
 473 MODULE_AUTHOR("Carlos Puchol <cpglinux@puchol.com>");
 474 MODULE_LICENSE("GPL and additional rights");