git.oblomov.eu Git - linux-2.6/blob - drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  *  $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
  15  */
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/sched.h>
  20 #include <linux/string.h>
  21 #include <linux/kernel.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/tty.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/8250_pci.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/byteorder.h>
  30 #include <asm/io.h>
  31
  32 #include "8250.h"
  33
  34 #undef SERIAL_DEBUG_PCI
  35
  36 /*
  37  * init function returns:
  38  *  > 0 - number of ports
  39  *  = 0 - use board->num_ports
  40  *  < 0 - error
  41  */
  42 struct pci_serial_quirk {
  43         u32     vendor;
  44         u32     device;
  45         u32     subvendor;
  46         u32     subdevice;
  47         int     (*init)(struct pci_dev *dev);
  48         int     (*setup)(struct serial_private *, struct pciserial_board *,
  49                          struct uart_port *, int);
  50         void    (*exit)(struct pci_dev *dev);
  51 };
  52
  53 #define PCI_NUM_BAR_RESOURCES   6
  54
  55 struct serial_private {
  56         struct pci_dev          *dev;
  57         unsigned int            nr;
  58         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  59         struct pci_serial_quirk *quirk;
  60         int                     line[0];
  61 };
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING "%s: %s\n"
  66                KERN_WARNING "Please send the output of lspci -vv, this\n"
  67                KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  68                KERN_WARNING "manufacturer and name of serial board or\n"
  69                KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
  70                pci_name(dev), str, dev->vendor, dev->device,
  71                dev->subsystem_vendor, dev->subsystem_device);
  72 }
  73
  74 static int
  75 setup_port(struct serial_private *priv, struct uart_port *port,
  76            int bar, int offset, int regshift)
  77 {
  78         struct pci_dev *dev = priv->dev;
  79         unsigned long base, len;
  80
  81         if (bar >= PCI_NUM_BAR_RESOURCES)
  82                 return -EINVAL;
  83
  84         base = pci_resource_start(dev, bar);
  85
  86         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  87                 len =  pci_resource_len(dev, bar);
  88
  89                 if (!priv->remapped_bar[bar])
  90                         priv->remapped_bar[bar] = ioremap(base, len);
  91                 if (!priv->remapped_bar[bar])
  92                         return -ENOMEM;
  93
  94                 port->iotype = UPIO_MEM;
  95                 port->iobase = 0;
  96                 port->mapbase = base + offset;
  97                 port->membase = priv->remapped_bar[bar] + offset;
  98                 port->regshift = regshift;
  99         } else {
 100                 port->iotype = UPIO_PORT;
 101                 port->iobase = base + offset;
 102                 port->mapbase = 0;
 103                 port->membase = NULL;
 104                 port->regshift = 0;
 105         }
 106         return 0;
 107 }
 108
 109 /*
 110  * AFAVLAB uses a different mixture of BARs and offsets
 111  * Not that ugly ;) -- HW
 112  */
 113 static int
 114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
 115               struct uart_port *port, int idx)
 116 {
 117         unsigned int bar, offset = board->first_offset;
 118
 119         bar = FL_GET_BASE(board->flags);
 120         if (idx < 4)
 121                 bar += idx;
 122         else {
 123                 bar = 4;
 124                 offset += (idx - 4) * board->uart_offset;
 125         }
 126
 127         return setup_port(priv, port, bar, offset, board->reg_shift);
 128 }
 129
 130 /*
 131  * HP's Remote Management Console.  The Diva chip came in several
 132  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 133  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 134  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 135  * one Diva chip, but it has been expanded to 5 UARTs.
 136  */
 137 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
 138 {
 139         int rc = 0;
 140
 141         switch (dev->subsystem_device) {
 142         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 143         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 144         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 145         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 146                 rc = 3;
 147                 break;
 148         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 149                 rc = 2;
 150                 break;
 151         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 152                 rc = 4;
 153                 break;
 154         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 155         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 156                 rc = 1;
 157                 break;
 158         }
 159
 160         return rc;
 161 }
 162
 163 /*
 164  * HP's Diva chip puts the 4th/5th serial port further out, and
 165  * some serial ports are supposed to be hidden on certain models.
 166  */
 167 static int
 168 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
 169               struct uart_port *port, int idx)
 170 {
 171         unsigned int offset = board->first_offset;
 172         unsigned int bar = FL_GET_BASE(board->flags);
 173
 174         switch (priv->dev->subsystem_device) {
 175         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 176                 if (idx == 3)
 177                         idx++;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 180                 if (idx > 0)
 181                         idx++;
 182                 if (idx > 2)
 183                         idx++;
 184                 break;
 185         }
 186         if (idx > 2)
 187                 offset = 0x18;
 188
 189         offset += idx * board->uart_offset;
 190
 191         return setup_port(priv, port, bar, offset, board->reg_shift);
 192 }
 193
 194 /*
 195  * Added for EKF Intel i960 serial boards
 196  */
 197 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
 198 {
 199         unsigned long oldval;
 200
 201         if (!(dev->subsystem_device & 0x1000))
 202                 return -ENODEV;
 203
 204         /* is firmware started? */
 205         pci_read_config_dword(dev, 0x44, (void*) &oldval);
 206         if (oldval == 0x00001000L) { /* RESET value */
 207                 printk(KERN_DEBUG "Local i960 firmware missing");
 208                 return -ENODEV;
 209         }
 210         return 0;
 211 }
 212
 213 /*
 214  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 215  * that the card interrupt be explicitly enabled or disabled.  This
 216  * seems to be mainly needed on card using the PLX which also use I/O
 217  * mapped memory.
 218  */
 219 static int __devinit pci_plx9050_init(struct pci_dev *dev)
 220 {
 221         u8 irq_config;
 222         void __iomem *p;
 223
 224         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 225                 moan_device("no memory in bar 0", dev);
 226                 return 0;
 227         }
 228
 229         irq_config = 0x41;
 230         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 231             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
 232                 irq_config = 0x43;
 233         }
 234         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 235             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
 236                 /*
 237                  * As the megawolf cards have the int pins active
 238                  * high, and have 2 UART chips, both ints must be
 239                  * enabled on the 9050. Also, the UARTS are set in
 240                  * 16450 mode by default, so we have to enable the
 241                  * 16C950 'enhanced' mode so that we can use the
 242                  * deep FIFOs
 243                  */
 244                 irq_config = 0x5b;
 245         }
 246
 247         /*
 248          * enable/disable interrupts
 249          */
 250         p = ioremap(pci_resource_start(dev, 0), 0x80);
 251         if (p == NULL)
 252                 return -ENOMEM;
 253         writel(irq_config, p + 0x4c);
 254
 255         /*
 256          * Read the register back to ensure that it took effect.
 257          */
 258         readl(p + 0x4c);
 259         iounmap(p);
 260
 261         return 0;
 262 }
 263
 264 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 265 {
 266         u8 __iomem *p;
 267
 268         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 269                 return;
 270
 271         /*
 272          * disable interrupts
 273          */
 274         p = ioremap(pci_resource_start(dev, 0), 0x80);
 275         if (p != NULL) {
 276                 writel(0, p + 0x4c);
 277
 278                 /*
 279                  * Read the register back to ensure that it took effect.
 280                  */
 281                 readl(p + 0x4c);
 282                 iounmap(p);
 283         }
 284 }
 285
 286 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 287 static int
 288 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
 289                 struct uart_port *port, int idx)
 290 {
 291         unsigned int bar, offset = board->first_offset;
 292
 293         bar = 0;
 294
 295         if (idx < 4) {
 296                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 297                 offset += idx * board->uart_offset;
 298         } else if (idx < 8) {
 299                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 300                 offset += idx * board->uart_offset + 0xC00;
 301         } else /* we have only 8 ports on PMC-OCTALPRO */
 302                 return 1;
 303
 304         return setup_port(priv, port, bar, offset, board->reg_shift);
 305 }
 306
 307 /*
 308 * This does initialization for PMC OCTALPRO cards:
 309 * maps the device memory, resets the UARTs (needed, bc
 310 * if the module is removed and inserted again, the card
 311 * is in the sleep mode) and enables global interrupt.
 312 */
 313
 314 /* global control register offset for SBS PMC-OctalPro */
 315 #define OCT_REG_CR_OFF          0x500
 316
 317 static int __devinit sbs_init(struct pci_dev *dev)
 318 {
 319         u8 __iomem *p;
 320
 321         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 322
 323         if (p == NULL)
 324                 return -ENOMEM;
 325         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 326         writeb(0x10,p + OCT_REG_CR_OFF);
 327         udelay(50);
 328         writeb(0x0,p + OCT_REG_CR_OFF);
 329
 330         /* Set bit-2 (INTENABLE) of Control Register */
 331         writeb(0x4, p + OCT_REG_CR_OFF);
 332         iounmap(p);
 333
 334         return 0;
 335 }
 336
 337 /*
 338  * Disables the global interrupt of PMC-OctalPro
 339  */
 340
 341 static void __devexit sbs_exit(struct pci_dev *dev)
 342 {
 343         u8 __iomem *p;
 344
 345         p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
 346         if (p != NULL) {
 347                 writeb(0, p + OCT_REG_CR_OFF);
 348         }
 349         iounmap(p);
 350 }
 351
 352 /*
 353  * SIIG serial cards have an PCI interface chip which also controls
 354  * the UART clocking frequency. Each UART can be clocked independently
 355  * (except cards equiped with 4 UARTs) and initial clocking settings
 356  * are stored in the EEPROM chip. It can cause problems because this
 357  * version of serial driver doesn't support differently clocked UART's
 358  * on single PCI card. To prevent this, initialization functions set
 359  * high frequency clocking for all UART's on given card. It is safe (I
 360  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 361  * with other OSes (like M$ DOS).
 362  *
 363  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 364  *
 365  * There is two family of SIIG serial cards with different PCI
 366  * interface chip and different configuration methods:
 367  *     - 10x cards have control registers in IO and/or memory space;
 368  *     - 20x cards have control registers in standard PCI configuration space.
 369  *
 370  * Note: all 10x cards have PCI device ids 0x10..
 371  *       all 20x cards have PCI device ids 0x20..
 372  *
 373  * There are also Quartet Serial cards which use Oxford Semiconductor
 374  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 375  *
 376  * Note: some SIIG cards are probed by the parport_serial object.
 377  */
 378
 379 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 380 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 381
 382 static int pci_siig10x_init(struct pci_dev *dev)
 383 {
 384         u16 data;
 385         void __iomem *p;
 386
 387         switch (dev->device & 0xfff8) {
 388         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 389                 data = 0xffdf;
 390                 break;
 391         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 392                 data = 0xf7ff;
 393                 break;
 394         default:                        /* 1S1P, 4S */
 395                 data = 0xfffb;
 396                 break;
 397         }
 398
 399         p = ioremap(pci_resource_start(dev, 0), 0x80);
 400         if (p == NULL)
 401                 return -ENOMEM;
 402
 403         writew(readw(p + 0x28) & data, p + 0x28);
 404         readw(p + 0x28);
 405         iounmap(p);
 406         return 0;
 407 }
 408
 409 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 410 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 411
 412 static int pci_siig20x_init(struct pci_dev *dev)
 413 {
 414         u8 data;
 415
 416         /* Change clock frequency for the first UART. */
 417         pci_read_config_byte(dev, 0x6f, &data);
 418         pci_write_config_byte(dev, 0x6f, data & 0xef);
 419
 420         /* If this card has 2 UART, we have to do the same with second UART. */
 421         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 422             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 423                 pci_read_config_byte(dev, 0x73, &data);
 424                 pci_write_config_byte(dev, 0x73, data & 0xef);
 425         }
 426         return 0;
 427 }
 428
 429 static int pci_siig_init(struct pci_dev *dev)
 430 {
 431         unsigned int type = dev->device & 0xff00;
 432
 433         if (type == 0x1000)
 434                 return pci_siig10x_init(dev);
 435         else if (type == 0x2000)
 436                 return pci_siig20x_init(dev);
 437
 438         moan_device("Unknown SIIG card", dev);
 439         return -ENODEV;
 440 }
 441
 442 static int pci_siig_setup(struct serial_private *priv,
 443                           struct pciserial_board *board,
 444                           struct uart_port *port, int idx)
 445 {
 446         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 447
 448         if (idx > 3) {
 449                 bar = 4;
 450                 offset = (idx - 4) * 8;
 451         }
 452
 453         return setup_port(priv, port, bar, offset, 0);
 454 }
 455
 456 /*
 457  * Timedia has an explosion of boards, and to avoid the PCI table from
 458  * growing *huge*, we use this function to collapse some 70 entries
 459  * in the PCI table into one, for sanity's and compactness's sake.
 460  */
 461 static unsigned short timedia_single_port[] = {
 462         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 463 };
 464
 465 static unsigned short timedia_dual_port[] = {
 466         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 467         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 468         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 469         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 470         0xD079, 0
 471 };
 472
 473 static unsigned short timedia_quad_port[] = {
 474         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 475         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 476         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 477         0xB157, 0
 478 };
 479
 480 static unsigned short timedia_eight_port[] = {
 481         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 482         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 483 };
 484
 485 static const struct timedia_struct {
 486         int num;
 487         unsigned short *ids;
 488 } timedia_data[] = {
 489         { 1, timedia_single_port },
 490         { 2, timedia_dual_port },
 491         { 4, timedia_quad_port },
 492         { 8, timedia_eight_port },
 493         { 0, NULL }
 494 };
 495
 496 static int __devinit pci_timedia_init(struct pci_dev *dev)
 497 {
 498         unsigned short *ids;
 499         int i, j;
 500
 501         for (i = 0; timedia_data[i].num; i++) {
 502                 ids = timedia_data[i].ids;
 503                 for (j = 0; ids[j]; j++)
 504                         if (dev->subsystem_device == ids[j])
 505                                 return timedia_data[i].num;
 506         }
 507         return 0;
 508 }
 509
 510 /*
 511  * Timedia/SUNIX uses a mixture of BARs and offsets
 512  * Ugh, this is ugly as all hell --- TYT
 513  */
 514 static int
 515 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
 516                   struct uart_port *port, int idx)
 517 {
 518         unsigned int bar = 0, offset = board->first_offset;
 519
 520         switch (idx) {
 521         case 0:
 522                 bar = 0;
 523                 break;
 524         case 1:
 525                 offset = board->uart_offset;
 526                 bar = 0;
 527                 break;
 528         case 2:
 529                 bar = 1;
 530                 break;
 531         case 3:
 532                 offset = board->uart_offset;
 533                 /* FALLTHROUGH */
 534         case 4: /* BAR 2 */
 535         case 5: /* BAR 3 */
 536         case 6: /* BAR 4 */
 537         case 7: /* BAR 5 */
 538                 bar = idx - 2;
 539         }
 540
 541         return setup_port(priv, port, bar, offset, board->reg_shift);
 542 }
 543
 544 /*
 545  * Some Titan cards are also a little weird
 546  */
 547 static int
 548 titan_400l_800l_setup(struct serial_private *priv,
 549                       struct pciserial_board *board,
 550                       struct uart_port *port, int idx)
 551 {
 552         unsigned int bar, offset = board->first_offset;
 553
 554         switch (idx) {
 555         case 0:
 556                 bar = 1;
 557                 break;
 558         case 1:
 559                 bar = 2;
 560                 break;
 561         default:
 562                 bar = 4;
 563                 offset = (idx - 2) * board->uart_offset;
 564         }
 565
 566         return setup_port(priv, port, bar, offset, board->reg_shift);
 567 }
 568
 569 static int __devinit pci_xircom_init(struct pci_dev *dev)
 570 {
 571         msleep(100);
 572         return 0;
 573 }
 574
 575 static int __devinit pci_netmos_init(struct pci_dev *dev)
 576 {
 577         /* subdevice 0x00PS means <P> parallel, <S> serial */
 578         unsigned int num_serial = dev->subsystem_device & 0xf;
 579
 580         if (num_serial == 0)
 581                 return -ENODEV;
 582         return num_serial;
 583 }
 584
 585 static int
 586 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
 587                   struct uart_port *port, int idx)
 588 {
 589         unsigned int bar, offset = board->first_offset, maxnr;
 590
 591         bar = FL_GET_BASE(board->flags);
 592         if (board->flags & FL_BASE_BARS)
 593                 bar += idx;
 594         else
 595                 offset += idx * board->uart_offset;
 596
 597         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) /
 598                 (8 << board->reg_shift);
 599
 600         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 601                 return 1;
 602
 603         return setup_port(priv, port, bar, offset, board->reg_shift);
 604 }
 605
 606 /* This should be in linux/pci_ids.h */
 607 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 608 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 609 #define PCI_DEVICE_ID_OCTPRO            0x0001
 610 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 611 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 612 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 613 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 614
 615 /*
 616  * Master list of serial port init/setup/exit quirks.
 617  * This does not describe the general nature of the port.
 618  * (ie, baud base, number and location of ports, etc)
 619  *
 620  * This list is ordered alphabetically by vendor then device.
 621  * Specific entries must come before more generic entries.
 622  */
 623 static struct pci_serial_quirk pci_serial_quirks[] = {
 624         /*
 625          * AFAVLAB cards.
 626          *  It is not clear whether this applies to all products.
 627          */
 628         {
 629                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
 630                 .device         = PCI_ANY_ID,
 631                 .subvendor      = PCI_ANY_ID,
 632                 .subdevice      = PCI_ANY_ID,
 633                 .setup          = afavlab_setup,
 634         },
 635         /*
 636          * HP Diva
 637          */
 638         {
 639                 .vendor         = PCI_VENDOR_ID_HP,
 640                 .device         = PCI_DEVICE_ID_HP_DIVA,
 641                 .subvendor      = PCI_ANY_ID,
 642                 .subdevice      = PCI_ANY_ID,
 643                 .init           = pci_hp_diva_init,
 644                 .setup          = pci_hp_diva_setup,
 645         },
 646         /*
 647          * Intel
 648          */
 649         {
 650                 .vendor         = PCI_VENDOR_ID_INTEL,
 651                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
 652                 .subvendor      = 0xe4bf,
 653                 .subdevice      = PCI_ANY_ID,
 654                 .init           = pci_inteli960ni_init,
 655                 .setup          = pci_default_setup,
 656         },
 657         /*
 658          * Panacom
 659          */
 660         {
 661                 .vendor         = PCI_VENDOR_ID_PANACOM,
 662                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
 663                 .subvendor      = PCI_ANY_ID,
 664                 .subdevice      = PCI_ANY_ID,
 665                 .init           = pci_plx9050_init,
 666                 .setup          = pci_default_setup,
 667                 .exit           = __devexit_p(pci_plx9050_exit),
 668         },
 669         {
 670                 .vendor         = PCI_VENDOR_ID_PANACOM,
 671                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
 672                 .subvendor      = PCI_ANY_ID,
 673                 .subdevice      = PCI_ANY_ID,
 674                 .init           = pci_plx9050_init,
 675                 .setup          = pci_default_setup,
 676                 .exit           = __devexit_p(pci_plx9050_exit),
 677         },
 678         /*
 679          * PLX
 680          */
 681         {
 682                 .vendor         = PCI_VENDOR_ID_PLX,
 683                 .device         = PCI_DEVICE_ID_PLX_9050,
 684                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
 685                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
 686                 .init           = pci_plx9050_init,
 687                 .setup          = pci_default_setup,
 688                 .exit           = __devexit_p(pci_plx9050_exit),
 689         },
 690         {
 691                 .vendor         = PCI_VENDOR_ID_PLX,
 692                 .device         = PCI_DEVICE_ID_PLX_9050,
 693                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
 694                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
 695                 .init           = pci_plx9050_init,
 696                 .setup          = pci_default_setup,
 697                 .exit           = __devexit_p(pci_plx9050_exit),
 698         },
 699         {
 700                 .vendor         = PCI_VENDOR_ID_PLX,
 701                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
 702                 .subvendor      = PCI_VENDOR_ID_PLX,
 703                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
 704                 .init           = pci_plx9050_init,
 705                 .setup          = pci_default_setup,
 706                 .exit           = __devexit_p(pci_plx9050_exit),
 707         },
 708         /*
 709          * SBS Technologies, Inc., PMC-OCTALPRO 232
 710          */
 711         {
 712                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 713                 .device         = PCI_DEVICE_ID_OCTPRO,
 714                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 715                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
 716                 .init           = sbs_init,
 717                 .setup          = sbs_setup,
 718                 .exit           = __devexit_p(sbs_exit),
 719         },
 720         /*
 721          * SBS Technologies, Inc., PMC-OCTALPRO 422
 722          */
 723         {
 724                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 725                 .device         = PCI_DEVICE_ID_OCTPRO,
 726                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 727                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
 728                 .init           = sbs_init,
 729                 .setup          = sbs_setup,
 730                 .exit           = __devexit_p(sbs_exit),
 731         },
 732         /*
 733          * SBS Technologies, Inc., P-Octal 232
 734          */
 735         {
 736                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 737                 .device         = PCI_DEVICE_ID_OCTPRO,
 738                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 739                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
 740                 .init           = sbs_init,
 741                 .setup          = sbs_setup,
 742                 .exit           = __devexit_p(sbs_exit),
 743         },
 744         /*
 745          * SBS Technologies, Inc., P-Octal 422
 746          */
 747         {
 748                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
 749                 .device         = PCI_DEVICE_ID_OCTPRO,
 750                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
 751                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
 752                 .init           = sbs_init,
 753                 .setup          = sbs_setup,
 754                 .exit           = __devexit_p(sbs_exit),
 755         },
 756         /*
 757          * SIIG cards.
 758          */
 759         {
 760                 .vendor         = PCI_VENDOR_ID_SIIG,
 761                 .device         = PCI_ANY_ID,
 762                 .subvendor      = PCI_ANY_ID,
 763                 .subdevice      = PCI_ANY_ID,
 764                 .init           = pci_siig_init,
 765                 .setup          = pci_siig_setup,
 766         },
 767         /*
 768          * Titan cards
 769          */
 770         {
 771                 .vendor         = PCI_VENDOR_ID_TITAN,
 772                 .device         = PCI_DEVICE_ID_TITAN_400L,
 773                 .subvendor      = PCI_ANY_ID,
 774                 .subdevice      = PCI_ANY_ID,
 775                 .setup          = titan_400l_800l_setup,
 776         },
 777         {
 778                 .vendor         = PCI_VENDOR_ID_TITAN,
 779                 .device         = PCI_DEVICE_ID_TITAN_800L,
 780                 .subvendor      = PCI_ANY_ID,
 781                 .subdevice      = PCI_ANY_ID,
 782                 .setup          = titan_400l_800l_setup,
 783         },
 784         /*
 785          * Timedia cards
 786          */
 787         {
 788                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 789                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
 790                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
 791                 .subdevice      = PCI_ANY_ID,
 792                 .init           = pci_timedia_init,
 793                 .setup          = pci_timedia_setup,
 794         },
 795         {
 796                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
 797                 .device         = PCI_ANY_ID,
 798                 .subvendor      = PCI_ANY_ID,
 799                 .subdevice      = PCI_ANY_ID,
 800                 .setup          = pci_timedia_setup,
 801         },
 802         /*
 803          * Xircom cards
 804          */
 805         {
 806                 .vendor         = PCI_VENDOR_ID_XIRCOM,
 807                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
 808                 .subvendor      = PCI_ANY_ID,
 809                 .subdevice      = PCI_ANY_ID,
 810                 .init           = pci_xircom_init,
 811                 .setup          = pci_default_setup,
 812         },
 813         /*
 814          * Netmos cards
 815          */
 816         {
 817                 .vendor         = PCI_VENDOR_ID_NETMOS,
 818                 .device         = PCI_ANY_ID,
 819                 .subvendor      = PCI_ANY_ID,
 820                 .subdevice      = PCI_ANY_ID,
 821                 .init           = pci_netmos_init,
 822                 .setup          = pci_default_setup,
 823         },
 824         /*
 825          * Default "match everything" terminator entry
 826          */
 827         {
 828                 .vendor         = PCI_ANY_ID,
 829                 .device         = PCI_ANY_ID,
 830                 .subvendor      = PCI_ANY_ID,
 831                 .subdevice      = PCI_ANY_ID,
 832                 .setup          = pci_default_setup,
 833         }
 834 };
 835
 836 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
 837 {
 838         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
 839 }
 840
 841 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
 842 {
 843         struct pci_serial_quirk *quirk;
 844
 845         for (quirk = pci_serial_quirks; ; quirk++)
 846                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
 847                     quirk_id_matches(quirk->device, dev->device) &&
 848                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
 849                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
 850                         break;
 851         return quirk;
 852 }
 853
 854 static inline int get_pci_irq(struct pci_dev *dev,
 855                                 struct pciserial_board *board)
 856 {
 857         if (board->flags & FL_NOIRQ)
 858                 return 0;
 859         else
 860                 return dev->irq;
 861 }
 862
 863 /*
 864  * This is the configuration table for all of the PCI serial boards
 865  * which we support.  It is directly indexed by the pci_board_num_t enum
 866  * value, which is encoded in the pci_device_id PCI probe table's
 867  * driver_data member.
 868  *
 869  * The makeup of these names are:
 870  *  pbn_bn{_bt}_n_baud{_offsetinhex}
 871  *
 872  *  bn          = PCI BAR number
 873  *  bt          = Index using PCI BARs
 874  *  n           = number of serial ports
 875  *  baud        = baud rate
 876  *  offsetinhex = offset for each sequential port (in hex)
 877  *
 878  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
 879  *
 880  * Please note: in theory if n = 1, _bt infix should make no difference.
 881  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
 882  */
 883 enum pci_board_num_t {
 884         pbn_default = 0,
 885
 886         pbn_b0_1_115200,
 887         pbn_b0_2_115200,
 888         pbn_b0_4_115200,
 889         pbn_b0_5_115200,
 890
 891         pbn_b0_1_921600,
 892         pbn_b0_2_921600,
 893         pbn_b0_4_921600,
 894
 895         pbn_b0_2_1130000,
 896
 897         pbn_b0_4_1152000,
 898
 899         pbn_b0_2_1843200,
 900         pbn_b0_4_1843200,
 901
 902         pbn_b0_2_1843200_200,
 903         pbn_b0_4_1843200_200,
 904         pbn_b0_8_1843200_200,
 905
 906         pbn_b0_bt_1_115200,
 907         pbn_b0_bt_2_115200,
 908         pbn_b0_bt_8_115200,
 909
 910         pbn_b0_bt_1_460800,
 911         pbn_b0_bt_2_460800,
 912         pbn_b0_bt_4_460800,
 913
 914         pbn_b0_bt_1_921600,
 915         pbn_b0_bt_2_921600,
 916         pbn_b0_bt_4_921600,
 917         pbn_b0_bt_8_921600,
 918
 919         pbn_b1_1_115200,
 920         pbn_b1_2_115200,
 921         pbn_b1_4_115200,
 922         pbn_b1_8_115200,
 923
 924         pbn_b1_1_921600,
 925         pbn_b1_2_921600,
 926         pbn_b1_4_921600,
 927         pbn_b1_8_921600,
 928
 929         pbn_b1_2_1250000,
 930
 931         pbn_b1_bt_2_921600,
 932
 933         pbn_b1_1_1382400,
 934         pbn_b1_2_1382400,
 935         pbn_b1_4_1382400,
 936         pbn_b1_8_1382400,
 937
 938         pbn_b2_1_115200,
 939         pbn_b2_8_115200,
 940
 941         pbn_b2_1_460800,
 942         pbn_b2_4_460800,
 943         pbn_b2_8_460800,
 944         pbn_b2_16_460800,
 945
 946         pbn_b2_1_921600,
 947         pbn_b2_4_921600,
 948         pbn_b2_8_921600,
 949
 950         pbn_b2_bt_1_115200,
 951         pbn_b2_bt_2_115200,
 952         pbn_b2_bt_4_115200,
 953
 954         pbn_b2_bt_2_921600,
 955         pbn_b2_bt_4_921600,
 956
 957         pbn_b3_2_115200,
 958         pbn_b3_4_115200,
 959         pbn_b3_8_115200,
 960
 961         /*
 962          * Board-specific versions.
 963          */
 964         pbn_panacom,
 965         pbn_panacom2,
 966         pbn_panacom4,
 967         pbn_exsys_4055,
 968         pbn_plx_romulus,
 969         pbn_oxsemi,
 970         pbn_intel_i960,
 971         pbn_sgi_ioc3,
 972         pbn_nec_nile4,
 973         pbn_computone_4,
 974         pbn_computone_6,
 975         pbn_computone_8,
 976         pbn_sbsxrsio,
 977         pbn_exar_XR17C152,
 978         pbn_exar_XR17C154,
 979         pbn_exar_XR17C158,
 980 };
 981
 982 /*
 983  * uart_offset - the space between channels
 984  * reg_shift   - describes how the UART registers are mapped
 985  *               to PCI memory by the card.
 986  * For example IER register on SBS, Inc. PMC-OctPro is located at
 987  * offset 0x10 from the UART base, while UART_IER is defined as 1
 988  * in include/linux/serial_reg.h,
 989  * see first lines of serial_in() and serial_out() in 8250.c
 990 */
 991
 992 static struct pciserial_board pci_boards[] __devinitdata = {
 993         [pbn_default] = {
 994                 .flags          = FL_BASE0,
 995                 .num_ports      = 1,
 996                 .base_baud      = 115200,
 997                 .uart_offset    = 8,
 998         },
 999         [pbn_b0_1_115200] = {
1000                 .flags          = FL_BASE0,
1001                 .num_ports      = 1,
1002                 .base_baud      = 115200,
1003                 .uart_offset    = 8,
1004         },
1005         [pbn_b0_2_115200] = {
1006                 .flags          = FL_BASE0,
1007                 .num_ports      = 2,
1008                 .base_baud      = 115200,
1009                 .uart_offset    = 8,
1010         },
1011         [pbn_b0_4_115200] = {
1012                 .flags          = FL_BASE0,
1013                 .num_ports      = 4,
1014                 .base_baud      = 115200,
1015                 .uart_offset    = 8,
1016         },
1017         [pbn_b0_5_115200] = {
1018                 .flags          = FL_BASE0,
1019                 .num_ports      = 5,
1020                 .base_baud      = 115200,
1021                 .uart_offset    = 8,
1022         },
1023
1024         [pbn_b0_1_921600] = {
1025                 .flags          = FL_BASE0,
1026                 .num_ports      = 1,
1027                 .base_baud      = 921600,
1028                 .uart_offset    = 8,
1029         },
1030         [pbn_b0_2_921600] = {
1031                 .flags          = FL_BASE0,
1032                 .num_ports      = 2,
1033                 .base_baud      = 921600,
1034                 .uart_offset    = 8,
1035         },
1036         [pbn_b0_4_921600] = {
1037                 .flags          = FL_BASE0,
1038                 .num_ports      = 4,
1039                 .base_baud      = 921600,
1040                 .uart_offset    = 8,
1041         },
1042
1043         [pbn_b0_2_1130000] = {
1044                 .flags          = FL_BASE0,
1045                 .num_ports      = 2,
1046                 .base_baud      = 1130000,
1047                 .uart_offset    = 8,
1048         },
1049
1050         [pbn_b0_4_1152000] = {
1051                 .flags          = FL_BASE0,
1052                 .num_ports      = 4,
1053                 .base_baud      = 1152000,
1054                 .uart_offset    = 8,
1055         },
1056
1057         [pbn_b0_2_1843200] = {
1058                 .flags          = FL_BASE0,
1059                 .num_ports      = 2,
1060                 .base_baud      = 1843200,
1061                 .uart_offset    = 8,
1062         },
1063         [pbn_b0_4_1843200] = {
1064                 .flags          = FL_BASE0,
1065                 .num_ports      = 4,
1066                 .base_baud      = 1843200,
1067                 .uart_offset    = 8,
1068         },
1069
1070         [pbn_b0_2_1843200_200] = {
1071                 .flags          = FL_BASE0,
1072                 .num_ports      = 2,
1073                 .base_baud      = 1843200,
1074                 .uart_offset    = 0x200,
1075         },
1076         [pbn_b0_4_1843200_200] = {
1077                 .flags          = FL_BASE0,
1078                 .num_ports      = 4,
1079                 .base_baud      = 1843200,
1080                 .uart_offset    = 0x200,
1081         },
1082         [pbn_b0_8_1843200_200] = {
1083                 .flags          = FL_BASE0,
1084                 .num_ports      = 8,
1085                 .base_baud      = 1843200,
1086                 .uart_offset    = 0x200,
1087         },
1088
1089         [pbn_b0_bt_1_115200] = {
1090                 .flags          = FL_BASE0|FL_BASE_BARS,
1091                 .num_ports      = 1,
1092                 .base_baud      = 115200,
1093                 .uart_offset    = 8,
1094         },
1095         [pbn_b0_bt_2_115200] = {
1096                 .flags          = FL_BASE0|FL_BASE_BARS,
1097                 .num_ports      = 2,
1098                 .base_baud      = 115200,
1099                 .uart_offset    = 8,
1100         },
1101         [pbn_b0_bt_8_115200] = {
1102                 .flags          = FL_BASE0|FL_BASE_BARS,
1103                 .num_ports      = 8,
1104                 .base_baud      = 115200,
1105                 .uart_offset    = 8,
1106         },
1107
1108         [pbn_b0_bt_1_460800] = {
1109                 .flags          = FL_BASE0|FL_BASE_BARS,
1110                 .num_ports      = 1,
1111                 .base_baud      = 460800,
1112                 .uart_offset    = 8,
1113         },
1114         [pbn_b0_bt_2_460800] = {
1115                 .flags          = FL_BASE0|FL_BASE_BARS,
1116                 .num_ports      = 2,
1117                 .base_baud      = 460800,
1118                 .uart_offset    = 8,
1119         },
1120         [pbn_b0_bt_4_460800] = {
1121                 .flags          = FL_BASE0|FL_BASE_BARS,
1122                 .num_ports      = 4,
1123                 .base_baud      = 460800,
1124                 .uart_offset    = 8,
1125         },
1126
1127         [pbn_b0_bt_1_921600] = {
1128                 .flags          = FL_BASE0|FL_BASE_BARS,
1129                 .num_ports      = 1,
1130                 .base_baud      = 921600,
1131                 .uart_offset    = 8,
1132         },
1133         [pbn_b0_bt_2_921600] = {
1134                 .flags          = FL_BASE0|FL_BASE_BARS,
1135                 .num_ports      = 2,
1136                 .base_baud      = 921600,
1137                 .uart_offset    = 8,
1138         },
1139         [pbn_b0_bt_4_921600] = {
1140                 .flags          = FL_BASE0|FL_BASE_BARS,
1141                 .num_ports      = 4,
1142                 .base_baud      = 921600,
1143                 .uart_offset    = 8,
1144         },
1145         [pbn_b0_bt_8_921600] = {
1146                 .flags          = FL_BASE0|FL_BASE_BARS,
1147                 .num_ports      = 8,
1148                 .base_baud      = 921600,
1149                 .uart_offset    = 8,
1150         },
1151
1152         [pbn_b1_1_115200] = {
1153                 .flags          = FL_BASE1,
1154                 .num_ports      = 1,
1155                 .base_baud      = 115200,
1156                 .uart_offset    = 8,
1157         },
1158         [pbn_b1_2_115200] = {
1159                 .flags          = FL_BASE1,
1160                 .num_ports      = 2,
1161                 .base_baud      = 115200,
1162                 .uart_offset    = 8,
1163         },
1164         [pbn_b1_4_115200] = {
1165                 .flags          = FL_BASE1,
1166                 .num_ports      = 4,
1167                 .base_baud      = 115200,
1168                 .uart_offset    = 8,
1169         },
1170         [pbn_b1_8_115200] = {
1171                 .flags          = FL_BASE1,
1172                 .num_ports      = 8,
1173                 .base_baud      = 115200,
1174                 .uart_offset    = 8,
1175         },
1176
1177         [pbn_b1_1_921600] = {
1178                 .flags          = FL_BASE1,
1179                 .num_ports      = 1,
1180                 .base_baud      = 921600,
1181                 .uart_offset    = 8,
1182         },
1183         [pbn_b1_2_921600] = {
1184                 .flags          = FL_BASE1,
1185                 .num_ports      = 2,
1186                 .base_baud      = 921600,
1187                 .uart_offset    = 8,
1188         },
1189         [pbn_b1_4_921600] = {
1190                 .flags          = FL_BASE1,
1191                 .num_ports      = 4,
1192                 .base_baud      = 921600,
1193                 .uart_offset    = 8,
1194         },
1195         [pbn_b1_8_921600] = {
1196                 .flags          = FL_BASE1,
1197                 .num_ports      = 8,
1198                 .base_baud      = 921600,
1199                 .uart_offset    = 8,
1200         },
1201         [pbn_b1_2_1250000] = {
1202                 .flags          = FL_BASE1,
1203                 .num_ports      = 2,
1204                 .base_baud      = 1250000,
1205                 .uart_offset    = 8,
1206         },
1207
1208         [pbn_b1_bt_2_921600] = {
1209                 .flags          = FL_BASE1|FL_BASE_BARS,
1210                 .num_ports      = 2,
1211                 .base_baud      = 921600,
1212                 .uart_offset    = 8,
1213         },
1214
1215         [pbn_b1_1_1382400] = {
1216                 .flags          = FL_BASE1,
1217                 .num_ports      = 1,
1218                 .base_baud      = 1382400,
1219                 .uart_offset    = 8,
1220         },
1221         [pbn_b1_2_1382400] = {
1222                 .flags          = FL_BASE1,
1223                 .num_ports      = 2,
1224                 .base_baud      = 1382400,
1225                 .uart_offset    = 8,
1226         },
1227         [pbn_b1_4_1382400] = {
1228                 .flags          = FL_BASE1,
1229                 .num_ports      = 4,
1230                 .base_baud      = 1382400,
1231                 .uart_offset    = 8,
1232         },
1233         [pbn_b1_8_1382400] = {
1234                 .flags          = FL_BASE1,
1235                 .num_ports      = 8,
1236                 .base_baud      = 1382400,
1237                 .uart_offset    = 8,
1238         },
1239
1240         [pbn_b2_1_115200] = {
1241                 .flags          = FL_BASE2,
1242                 .num_ports      = 1,
1243                 .base_baud      = 115200,
1244                 .uart_offset    = 8,
1245         },
1246         [pbn_b2_8_115200] = {
1247                 .flags          = FL_BASE2,
1248                 .num_ports      = 8,
1249                 .base_baud      = 115200,
1250                 .uart_offset    = 8,
1251         },
1252
1253         [pbn_b2_1_460800] = {
1254                 .flags          = FL_BASE2,
1255                 .num_ports      = 1,
1256                 .base_baud      = 460800,
1257                 .uart_offset    = 8,
1258         },
1259         [pbn_b2_4_460800] = {
1260                 .flags          = FL_BASE2,
1261                 .num_ports      = 4,
1262                 .base_baud      = 460800,
1263                 .uart_offset    = 8,
1264         },
1265         [pbn_b2_8_460800] = {
1266                 .flags          = FL_BASE2,
1267                 .num_ports      = 8,
1268                 .base_baud      = 460800,
1269                 .uart_offset    = 8,
1270         },
1271         [pbn_b2_16_460800] = {
1272                 .flags          = FL_BASE2,
1273                 .num_ports      = 16,
1274                 .base_baud      = 460800,
1275                 .uart_offset    = 8,
1276          },
1277
1278         [pbn_b2_1_921600] = {
1279                 .flags          = FL_BASE2,
1280                 .num_ports      = 1,
1281                 .base_baud      = 921600,
1282                 .uart_offset    = 8,
1283         },
1284         [pbn_b2_4_921600] = {
1285                 .flags          = FL_BASE2,
1286                 .num_ports      = 4,
1287                 .base_baud      = 921600,
1288                 .uart_offset    = 8,
1289         },
1290         [pbn_b2_8_921600] = {
1291                 .flags          = FL_BASE2,
1292                 .num_ports      = 8,
1293                 .base_baud      = 921600,
1294                 .uart_offset    = 8,
1295         },
1296
1297         [pbn_b2_bt_1_115200] = {
1298                 .flags          = FL_BASE2|FL_BASE_BARS,
1299                 .num_ports      = 1,
1300                 .base_baud      = 115200,
1301                 .uart_offset    = 8,
1302         },
1303         [pbn_b2_bt_2_115200] = {
1304                 .flags          = FL_BASE2|FL_BASE_BARS,
1305                 .num_ports      = 2,
1306                 .base_baud      = 115200,
1307                 .uart_offset    = 8,
1308         },
1309         [pbn_b2_bt_4_115200] = {
1310                 .flags          = FL_BASE2|FL_BASE_BARS,
1311                 .num_ports      = 4,
1312                 .base_baud      = 115200,
1313                 .uart_offset    = 8,
1314         },
1315
1316         [pbn_b2_bt_2_921600] = {
1317                 .flags          = FL_BASE2|FL_BASE_BARS,
1318                 .num_ports      = 2,
1319                 .base_baud      = 921600,
1320                 .uart_offset    = 8,
1321         },
1322         [pbn_b2_bt_4_921600] = {
1323                 .flags          = FL_BASE2|FL_BASE_BARS,
1324                 .num_ports      = 4,
1325                 .base_baud      = 921600,
1326                 .uart_offset    = 8,
1327         },
1328
1329         [pbn_b3_2_115200] = {
1330                 .flags          = FL_BASE3,
1331                 .num_ports      = 2,
1332                 .base_baud      = 115200,
1333                 .uart_offset    = 8,
1334         },
1335         [pbn_b3_4_115200] = {
1336                 .flags          = FL_BASE3,
1337                 .num_ports      = 4,
1338                 .base_baud      = 115200,
1339                 .uart_offset    = 8,
1340         },
1341         [pbn_b3_8_115200] = {
1342                 .flags          = FL_BASE3,
1343                 .num_ports      = 8,
1344                 .base_baud      = 115200,
1345                 .uart_offset    = 8,
1346         },
1347
1348         /*
1349          * Entries following this are board-specific.
1350          */
1351
1352         /*
1353          * Panacom - IOMEM
1354          */
1355         [pbn_panacom] = {
1356                 .flags          = FL_BASE2,
1357                 .num_ports      = 2,
1358                 .base_baud      = 921600,
1359                 .uart_offset    = 0x400,
1360                 .reg_shift      = 7,
1361         },
1362         [pbn_panacom2] = {
1363                 .flags          = FL_BASE2|FL_BASE_BARS,
1364                 .num_ports      = 2,
1365                 .base_baud      = 921600,
1366                 .uart_offset    = 0x400,
1367                 .reg_shift      = 7,
1368         },
1369         [pbn_panacom4] = {
1370                 .flags          = FL_BASE2|FL_BASE_BARS,
1371                 .num_ports      = 4,
1372                 .base_baud      = 921600,
1373                 .uart_offset    = 0x400,
1374                 .reg_shift      = 7,
1375         },
1376
1377         [pbn_exsys_4055] = {
1378                 .flags          = FL_BASE2,
1379                 .num_ports      = 4,
1380                 .base_baud      = 115200,
1381                 .uart_offset    = 8,
1382         },
1383
1384         /* I think this entry is broken - the first_offset looks wrong --rmk */
1385         [pbn_plx_romulus] = {
1386                 .flags          = FL_BASE2,
1387                 .num_ports      = 4,
1388                 .base_baud      = 921600,
1389                 .uart_offset    = 8 << 2,
1390                 .reg_shift      = 2,
1391                 .first_offset   = 0x03,
1392         },
1393
1394         /*
1395          * This board uses the size of PCI Base region 0 to
1396          * signal now many ports are available
1397          */
1398         [pbn_oxsemi] = {
1399                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
1400                 .num_ports      = 32,
1401                 .base_baud      = 115200,
1402                 .uart_offset    = 8,
1403         },
1404
1405         /*
1406          * EKF addition for i960 Boards form EKF with serial port.
1407          * Max 256 ports.
1408          */
1409         [pbn_intel_i960] = {
1410                 .flags          = FL_BASE0,
1411                 .num_ports      = 32,
1412                 .base_baud      = 921600,
1413                 .uart_offset    = 8 << 2,
1414                 .reg_shift      = 2,
1415                 .first_offset   = 0x10000,
1416         },
1417         [pbn_sgi_ioc3] = {
1418                 .flags          = FL_BASE0|FL_NOIRQ,
1419                 .num_ports      = 1,
1420                 .base_baud      = 458333,
1421                 .uart_offset    = 8,
1422                 .reg_shift      = 0,
1423                 .first_offset   = 0x20178,
1424         },
1425
1426         /*
1427          * NEC Vrc-5074 (Nile 4) builtin UART.
1428          */
1429         [pbn_nec_nile4] = {
1430                 .flags          = FL_BASE0,
1431                 .num_ports      = 1,
1432                 .base_baud      = 520833,
1433                 .uart_offset    = 8 << 3,
1434                 .reg_shift      = 3,
1435                 .first_offset   = 0x300,
1436         },
1437
1438         /*
1439          * Computone - uses IOMEM.
1440          */
1441         [pbn_computone_4] = {
1442                 .flags          = FL_BASE0,
1443                 .num_ports      = 4,
1444                 .base_baud      = 921600,
1445                 .uart_offset    = 0x40,
1446                 .reg_shift      = 2,
1447                 .first_offset   = 0x200,
1448         },
1449         [pbn_computone_6] = {
1450                 .flags          = FL_BASE0,
1451                 .num_ports      = 6,
1452                 .base_baud      = 921600,
1453                 .uart_offset    = 0x40,
1454                 .reg_shift      = 2,
1455                 .first_offset   = 0x200,
1456         },
1457         [pbn_computone_8] = {
1458                 .flags          = FL_BASE0,
1459                 .num_ports      = 8,
1460                 .base_baud      = 921600,
1461                 .uart_offset    = 0x40,
1462                 .reg_shift      = 2,
1463                 .first_offset   = 0x200,
1464         },
1465         [pbn_sbsxrsio] = {
1466                 .flags          = FL_BASE0,
1467                 .num_ports      = 8,
1468                 .base_baud      = 460800,
1469                 .uart_offset    = 256,
1470                 .reg_shift      = 4,
1471         },
1472         /*
1473          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1474          *  Only basic 16550A support.
1475          *  XR17C15[24] are not tested, but they should work.
1476          */
1477         [pbn_exar_XR17C152] = {
1478                 .flags          = FL_BASE0,
1479                 .num_ports      = 2,
1480                 .base_baud      = 921600,
1481                 .uart_offset    = 0x200,
1482         },
1483         [pbn_exar_XR17C154] = {
1484                 .flags          = FL_BASE0,
1485                 .num_ports      = 4,
1486                 .base_baud      = 921600,
1487                 .uart_offset    = 0x200,
1488         },
1489         [pbn_exar_XR17C158] = {
1490                 .flags          = FL_BASE0,
1491                 .num_ports      = 8,
1492                 .base_baud      = 921600,
1493                 .uart_offset    = 0x200,
1494         },
1495 };
1496
1497 /*
1498  * Given a complete unknown PCI device, try to use some heuristics to
1499  * guess what the configuration might be, based on the pitiful PCI
1500  * serial specs.  Returns 0 on success, 1 on failure.
1501  */
1502 static int __devinit
1503 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1504 {
1505         int num_iomem, num_port, first_port = -1, i;
1506
1507         /*
1508          * If it is not a communications device or the programming
1509          * interface is greater than 6, give up.
1510          *
1511          * (Should we try to make guesses for multiport serial devices
1512          * later?)
1513          */
1514         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1515              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1516             (dev->class & 0xff) > 6)
1517                 return -ENODEV;
1518
1519         num_iomem = num_port = 0;
1520         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1521                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1522                         num_port++;
1523                         if (first_port == -1)
1524                                 first_port = i;
1525                 }
1526                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1527                         num_iomem++;
1528         }
1529
1530         /*
1531          * If there is 1 or 0 iomem regions, and exactly one port,
1532          * use it.  We guess the number of ports based on the IO
1533          * region size.
1534          */
1535         if (num_iomem <= 1 && num_port == 1) {
1536                 board->flags = first_port;
1537                 board->num_ports = pci_resource_len(dev, first_port) / 8;
1538                 return 0;
1539         }
1540
1541         /*
1542          * Now guess if we've got a board which indexes by BARs.
1543          * Each IO BAR should be 8 bytes, and they should follow
1544          * consecutively.
1545          */
1546         first_port = -1;
1547         num_port = 0;
1548         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1549                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1550                     pci_resource_len(dev, i) == 8 &&
1551                     (first_port == -1 || (first_port + num_port) == i)) {
1552                         num_port++;
1553                         if (first_port == -1)
1554                                 first_port = i;
1555                 }
1556         }
1557
1558         if (num_port > 1) {
1559                 board->flags = first_port | FL_BASE_BARS;
1560                 board->num_ports = num_port;
1561                 return 0;
1562         }
1563
1564         return -ENODEV;
1565 }
1566
1567 static inline int
1568 serial_pci_matches(struct pciserial_board *board,
1569                    struct pciserial_board *guessed)
1570 {
1571         return
1572             board->num_ports == guessed->num_ports &&
1573             board->base_baud == guessed->base_baud &&
1574             board->uart_offset == guessed->uart_offset &&
1575             board->reg_shift == guessed->reg_shift &&
1576             board->first_offset == guessed->first_offset;
1577 }
1578
1579 struct serial_private *
1580 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1581 {
1582         struct uart_port serial_port;
1583         struct serial_private *priv;
1584         struct pci_serial_quirk *quirk;
1585         int rc, nr_ports, i;
1586
1587         nr_ports = board->num_ports;
1588
1589         /*
1590          * Find an init and setup quirks.
1591          */
1592         quirk = find_quirk(dev);
1593
1594         /*
1595          * Run the new-style initialization function.
1596          * The initialization function returns:
1597          *  <0  - error
1598          *   0  - use board->num_ports
1599          *  >0  - number of ports
1600          */
1601         if (quirk->init) {
1602                 rc = quirk->init(dev);
1603                 if (rc < 0) {
1604                         priv = ERR_PTR(rc);
1605                         goto err_out;
1606                 }
1607                 if (rc)
1608                         nr_ports = rc;
1609         }
1610
1611         priv = kmalloc(sizeof(struct serial_private) +
1612                        sizeof(unsigned int) * nr_ports,
1613                        GFP_KERNEL);
1614         if (!priv) {
1615                 priv = ERR_PTR(-ENOMEM);
1616                 goto err_deinit;
1617         }
1618
1619         memset(priv, 0, sizeof(struct serial_private) +
1620                         sizeof(unsigned int) * nr_ports);
1621
1622         priv->dev = dev;
1623         priv->quirk = quirk;
1624
1625         memset(&serial_port, 0, sizeof(struct uart_port));
1626         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1627         serial_port.uartclk = board->base_baud * 16;
1628         serial_port.irq = get_pci_irq(dev, board);
1629         serial_port.dev = &dev->dev;
1630
1631         for (i = 0; i < nr_ports; i++) {
1632                 if (quirk->setup(priv, board, &serial_port, i))
1633                         break;
1634
1635 #ifdef SERIAL_DEBUG_PCI
1636                 printk("Setup PCI port: port %x, irq %d, type %d\n",
1637                        serial_port.iobase, serial_port.irq, serial_port.iotype);
1638 #endif
1639
1640                 priv->line[i] = serial8250_register_port(&serial_port);
1641                 if (priv->line[i] < 0) {
1642                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1643                         break;
1644                 }
1645         }
1646
1647         priv->nr = i;
1648
1649         return priv;
1650
1651  err_deinit:
1652         if (quirk->exit)
1653                 quirk->exit(dev);
1654  err_out:
1655         return priv;
1656 }
1657 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1658
1659 void pciserial_remove_ports(struct serial_private *priv)
1660 {
1661         struct pci_serial_quirk *quirk;
1662         int i;
1663
1664         for (i = 0; i < priv->nr; i++)
1665                 serial8250_unregister_port(priv->line[i]);
1666
1667         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1668                 if (priv->remapped_bar[i])
1669                         iounmap(priv->remapped_bar[i]);
1670                 priv->remapped_bar[i] = NULL;
1671         }
1672
1673         /*
1674          * Find the exit quirks.
1675          */
1676         quirk = find_quirk(priv->dev);
1677         if (quirk->exit)
1678                 quirk->exit(priv->dev);
1679
1680         kfree(priv);
1681 }
1682 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1683
1684 void pciserial_suspend_ports(struct serial_private *priv)
1685 {
1686         int i;
1687
1688         for (i = 0; i < priv->nr; i++)
1689                 if (priv->line[i] >= 0)
1690                         serial8250_suspend_port(priv->line[i]);
1691 }
1692 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1693
1694 void pciserial_resume_ports(struct serial_private *priv)
1695 {
1696         int i;
1697
1698         /*
1699          * Ensure that the board is correctly configured.
1700          */
1701         if (priv->quirk->init)
1702                 priv->quirk->init(priv->dev);
1703
1704         for (i = 0; i < priv->nr; i++)
1705                 if (priv->line[i] >= 0)
1706                         serial8250_resume_port(priv->line[i]);
1707 }
1708 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1709
1710 /*
1711  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
1712  * to the arrangement of serial ports on a PCI card.
1713  */
1714 static int __devinit
1715 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1716 {
1717         struct serial_private *priv;
1718         struct pciserial_board *board, tmp;
1719         int rc;
1720
1721         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1722                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1723                         ent->driver_data);
1724                 return -EINVAL;
1725         }
1726
1727         board = &pci_boards[ent->driver_data];
1728
1729         rc = pci_enable_device(dev);
1730         if (rc)
1731                 return rc;
1732
1733         if (ent->driver_data == pbn_default) {
1734                 /*
1735                  * Use a copy of the pci_board entry for this;
1736                  * avoid changing entries in the table.
1737                  */
1738                 memcpy(&tmp, board, sizeof(struct pciserial_board));
1739                 board = &tmp;
1740
1741                 /*
1742                  * We matched one of our class entries.  Try to
1743                  * determine the parameters of this board.
1744                  */
1745                 rc = serial_pci_guess_board(dev, board);
1746                 if (rc)
1747                         goto disable;
1748         } else {
1749                 /*
1750                  * We matched an explicit entry.  If we are able to
1751                  * detect this boards settings with our heuristic,
1752                  * then we no longer need this entry.
1753                  */
1754                 memcpy(&tmp, &pci_boards[pbn_default],
1755                        sizeof(struct pciserial_board));
1756                 rc = serial_pci_guess_board(dev, &tmp);
1757                 if (rc == 0 && serial_pci_matches(board, &tmp))
1758                         moan_device("Redundant entry in serial pci_table.",
1759                                     dev);
1760         }
1761
1762         priv = pciserial_init_ports(dev, board);
1763         if (!IS_ERR(priv)) {
1764                 pci_set_drvdata(dev, priv);
1765                 return 0;
1766         }
1767
1768         rc = PTR_ERR(priv);
1769
1770  disable:
1771         pci_disable_device(dev);
1772         return rc;
1773 }
1774
1775 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1776 {
1777         struct serial_private *priv = pci_get_drvdata(dev);
1778
1779         pci_set_drvdata(dev, NULL);
1780
1781         pciserial_remove_ports(priv);
1782
1783         pci_disable_device(dev);
1784 }
1785
1786 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1787 {
1788         struct serial_private *priv = pci_get_drvdata(dev);
1789
1790         if (priv)
1791                 pciserial_suspend_ports(priv);
1792
1793         pci_save_state(dev);
1794         pci_set_power_state(dev, pci_choose_state(dev, state));
1795         return 0;
1796 }
1797
1798 static int pciserial_resume_one(struct pci_dev *dev)
1799 {
1800         struct serial_private *priv = pci_get_drvdata(dev);
1801
1802         pci_set_power_state(dev, PCI_D0);
1803         pci_restore_state(dev);
1804
1805         if (priv) {
1806                 /*
1807                  * The device may have been disabled.  Re-enable it.
1808                  */
1809                 pci_enable_device(dev);
1810
1811                 pciserial_resume_ports(priv);
1812         }
1813         return 0;
1814 }
1815
1816 static struct pci_device_id serial_pci_tbl[] = {
1817         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1818                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1819                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1820                 pbn_b1_8_1382400 },
1821         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1822                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1823                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1824                 pbn_b1_4_1382400 },
1825         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1826                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1827                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1828                 pbn_b1_2_1382400 },
1829         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1830                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1831                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1832                 pbn_b1_8_1382400 },
1833         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1834                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1835                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1836                 pbn_b1_4_1382400 },
1837         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1838                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1839                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1840                 pbn_b1_2_1382400 },
1841         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1842                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1843                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1844                 pbn_b1_8_921600 },
1845         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1846                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1847                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1848                 pbn_b1_8_921600 },
1849         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1850                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1851                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1852                 pbn_b1_4_921600 },
1853         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1854                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1855                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1856                 pbn_b1_4_921600 },
1857         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1858                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1859                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1860                 pbn_b1_2_921600 },
1861         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1862                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1863                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1864                 pbn_b1_8_921600 },
1865         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1866                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1867                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1868                 pbn_b1_8_921600 },
1869         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1870                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1871                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1872                 pbn_b1_4_921600 },
1873         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1874                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1875                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1876                 pbn_b1_2_1250000 },
1877         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1878                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1879                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1880                 pbn_b0_2_1843200 },
1881         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1882                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1883                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1884                 pbn_b0_4_1843200 },
1885         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1886                 PCI_VENDOR_ID_AFAVLAB,
1887                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
1888                 pbn_b0_4_1152000 },
1889         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1890                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1891                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1892                 pbn_b0_2_1843200_200 },
1893         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1894                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1895                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1896                 pbn_b0_4_1843200_200 },
1897         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1898                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1899                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1900                 pbn_b0_8_1843200_200 },
1901         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1902                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1903                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1904                 pbn_b0_2_1843200_200 },
1905         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1906                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1907                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1908                 pbn_b0_4_1843200_200 },
1909         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1910                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1911                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1912                 pbn_b0_8_1843200_200 },
1913         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1914                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1915                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1916                 pbn_b0_2_1843200_200 },
1917         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1918                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1919                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1920                 pbn_b0_4_1843200_200 },
1921         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1922                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1923                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1924                 pbn_b0_8_1843200_200 },
1925         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1926                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1927                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1928                 pbn_b0_2_1843200_200 },
1929         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1930                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1931                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1932                 pbn_b0_4_1843200_200 },
1933         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1934                 PCI_SUBVENDOR_ID_CONNECT_TECH,
1935                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1936                 pbn_b0_8_1843200_200 },
1937
1938         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1939                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1940                 pbn_b2_bt_1_115200 },
1941         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1942                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1943                 pbn_b2_bt_2_115200 },
1944         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1945                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1946                 pbn_b2_bt_4_115200 },
1947         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1948                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1949                 pbn_b2_bt_2_115200 },
1950         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1951                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1952                 pbn_b2_bt_4_115200 },
1953         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1954                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1955                 pbn_b2_8_115200 },
1956         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1957                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1958                 pbn_b2_8_115200 },
1959
1960         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1961                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1962                 pbn_b2_bt_2_115200 },
1963         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1964                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1965                 pbn_b2_bt_2_921600 },
1966         /*
1967          * VScom SPCOM800, from sl@s.pl
1968          */
1969         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1970                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1971                 pbn_b2_8_921600 },
1972         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1973                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1974                 pbn_b2_4_921600 },
1975         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1976                 PCI_SUBVENDOR_ID_KEYSPAN,
1977                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1978                 pbn_panacom },
1979         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1980                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1981                 pbn_panacom4 },
1982         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1983                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1984                 pbn_panacom2 },
1985         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1986                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1987                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1988                 pbn_b2_4_460800 },
1989         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1990                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1991                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1992                 pbn_b2_8_460800 },
1993         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1994                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1995                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1996                 pbn_b2_16_460800 },
1997         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1998                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1999                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2000                 pbn_b2_16_460800 },
2001         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2002                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2003                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2004                 pbn_b2_4_460800 },
2005         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2006                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2007                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2008                 pbn_b2_8_460800 },
2009         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2010                 PCI_SUBVENDOR_ID_EXSYS,
2011                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2012                 pbn_exsys_4055 },
2013         /*
2014          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2015          * (Exoray@isys.ca)
2016          */
2017         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2018                 0x10b5, 0x106a, 0, 0,
2019                 pbn_plx_romulus },
2020         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2021                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2022                 pbn_b1_4_115200 },
2023         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2024                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2025                 pbn_b1_2_115200 },
2026         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2027                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2028                 pbn_b1_8_115200 },
2029         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2030                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2031                 pbn_b1_8_115200 },
2032         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2033                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2034                 pbn_b0_4_921600 },
2035         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2036                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2037                 pbn_b0_4_1152000 },
2038
2039                 /*
2040                  * The below card is a little controversial since it is the
2041                  * subject of a PCI vendor/device ID clash.  (See
2042                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2043                  * For now just used the hex ID 0x950a.
2044                  */
2045         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2046                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2047                 pbn_b0_2_1130000 },
2048         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2049                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2050                 pbn_b0_4_115200 },
2051         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2052                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2053                 pbn_b0_bt_2_921600 },
2054
2055         /*
2056          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2057          * from skokodyn@yahoo.com
2058          */
2059         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2060                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2061                 pbn_sbsxrsio },
2062         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2063                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2064                 pbn_sbsxrsio },
2065         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2066                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2067                 pbn_sbsxrsio },
2068         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2069                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2070                 pbn_sbsxrsio },
2071
2072         /*
2073          * Digitan DS560-558, from jimd@esoft.com
2074          */
2075         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2077                 pbn_b1_1_115200 },
2078
2079         /*
2080          * Titan Electronic cards
2081          *  The 400L and 800L have a custom setup quirk.
2082          */
2083         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2084                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2085                 pbn_b0_1_921600 },
2086         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2087                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2088                 pbn_b0_2_921600 },
2089         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2090                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2091                 pbn_b0_4_921600 },
2092         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2093                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2094                 pbn_b0_4_921600 },
2095         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2096                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2097                 pbn_b1_1_921600 },
2098         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2099                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2100                 pbn_b1_bt_2_921600 },
2101         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2102                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2103                 pbn_b0_bt_4_921600 },
2104         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2105                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2106                 pbn_b0_bt_8_921600 },
2107
2108         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110                 pbn_b2_1_460800 },
2111         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2112                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2113                 pbn_b2_1_460800 },
2114         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2115                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2116                 pbn_b2_1_460800 },
2117         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2118                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2119                 pbn_b2_bt_2_921600 },
2120         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2121                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2122                 pbn_b2_bt_2_921600 },
2123         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2124                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2125                 pbn_b2_bt_2_921600 },
2126         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2127                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2128                 pbn_b2_bt_4_921600 },
2129         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2130                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2131                 pbn_b2_bt_4_921600 },
2132         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2133                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2134                 pbn_b2_bt_4_921600 },
2135         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2136                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2137                 pbn_b0_1_921600 },
2138         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2139                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2140                 pbn_b0_1_921600 },
2141         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2142                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2143                 pbn_b0_1_921600 },
2144         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2145                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2146                 pbn_b0_bt_2_921600 },
2147         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2148                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2149                 pbn_b0_bt_2_921600 },
2150         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2151                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2152                 pbn_b0_bt_2_921600 },
2153         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2154                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2155                 pbn_b0_bt_4_921600 },
2156         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2157                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2158                 pbn_b0_bt_4_921600 },
2159         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2160                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2161                 pbn_b0_bt_4_921600 },
2162         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2163                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2164                 pbn_b0_bt_8_921600 },
2165         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2166                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2167                 pbn_b0_bt_8_921600 },
2168         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2169                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2170                 pbn_b0_bt_8_921600 },
2171
2172         /*
2173          * Computone devices submitted by Doug McNash dmcnash@computone.com
2174          */
2175         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2176                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2177                 0, 0, pbn_computone_4 },
2178         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2179                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2180                 0, 0, pbn_computone_8 },
2181         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2182                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2183                 0, 0, pbn_computone_6 },
2184
2185         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2186                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2187                 pbn_oxsemi },
2188         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2189                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2190                 pbn_b0_bt_1_921600 },
2191
2192         /*
2193          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2194          */
2195         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2196                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2197                 pbn_b0_bt_8_115200 },
2198         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2199                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2200                 pbn_b0_bt_8_115200 },
2201
2202         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2203                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2204                 pbn_b0_bt_2_115200 },
2205         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2206                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2207                 pbn_b0_bt_2_115200 },
2208         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2209                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2210                 pbn_b0_bt_2_115200 },
2211         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2212                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2213                 pbn_b0_bt_4_460800 },
2214         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2215                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2216                 pbn_b0_bt_4_460800 },
2217         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2218                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2219                 pbn_b0_bt_2_460800 },
2220         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2221                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2222                 pbn_b0_bt_2_460800 },
2223         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2224                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2225                 pbn_b0_bt_2_460800 },
2226         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2227                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2228                 pbn_b0_bt_1_115200 },
2229         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2230                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2231                 pbn_b0_bt_1_460800 },
2232
2233         /*
2234          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2235          */
2236         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2237                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2238                 pbn_b1_1_1382400 },
2239
2240         /*
2241          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2242          */
2243         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2245                 pbn_b1_1_1382400 },
2246
2247         /*
2248          * RAStel 2 port modem, gerg@moreton.com.au
2249          */
2250         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2251                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2252                 pbn_b2_bt_2_115200 },
2253
2254         /*
2255          * EKF addition for i960 Boards form EKF with serial port
2256          */
2257         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2258                 0xE4BF, PCI_ANY_ID, 0, 0,
2259                 pbn_intel_i960 },
2260
2261         /*
2262          * Xircom Cardbus/Ethernet combos
2263          */
2264         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2265                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2266                 pbn_b0_1_115200 },
2267         /*
2268          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2269          */
2270         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2272                 pbn_b0_1_115200 },
2273
2274         /*
2275          * Untested PCI modems, sent in from various folks...
2276          */
2277
2278         /*
2279          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2280          */
2281         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
2282                 0x1048, 0x1500, 0, 0,
2283                 pbn_b1_1_115200 },
2284
2285         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2286                 0xFF00, 0, 0, 0,
2287                 pbn_sgi_ioc3 },
2288
2289         /*
2290          * HP Diva card
2291          */
2292         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2293                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2294                 pbn_b1_1_115200 },
2295         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2297                 pbn_b0_5_115200 },
2298         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2300                 pbn_b2_1_115200 },
2301
2302         /*
2303          * NEC Vrc-5074 (Nile 4) builtin UART.
2304          */
2305         {       PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2306                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2307                 pbn_nec_nile4 },
2308
2309         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2310                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2311                 pbn_b3_2_115200 },
2312         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2313                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2314                 pbn_b3_4_115200 },
2315         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2316                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2317                 pbn_b3_8_115200 },
2318
2319         /*
2320          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2321          */
2322         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2323                 PCI_ANY_ID, PCI_ANY_ID,
2324                 0,
2325                 0, pbn_exar_XR17C152 },
2326         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2327                 PCI_ANY_ID, PCI_ANY_ID,
2328                 0,
2329                 0, pbn_exar_XR17C154 },
2330         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2331                 PCI_ANY_ID, PCI_ANY_ID,
2332                 0,
2333                 0, pbn_exar_XR17C158 },
2334
2335         /*
2336          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2337          */
2338         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2339                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2340                 pbn_b0_1_115200 },
2341
2342         /*
2343          * These entries match devices with class COMMUNICATION_SERIAL,
2344          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2345          */
2346         {       PCI_ANY_ID, PCI_ANY_ID,
2347                 PCI_ANY_ID, PCI_ANY_ID,
2348                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2349                 0xffff00, pbn_default },
2350         {       PCI_ANY_ID, PCI_ANY_ID,
2351                 PCI_ANY_ID, PCI_ANY_ID,
2352                 PCI_CLASS_COMMUNICATION_MODEM << 8,
2353                 0xffff00, pbn_default },
2354         {       PCI_ANY_ID, PCI_ANY_ID,
2355                 PCI_ANY_ID, PCI_ANY_ID,
2356                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2357                 0xffff00, pbn_default },
2358         { 0, }
2359 };
2360
2361 static struct pci_driver serial_pci_driver = {
2362         .name           = "serial",
2363         .probe          = pciserial_init_one,
2364         .remove         = __devexit_p(pciserial_remove_one),
2365         .suspend        = pciserial_suspend_one,
2366         .resume         = pciserial_resume_one,
2367         .id_table       = serial_pci_tbl,
2368 };
2369
2370 static int __init serial8250_pci_init(void)
2371 {
2372         return pci_register_driver(&serial_pci_driver);
2373 }
2374
2375 static void __exit serial8250_pci_exit(void)
2376 {
2377         pci_unregister_driver(&serial_pci_driver);
2378 }
2379
2380 module_init(serial8250_pci_init);
2381 module_exit(serial8250_pci_exit);
2382
2383 MODULE_LICENSE("GPL");
2384 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2385 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);