1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
5 * OMAP3430 Clock Management register bits
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
19 /* Bits shared between registers */
21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
22 #define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
23 #define OMAP3430ES2_EN_MMC3_SHIFT 30
24 #define OMAP3430_EN_MSPRO (1 << 23)
25 #define OMAP3430_EN_MSPRO_SHIFT 23
26 #define OMAP3430_EN_HDQ (1 << 22)
27 #define OMAP3430_EN_HDQ_SHIFT 22
28 #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5)
29 #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
30 #define OMAP3430ES1_EN_D2D (1 << 3)
31 #define OMAP3430ES1_EN_D2D_SHIFT 3
32 #define OMAP3430_EN_SSI (1 << 0)
33 #define OMAP3430_EN_SSI_SHIFT 0
35 /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
36 #define OMAP3430ES2_EN_USBTLL_SHIFT 2
37 #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
39 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
40 #define OMAP3430_EN_WDT2 (1 << 5)
41 #define OMAP3430_EN_WDT2_SHIFT 5
43 /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
44 #define OMAP3430_EN_CAM (1 << 0)
45 #define OMAP3430_EN_CAM_SHIFT 0
47 /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
48 #define OMAP3430_EN_WDT3 (1 << 12)
49 #define OMAP3430_EN_WDT3_SHIFT 12
51 /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
52 #define OMAP3430_OVERRIDE_ENABLE (1 << 19)
55 /* Bits specific to each register */
58 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0)
60 /* CM_CLKEN_PLL_IVA2 */
61 #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
62 #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
63 #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
64 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
65 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
66 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
67 #define OMAP3430_EN_IVA2_DPLL_SHIFT 0
68 #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
71 #define OMAP3430_ST_IVA2 (1 << 0)
73 /* CM_IDLEST_PLL_IVA2 */
74 #define OMAP3430_ST_IVA2_CLK (1 << 0)
76 /* CM_AUTOIDLE_PLL_IVA2 */
77 #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
78 #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
80 /* CM_CLKSEL1_PLL_IVA2 */
81 #define OMAP3430_IVA2_CLK_SRC_SHIFT 19
82 #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19)
83 #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
84 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
85 #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
86 #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
88 /* CM_CLKSEL2_PLL_IVA2 */
89 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
90 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
92 /* CM_CLKSTCTRL_IVA2 */
93 #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
94 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
97 #define OMAP3430_CLKACTIVITY_IVA2 (1 << 0)
99 /* CM_REVISION specific bits */
101 /* CM_SYSCONFIG specific bits */
103 /* CM_CLKEN_PLL_MPU */
104 #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
105 #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
106 #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
107 #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
108 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
109 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
110 #define OMAP3430_EN_MPU_DPLL_SHIFT 0
111 #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
114 #define OMAP3430_ST_MPU (1 << 0)
116 /* CM_IDLEST_PLL_MPU */
117 #define OMAP3430_ST_MPU_CLK (1 << 0)
119 /* CM_AUTOIDLE_PLL_MPU */
120 #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
121 #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
123 /* CM_CLKSEL1_PLL_MPU */
124 #define OMAP3430_MPU_CLK_SRC_SHIFT 19
125 #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19)
126 #define OMAP3430_MPU_DPLL_MULT_SHIFT 8
127 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
128 #define OMAP3430_MPU_DPLL_DIV_SHIFT 0
129 #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
131 /* CM_CLKSEL2_PLL_MPU */
132 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
133 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
135 /* CM_CLKSTCTRL_MPU */
136 #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
137 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
140 #define OMAP3430_CLKACTIVITY_MPU (1 << 0)
142 /* CM_FCLKEN1_CORE specific bits */
144 /* CM_ICLKEN1_CORE specific bits */
145 #define OMAP3430_EN_ICR (1 << 29)
146 #define OMAP3430_EN_ICR_SHIFT 29
147 #define OMAP3430_EN_AES2 (1 << 28)
148 #define OMAP3430_EN_AES2_SHIFT 28
149 #define OMAP3430_EN_SHA12 (1 << 27)
150 #define OMAP3430_EN_SHA12_SHIFT 27
151 #define OMAP3430_EN_DES2 (1 << 26)
152 #define OMAP3430_EN_DES2_SHIFT 26
153 #define OMAP3430ES1_EN_FAC (1 << 8)
154 #define OMAP3430ES1_EN_FAC_SHIFT 8
155 #define OMAP3430_EN_MAILBOXES (1 << 7)
156 #define OMAP3430_EN_MAILBOXES_SHIFT 7
157 #define OMAP3430_EN_OMAPCTRL (1 << 6)
158 #define OMAP3430_EN_OMAPCTRL_SHIFT 6
159 #define OMAP3430_EN_SDRC (1 << 1)
160 #define OMAP3430_EN_SDRC_SHIFT 1
162 /* CM_ICLKEN2_CORE */
163 #define OMAP3430_EN_PKA (1 << 4)
164 #define OMAP3430_EN_PKA_SHIFT 4
165 #define OMAP3430_EN_AES1 (1 << 3)
166 #define OMAP3430_EN_AES1_SHIFT 3
167 #define OMAP3430_EN_RNG (1 << 2)
168 #define OMAP3430_EN_RNG_SHIFT 2
169 #define OMAP3430_EN_SHA11 (1 << 1)
170 #define OMAP3430_EN_SHA11_SHIFT 1
171 #define OMAP3430_EN_DES1 (1 << 0)
172 #define OMAP3430_EN_DES1_SHIFT 0
174 /* CM_FCLKEN3_CORE specific bits */
175 #define OMAP3430ES2_EN_TS_SHIFT 1
176 #define OMAP3430ES2_EN_TS_MASK (1 << 1)
177 #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
178 #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
180 /* CM_IDLEST1_CORE specific bits */
181 #define OMAP3430_ST_ICR (1 << 29)
182 #define OMAP3430_ST_AES2 (1 << 28)
183 #define OMAP3430_ST_SHA12 (1 << 27)
184 #define OMAP3430_ST_DES2 (1 << 26)
185 #define OMAP3430_ST_MSPRO (1 << 23)
186 #define OMAP3430_ST_HDQ (1 << 22)
187 #define OMAP3430ES1_ST_FAC (1 << 8)
188 #define OMAP3430ES1_ST_MAILBOXES (1 << 7)
189 #define OMAP3430_ST_OMAPCTRL (1 << 6)
190 #define OMAP3430_ST_SDMA (1 << 2)
191 #define OMAP3430_ST_SDRC (1 << 1)
192 #define OMAP3430_ST_SSI (1 << 0)
194 /* CM_IDLEST2_CORE */
195 #define OMAP3430_ST_PKA (1 << 4)
196 #define OMAP3430_ST_AES1 (1 << 3)
197 #define OMAP3430_ST_RNG (1 << 2)
198 #define OMAP3430_ST_SHA11 (1 << 1)
199 #define OMAP3430_ST_DES1 (1 << 0)
201 /* CM_IDLEST3_CORE */
202 #define OMAP3430ES2_ST_USBTLL_SHIFT 2
203 #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
205 /* CM_AUTOIDLE1_CORE */
206 #define OMAP3430_AUTO_AES2 (1 << 28)
207 #define OMAP3430_AUTO_AES2_SHIFT 28
208 #define OMAP3430_AUTO_SHA12 (1 << 27)
209 #define OMAP3430_AUTO_SHA12_SHIFT 27
210 #define OMAP3430_AUTO_DES2 (1 << 26)
211 #define OMAP3430_AUTO_DES2_SHIFT 26
212 #define OMAP3430_AUTO_MMC2 (1 << 25)
213 #define OMAP3430_AUTO_MMC2_SHIFT 25
214 #define OMAP3430_AUTO_MMC1 (1 << 24)
215 #define OMAP3430_AUTO_MMC1_SHIFT 24
216 #define OMAP3430_AUTO_MSPRO (1 << 23)
217 #define OMAP3430_AUTO_MSPRO_SHIFT 23
218 #define OMAP3430_AUTO_HDQ (1 << 22)
219 #define OMAP3430_AUTO_HDQ_SHIFT 22
220 #define OMAP3430_AUTO_MCSPI4 (1 << 21)
221 #define OMAP3430_AUTO_MCSPI4_SHIFT 21
222 #define OMAP3430_AUTO_MCSPI3 (1 << 20)
223 #define OMAP3430_AUTO_MCSPI3_SHIFT 20
224 #define OMAP3430_AUTO_MCSPI2 (1 << 19)
225 #define OMAP3430_AUTO_MCSPI2_SHIFT 19
226 #define OMAP3430_AUTO_MCSPI1 (1 << 18)
227 #define OMAP3430_AUTO_MCSPI1_SHIFT 18
228 #define OMAP3430_AUTO_I2C3 (1 << 17)
229 #define OMAP3430_AUTO_I2C3_SHIFT 17
230 #define OMAP3430_AUTO_I2C2 (1 << 16)
231 #define OMAP3430_AUTO_I2C2_SHIFT 16
232 #define OMAP3430_AUTO_I2C1 (1 << 15)
233 #define OMAP3430_AUTO_I2C1_SHIFT 15
234 #define OMAP3430_AUTO_UART2 (1 << 14)
235 #define OMAP3430_AUTO_UART2_SHIFT 14
236 #define OMAP3430_AUTO_UART1 (1 << 13)
237 #define OMAP3430_AUTO_UART1_SHIFT 13
238 #define OMAP3430_AUTO_GPT11 (1 << 12)
239 #define OMAP3430_AUTO_GPT11_SHIFT 12
240 #define OMAP3430_AUTO_GPT10 (1 << 11)
241 #define OMAP3430_AUTO_GPT10_SHIFT 11
242 #define OMAP3430_AUTO_MCBSP5 (1 << 10)
243 #define OMAP3430_AUTO_MCBSP5_SHIFT 10
244 #define OMAP3430_AUTO_MCBSP1 (1 << 9)
245 #define OMAP3430_AUTO_MCBSP1_SHIFT 9
246 #define OMAP3430ES1_AUTO_FAC (1 << 8)
247 #define OMAP3430ES1_AUTO_FAC_SHIFT 8
248 #define OMAP3430_AUTO_MAILBOXES (1 << 7)
249 #define OMAP3430_AUTO_MAILBOXES_SHIFT 7
250 #define OMAP3430_AUTO_OMAPCTRL (1 << 6)
251 #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
252 #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5)
253 #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
254 #define OMAP3430_AUTO_HSOTGUSB (1 << 4)
255 #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
256 #define OMAP3430ES1_AUTO_D2D (1 << 3)
257 #define OMAP3430ES1_AUTO_D2D_SHIFT 3
258 #define OMAP3430_AUTO_SSI (1 << 0)
259 #define OMAP3430_AUTO_SSI_SHIFT 0
261 /* CM_AUTOIDLE2_CORE */
262 #define OMAP3430_AUTO_PKA (1 << 4)
263 #define OMAP3430_AUTO_PKA_SHIFT 4
264 #define OMAP3430_AUTO_AES1 (1 << 3)
265 #define OMAP3430_AUTO_AES1_SHIFT 3
266 #define OMAP3430_AUTO_RNG (1 << 2)
267 #define OMAP3430_AUTO_RNG_SHIFT 2
268 #define OMAP3430_AUTO_SHA11 (1 << 1)
269 #define OMAP3430_AUTO_SHA11_SHIFT 1
270 #define OMAP3430_AUTO_DES1 (1 << 0)
271 #define OMAP3430_AUTO_DES1_SHIFT 0
273 /* CM_AUTOIDLE3_CORE */
274 #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
275 #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
278 #define OMAP3430_CLKSEL_SSI_SHIFT 8
279 #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
280 #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
281 #define OMAP3430_CLKSEL_GPT11_SHIFT 7
282 #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
283 #define OMAP3430_CLKSEL_GPT10_SHIFT 6
284 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
285 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
286 #define OMAP3430_CLKSEL_L4_SHIFT 2
287 #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
288 #define OMAP3430_CLKSEL_L3_SHIFT 0
289 #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
291 /* CM_CLKSTCTRL_CORE */
292 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
293 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
294 #define OMAP3430_CLKTRCTRL_L4_SHIFT 2
295 #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
296 #define OMAP3430_CLKTRCTRL_L3_SHIFT 0
297 #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
299 /* CM_CLKSTST_CORE */
300 #define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2)
301 #define OMAP3430_CLKACTIVITY_L4 (1 << 1)
302 #define OMAP3430_CLKACTIVITY_L3 (1 << 0)
305 #define OMAP3430ES1_EN_3D (1 << 2)
306 #define OMAP3430ES1_EN_3D_SHIFT 2
307 #define OMAP3430ES1_EN_2D (1 << 1)
308 #define OMAP3430ES1_EN_2D_SHIFT 1
310 /* CM_ICLKEN_GFX specific bits */
312 /* CM_IDLEST_GFX specific bits */
314 /* CM_CLKSEL_GFX specific bits */
316 /* CM_SLEEPDEP_GFX specific bits */
318 /* CM_CLKSTCTRL_GFX */
319 #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
320 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
323 #define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0)
326 #define OMAP3430ES2_EN_SGX_SHIFT 1
327 #define OMAP3430ES2_EN_SGX_MASK (1 << 1)
330 #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
331 #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
333 /* CM_FCLKEN_WKUP specific bits */
334 #define OMAP3430ES2_EN_USIMOCP_SHIFT 9
336 /* CM_ICLKEN_WKUP specific bits */
337 #define OMAP3430_EN_WDT1 (1 << 4)
338 #define OMAP3430_EN_WDT1_SHIFT 4
339 #define OMAP3430_EN_32KSYNC (1 << 2)
340 #define OMAP3430_EN_32KSYNC_SHIFT 2
342 /* CM_IDLEST_WKUP specific bits */
343 #define OMAP3430_ST_WDT2 (1 << 5)
344 #define OMAP3430_ST_WDT1 (1 << 4)
345 #define OMAP3430_ST_32KSYNC (1 << 2)
347 /* CM_AUTOIDLE_WKUP */
348 #define OMAP3430_AUTO_WDT2 (1 << 5)
349 #define OMAP3430_AUTO_WDT2_SHIFT 5
350 #define OMAP3430_AUTO_WDT1 (1 << 4)
351 #define OMAP3430_AUTO_WDT1_SHIFT 4
352 #define OMAP3430_AUTO_GPIO1 (1 << 3)
353 #define OMAP3430_AUTO_GPIO1_SHIFT 3
354 #define OMAP3430_AUTO_32KSYNC (1 << 2)
355 #define OMAP3430_AUTO_32KSYNC_SHIFT 2
356 #define OMAP3430_AUTO_GPT12 (1 << 1)
357 #define OMAP3430_AUTO_GPT12_SHIFT 1
358 #define OMAP3430_AUTO_GPT1 (1 << 0)
359 #define OMAP3430_AUTO_GPT1_SHIFT 0
362 #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
363 #define OMAP3430_CLKSEL_RM_SHIFT 1
364 #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
365 #define OMAP3430_CLKSEL_GPT1_SHIFT 0
366 #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
369 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
370 #define OMAP3430_PWRDN_CAM_SHIFT 30
371 #define OMAP3430_PWRDN_DSS1_SHIFT 29
372 #define OMAP3430_PWRDN_TV_SHIFT 28
373 #define OMAP3430_PWRDN_96M_SHIFT 27
374 #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
375 #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
376 #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
377 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
378 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
379 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
380 #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
381 #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
382 #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
383 #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
384 #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
385 #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
386 #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
387 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
388 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
389 #define OMAP3430_EN_CORE_DPLL_SHIFT 0
390 #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
393 #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
394 #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
395 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
396 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
397 #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
398 #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
399 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
401 /* CM_IDLEST_CKGEN */
402 #define OMAP3430_ST_54M_CLK (1 << 5)
403 #define OMAP3430_ST_12M_CLK (1 << 4)
404 #define OMAP3430_ST_48M_CLK (1 << 3)
405 #define OMAP3430_ST_96M_CLK (1 << 2)
406 #define OMAP3430_ST_PERIPH_CLK (1 << 1)
407 #define OMAP3430_ST_CORE_CLK (1 << 0)
409 /* CM_IDLEST2_CKGEN */
410 #define OMAP3430ES2_ST_120M_CLK_SHIFT 1
411 #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
412 #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
413 #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
415 /* CM_AUTOIDLE_PLL */
416 #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
417 #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
418 #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
419 #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
422 /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
423 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
424 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
425 #define OMAP3430_CORE_DPLL_MULT_SHIFT 16
426 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
427 #define OMAP3430_CORE_DPLL_DIV_SHIFT 8
428 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
429 #define OMAP3430_SOURCE_54M (1 << 5)
430 #define OMAP3430_SOURCE_48M (1 << 3)
433 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
434 #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
435 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
436 #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
439 #define OMAP3430_DIV_96M_SHIFT 0
440 #define OMAP3430_DIV_96M_MASK (0x1f << 0)
443 #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
444 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
445 #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
446 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
449 #define OMAP3430ES2_DIV_120M_SHIFT 0
450 #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
453 #define OMAP3430_CLKOUT2_EN_SHIFT 7
454 #define OMAP3430_CLKOUT2_EN (1 << 7)
455 #define OMAP3430_CLKOUT2_DIV_SHIFT 3
456 #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
457 #define OMAP3430_CLKOUT2SOURCE_SHIFT 0
458 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
461 #define OMAP3430_EN_TV (1 << 2)
462 #define OMAP3430_EN_TV_SHIFT 2
463 #define OMAP3430_EN_DSS2 (1 << 1)
464 #define OMAP3430_EN_DSS2_SHIFT 1
465 #define OMAP3430_EN_DSS1 (1 << 0)
466 #define OMAP3430_EN_DSS1_SHIFT 0
469 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0)
470 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
473 #define OMAP3430_ST_DSS (1 << 0)
475 /* CM_AUTOIDLE_DSS */
476 #define OMAP3430_AUTO_DSS (1 << 0)
477 #define OMAP3430_AUTO_DSS_SHIFT 0
480 #define OMAP3430_CLKSEL_TV_SHIFT 8
481 #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
482 #define OMAP3430_CLKSEL_DSS1_SHIFT 0
483 #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
485 /* CM_SLEEPDEP_DSS specific bits */
487 /* CM_CLKSTCTRL_DSS */
488 #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
489 #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
492 #define OMAP3430_CLKACTIVITY_DSS (1 << 0)
494 /* CM_FCLKEN_CAM specific bits */
496 /* CM_ICLKEN_CAM specific bits */
499 #define OMAP3430_ST_CAM (1 << 0)
501 /* CM_AUTOIDLE_CAM */
502 #define OMAP3430_AUTO_CAM (1 << 0)
503 #define OMAP3430_AUTO_CAM_SHIFT 0
506 #define OMAP3430_CLKSEL_CAM_SHIFT 0
507 #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
509 /* CM_SLEEPDEP_CAM specific bits */
511 /* CM_CLKSTCTRL_CAM */
512 #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
513 #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
516 #define OMAP3430_CLKACTIVITY_CAM (1 << 0)
518 /* CM_FCLKEN_PER specific bits */
520 /* CM_ICLKEN_PER specific bits */
523 #define OMAP3430_ST_WDT3 (1 << 12)
524 #define OMAP3430_ST_MCBSP4 (1 << 2)
525 #define OMAP3430_ST_MCBSP3 (1 << 1)
526 #define OMAP3430_ST_MCBSP2 (1 << 0)
528 /* CM_AUTOIDLE_PER */
529 #define OMAP3430_AUTO_GPIO6 (1 << 17)
530 #define OMAP3430_AUTO_GPIO6_SHIFT 17
531 #define OMAP3430_AUTO_GPIO5 (1 << 16)
532 #define OMAP3430_AUTO_GPIO5_SHIFT 16
533 #define OMAP3430_AUTO_GPIO4 (1 << 15)
534 #define OMAP3430_AUTO_GPIO4_SHIFT 15
535 #define OMAP3430_AUTO_GPIO3 (1 << 14)
536 #define OMAP3430_AUTO_GPIO3_SHIFT 14
537 #define OMAP3430_AUTO_GPIO2 (1 << 13)
538 #define OMAP3430_AUTO_GPIO2_SHIFT 13
539 #define OMAP3430_AUTO_WDT3 (1 << 12)
540 #define OMAP3430_AUTO_WDT3_SHIFT 12
541 #define OMAP3430_AUTO_UART3 (1 << 11)
542 #define OMAP3430_AUTO_UART3_SHIFT 11
543 #define OMAP3430_AUTO_GPT9 (1 << 10)
544 #define OMAP3430_AUTO_GPT9_SHIFT 10
545 #define OMAP3430_AUTO_GPT8 (1 << 9)
546 #define OMAP3430_AUTO_GPT8_SHIFT 9
547 #define OMAP3430_AUTO_GPT7 (1 << 8)
548 #define OMAP3430_AUTO_GPT7_SHIFT 8
549 #define OMAP3430_AUTO_GPT6 (1 << 7)
550 #define OMAP3430_AUTO_GPT6_SHIFT 7
551 #define OMAP3430_AUTO_GPT5 (1 << 6)
552 #define OMAP3430_AUTO_GPT5_SHIFT 6
553 #define OMAP3430_AUTO_GPT4 (1 << 5)
554 #define OMAP3430_AUTO_GPT4_SHIFT 5
555 #define OMAP3430_AUTO_GPT3 (1 << 4)
556 #define OMAP3430_AUTO_GPT3_SHIFT 4
557 #define OMAP3430_AUTO_GPT2 (1 << 3)
558 #define OMAP3430_AUTO_GPT2_SHIFT 3
559 #define OMAP3430_AUTO_MCBSP4 (1 << 2)
560 #define OMAP3430_AUTO_MCBSP4_SHIFT 2
561 #define OMAP3430_AUTO_MCBSP3 (1 << 1)
562 #define OMAP3430_AUTO_MCBSP3_SHIFT 1
563 #define OMAP3430_AUTO_MCBSP2 (1 << 0)
564 #define OMAP3430_AUTO_MCBSP2_SHIFT 0
567 #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
568 #define OMAP3430_CLKSEL_GPT9_SHIFT 7
569 #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
570 #define OMAP3430_CLKSEL_GPT8_SHIFT 6
571 #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
572 #define OMAP3430_CLKSEL_GPT7_SHIFT 5
573 #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
574 #define OMAP3430_CLKSEL_GPT6_SHIFT 4
575 #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
576 #define OMAP3430_CLKSEL_GPT5_SHIFT 3
577 #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
578 #define OMAP3430_CLKSEL_GPT4_SHIFT 2
579 #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
580 #define OMAP3430_CLKSEL_GPT3_SHIFT 1
581 #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
582 #define OMAP3430_CLKSEL_GPT2_SHIFT 0
584 /* CM_SLEEPDEP_PER specific bits */
585 #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2)
587 /* CM_CLKSTCTRL_PER */
588 #define OMAP3430_CLKTRCTRL_PER_SHIFT 0
589 #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
592 #define OMAP3430_CLKACTIVITY_PER (1 << 0)
595 #define OMAP3430_DIV_DPLL4_SHIFT 24
596 #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
597 #define OMAP3430_DIV_DPLL3_SHIFT 16
598 #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
599 #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
600 #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
601 #define OMAP3430_CLKSEL_PCLK_SHIFT 8
602 #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
603 #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
604 #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
605 #define OMAP3430_CLKSEL_ATCLK_SHIFT 4
606 #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
607 #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
608 #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
609 #define OMAP3430_MUX_CTRL_SHIFT 0
610 #define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
612 /* CM_CLKSTCTRL_EMU */
613 #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
614 #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
617 #define OMAP3430_CLKACTIVITY_EMU (1 << 0)
619 /* CM_CLKSEL2_EMU specific bits */
620 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
621 #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
622 #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
623 #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
625 /* CM_CLKSEL3_EMU specific bits */
626 #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
627 #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
628 #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
629 #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
632 #define OMAP3430_CLKOUT2_POL (1 << 0)
635 #define OMAP3430_ST_NEON (1 << 0)
637 /* CM_CLKSTCTRL_NEON */
638 #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
639 #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
641 /* CM_FCLKEN_USBHOST */
642 #define OMAP3430ES2_EN_USBHOST2_SHIFT 1
643 #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
644 #define OMAP3430ES2_EN_USBHOST1_SHIFT 0
645 #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
647 /* CM_ICLKEN_USBHOST */
648 #define OMAP3430ES2_EN_USBHOST_SHIFT 0
649 #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
651 /* CM_IDLEST_USBHOST */
653 /* CM_AUTOIDLE_USBHOST */
654 #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
655 #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
657 /* CM_SLEEPDEP_USBHOST */
658 #define OMAP3430ES2_EN_MPU_SHIFT 1
659 #define OMAP3430ES2_EN_MPU_MASK (1 << 1)
660 #define OMAP3430ES2_EN_IVA2_SHIFT 2
661 #define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
663 /* CM_CLKSTCTRL_USBHOST */
664 #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
665 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
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