2 * Copyright (C) 2005-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/delay.h>
10 #include <linux/dw_dmac.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/gpio.h>
16 #include <linux/spi/spi.h>
17 #include <linux/usb/atmel_usba_udc.h>
19 #include <asm/atmel-mci.h>
23 #include <mach/at32ap700x.h>
24 #include <mach/board.h>
25 #include <mach/hmatrix.h>
26 #include <mach/portmux.h>
27 #include <mach/sram.h>
29 #include <video/atmel_lcdc.h>
39 .end = base + 0x3ff, \
40 .flags = IORESOURCE_MEM, \
46 .flags = IORESOURCE_IRQ, \
48 #define NAMED_IRQ(num, _name) \
53 .flags = IORESOURCE_IRQ, \
56 /* REVISIT these assume *every* device supports DMA, but several
57 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
59 #define DEFINE_DEV(_name, _id) \
60 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
61 static struct platform_device _name##_id##_device = { \
65 .dma_mask = &_name##_id##_dma_mask, \
66 .coherent_dma_mask = DMA_32BIT_MASK, \
68 .resource = _name##_id##_resource, \
69 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
71 #define DEFINE_DEV_DATA(_name, _id) \
72 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
73 static struct platform_device _name##_id##_device = { \
77 .dma_mask = &_name##_id##_dma_mask, \
78 .platform_data = &_name##_id##_data, \
79 .coherent_dma_mask = DMA_32BIT_MASK, \
81 .resource = _name##_id##_resource, \
82 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
85 #define select_peripheral(pin, periph, flags) \
86 at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
88 #define DEV_CLK(_name, devname, bus, _index) \
89 static struct clk devname##_##_name = { \
91 .dev = &devname##_device.dev, \
92 .parent = &bus##_clk, \
93 .mode = bus##_clk_mode, \
94 .get_rate = bus##_clk_get_rate, \
98 static DEFINE_SPINLOCK(pm_lock);
100 static struct clk osc0;
101 static struct clk osc1;
103 static unsigned long osc_get_rate(struct clk *clk)
105 return at32_board_osc_rates[clk->index];
108 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
110 unsigned long div, mul, rate;
112 div = PM_BFEXT(PLLDIV, control) + 1;
113 mul = PM_BFEXT(PLLMUL, control) + 1;
115 rate = clk->parent->get_rate(clk->parent);
116 rate = (rate + div / 2) / div;
122 static long pll_set_rate(struct clk *clk, unsigned long rate,
126 unsigned long mul_best_fit = 0;
128 unsigned long div_min;
129 unsigned long div_max;
130 unsigned long div_best_fit = 0;
132 unsigned long pll_in;
133 unsigned long actual = 0;
134 unsigned long rate_error;
135 unsigned long rate_error_prev = ~0UL;
138 /* Rate must be between 80 MHz and 200 Mhz. */
139 if (rate < 80000000UL || rate > 200000000UL)
142 ctrl = PM_BF(PLLOPT, 4);
143 base = clk->parent->get_rate(clk->parent);
145 /* PLL input frequency must be between 6 MHz and 32 MHz. */
146 div_min = DIV_ROUND_UP(base, 32000000UL);
147 div_max = base / 6000000UL;
149 if (div_max < div_min)
152 for (div = div_min; div <= div_max; div++) {
153 pll_in = (base + div / 2) / div;
154 mul = (rate + pll_in / 2) / pll_in;
159 actual = pll_in * mul;
160 rate_error = abs(actual - rate);
162 if (rate_error < rate_error_prev) {
165 rate_error_prev = rate_error;
172 if (div_best_fit == 0)
175 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
176 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
177 ctrl |= PM_BF(PLLCOUNT, 16);
179 if (clk->parent == &osc1)
180 ctrl |= PM_BIT(PLLOSC);
187 static unsigned long pll0_get_rate(struct clk *clk)
191 control = pm_readl(PLL0);
193 return pll_get_rate(clk, control);
196 static void pll1_mode(struct clk *clk, int enabled)
198 unsigned long timeout;
202 ctrl = pm_readl(PLL1);
205 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
206 pr_debug("clk %s: failed to enable, rate not set\n",
211 ctrl |= PM_BIT(PLLEN);
212 pm_writel(PLL1, ctrl);
214 /* Wait for PLL lock. */
215 for (timeout = 10000; timeout; timeout--) {
216 status = pm_readl(ISR);
217 if (status & PM_BIT(LOCK1))
222 if (!(status & PM_BIT(LOCK1)))
223 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
226 ctrl &= ~PM_BIT(PLLEN);
227 pm_writel(PLL1, ctrl);
231 static unsigned long pll1_get_rate(struct clk *clk)
235 control = pm_readl(PLL1);
237 return pll_get_rate(clk, control);
240 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
243 unsigned long actual_rate;
245 actual_rate = pll_set_rate(clk, rate, &ctrl);
248 if (actual_rate != rate)
252 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
253 clk->name, rate, actual_rate);
254 pm_writel(PLL1, ctrl);
260 static int pll1_set_parent(struct clk *clk, struct clk *parent)
267 ctrl = pm_readl(PLL1);
268 WARN_ON(ctrl & PM_BIT(PLLEN));
271 ctrl &= ~PM_BIT(PLLOSC);
272 else if (parent == &osc1)
273 ctrl |= PM_BIT(PLLOSC);
277 pm_writel(PLL1, ctrl);
278 clk->parent = parent;
284 * The AT32AP7000 has five primary clock sources: One 32kHz
285 * oscillator, two crystal oscillators and two PLLs.
287 static struct clk osc32k = {
289 .get_rate = osc_get_rate,
293 static struct clk osc0 = {
295 .get_rate = osc_get_rate,
299 static struct clk osc1 = {
301 .get_rate = osc_get_rate,
304 static struct clk pll0 = {
306 .get_rate = pll0_get_rate,
309 static struct clk pll1 = {
312 .get_rate = pll1_get_rate,
313 .set_rate = pll1_set_rate,
314 .set_parent = pll1_set_parent,
319 * The main clock can be either osc0 or pll0. The boot loader may
320 * have chosen one for us, so we don't really know which one until we
321 * have a look at the SM.
323 static struct clk *main_clock;
326 * Synchronous clocks are generated from the main clock. The clocks
327 * must satisfy the constraint
328 * fCPU >= fHSB >= fPB
329 * i.e. each clock must not be faster than its parent.
331 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
333 return main_clock->get_rate(main_clock) >> shift;
336 static void cpu_clk_mode(struct clk *clk, int enabled)
341 spin_lock_irqsave(&pm_lock, flags);
342 mask = pm_readl(CPU_MASK);
344 mask |= 1 << clk->index;
346 mask &= ~(1 << clk->index);
347 pm_writel(CPU_MASK, mask);
348 spin_unlock_irqrestore(&pm_lock, flags);
351 static unsigned long cpu_clk_get_rate(struct clk *clk)
353 unsigned long cksel, shift = 0;
355 cksel = pm_readl(CKSEL);
356 if (cksel & PM_BIT(CPUDIV))
357 shift = PM_BFEXT(CPUSEL, cksel) + 1;
359 return bus_clk_get_rate(clk, shift);
362 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
365 unsigned long parent_rate, child_div, actual_rate, div;
367 parent_rate = clk->parent->get_rate(clk->parent);
368 control = pm_readl(CKSEL);
370 if (control & PM_BIT(HSBDIV))
371 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
375 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
376 actual_rate = parent_rate;
377 control &= ~PM_BIT(CPUDIV);
380 div = (parent_rate + rate / 2) / rate;
383 cpusel = (div > 1) ? (fls(div) - 2) : 0;
384 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
385 actual_rate = parent_rate / (1 << (cpusel + 1));
388 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
389 clk->name, rate, actual_rate);
392 pm_writel(CKSEL, control);
397 static void hsb_clk_mode(struct clk *clk, int enabled)
402 spin_lock_irqsave(&pm_lock, flags);
403 mask = pm_readl(HSB_MASK);
405 mask |= 1 << clk->index;
407 mask &= ~(1 << clk->index);
408 pm_writel(HSB_MASK, mask);
409 spin_unlock_irqrestore(&pm_lock, flags);
412 static unsigned long hsb_clk_get_rate(struct clk *clk)
414 unsigned long cksel, shift = 0;
416 cksel = pm_readl(CKSEL);
417 if (cksel & PM_BIT(HSBDIV))
418 shift = PM_BFEXT(HSBSEL, cksel) + 1;
420 return bus_clk_get_rate(clk, shift);
423 static void pba_clk_mode(struct clk *clk, int enabled)
428 spin_lock_irqsave(&pm_lock, flags);
429 mask = pm_readl(PBA_MASK);
431 mask |= 1 << clk->index;
433 mask &= ~(1 << clk->index);
434 pm_writel(PBA_MASK, mask);
435 spin_unlock_irqrestore(&pm_lock, flags);
438 static unsigned long pba_clk_get_rate(struct clk *clk)
440 unsigned long cksel, shift = 0;
442 cksel = pm_readl(CKSEL);
443 if (cksel & PM_BIT(PBADIV))
444 shift = PM_BFEXT(PBASEL, cksel) + 1;
446 return bus_clk_get_rate(clk, shift);
449 static void pbb_clk_mode(struct clk *clk, int enabled)
454 spin_lock_irqsave(&pm_lock, flags);
455 mask = pm_readl(PBB_MASK);
457 mask |= 1 << clk->index;
459 mask &= ~(1 << clk->index);
460 pm_writel(PBB_MASK, mask);
461 spin_unlock_irqrestore(&pm_lock, flags);
464 static unsigned long pbb_clk_get_rate(struct clk *clk)
466 unsigned long cksel, shift = 0;
468 cksel = pm_readl(CKSEL);
469 if (cksel & PM_BIT(PBBDIV))
470 shift = PM_BFEXT(PBBSEL, cksel) + 1;
472 return bus_clk_get_rate(clk, shift);
475 static struct clk cpu_clk = {
477 .get_rate = cpu_clk_get_rate,
478 .set_rate = cpu_clk_set_rate,
481 static struct clk hsb_clk = {
484 .get_rate = hsb_clk_get_rate,
486 static struct clk pba_clk = {
489 .mode = hsb_clk_mode,
490 .get_rate = pba_clk_get_rate,
493 static struct clk pbb_clk = {
496 .mode = hsb_clk_mode,
497 .get_rate = pbb_clk_get_rate,
502 /* --------------------------------------------------------------------
503 * Generic Clock operations
504 * -------------------------------------------------------------------- */
506 static void genclk_mode(struct clk *clk, int enabled)
510 control = pm_readl(GCCTRL(clk->index));
512 control |= PM_BIT(CEN);
514 control &= ~PM_BIT(CEN);
515 pm_writel(GCCTRL(clk->index), control);
518 static unsigned long genclk_get_rate(struct clk *clk)
521 unsigned long div = 1;
523 control = pm_readl(GCCTRL(clk->index));
524 if (control & PM_BIT(DIVEN))
525 div = 2 * (PM_BFEXT(DIV, control) + 1);
527 return clk->parent->get_rate(clk->parent) / div;
530 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
533 unsigned long parent_rate, actual_rate, div;
535 parent_rate = clk->parent->get_rate(clk->parent);
536 control = pm_readl(GCCTRL(clk->index));
538 if (rate > 3 * parent_rate / 4) {
539 actual_rate = parent_rate;
540 control &= ~PM_BIT(DIVEN);
542 div = (parent_rate + rate) / (2 * rate) - 1;
543 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
544 actual_rate = parent_rate / (2 * (div + 1));
547 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
548 clk->name, rate, actual_rate);
551 pm_writel(GCCTRL(clk->index), control);
556 int genclk_set_parent(struct clk *clk, struct clk *parent)
560 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
561 clk->name, parent->name, clk->parent->name);
563 control = pm_readl(GCCTRL(clk->index));
565 if (parent == &osc1 || parent == &pll1)
566 control |= PM_BIT(OSCSEL);
567 else if (parent == &osc0 || parent == &pll0)
568 control &= ~PM_BIT(OSCSEL);
572 if (parent == &pll0 || parent == &pll1)
573 control |= PM_BIT(PLLSEL);
575 control &= ~PM_BIT(PLLSEL);
577 pm_writel(GCCTRL(clk->index), control);
578 clk->parent = parent;
583 static void __init genclk_init_parent(struct clk *clk)
588 BUG_ON(clk->index > 7);
590 control = pm_readl(GCCTRL(clk->index));
591 if (control & PM_BIT(OSCSEL))
592 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
594 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
596 clk->parent = parent;
599 static struct dw_dma_platform_data dw_dmac0_data = {
603 static struct resource dw_dmac0_resource[] = {
607 DEFINE_DEV_DATA(dw_dmac, 0);
608 DEV_CLK(hclk, dw_dmac0, hsb, 10);
610 /* --------------------------------------------------------------------
612 * -------------------------------------------------------------------- */
613 static struct resource at32_pm0_resource[] = {
617 .flags = IORESOURCE_MEM,
622 static struct resource at32ap700x_rtc0_resource[] = {
626 .flags = IORESOURCE_MEM,
631 static struct resource at32_wdt0_resource[] = {
635 .flags = IORESOURCE_MEM,
639 static struct resource at32_eic0_resource[] = {
643 .flags = IORESOURCE_MEM,
648 DEFINE_DEV(at32_pm, 0);
649 DEFINE_DEV(at32ap700x_rtc, 0);
650 DEFINE_DEV(at32_wdt, 0);
651 DEFINE_DEV(at32_eic, 0);
654 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
657 static struct clk at32_pm_pclk = {
659 .dev = &at32_pm0_device.dev,
661 .mode = pbb_clk_mode,
662 .get_rate = pbb_clk_get_rate,
667 static struct resource intc0_resource[] = {
670 struct platform_device at32_intc0_device = {
673 .resource = intc0_resource,
674 .num_resources = ARRAY_SIZE(intc0_resource),
676 DEV_CLK(pclk, at32_intc0, pbb, 1);
678 static struct clk ebi_clk = {
681 .mode = hsb_clk_mode,
682 .get_rate = hsb_clk_get_rate,
685 static struct clk hramc_clk = {
688 .mode = hsb_clk_mode,
689 .get_rate = hsb_clk_get_rate,
693 static struct clk sdramc_clk = {
694 .name = "sdramc_clk",
696 .mode = pbb_clk_mode,
697 .get_rate = pbb_clk_get_rate,
702 static struct resource smc0_resource[] = {
706 DEV_CLK(pclk, smc0, pbb, 13);
707 DEV_CLK(mck, smc0, hsb, 0);
709 static struct platform_device pdc_device = {
713 DEV_CLK(hclk, pdc, hsb, 4);
714 DEV_CLK(pclk, pdc, pba, 16);
716 static struct clk pico_clk = {
719 .mode = cpu_clk_mode,
720 .get_rate = cpu_clk_get_rate,
724 /* --------------------------------------------------------------------
726 * -------------------------------------------------------------------- */
728 struct clk at32_hmatrix_clk = {
729 .name = "hmatrix_clk",
731 .mode = pbb_clk_mode,
732 .get_rate = pbb_clk_get_rate,
738 * Set bits in the HMATRIX Special Function Register (SFR) used by the
739 * External Bus Interface (EBI). This can be used to enable special
740 * features like CompactFlash support, NAND Flash support, etc. on
741 * certain chipselects.
743 static inline void set_ebi_sfr_bits(u32 mask)
745 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
748 /* --------------------------------------------------------------------
750 * -------------------------------------------------------------------- */
752 static struct resource at32_tcb0_resource[] = {
756 static struct platform_device at32_tcb0_device = {
759 .resource = at32_tcb0_resource,
760 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
762 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
764 static struct resource at32_tcb1_resource[] = {
768 static struct platform_device at32_tcb1_device = {
771 .resource = at32_tcb1_resource,
772 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
774 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
776 /* --------------------------------------------------------------------
778 * -------------------------------------------------------------------- */
780 static struct resource pio0_resource[] = {
785 DEV_CLK(mck, pio0, pba, 10);
787 static struct resource pio1_resource[] = {
792 DEV_CLK(mck, pio1, pba, 11);
794 static struct resource pio2_resource[] = {
799 DEV_CLK(mck, pio2, pba, 12);
801 static struct resource pio3_resource[] = {
806 DEV_CLK(mck, pio3, pba, 13);
808 static struct resource pio4_resource[] = {
813 DEV_CLK(mck, pio4, pba, 14);
815 void __init at32_add_system_devices(void)
817 platform_device_register(&at32_pm0_device);
818 platform_device_register(&at32_intc0_device);
819 platform_device_register(&at32ap700x_rtc0_device);
820 platform_device_register(&at32_wdt0_device);
821 platform_device_register(&at32_eic0_device);
822 platform_device_register(&smc0_device);
823 platform_device_register(&pdc_device);
824 platform_device_register(&dw_dmac0_device);
826 platform_device_register(&at32_tcb0_device);
827 platform_device_register(&at32_tcb1_device);
829 platform_device_register(&pio0_device);
830 platform_device_register(&pio1_device);
831 platform_device_register(&pio2_device);
832 platform_device_register(&pio3_device);
833 platform_device_register(&pio4_device);
836 /* --------------------------------------------------------------------
838 * -------------------------------------------------------------------- */
839 static struct resource atmel_psif0_resource[] __initdata = {
843 .flags = IORESOURCE_MEM,
847 static struct clk atmel_psif0_pclk = {
850 .mode = pba_clk_mode,
851 .get_rate = pba_clk_get_rate,
855 static struct resource atmel_psif1_resource[] __initdata = {
859 .flags = IORESOURCE_MEM,
863 static struct clk atmel_psif1_pclk = {
866 .mode = pba_clk_mode,
867 .get_rate = pba_clk_get_rate,
871 struct platform_device *__init at32_add_device_psif(unsigned int id)
873 struct platform_device *pdev;
875 if (!(id == 0 || id == 1))
878 pdev = platform_device_alloc("atmel_psif", id);
884 if (platform_device_add_resources(pdev, atmel_psif0_resource,
885 ARRAY_SIZE(atmel_psif0_resource)))
886 goto err_add_resources;
887 atmel_psif0_pclk.dev = &pdev->dev;
888 select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
889 select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
892 if (platform_device_add_resources(pdev, atmel_psif1_resource,
893 ARRAY_SIZE(atmel_psif1_resource)))
894 goto err_add_resources;
895 atmel_psif1_pclk.dev = &pdev->dev;
896 select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
897 select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
903 platform_device_add(pdev);
907 platform_device_put(pdev);
911 /* --------------------------------------------------------------------
913 * -------------------------------------------------------------------- */
915 static struct atmel_uart_data atmel_usart0_data = {
919 static struct resource atmel_usart0_resource[] = {
923 DEFINE_DEV_DATA(atmel_usart, 0);
924 DEV_CLK(usart, atmel_usart0, pba, 3);
926 static struct atmel_uart_data atmel_usart1_data = {
930 static struct resource atmel_usart1_resource[] = {
934 DEFINE_DEV_DATA(atmel_usart, 1);
935 DEV_CLK(usart, atmel_usart1, pba, 4);
937 static struct atmel_uart_data atmel_usart2_data = {
941 static struct resource atmel_usart2_resource[] = {
945 DEFINE_DEV_DATA(atmel_usart, 2);
946 DEV_CLK(usart, atmel_usart2, pba, 5);
948 static struct atmel_uart_data atmel_usart3_data = {
952 static struct resource atmel_usart3_resource[] = {
956 DEFINE_DEV_DATA(atmel_usart, 3);
957 DEV_CLK(usart, atmel_usart3, pba, 6);
959 static inline void configure_usart0_pins(void)
961 select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
962 select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
965 static inline void configure_usart1_pins(void)
967 select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
968 select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
971 static inline void configure_usart2_pins(void)
973 select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
974 select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
977 static inline void configure_usart3_pins(void)
979 select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
980 select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
983 static struct platform_device *__initdata at32_usarts[4];
985 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
987 struct platform_device *pdev;
991 pdev = &atmel_usart0_device;
992 configure_usart0_pins();
995 pdev = &atmel_usart1_device;
996 configure_usart1_pins();
999 pdev = &atmel_usart2_device;
1000 configure_usart2_pins();
1003 pdev = &atmel_usart3_device;
1004 configure_usart3_pins();
1010 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1011 /* Addresses in the P4 segment are permanently mapped 1:1 */
1012 struct atmel_uart_data *data = pdev->dev.platform_data;
1013 data->regs = (void __iomem *)pdev->resource[0].start;
1017 at32_usarts[line] = pdev;
1020 struct platform_device *__init at32_add_device_usart(unsigned int id)
1022 platform_device_register(at32_usarts[id]);
1023 return at32_usarts[id];
1026 struct platform_device *atmel_default_console_device;
1028 void __init at32_setup_serial_console(unsigned int usart_id)
1030 atmel_default_console_device = at32_usarts[usart_id];
1033 /* --------------------------------------------------------------------
1035 * -------------------------------------------------------------------- */
1037 #ifdef CONFIG_CPU_AT32AP7000
1038 static struct eth_platform_data macb0_data;
1039 static struct resource macb0_resource[] = {
1043 DEFINE_DEV_DATA(macb, 0);
1044 DEV_CLK(hclk, macb0, hsb, 8);
1045 DEV_CLK(pclk, macb0, pbb, 6);
1047 static struct eth_platform_data macb1_data;
1048 static struct resource macb1_resource[] = {
1052 DEFINE_DEV_DATA(macb, 1);
1053 DEV_CLK(hclk, macb1, hsb, 9);
1054 DEV_CLK(pclk, macb1, pbb, 7);
1056 struct platform_device *__init
1057 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1059 struct platform_device *pdev;
1063 pdev = &macb0_device;
1065 select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
1066 select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
1067 select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
1068 select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
1069 select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
1070 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1071 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1072 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1073 select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
1074 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1076 if (!data->is_rmii) {
1077 select_peripheral(PC(0), PERIPH_A, 0); /* COL */
1078 select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
1079 select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
1080 select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
1081 select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
1082 select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1083 select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1084 select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1085 select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
1090 pdev = &macb1_device;
1092 select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
1093 select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
1094 select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
1095 select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
1096 select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
1097 select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
1098 select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
1099 select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
1100 select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
1101 select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
1103 if (!data->is_rmii) {
1104 select_peripheral(PC(19), PERIPH_B, 0); /* COL */
1105 select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
1106 select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1107 select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1108 select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1109 select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1110 select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1111 select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1112 select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
1120 memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1121 platform_device_register(pdev);
1127 /* --------------------------------------------------------------------
1129 * -------------------------------------------------------------------- */
1130 static struct resource atmel_spi0_resource[] = {
1134 DEFINE_DEV(atmel_spi, 0);
1135 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1137 static struct resource atmel_spi1_resource[] = {
1141 DEFINE_DEV(atmel_spi, 1);
1142 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1145 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1146 unsigned int n, const u8 *pins)
1148 unsigned int pin, mode;
1150 for (; n; n--, b++) {
1151 b->bus_num = bus_num;
1152 if (b->chip_select >= 4)
1154 pin = (unsigned)b->controller_data;
1156 pin = pins[b->chip_select];
1157 b->controller_data = (void *)pin;
1159 mode = AT32_GPIOF_OUTPUT;
1160 if (!(b->mode & SPI_CS_HIGH))
1161 mode |= AT32_GPIOF_HIGH;
1162 at32_select_gpio(pin, mode);
1166 struct platform_device *__init
1167 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1170 * Manage the chipselects as GPIOs, normally using the same pins
1171 * the SPI controller expects; but boards can use other pins.
1173 static u8 __initdata spi0_pins[] =
1174 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1175 GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1176 static u8 __initdata spi1_pins[] =
1177 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1178 GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1179 struct platform_device *pdev;
1183 pdev = &atmel_spi0_device;
1184 /* pullup MISO so a level is always defined */
1185 select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP);
1186 select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
1187 select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
1188 at32_spi_setup_slaves(0, b, n, spi0_pins);
1192 pdev = &atmel_spi1_device;
1193 /* pullup MISO so a level is always defined */
1194 select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP);
1195 select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
1196 select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
1197 at32_spi_setup_slaves(1, b, n, spi1_pins);
1204 spi_register_board_info(b, n);
1205 platform_device_register(pdev);
1209 /* --------------------------------------------------------------------
1211 * -------------------------------------------------------------------- */
1212 static struct resource atmel_twi0_resource[] __initdata = {
1216 static struct clk atmel_twi0_pclk = {
1219 .mode = pba_clk_mode,
1220 .get_rate = pba_clk_get_rate,
1224 struct platform_device *__init at32_add_device_twi(unsigned int id,
1225 struct i2c_board_info *b,
1228 struct platform_device *pdev;
1233 pdev = platform_device_alloc("atmel_twi", id);
1237 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1238 ARRAY_SIZE(atmel_twi0_resource)))
1239 goto err_add_resources;
1241 select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
1242 select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
1244 atmel_twi0_pclk.dev = &pdev->dev;
1247 i2c_register_board_info(id, b, n);
1249 platform_device_add(pdev);
1253 platform_device_put(pdev);
1257 /* --------------------------------------------------------------------
1259 * -------------------------------------------------------------------- */
1260 static struct resource atmel_mci0_resource[] __initdata = {
1264 static struct clk atmel_mci0_pclk = {
1267 .mode = pbb_clk_mode,
1268 .get_rate = pbb_clk_get_rate,
1272 struct platform_device *__init
1273 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1275 struct platform_device *pdev;
1277 if (id != 0 || !data)
1280 /* Must have at least one usable slot */
1281 if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1284 pdev = platform_device_alloc("atmel_mci", id);
1288 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1289 ARRAY_SIZE(atmel_mci0_resource)))
1293 if (platform_device_add_data(pdev, data,
1294 sizeof(struct mci_platform_data)))
1297 /* CLK line is common to both slots */
1298 select_peripheral(PA(10), PERIPH_A, 0);
1300 switch (data->slot[0].bus_width) {
1302 select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1303 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1304 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1307 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
1308 select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1310 if (gpio_is_valid(data->slot[0].detect_pin))
1311 at32_select_gpio(data->slot[0].detect_pin, 0);
1312 if (gpio_is_valid(data->slot[0].wp_pin))
1313 at32_select_gpio(data->slot[0].wp_pin, 0);
1316 /* Slot is unused */
1322 switch (data->slot[1].bus_width) {
1324 select_peripheral(PB(8), PERIPH_B, 0); /* DATA1 */
1325 select_peripheral(PB(9), PERIPH_B, 0); /* DATA2 */
1326 select_peripheral(PB(10), PERIPH_B, 0); /* DATA3 */
1329 select_peripheral(PB(6), PERIPH_B, 0); /* CMD */
1330 select_peripheral(PB(7), PERIPH_B, 0); /* DATA0 */
1332 if (gpio_is_valid(data->slot[1].detect_pin))
1333 at32_select_gpio(data->slot[1].detect_pin, 0);
1334 if (gpio_is_valid(data->slot[1].wp_pin))
1335 at32_select_gpio(data->slot[1].wp_pin, 0);
1338 /* Slot is unused */
1341 if (!data->slot[0].bus_width)
1344 data->slot[1].bus_width = 0;
1348 atmel_mci0_pclk.dev = &pdev->dev;
1350 platform_device_add(pdev);
1354 platform_device_put(pdev);
1358 /* --------------------------------------------------------------------
1360 * -------------------------------------------------------------------- */
1361 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1362 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1363 static struct resource atmel_lcdfb0_resource[] = {
1365 .start = 0xff000000,
1367 .flags = IORESOURCE_MEM,
1371 /* Placeholder for pre-allocated fb memory */
1372 .start = 0x00000000,
1377 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1378 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1379 static struct clk atmel_lcdfb0_pixclk = {
1381 .dev = &atmel_lcdfb0_device.dev,
1382 .mode = genclk_mode,
1383 .get_rate = genclk_get_rate,
1384 .set_rate = genclk_set_rate,
1385 .set_parent = genclk_set_parent,
1389 struct platform_device *__init
1390 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1391 unsigned long fbmem_start, unsigned long fbmem_len,
1392 unsigned int pin_config)
1394 struct platform_device *pdev;
1395 struct atmel_lcdfb_info *info;
1396 struct fb_monspecs *monspecs;
1397 struct fb_videomode *modedb;
1398 unsigned int modedb_size;
1401 * Do a deep copy of the fb data, monspecs and modedb. Make
1402 * sure all allocations are done before setting up the
1405 monspecs = kmemdup(data->default_monspecs,
1406 sizeof(struct fb_monspecs), GFP_KERNEL);
1410 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1411 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1413 goto err_dup_modedb;
1414 monspecs->modedb = modedb;
1418 pdev = &atmel_lcdfb0_device;
1420 switch (pin_config) {
1422 select_peripheral(PC(19), PERIPH_A, 0); /* CC */
1423 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1424 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1425 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1426 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
1427 select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
1428 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1429 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
1430 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
1431 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
1432 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
1433 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
1434 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1435 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1436 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1437 select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
1438 select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
1439 select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
1440 select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
1441 select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
1442 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1443 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1444 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1445 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1446 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1447 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1448 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1449 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1450 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1451 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1452 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1455 select_peripheral(PE(0), PERIPH_B, 0); /* CC */
1456 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
1457 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
1458 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
1459 select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
1460 select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
1461 select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
1462 select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
1463 select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
1464 select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
1465 select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
1466 select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
1467 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
1468 select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
1469 select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
1470 select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
1471 select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
1472 select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1473 select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1474 select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1475 select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
1476 select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
1477 select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
1478 select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1479 select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1480 select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1481 select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1482 select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1483 select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1484 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1485 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1488 goto err_invalid_id;
1491 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1492 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1496 goto err_invalid_id;
1500 pdev->resource[2].start = fbmem_start;
1501 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1502 pdev->resource[2].flags = IORESOURCE_MEM;
1505 info = pdev->dev.platform_data;
1506 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1507 info->default_monspecs = monspecs;
1509 platform_device_register(pdev);
1520 /* --------------------------------------------------------------------
1522 * -------------------------------------------------------------------- */
1523 static struct resource atmel_pwm0_resource[] __initdata = {
1527 static struct clk atmel_pwm0_mck = {
1530 .mode = pbb_clk_mode,
1531 .get_rate = pbb_clk_get_rate,
1535 struct platform_device *__init at32_add_device_pwm(u32 mask)
1537 struct platform_device *pdev;
1542 pdev = platform_device_alloc("atmel_pwm", 0);
1546 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1547 ARRAY_SIZE(atmel_pwm0_resource)))
1550 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1553 if (mask & (1 << 0))
1554 select_peripheral(PA(28), PERIPH_A, 0);
1555 if (mask & (1 << 1))
1556 select_peripheral(PA(29), PERIPH_A, 0);
1557 if (mask & (1 << 2))
1558 select_peripheral(PA(21), PERIPH_B, 0);
1559 if (mask & (1 << 3))
1560 select_peripheral(PA(22), PERIPH_B, 0);
1562 atmel_pwm0_mck.dev = &pdev->dev;
1564 platform_device_add(pdev);
1569 platform_device_put(pdev);
1573 /* --------------------------------------------------------------------
1575 * -------------------------------------------------------------------- */
1576 static struct resource ssc0_resource[] = {
1581 DEV_CLK(pclk, ssc0, pba, 7);
1583 static struct resource ssc1_resource[] = {
1588 DEV_CLK(pclk, ssc1, pba, 8);
1590 static struct resource ssc2_resource[] = {
1595 DEV_CLK(pclk, ssc2, pba, 9);
1597 struct platform_device *__init
1598 at32_add_device_ssc(unsigned int id, unsigned int flags)
1600 struct platform_device *pdev;
1604 pdev = &ssc0_device;
1605 if (flags & ATMEL_SSC_RF)
1606 select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1607 if (flags & ATMEL_SSC_RK)
1608 select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1609 if (flags & ATMEL_SSC_TK)
1610 select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1611 if (flags & ATMEL_SSC_TF)
1612 select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1613 if (flags & ATMEL_SSC_TD)
1614 select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1615 if (flags & ATMEL_SSC_RD)
1616 select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1619 pdev = &ssc1_device;
1620 if (flags & ATMEL_SSC_RF)
1621 select_peripheral(PA(0), PERIPH_B, 0); /* RF */
1622 if (flags & ATMEL_SSC_RK)
1623 select_peripheral(PA(1), PERIPH_B, 0); /* RK */
1624 if (flags & ATMEL_SSC_TK)
1625 select_peripheral(PA(2), PERIPH_B, 0); /* TK */
1626 if (flags & ATMEL_SSC_TF)
1627 select_peripheral(PA(3), PERIPH_B, 0); /* TF */
1628 if (flags & ATMEL_SSC_TD)
1629 select_peripheral(PA(4), PERIPH_B, 0); /* TD */
1630 if (flags & ATMEL_SSC_RD)
1631 select_peripheral(PA(5), PERIPH_B, 0); /* RD */
1634 pdev = &ssc2_device;
1635 if (flags & ATMEL_SSC_TD)
1636 select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1637 if (flags & ATMEL_SSC_RD)
1638 select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1639 if (flags & ATMEL_SSC_TK)
1640 select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1641 if (flags & ATMEL_SSC_TF)
1642 select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1643 if (flags & ATMEL_SSC_RF)
1644 select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1645 if (flags & ATMEL_SSC_RK)
1646 select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1652 platform_device_register(pdev);
1656 /* --------------------------------------------------------------------
1657 * USB Device Controller
1658 * -------------------------------------------------------------------- */
1659 static struct resource usba0_resource[] __initdata = {
1661 .start = 0xff300000,
1663 .flags = IORESOURCE_MEM,
1665 .start = 0xfff03000,
1667 .flags = IORESOURCE_MEM,
1671 static struct clk usba0_pclk = {
1674 .mode = pbb_clk_mode,
1675 .get_rate = pbb_clk_get_rate,
1678 static struct clk usba0_hclk = {
1681 .mode = hsb_clk_mode,
1682 .get_rate = hsb_clk_get_rate,
1686 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1690 .fifo_size = maxpkt, \
1691 .nr_banks = maxbk, \
1696 static struct usba_ep_data at32_usba_ep[] __initdata = {
1697 EP("ep0", 0, 64, 1, 0, 0),
1698 EP("ep1", 1, 512, 2, 1, 1),
1699 EP("ep2", 2, 512, 2, 1, 1),
1700 EP("ep3-int", 3, 64, 3, 1, 0),
1701 EP("ep4-int", 4, 64, 3, 1, 0),
1702 EP("ep5", 5, 1024, 3, 1, 1),
1703 EP("ep6", 6, 1024, 3, 1, 1),
1708 struct platform_device *__init
1709 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1712 * pdata doesn't have room for any endpoints, so we need to
1713 * append room for the ones we need right after it.
1716 struct usba_platform_data pdata;
1717 struct usba_ep_data ep[7];
1719 struct platform_device *pdev;
1724 pdev = platform_device_alloc("atmel_usba_udc", 0);
1728 if (platform_device_add_resources(pdev, usba0_resource,
1729 ARRAY_SIZE(usba0_resource)))
1733 usba_data.pdata.vbus_pin = data->vbus_pin;
1735 usba_data.pdata.vbus_pin = -EINVAL;
1737 data = &usba_data.pdata;
1738 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1739 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1741 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1744 if (data->vbus_pin >= 0)
1745 at32_select_gpio(data->vbus_pin, 0);
1747 usba0_pclk.dev = &pdev->dev;
1748 usba0_hclk.dev = &pdev->dev;
1750 platform_device_add(pdev);
1755 platform_device_put(pdev);
1759 /* --------------------------------------------------------------------
1760 * IDE / CompactFlash
1761 * -------------------------------------------------------------------- */
1762 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1763 static struct resource at32_smc_cs4_resource[] __initdata = {
1765 .start = 0x04000000,
1767 .flags = IORESOURCE_MEM,
1769 IRQ(~0UL), /* Magic IRQ will be overridden */
1771 static struct resource at32_smc_cs5_resource[] __initdata = {
1773 .start = 0x20000000,
1775 .flags = IORESOURCE_MEM,
1777 IRQ(~0UL), /* Magic IRQ will be overridden */
1780 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1781 unsigned int cs, unsigned int extint)
1783 static unsigned int extint_pin_map[4] __initdata = {
1789 static bool common_pins_initialized __initdata = false;
1790 unsigned int extint_pin;
1793 if (extint >= ARRAY_SIZE(extint_pin_map))
1795 extint_pin = extint_pin_map[extint];
1799 ret = platform_device_add_resources(pdev,
1800 at32_smc_cs4_resource,
1801 ARRAY_SIZE(at32_smc_cs4_resource));
1805 select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
1806 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1809 ret = platform_device_add_resources(pdev,
1810 at32_smc_cs5_resource,
1811 ARRAY_SIZE(at32_smc_cs5_resource));
1815 select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
1816 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1822 if (!common_pins_initialized) {
1823 select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
1824 select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
1825 select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
1826 select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
1827 common_pins_initialized = true;
1830 at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1832 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1833 pdev->resource[1].end = pdev->resource[1].start;
1838 struct platform_device *__init
1839 at32_add_device_ide(unsigned int id, unsigned int extint,
1840 struct ide_platform_data *data)
1842 struct platform_device *pdev;
1844 pdev = platform_device_alloc("at32_ide", id);
1848 if (platform_device_add_data(pdev, data,
1849 sizeof(struct ide_platform_data)))
1852 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1855 platform_device_add(pdev);
1859 platform_device_put(pdev);
1863 struct platform_device *__init
1864 at32_add_device_cf(unsigned int id, unsigned int extint,
1865 struct cf_platform_data *data)
1867 struct platform_device *pdev;
1869 pdev = platform_device_alloc("at32_cf", id);
1873 if (platform_device_add_data(pdev, data,
1874 sizeof(struct cf_platform_data)))
1877 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1880 if (gpio_is_valid(data->detect_pin))
1881 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1882 if (gpio_is_valid(data->reset_pin))
1883 at32_select_gpio(data->reset_pin, 0);
1884 if (gpio_is_valid(data->vcc_pin))
1885 at32_select_gpio(data->vcc_pin, 0);
1886 /* READY is used as extint, so we can't select it as gpio */
1888 platform_device_add(pdev);
1892 platform_device_put(pdev);
1897 /* --------------------------------------------------------------------
1898 * NAND Flash / SmartMedia
1899 * -------------------------------------------------------------------- */
1900 static struct resource smc_cs3_resource[] __initdata = {
1902 .start = 0x0c000000,
1904 .flags = IORESOURCE_MEM,
1906 .start = 0xfff03c00,
1908 .flags = IORESOURCE_MEM,
1912 struct platform_device *__init
1913 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1915 struct platform_device *pdev;
1917 if (id != 0 || !data)
1920 pdev = platform_device_alloc("atmel_nand", id);
1924 if (platform_device_add_resources(pdev, smc_cs3_resource,
1925 ARRAY_SIZE(smc_cs3_resource)))
1928 if (platform_device_add_data(pdev, data,
1929 sizeof(struct atmel_nand_data)))
1932 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1933 if (data->enable_pin)
1934 at32_select_gpio(data->enable_pin,
1935 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1937 at32_select_gpio(data->rdy_pin, 0);
1939 at32_select_gpio(data->det_pin, 0);
1941 platform_device_add(pdev);
1945 platform_device_put(pdev);
1949 /* --------------------------------------------------------------------
1951 * -------------------------------------------------------------------- */
1952 static struct resource atmel_ac97c0_resource[] __initdata = {
1956 static struct clk atmel_ac97c0_pclk = {
1959 .mode = pbb_clk_mode,
1960 .get_rate = pbb_clk_get_rate,
1964 struct platform_device *__init
1965 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
1967 struct platform_device *pdev;
1968 struct ac97c_platform_data _data;
1973 pdev = platform_device_alloc("atmel_ac97c", id);
1977 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1978 ARRAY_SIZE(atmel_ac97c0_resource)))
1983 memset(data, 0, sizeof(struct ac97c_platform_data));
1984 data->reset_pin = GPIO_PIN_NONE;
1987 data->dma_rx_periph_id = 3;
1988 data->dma_tx_periph_id = 4;
1989 data->dma_controller_id = 0;
1991 if (platform_device_add_data(pdev, data,
1992 sizeof(struct ac97c_platform_data)))
1995 select_peripheral(PB(20), PERIPH_B, 0); /* SDO */
1996 select_peripheral(PB(21), PERIPH_B, 0); /* SYNC */
1997 select_peripheral(PB(22), PERIPH_B, 0); /* SCLK */
1998 select_peripheral(PB(23), PERIPH_B, 0); /* SDI */
2000 /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
2001 if (data->reset_pin != GPIO_PIN_NONE)
2002 at32_select_gpio(data->reset_pin, 0);
2004 atmel_ac97c0_pclk.dev = &pdev->dev;
2006 platform_device_add(pdev);
2010 platform_device_put(pdev);
2014 /* --------------------------------------------------------------------
2016 * -------------------------------------------------------------------- */
2017 static struct resource abdac0_resource[] __initdata = {
2021 static struct clk abdac0_pclk = {
2024 .mode = pbb_clk_mode,
2025 .get_rate = pbb_clk_get_rate,
2028 static struct clk abdac0_sample_clk = {
2029 .name = "sample_clk",
2030 .mode = genclk_mode,
2031 .get_rate = genclk_get_rate,
2032 .set_rate = genclk_set_rate,
2033 .set_parent = genclk_set_parent,
2037 struct platform_device *__init at32_add_device_abdac(unsigned int id)
2039 struct platform_device *pdev;
2044 pdev = platform_device_alloc("abdac", id);
2048 if (platform_device_add_resources(pdev, abdac0_resource,
2049 ARRAY_SIZE(abdac0_resource)))
2050 goto err_add_resources;
2052 select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
2053 select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
2054 select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
2055 select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
2057 abdac0_pclk.dev = &pdev->dev;
2058 abdac0_sample_clk.dev = &pdev->dev;
2060 platform_device_add(pdev);
2064 platform_device_put(pdev);
2068 /* --------------------------------------------------------------------
2070 * -------------------------------------------------------------------- */
2071 static struct clk gclk0 = {
2073 .mode = genclk_mode,
2074 .get_rate = genclk_get_rate,
2075 .set_rate = genclk_set_rate,
2076 .set_parent = genclk_set_parent,
2079 static struct clk gclk1 = {
2081 .mode = genclk_mode,
2082 .get_rate = genclk_get_rate,
2083 .set_rate = genclk_set_rate,
2084 .set_parent = genclk_set_parent,
2087 static struct clk gclk2 = {
2089 .mode = genclk_mode,
2090 .get_rate = genclk_get_rate,
2091 .set_rate = genclk_set_rate,
2092 .set_parent = genclk_set_parent,
2095 static struct clk gclk3 = {
2097 .mode = genclk_mode,
2098 .get_rate = genclk_get_rate,
2099 .set_rate = genclk_set_rate,
2100 .set_parent = genclk_set_parent,
2103 static struct clk gclk4 = {
2105 .mode = genclk_mode,
2106 .get_rate = genclk_get_rate,
2107 .set_rate = genclk_set_rate,
2108 .set_parent = genclk_set_parent,
2112 struct clk *at32_clock_list[] = {
2143 &atmel_usart0_usart,
2144 &atmel_usart1_usart,
2145 &atmel_usart2_usart,
2146 &atmel_usart3_usart,
2148 #if defined(CONFIG_CPU_AT32AP7000)
2154 &atmel_spi0_spi_clk,
2155 &atmel_spi1_spi_clk,
2158 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2160 &atmel_lcdfb0_pixclk,
2176 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
2178 void __init setup_platform(void)
2180 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2183 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2185 cpu_clk.parent = &pll0;
2188 cpu_clk.parent = &osc0;
2191 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2192 pll0.parent = &osc1;
2193 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2194 pll1.parent = &osc1;
2196 genclk_init_parent(&gclk0);
2197 genclk_init_parent(&gclk1);
2198 genclk_init_parent(&gclk2);
2199 genclk_init_parent(&gclk3);
2200 genclk_init_parent(&gclk4);
2201 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2202 genclk_init_parent(&atmel_lcdfb0_pixclk);
2204 genclk_init_parent(&abdac0_sample_clk);
2207 * Turn on all clocks that have at least one user already, and
2208 * turn off everything else. We only do this for module
2209 * clocks, and even though it isn't particularly pretty to
2210 * check the address of the mode function, it should do the
2213 for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
2214 struct clk *clk = at32_clock_list[i];
2216 if (clk->users == 0)
2219 if (clk->mode == &cpu_clk_mode)
2220 cpu_mask |= 1 << clk->index;
2221 else if (clk->mode == &hsb_clk_mode)
2222 hsb_mask |= 1 << clk->index;
2223 else if (clk->mode == &pba_clk_mode)
2224 pba_mask |= 1 << clk->index;
2225 else if (clk->mode == &pbb_clk_mode)
2226 pbb_mask |= 1 << clk->index;
2229 pm_writel(CPU_MASK, cpu_mask);
2230 pm_writel(HSB_MASK, hsb_mask);
2231 pm_writel(PBA_MASK, pba_mask);
2232 pm_writel(PBB_MASK, pbb_mask);
2234 /* Initialize the port muxes */
2235 at32_init_pio(&pio0_device);
2236 at32_init_pio(&pio1_device);
2237 at32_init_pio(&pio2_device);
2238 at32_init_pio(&pio3_device);
2239 at32_init_pio(&pio4_device);
2242 struct gen_pool *sram_pool;
2244 static int __init sram_init(void)
2246 struct gen_pool *pool;
2248 /* 1KiB granularity */
2249 pool = gen_pool_create(10, -1);
2253 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2260 gen_pool_destroy(pool);
2262 pr_err("Failed to create SRAM pool\n");
2265 core_initcall(sram_init);