4 * Driver for ST STV0900 satellite demodulator IC.
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2009 NetUP Inc.
8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include "stv0900_reg.h"
28 #include "stv0900_priv.h"
30 int stv0900_check_signal_presence(struct stv0900_internal *i_params,
31 enum fe_stv0900_demod_num demod)
42 carr_offset = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8)
43 | stv0900_read_reg(i_params,
45 carr_offset = ge2comp(carr_offset, 16);
46 agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
47 | stv0900_read_reg(i_params,
49 max_carrier = i_params->dmd1_srch_range / 1000;
52 carr_offset = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8)
53 | stv0900_read_reg(i_params,
55 carr_offset = ge2comp(carr_offset, 16);
56 agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
57 | stv0900_read_reg(i_params,
59 max_carrier = i_params->dmd2_srch_range / 1000;
63 max_carrier += (max_carrier / 10);
64 max_carrier = 65536 * (max_carrier / 2);
65 max_carrier /= i_params->mclk / 1000;
66 if (max_carrier > 0x4000)
69 if ((agc2_integr > 0x2000)
70 || (carr_offset > + 2*max_carrier)
71 || (carr_offset < -2*max_carrier))
79 static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
80 s32 *frequency_inc, s32 *sw_timeout,
82 enum fe_stv0900_demod_num demod)
84 s32 timeout, freq_inc, max_steps, srate, max_carrier;
86 enum fe_stv0900_search_standard standard;
91 srate = i_params->dmd1_symbol_rate;
92 max_carrier = i_params->dmd1_srch_range / 1000;
93 max_carrier += max_carrier / 10;
94 standard = i_params->dmd1_srch_standard;
97 srate = i_params->dmd2_symbol_rate;
98 max_carrier = i_params->dmd2_srch_range / 1000;
99 max_carrier += max_carrier / 10;
100 standard = i_params->dmd2_srch_stndrd;
104 max_carrier = 65536 * (max_carrier / 2);
105 max_carrier /= i_params->mclk / 1000;
107 if (max_carrier > 0x4000)
108 max_carrier = 0x4000;
111 freq_inc /= i_params->mclk >> 10;
112 freq_inc = freq_inc << 6;
115 case STV0900_SEARCH_DVBS1:
116 case STV0900_SEARCH_DSS:
120 case STV0900_SEARCH_DVBS2:
124 case STV0900_AUTO_SEARCH:
133 if ((freq_inc > max_carrier) || (freq_inc < 0))
134 freq_inc = max_carrier / 2;
139 timeout /= srate / 1000;
141 if ((timeout > 100) || (timeout < 0))
144 max_steps = (max_carrier / freq_inc) + 1;
146 if ((max_steps > 100) || (max_steps < 0)) {
148 freq_inc = max_carrier / max_steps;
151 *frequency_inc = freq_inc;
152 *sw_timeout = timeout;
157 static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
158 s32 FreqIncr, s32 Timeout, int zigzag,
159 s32 MaxStep, enum fe_stv0900_demod_num demod)
168 case STV0900_DEMOD_1:
170 max_carrier = i_params->dmd1_srch_range / 1000;
171 max_carrier += (max_carrier / 10);
173 case STV0900_DEMOD_2:
174 max_carrier = i_params->dmd2_srch_range / 1000;
175 max_carrier += (max_carrier / 10);
179 max_carrier = 65536 * (max_carrier / 2);
180 max_carrier /= i_params->mclk / 1000;
182 if (max_carrier > 0x4000)
183 max_carrier = 0x4000;
188 freqOffset = -max_carrier + FreqIncr;
194 case STV0900_DEMOD_1:
196 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
197 stv0900_write_reg(i_params, R0900_P1_CFRINIT1,
198 (freqOffset / 256) & 0xFF);
199 stv0900_write_reg(i_params, R0900_P1_CFRINIT0,
201 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
202 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
204 if (i_params->chip_id == 0x12) {
205 stv0900_write_bits(i_params,
206 F0900_P1_RST_HWARE, 1);
207 stv0900_write_bits(i_params,
208 F0900_P1_RST_HWARE, 0);
211 case STV0900_DEMOD_2:
212 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
213 stv0900_write_reg(i_params, R0900_P2_CFRINIT1,
214 (freqOffset / 256) & 0xFF);
215 stv0900_write_reg(i_params, R0900_P2_CFRINIT0,
217 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
218 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
220 if (i_params->chip_id == 0x12) {
221 stv0900_write_bits(i_params,
222 F0900_P2_RST_HWARE, 1);
223 stv0900_write_bits(i_params,
224 F0900_P2_RST_HWARE, 0);
229 if (zigzag == TRUE) {
231 freqOffset = -freqOffset - 2 * FreqIncr;
233 freqOffset = -freqOffset;
235 freqOffset += + 2 * FreqIncr;
238 lock = stv0900_get_demod_lock(i_params, demod, Timeout);
239 no_signal = stv0900_check_signal_presence(i_params, demod);
241 } while ((lock == FALSE)
242 && (no_signal == FALSE)
243 && ((freqOffset - FreqIncr) < max_carrier)
244 && ((freqOffset + FreqIncr) > -max_carrier)
245 && (stepCpt < MaxStep));
248 case STV0900_DEMOD_1:
250 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
252 case STV0900_DEMOD_2:
253 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
260 int stv0900_sw_algo(struct stv0900_internal *i_params,
261 enum fe_stv0900_demod_num demod)
269 s32 freqIncrement, softStepTimeout, trialCounter, max_steps;
271 stv0900_get_sw_loop_params(i_params, &freqIncrement, &softStepTimeout,
274 case STV0900_DEMOD_1:
276 switch (i_params->dmd1_srch_standard) {
277 case STV0900_SEARCH_DVBS1:
278 case STV0900_SEARCH_DSS:
279 if (i_params->chip_id >= 0x20)
280 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
283 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
286 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x49);
289 case STV0900_SEARCH_DVBS2:
290 if (i_params->chip_id >= 0x20)
291 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
294 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
297 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD,
302 case STV0900_AUTO_SEARCH:
304 if (i_params->chip_id >= 0x20) {
305 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
307 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
310 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
312 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
316 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD,
324 lock = stv0900_search_carr_sw_loop(i_params,
330 no_signal = stv0900_check_signal_presence(i_params,
334 || (no_signal == TRUE)
335 || (trialCounter == 2)) {
337 if (i_params->chip_id >= 0x20) {
338 stv0900_write_reg(i_params,
341 stv0900_write_reg(i_params,
345 stv0900_write_reg(i_params,
348 stv0900_write_reg(i_params,
353 if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS2_FOUND)) {
354 msleep(softStepTimeout);
355 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
357 if (dvbs2_fly_wheel < 0xd) {
358 msleep(softStepTimeout);
359 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
362 if (dvbs2_fly_wheel < 0xd) {
365 if (trialCounter < 2) {
366 if (i_params->chip_id >= 0x20)
367 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x79);
369 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x68);
371 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x89);
377 } while ((lock == FALSE)
378 && (trialCounter < 2)
379 && (no_signal == FALSE));
382 case STV0900_DEMOD_2:
383 switch (i_params->dmd2_srch_stndrd) {
384 case STV0900_SEARCH_DVBS1:
385 case STV0900_SEARCH_DSS:
386 if (i_params->chip_id >= 0x20)
387 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
390 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
393 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD,
397 case STV0900_SEARCH_DVBS2:
398 if (i_params->chip_id >= 0x20)
399 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
402 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
405 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89);
408 case STV0900_AUTO_SEARCH:
410 if (i_params->chip_id >= 0x20) {
411 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
413 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
416 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
418 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
422 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0xc9);
431 lock = stv0900_search_carr_sw_loop(i_params,
437 no_signal = stv0900_check_signal_presence(i_params,
441 || (no_signal == TRUE)
442 || (trialCounter == 2)) {
443 if (i_params->chip_id >= 0x20) {
444 stv0900_write_reg(i_params,
447 stv0900_write_reg(i_params,
451 stv0900_write_reg(i_params,
454 stv0900_write_reg(i_params,
459 if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS2_FOUND)) {
460 msleep(softStepTimeout);
461 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
462 if (dvbs2_fly_wheel < 0xd) {
463 msleep(softStepTimeout);
464 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
467 if (dvbs2_fly_wheel < 0xd) {
469 if (trialCounter < 2) {
470 if (i_params->chip_id >= 0x20)
471 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x79);
473 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x68);
475 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89);
481 } while ((lock == FALSE) && (trialCounter < 2) && (no_signal == FALSE));
489 static u32 stv0900_get_symbol_rate(struct stv0900_internal *i_params,
491 enum fe_stv0900_demod_num demod)
493 s32 sfr_field3, sfr_field2, sfr_field1, sfr_field0,
494 rem1, rem2, intval1, intval2, srate;
496 dmd_reg(sfr_field3, F0900_P1_SYMB_FREQ3, F0900_P2_SYMB_FREQ3);
497 dmd_reg(sfr_field2, F0900_P1_SYMB_FREQ2, F0900_P2_SYMB_FREQ2);
498 dmd_reg(sfr_field1, F0900_P1_SYMB_FREQ1, F0900_P2_SYMB_FREQ1);
499 dmd_reg(sfr_field0, F0900_P1_SYMB_FREQ0, F0900_P2_SYMB_FREQ0);
501 srate = (stv0900_get_bits(i_params, sfr_field3) << 24) +
502 (stv0900_get_bits(i_params, sfr_field2) << 16) +
503 (stv0900_get_bits(i_params, sfr_field1) << 8) +
504 (stv0900_get_bits(i_params, sfr_field0));
505 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
506 srate, stv0900_get_bits(i_params, sfr_field0),
507 stv0900_get_bits(i_params, sfr_field1),
508 stv0900_get_bits(i_params, sfr_field2),
509 stv0900_get_bits(i_params, sfr_field3));
511 intval1 = (mclk) >> 16;
512 intval2 = (srate) >> 16;
514 rem1 = (mclk) % 0x10000;
515 rem2 = (srate) % 0x10000;
516 srate = (intval1 * intval2) +
517 ((intval1 * rem2) >> 16) +
518 ((intval2 * rem1) >> 16);
523 static void stv0900_set_symbol_rate(struct stv0900_internal *i_params,
525 enum fe_stv0900_demod_num demod)
530 dprintk(KERN_INFO "%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
533 dmd_reg(sfr_init_reg, R0900_P1_SFRINIT1, R0900_P2_SFRINIT1);
535 if (srate > 60000000) {
537 symb /= (mclk >> 12);
538 } else if (srate > 6000000) {
540 symb /= (mclk >> 10);
546 stv0900_write_reg(i_params, sfr_init_reg, (symb >> 8) & 0x7F);
547 stv0900_write_reg(i_params, sfr_init_reg + 1, (symb & 0xFF));
550 static void stv0900_set_max_symbol_rate(struct stv0900_internal *i_params,
552 enum fe_stv0900_demod_num demod)
557 dmd_reg(sfr_max_reg, R0900_P1_SFRUP1, R0900_P2_SFRUP1);
559 srate = 105 * (srate / 100);
561 if (srate > 60000000) {
563 symb /= (mclk >> 12);
564 } else if (srate > 6000000) {
566 symb /= (mclk >> 10);
573 stv0900_write_reg(i_params, sfr_max_reg, (symb >> 8) & 0x7F);
574 stv0900_write_reg(i_params, sfr_max_reg + 1, (symb & 0xFF));
576 stv0900_write_reg(i_params, sfr_max_reg, 0x7F);
577 stv0900_write_reg(i_params, sfr_max_reg + 1, 0xFF);
581 static void stv0900_set_min_symbol_rate(struct stv0900_internal *i_params,
583 enum fe_stv0900_demod_num demod)
588 dmd_reg(sfr_min_reg, R0900_P1_SFRLOW1, R0900_P2_SFRLOW1);
590 srate = 95 * (srate / 100);
591 if (srate > 60000000) {
593 symb /= (mclk >> 12);
595 } else if (srate > 6000000) {
597 symb /= (mclk >> 10);
604 stv0900_write_reg(i_params, sfr_min_reg, (symb >> 8) & 0xFF);
605 stv0900_write_reg(i_params, sfr_min_reg + 1, (symb & 0xFF));
608 static s32 stv0900_get_timing_offst(struct stv0900_internal *i_params,
610 enum fe_stv0900_demod_num demod)
615 dmd_reg(tmgreg, R0900_P1_TMGREG2, R0900_P2_TMGREG2);
617 timingoffset = (stv0900_read_reg(i_params, tmgreg) << 16) +
618 (stv0900_read_reg(i_params, tmgreg + 1) << 8) +
619 (stv0900_read_reg(i_params, tmgreg + 2));
621 timingoffset = ge2comp(timingoffset, 24);
624 if (timingoffset == 0)
627 timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
633 static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *i_params,
634 enum fe_stv0900_demod_num demod)
636 s32 rolloff, man_fld, matstr_reg, rolloff_ctl_fld;
638 dmd_reg(man_fld, F0900_P1_MANUAL_ROLLOFF, F0900_P2_MANUAL_ROLLOFF);
639 dmd_reg(matstr_reg, R0900_P1_MATSTR1, R0900_P2_MATSTR1);
640 dmd_reg(rolloff_ctl_fld, F0900_P1_ROLLOFF_CONTROL,
641 F0900_P2_ROLLOFF_CONTROL);
643 if (i_params->chip_id == 0x10) {
644 stv0900_write_bits(i_params, man_fld, 1);
645 rolloff = stv0900_read_reg(i_params, matstr_reg) & 0x03;
646 stv0900_write_bits(i_params, rolloff_ctl_fld, rolloff);
648 stv0900_write_bits(i_params, man_fld, 0);
651 static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
668 return srate + (srate * rolloff) / 100;
671 static int stv0900_check_timing_lock(struct stv0900_internal *i_params,
672 enum fe_stv0900_demod_num demod)
674 int timingLock = FALSE;
682 case STV0900_DEMOD_1:
684 carFreq = stv0900_read_reg(i_params, R0900_P1_CARFREQ);
685 tmgTHhigh = stv0900_read_reg(i_params, R0900_P1_TMGTHRISE);
686 tmgTHLow = stv0900_read_reg(i_params, R0900_P1_TMGTHFALL);
687 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20);
688 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x0);
689 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
690 stv0900_write_reg(i_params, R0900_P1_RTC, 0x80);
691 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x40);
692 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x0);
693 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0x0);
694 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0x0);
695 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x65);
696 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
699 for (i = 0; i < 10; i++) {
700 if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2)
709 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
710 stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
711 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
712 stv0900_write_reg(i_params, R0900_P1_CARFREQ, carFreq);
713 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, tmgTHhigh);
714 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, tmgTHLow);
716 case STV0900_DEMOD_2:
717 carFreq = stv0900_read_reg(i_params, R0900_P2_CARFREQ);
718 tmgTHhigh = stv0900_read_reg(i_params, R0900_P2_TMGTHRISE);
719 tmgTHLow = stv0900_read_reg(i_params, R0900_P2_TMGTHFALL);
720 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20);
721 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0);
722 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
723 stv0900_write_reg(i_params, R0900_P2_RTC, 0x80);
724 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x40);
725 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x0);
726 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0x0);
727 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0x0);
728 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x65);
729 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
731 for (i = 0; i < 10; i++) {
732 if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2)
741 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
742 stv0900_write_reg(i_params, R0900_P2_RTC, 0x88);
743 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68);
744 stv0900_write_reg(i_params, R0900_P2_CARFREQ, carFreq);
745 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, tmgTHhigh);
746 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, tmgTHLow);
753 static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
756 struct stv0900_state *state = fe->demodulator_priv;
757 struct stv0900_internal *i_params = state->internal;
758 enum fe_stv0900_demod_num demod = state->demod;
761 s32 srate, search_range, locktimeout,
762 currier_step, nb_steps, current_step,
763 direction, tuner_freq, timeout;
766 case STV0900_DEMOD_1:
768 srate = i_params->dmd1_symbol_rate;
769 search_range = i_params->dmd1_srch_range;
772 case STV0900_DEMOD_2:
773 srate = i_params->dmd2_symbol_rate;
774 search_range = i_params->dmd2_srch_range;
778 if (srate >= 10000000)
779 locktimeout = demod_timeout / 3;
781 locktimeout = demod_timeout / 2;
783 lock = stv0900_get_demod_lock(i_params, demod, locktimeout);
786 if (srate >= 10000000) {
787 if (stv0900_check_timing_lock(i_params, demod) == TRUE) {
789 case STV0900_DEMOD_1:
791 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
792 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
794 case STV0900_DEMOD_2:
795 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
796 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
800 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
804 if (srate <= 4000000)
806 else if (srate <= 7000000)
808 else if (srate <= 10000000)
813 nb_steps = ((search_range / 1000) / currier_step);
815 nb_steps = (2 * (nb_steps + 1));
818 else if (nb_steps > 12)
823 timeout = (demod_timeout / 3);
828 case STV0900_DEMOD_1:
831 tuner_freq = i_params->tuner1_freq;
832 i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + i_params->dmd1_symbol_rate;
834 while ((current_step <= nb_steps) && (lock == FALSE)) {
837 tuner_freq += (current_step * currier_step);
839 tuner_freq -= (current_step * currier_step);
841 stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw);
842 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
843 if (i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS2) {
844 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
845 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
846 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
847 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
850 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
851 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
852 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
853 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
854 lock = stv0900_get_demod_lock(i_params, demod, timeout);
860 case STV0900_DEMOD_2:
862 tuner_freq = i_params->tuner2_freq;
863 i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + srate;
865 while ((current_step <= nb_steps) && (lock == FALSE)) {
868 tuner_freq += (current_step * currier_step);
870 tuner_freq -= (current_step * currier_step);
872 stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw);
873 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
874 if (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS2) {
875 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
876 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
877 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
878 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
881 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0);
882 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0);
883 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
884 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
885 lock = stv0900_get_demod_lock(i_params, demod, timeout);
898 static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
900 enum fe_stv0900_search_algo algo)
903 case STV0900_BLIND_SEARCH:
904 if (srate <= 1500000) {
905 (*demod_timeout) = 1500;
906 (*fec_timeout) = 400;
907 } else if (srate <= 5000000) {
908 (*demod_timeout) = 1000;
909 (*fec_timeout) = 300;
911 (*demod_timeout) = 700;
912 (*fec_timeout) = 100;
916 case STV0900_COLD_START:
917 case STV0900_WARM_START:
919 if (srate <= 1000000) {
920 (*demod_timeout) = 3000;
921 (*fec_timeout) = 1700;
922 } else if (srate <= 2000000) {
923 (*demod_timeout) = 2500;
924 (*fec_timeout) = 1100;
925 } else if (srate <= 5000000) {
926 (*demod_timeout) = 1000;
927 (*fec_timeout) = 550;
928 } else if (srate <= 10000000) {
929 (*demod_timeout) = 700;
930 (*fec_timeout) = 250;
931 } else if (srate <= 20000000) {
932 (*demod_timeout) = 400;
933 (*fec_timeout) = 130;
937 (*demod_timeout) = 300;
938 (*fec_timeout) = 100;
945 if (algo == STV0900_WARM_START)
946 (*demod_timeout) /= 2;
949 static void stv0900_set_viterbi_tracq(struct stv0900_internal *i_params,
950 enum fe_stv0900_demod_num demod)
955 dprintk(KERN_INFO "%s\n", __func__);
957 dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12);
959 stv0900_write_reg(i_params, vth_reg++, 0xd0);
960 stv0900_write_reg(i_params, vth_reg++, 0x7d);
961 stv0900_write_reg(i_params, vth_reg++, 0x53);
962 stv0900_write_reg(i_params, vth_reg++, 0x2F);
963 stv0900_write_reg(i_params, vth_reg++, 0x24);
964 stv0900_write_reg(i_params, vth_reg++, 0x1F);
967 static void stv0900_set_viterbi_standard(struct stv0900_internal *i_params,
968 enum fe_stv0900_search_standard Standard,
969 enum fe_stv0900_fec PunctureRate,
970 enum fe_stv0900_demod_num demod)
976 dprintk(KERN_INFO "%s: ViterbiStandard = ", __func__);
979 case STV0900_DEMOD_1:
981 fecmReg = R0900_P1_FECM;
982 prvitReg = R0900_P1_PRVIT;
984 case STV0900_DEMOD_2:
985 fecmReg = R0900_P2_FECM;
986 prvitReg = R0900_P2_PRVIT;
991 case STV0900_AUTO_SEARCH:
993 stv0900_write_reg(i_params, fecmReg, 0x10);
994 stv0900_write_reg(i_params, prvitReg, 0x3F);
996 case STV0900_SEARCH_DVBS1:
998 stv0900_write_reg(i_params, fecmReg, 0x00);
999 switch (PunctureRate) {
1000 case STV0900_FEC_UNKNOWN:
1002 stv0900_write_reg(i_params, prvitReg, 0x2F);
1004 case STV0900_FEC_1_2:
1005 stv0900_write_reg(i_params, prvitReg, 0x01);
1007 case STV0900_FEC_2_3:
1008 stv0900_write_reg(i_params, prvitReg, 0x02);
1010 case STV0900_FEC_3_4:
1011 stv0900_write_reg(i_params, prvitReg, 0x04);
1013 case STV0900_FEC_5_6:
1014 stv0900_write_reg(i_params, prvitReg, 0x08);
1016 case STV0900_FEC_7_8:
1017 stv0900_write_reg(i_params, prvitReg, 0x20);
1022 case STV0900_SEARCH_DSS:
1024 stv0900_write_reg(i_params, fecmReg, 0x80);
1025 switch (PunctureRate) {
1026 case STV0900_FEC_UNKNOWN:
1028 stv0900_write_reg(i_params, prvitReg, 0x13);
1030 case STV0900_FEC_1_2:
1031 stv0900_write_reg(i_params, prvitReg, 0x01);
1033 case STV0900_FEC_2_3:
1034 stv0900_write_reg(i_params, prvitReg, 0x02);
1036 case STV0900_FEC_6_7:
1037 stv0900_write_reg(i_params, prvitReg, 0x10);
1046 static void stv0900_track_optimization(struct dvb_frontend *fe)
1048 struct stv0900_state *state = fe->demodulator_priv;
1049 struct stv0900_internal *i_params = state->internal;
1050 enum fe_stv0900_demod_num demod = state->demod;
1052 s32 srate, pilots, aclc, freq1, freq0,
1053 i = 0, timed, timef, blindTunSw = 0;
1055 enum fe_stv0900_rolloff rolloff;
1056 enum fe_stv0900_modcode foundModcod;
1058 dprintk(KERN_INFO "%s\n", __func__);
1060 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1061 srate += stv0900_get_timing_offst(i_params, srate, demod);
1064 case STV0900_DEMOD_1:
1066 switch (i_params->dmd1_rslts.standard) {
1067 case STV0900_DVBS1_STANDARD:
1068 if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
1069 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1070 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
1073 stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff);
1074 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
1075 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
1077 case STV0900_DSS_STANDARD:
1078 if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
1079 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1080 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
1083 stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff);
1084 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
1085 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
1087 case STV0900_DVBS2_STANDARD:
1088 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
1089 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
1090 stv0900_write_reg(i_params, R0900_P1_ACLC, 0);
1091 stv0900_write_reg(i_params, R0900_P1_BCLC, 0);
1092 if (i_params->dmd1_rslts.frame_length == STV0900_LONG_FRAME) {
1093 foundModcod = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD);
1094 pilots = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01;
1095 aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
1096 if (foundModcod <= STV0900_QPSK_910)
1097 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
1098 else if (foundModcod <= STV0900_8PSK_910) {
1099 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1100 stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
1103 if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) {
1104 if (foundModcod <= STV0900_16APSK_910) {
1105 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1106 stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
1107 } else if (foundModcod <= STV0900_32APSK_910) {
1108 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1109 stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
1114 aclc = stv0900_get_optim_short_carr_loop(srate, i_params->dmd1_rslts.modulation, i_params->chip_id);
1115 if (i_params->dmd1_rslts.modulation == STV0900_QPSK)
1116 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
1118 else if (i_params->dmd1_rslts.modulation == STV0900_8PSK) {
1119 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1120 stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
1121 } else if (i_params->dmd1_rslts.modulation == STV0900_16APSK) {
1122 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1123 stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
1124 } else if (i_params->dmd1_rslts.modulation == STV0900_32APSK) {
1125 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1126 stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
1131 if (i_params->chip_id <= 0x11) {
1132 if (i_params->demod_mode != STV0900_SINGLE)
1133 stv0900_activate_s2_modcode(i_params, demod);
1137 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67);
1139 case STV0900_UNKNOWN_STANDARD:
1141 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1142 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
1146 freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2);
1147 freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1);
1148 rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS);
1149 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
1150 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00);
1151 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0);
1152 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
1153 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
1154 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1155 stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
1156 stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
1160 if (i_params->chip_id >= 0x20) {
1161 if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) {
1162 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0a);
1163 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x0);
1167 if (i_params->chip_id < 0x20)
1168 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x08);
1170 if (i_params->chip_id == 0x10)
1171 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0x0A);
1173 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
1175 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd1_symbol_rate < 10000000)) {
1176 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1177 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1178 i_params->tuner1_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000;
1180 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) {
1181 if (i_params->dmd1_srch_algo != STV0900_WARM_START)
1182 stv0900_set_bandwidth(fe, i_params->tuner1_bw);
1185 if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000))
1190 stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START);
1192 if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) {
1193 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
1194 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1195 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1196 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1198 while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) {
1199 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
1200 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1201 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1202 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1209 if (i_params->chip_id >= 0x20)
1210 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49);
1212 if ((i_params->dmd1_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd1_rslts.standard == STV0900_DSS_STANDARD))
1213 stv0900_set_viterbi_tracq(i_params, demod);
1217 case STV0900_DEMOD_2:
1218 switch (i_params->dmd2_rslts.standard) {
1219 case STV0900_DVBS1_STANDARD:
1221 if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) {
1222 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
1223 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
1226 stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff);
1227 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
1228 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
1230 case STV0900_DSS_STANDARD:
1231 if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) {
1232 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
1233 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
1236 stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff);
1237 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
1238 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
1240 case STV0900_DVBS2_STANDARD:
1241 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
1242 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
1243 stv0900_write_reg(i_params, R0900_P2_ACLC, 0);
1244 stv0900_write_reg(i_params, R0900_P2_BCLC, 0);
1245 if (i_params->dmd2_rslts.frame_length == STV0900_LONG_FRAME) {
1246 foundModcod = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
1247 pilots = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
1248 aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
1249 if (foundModcod <= STV0900_QPSK_910)
1250 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
1251 else if (foundModcod <= STV0900_8PSK_910) {
1252 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1253 stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
1256 if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) {
1257 if (foundModcod <= STV0900_16APSK_910) {
1258 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1259 stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
1260 } else if (foundModcod <= STV0900_32APSK_910) {
1261 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1262 stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
1268 aclc = stv0900_get_optim_short_carr_loop(srate,
1269 i_params->dmd2_rslts.modulation,
1272 if (i_params->dmd2_rslts.modulation == STV0900_QPSK)
1273 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
1275 else if (i_params->dmd2_rslts.modulation == STV0900_8PSK) {
1276 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1277 stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
1278 } else if (i_params->dmd2_rslts.modulation == STV0900_16APSK) {
1279 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1280 stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
1281 } else if (i_params->dmd2_rslts.modulation == STV0900_32APSK) {
1282 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1283 stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
1287 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67);
1290 case STV0900_UNKNOWN_STANDARD:
1292 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
1293 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
1297 freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2);
1298 freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1);
1299 rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS);
1300 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
1301 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00);
1302 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0);
1303 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1304 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
1305 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1306 stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
1307 stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
1311 if (i_params->chip_id >= 0x20) {
1312 if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) {
1313 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0a);
1314 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x0);
1318 if (i_params->chip_id < 0x20)
1319 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x08);
1321 if (i_params->chip_id == 0x10)
1322 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0x0a);
1324 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
1325 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd2_symbol_rate < 10000000)) {
1326 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1327 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1328 i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000;
1330 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) {
1331 if (i_params->dmd2_srch_algo != STV0900_WARM_START)
1332 stv0900_set_bandwidth(fe, i_params->tuner2_bw);
1335 if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000))
1340 stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START);
1341 if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) {
1342 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
1343 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1344 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1345 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1347 while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) {
1348 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
1349 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1350 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1351 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1357 if (i_params->chip_id >= 0x20)
1358 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
1360 if ((i_params->dmd2_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd2_rslts.standard == STV0900_DSS_STANDARD))
1361 stv0900_set_viterbi_tracq(i_params, demod);
1367 static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv0900_demod_num demod, s32 time_out)
1369 s32 timer = 0, lock = 0, header_field, pktdelin_field, lock_vit_field;
1371 enum fe_stv0900_search_state dmd_state;
1373 dprintk(KERN_INFO "%s\n", __func__);
1375 dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
1376 dmd_reg(pktdelin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
1377 dmd_reg(lock_vit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
1379 dmd_state = stv0900_get_bits(i_params, header_field);
1381 while ((timer < time_out) && (lock == 0)) {
1382 switch (dmd_state) {
1383 case STV0900_SEARCH:
1384 case STV0900_PLH_DETECTED:
1388 case STV0900_DVBS2_FOUND:
1389 lock = stv0900_get_bits(i_params, pktdelin_field);
1391 case STV0900_DVBS_FOUND:
1392 lock = stv0900_get_bits(i_params, lock_vit_field);
1403 dprintk("DEMOD FEC LOCK OK\n");
1405 dprintk("DEMOD FEC LOCK FAIL\n");
1410 static int stv0900_wait_for_lock(struct stv0900_internal *i_params,
1411 enum fe_stv0900_demod_num demod,
1412 s32 dmd_timeout, s32 fec_timeout)
1415 s32 timer = 0, lock = 0, str_merg_rst_fld, str_merg_lock_fld;
1417 dprintk(KERN_INFO "%s\n", __func__);
1419 dmd_reg(str_merg_rst_fld, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE);
1420 dmd_reg(str_merg_lock_fld, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
1422 lock = stv0900_get_demod_lock(i_params, demod, dmd_timeout);
1425 lock = lock && stv0900_get_fec_lock(i_params, demod, fec_timeout);
1430 dprintk(KERN_INFO "%s: Timer = %d, time_out = %d\n", __func__, timer, fec_timeout);
1432 while ((timer < fec_timeout) && (lock == 0)) {
1433 lock = stv0900_get_bits(i_params, str_merg_lock_fld);
1440 dprintk(KERN_INFO "%s: DEMOD LOCK OK\n", __func__);
1442 dprintk(KERN_INFO "%s: DEMOD LOCK FAIL\n", __func__);
1450 enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1451 enum fe_stv0900_demod_num demod)
1453 struct stv0900_state *state = fe->demodulator_priv;
1454 struct stv0900_internal *i_params = state->internal;
1455 enum fe_stv0900_tracking_standard fnd_standard;
1459 dprintk(KERN_INFO "%s\n", __func__);
1461 dmd_reg(state_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE);
1462 dmd_reg(dss_dvb_field, F0900_P1_DSS_DVB, F0900_P2_DSS_DVB);
1464 if (stv0900_get_bits(i_params, state_field) == 2)
1465 fnd_standard = STV0900_DVBS2_STANDARD;
1467 else if (stv0900_get_bits(i_params, state_field) == 3) {
1468 if (stv0900_get_bits(i_params, dss_dvb_field) == 1)
1469 fnd_standard = STV0900_DSS_STANDARD;
1471 fnd_standard = STV0900_DVBS1_STANDARD;
1473 fnd_standard = STV0900_UNKNOWN_STANDARD;
1475 return fnd_standard;
1478 static s32 stv0900_get_carr_freq(struct stv0900_internal *i_params, u32 mclk,
1479 enum fe_stv0900_demod_num demod)
1481 s32 cfr_field2, cfr_field1, cfr_field0,
1482 derot, rem1, rem2, intval1, intval2;
1484 dmd_reg(cfr_field2, F0900_P1_CAR_FREQ2, F0900_P2_CAR_FREQ2);
1485 dmd_reg(cfr_field1, F0900_P1_CAR_FREQ1, F0900_P2_CAR_FREQ1);
1486 dmd_reg(cfr_field0, F0900_P1_CAR_FREQ0, F0900_P2_CAR_FREQ0);
1488 derot = (stv0900_get_bits(i_params, cfr_field2) << 16) +
1489 (stv0900_get_bits(i_params, cfr_field1) << 8) +
1490 (stv0900_get_bits(i_params, cfr_field0));
1492 derot = ge2comp(derot, 24);
1493 intval1 = mclk >> 12;
1494 intval2 = derot >> 12;
1495 rem1 = mclk % 0x1000;
1496 rem2 = derot % 0x1000;
1497 derot = (intval1 * intval2) +
1498 ((intval1 * rem2) >> 12) +
1499 ((intval2 * rem1) >> 12);
1504 static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1506 struct dvb_frontend_ops *frontend_ops = NULL;
1507 struct dvb_tuner_ops *tuner_ops = NULL;
1511 frontend_ops = &fe->ops;
1513 if (&frontend_ops->tuner_ops)
1514 tuner_ops = &frontend_ops->tuner_ops;
1516 if (tuner_ops->get_frequency) {
1517 if ((tuner_ops->get_frequency(fe, &frequency)) < 0)
1518 dprintk("%s: Invalid parameter\n", __func__);
1520 dprintk("%s: Frequency=%d\n", __func__, frequency);
1527 static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *i_params,
1528 enum fe_stv0900_demod_num demod)
1530 s32 rate_fld, vit_curpun_fld;
1531 enum fe_stv0900_fec prate;
1533 dmd_reg(vit_curpun_fld, F0900_P1_VIT_CURPUN, F0900_P2_VIT_CURPUN);
1534 rate_fld = stv0900_get_bits(i_params, vit_curpun_fld);
1538 prate = STV0900_FEC_1_2;
1541 prate = STV0900_FEC_2_3;
1544 prate = STV0900_FEC_3_4;
1547 prate = STV0900_FEC_5_6;
1550 prate = STV0900_FEC_6_7;
1553 prate = STV0900_FEC_7_8;
1556 prate = STV0900_FEC_UNKNOWN;
1563 static enum fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1565 struct stv0900_state *state = fe->demodulator_priv;
1566 struct stv0900_internal *i_params = state->internal;
1567 enum fe_stv0900_demod_num demod = state->demod;
1568 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1577 case STV0900_DEMOD_1:
1579 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
1580 timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2);
1582 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x5c);
1584 while ((i <= 50) && (timing != 0) && (timing != 0xFF)) {
1585 timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2);
1591 i_params->dmd1_rslts.standard = stv0900_get_standard(fe, demod);
1592 i_params->dmd1_rslts.frequency = stv0900_get_tuner_freq(fe);
1593 offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000;
1594 i_params->dmd1_rslts.frequency += offsetFreq;
1595 i_params->dmd1_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1596 srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd1_rslts.symbol_rate, demod);
1597 i_params->dmd1_rslts.symbol_rate += srate_offset;
1598 i_params->dmd1_rslts.fec = stv0900_get_vit_fec(i_params, demod);
1599 i_params->dmd1_rslts.modcode = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD);
1600 i_params->dmd1_rslts.pilot = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01;
1601 i_params->dmd1_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE)) >> 1;
1602 i_params->dmd1_rslts.rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS);
1603 switch (i_params->dmd1_rslts.standard) {
1604 case STV0900_DVBS2_STANDARD:
1605 i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_SPECINV_DEMOD);
1606 if (i_params->dmd1_rslts.modcode <= STV0900_QPSK_910)
1607 i_params->dmd1_rslts.modulation = STV0900_QPSK;
1608 else if (i_params->dmd1_rslts.modcode <= STV0900_8PSK_910)
1609 i_params->dmd1_rslts.modulation = STV0900_8PSK;
1610 else if (i_params->dmd1_rslts.modcode <= STV0900_16APSK_910)
1611 i_params->dmd1_rslts.modulation = STV0900_16APSK;
1612 else if (i_params->dmd1_rslts.modcode <= STV0900_32APSK_910)
1613 i_params->dmd1_rslts.modulation = STV0900_32APSK;
1615 i_params->dmd1_rslts.modulation = STV0900_UNKNOWN;
1617 case STV0900_DVBS1_STANDARD:
1618 case STV0900_DSS_STANDARD:
1619 i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_IQINV);
1620 i_params->dmd1_rslts.modulation = STV0900_QPSK;
1626 if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000)) {
1627 offsetFreq = i_params->dmd1_rslts.frequency - i_params->tuner1_freq;
1628 i_params->tuner1_freq = stv0900_get_tuner_freq(fe);
1629 if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500))
1630 range = STV0900_RANGEOK;
1632 if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd1_rslts.symbol_rate, i_params->dmd1_rslts.rolloff) / 2000))
1633 range = STV0900_RANGEOK;
1635 range = STV0900_OUTOFRANGE;
1638 if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500))
1639 range = STV0900_RANGEOK;
1641 range = STV0900_OUTOFRANGE;
1644 case STV0900_DEMOD_2:
1645 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
1646 timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2);
1648 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x5c);
1650 while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1651 timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2);
1657 i_params->dmd2_rslts.standard = stv0900_get_standard(fe, demod);
1658 i_params->dmd2_rslts.frequency = stv0900_get_tuner_freq(fe);
1659 offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000;
1660 i_params->dmd2_rslts.frequency += offsetFreq;
1661 i_params->dmd2_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1662 srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd2_rslts.symbol_rate, demod);
1663 i_params->dmd2_rslts.symbol_rate += srate_offset;
1664 i_params->dmd2_rslts.fec = stv0900_get_vit_fec(i_params, demod);
1665 i_params->dmd2_rslts.modcode = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
1666 i_params->dmd2_rslts.pilot = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
1667 i_params->dmd2_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE)) >> 1;
1668 i_params->dmd2_rslts.rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS);
1669 switch (i_params->dmd2_rslts.standard) {
1670 case STV0900_DVBS2_STANDARD:
1671 i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_SPECINV_DEMOD);
1672 if (i_params->dmd2_rslts.modcode <= STV0900_QPSK_910)
1673 i_params->dmd2_rslts.modulation = STV0900_QPSK;
1674 else if (i_params->dmd2_rslts.modcode <= STV0900_8PSK_910)
1675 i_params->dmd2_rslts.modulation = STV0900_8PSK;
1676 else if (i_params->dmd2_rslts.modcode <= STV0900_16APSK_910)
1677 i_params->dmd2_rslts.modulation = STV0900_16APSK;
1678 else if (i_params->dmd2_rslts.modcode <= STV0900_32APSK_910)
1679 i_params->dmd2_rslts.modulation = STV0900_32APSK;
1681 i_params->dmd2_rslts.modulation = STV0900_UNKNOWN;
1683 case STV0900_DVBS1_STANDARD:
1684 case STV0900_DSS_STANDARD:
1685 i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_IQINV);
1686 i_params->dmd2_rslts.modulation = STV0900_QPSK;
1692 if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000)) {
1693 offsetFreq = i_params->dmd2_rslts.frequency - i_params->tuner2_freq;
1694 i_params->tuner2_freq = stv0900_get_tuner_freq(fe);
1696 if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500))
1697 range = STV0900_RANGEOK;
1699 if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd2_rslts.symbol_rate, i_params->dmd2_rslts.rolloff) / 2000))
1700 range = STV0900_RANGEOK;
1702 range = STV0900_OUTOFRANGE;
1704 if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500))
1705 range = STV0900_RANGEOK;
1707 range = STV0900_OUTOFRANGE;
1716 static enum fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1718 struct stv0900_state *state = fe->demodulator_priv;
1719 struct stv0900_internal *i_params = state->internal;
1720 enum fe_stv0900_demod_num demod = state->demod;
1722 s32 srate, demod_timeout,
1723 fec_timeout, freq1, freq0;
1724 enum fe_stv0900_signal_type signal_type = STV0900_NODATA;;
1727 case STV0900_DEMOD_1:
1729 i_params->dmd1_rslts.locked = FALSE;
1730 if (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) {
1731 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1732 srate += stv0900_get_timing_offst(i_params, srate, demod);
1733 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH)
1734 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1736 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START);
1737 freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2);
1738 freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1);
1739 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
1740 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED);
1741 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
1742 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1743 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1744 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1745 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1746 i_params->dmd1_rslts.locked = TRUE;
1747 signal_type = stv0900_get_signal_params(fe);
1748 stv0900_track_optimization(fe);
1750 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL);
1751 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1c);
1752 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1753 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1754 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1755 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1756 i_params->dmd1_rslts.locked = TRUE;
1757 signal_type = stv0900_get_signal_params(fe);
1758 stv0900_track_optimization(fe);
1764 i_params->dmd1_rslts.locked = FALSE;
1767 case STV0900_DEMOD_2:
1768 i_params->dmd2_rslts.locked = FALSE;
1769 if (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) {
1770 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1771 srate += stv0900_get_timing_offst(i_params, srate, demod);
1773 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH)
1774 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1776 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START);
1777 freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2);
1778 freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1);
1779 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1780 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED);
1781 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
1782 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1783 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1784 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1786 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1787 i_params->dmd2_rslts.locked = TRUE;
1788 signal_type = stv0900_get_signal_params(fe);
1789 stv0900_track_optimization(fe);
1791 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL);
1792 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1c);
1793 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1794 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1795 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1797 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1798 i_params->dmd2_rslts.locked = TRUE;
1799 signal_type = stv0900_get_signal_params(fe);
1800 stv0900_track_optimization(fe);
1806 i_params->dmd1_rslts.locked = FALSE;
1814 static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
1815 enum fe_stv0900_demod_num demod)
1817 u32 minagc2level = 0xffff,
1819 init_freq, freq_step;
1821 s32 i, j, nb_steps, direction;
1823 dprintk(KERN_INFO "%s\n", __func__);
1826 case STV0900_DEMOD_1:
1828 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
1829 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1);
1830 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1);
1832 stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83);
1833 stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0);
1835 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82);
1836 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0);
1837 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0);
1839 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
1840 nb_steps = -1 + (i_params->dmd1_srch_range / 1000000);
1842 nb_steps = (2 * nb_steps) + 1;
1849 freq_step = (1000000 << 8) / (i_params->mclk >> 8);
1853 for (i = 0; i < nb_steps; i++) {
1855 init_freq = init_freq + (freq_step * i);
1857 init_freq = init_freq - (freq_step * i);
1860 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C);
1861 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (init_freq >> 8) & 0xff);
1862 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, init_freq & 0xff);
1863 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x58);
1867 for (j = 0; j < 10; j++)
1868 agc2level += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
1869 | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
1873 if (agc2level < minagc2level)
1874 minagc2level = agc2level;
1877 case STV0900_DEMOD_2:
1878 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
1879 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
1880 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
1881 stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
1882 stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
1883 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
1884 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
1885 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
1886 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
1887 nb_steps = -1 + (i_params->dmd2_srch_range / 1000000);
1889 nb_steps = (2 * nb_steps) + 1;
1895 freq_step = (1000000 << 8) / (i_params->mclk >> 8);
1897 for (i = 0; i < nb_steps; i++) {
1899 init_freq = init_freq + (freq_step * i);
1901 init_freq = init_freq - (freq_step * i);
1905 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C);
1906 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (init_freq >> 8) & 0xff);
1907 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, init_freq & 0xff);
1908 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x58);
1912 for (j = 0; j < 10; j++)
1913 agc2level += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
1914 | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
1918 if (agc2level < minagc2level)
1919 minagc2level = agc2level;
1924 return (u16)minagc2level;
1927 static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1929 struct stv0900_state *state = fe->demodulator_priv;
1930 struct stv0900_internal *i_params = state->internal;
1931 enum fe_stv0900_demod_num demod = state->demod;
1932 int timingLock = FALSE;
1933 s32 i, timingcpt = 0,
1939 u32 coarse_srate = 0, agc2_integr = 0, currier_step = 1200;
1942 case STV0900_DEMOD_1:
1944 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1F);
1945 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0x12);
1946 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xf0);
1947 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xe0);
1948 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1);
1949 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1);
1950 stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83);
1951 stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0);
1952 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82);
1953 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0);
1954 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0);
1955 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x50);
1957 if (i_params->chip_id >= 0x20) {
1958 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x6a);
1959 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x95);
1961 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
1962 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x73);
1965 if (i_params->dmd1_symbol_rate <= 2000000)
1966 currier_step = 1000;
1967 else if (i_params->dmd1_symbol_rate <= 5000000)
1968 currier_step = 2000;
1969 else if (i_params->dmd1_symbol_rate <= 12000000)
1970 currier_step = 3000;
1972 currier_step = 5000;
1974 nb_steps = -1 + ((i_params->dmd1_srch_range / 1000) / currier_step);
1976 nb_steps = (2 * nb_steps) + 1;
1981 else if (nb_steps > 10) {
1983 currier_step = (i_params->dmd1_srch_range / 1000) / 10;
1989 tuner_freq = i_params->tuner1_freq;
1991 while ((timingLock == FALSE) && (current_step < nb_steps)) {
1992 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5F);
1993 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x0);
1997 for (i = 0; i < 10; i++) {
1998 if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2)
2001 agc2_integr += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8) | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
2006 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2010 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n", tuner_freq, agc2_integr, coarse_srate, timingcpt);
2012 if ((timingcpt >= 5) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000)) {
2016 else if (current_step < nb_steps) {
2018 tuner_freq += (current_step * currier_step);
2020 tuner_freq -= (current_step * currier_step);
2022 stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw);
2026 if (timingLock == FALSE)
2029 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2031 case STV0900_DEMOD_2:
2032 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1F);
2033 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0x12);
2034 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xf0);
2035 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xe0);
2036 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
2037 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
2038 stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
2039 stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
2040 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
2041 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
2042 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
2043 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x50);
2045 if (i_params->chip_id >= 0x20) {
2046 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x6a);
2047 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x95);
2049 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
2050 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x73);
2053 if (i_params->dmd2_symbol_rate <= 2000000)
2054 currier_step = 1000;
2055 else if (i_params->dmd2_symbol_rate <= 5000000)
2056 currier_step = 2000;
2057 else if (i_params->dmd2_symbol_rate <= 12000000)
2058 currier_step = 3000;
2060 currier_step = 5000;
2063 nb_steps = -1 + ((i_params->dmd2_srch_range / 1000) / currier_step);
2065 nb_steps = (2 * nb_steps) + 1;
2069 else if (nb_steps > 10) {
2071 currier_step = (i_params->dmd2_srch_range / 1000) / 10;
2076 tuner_freq = i_params->tuner2_freq;
2078 while ((timingLock == FALSE) && (current_step < nb_steps)) {
2079 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5F);
2080 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x0);
2085 for (i = 0; i < 20; i++) {
2086 if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2)
2088 agc2_integr += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
2089 | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
2093 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2094 if ((timingcpt >= 10) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000))
2101 tuner_freq += (current_step * currier_step);
2103 tuner_freq -= (current_step * currier_step);
2105 stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw);
2109 if (timingLock == FALSE)
2112 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2116 return coarse_srate;
2119 static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
2121 struct stv0900_state *state = fe->demodulator_priv;
2122 struct stv0900_internal *i_params = state->internal;
2123 enum fe_stv0900_demod_num demod = state->demod;
2128 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2131 case STV0900_DEMOD_1:
2133 coarse_freq = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8)
2134 | stv0900_read_reg(i_params, R0900_P1_CFR1);
2135 symb = 13 * (coarse_srate / 10);
2137 if (symb < i_params->dmd1_symbol_rate)
2140 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
2141 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
2142 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20);
2143 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x00);
2144 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
2145 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
2147 if (i_params->chip_id >= 0x20)
2148 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49);
2150 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
2152 if (coarse_srate > 3000000) {
2153 symb = 13 * (coarse_srate / 10);
2154 symb = (symb / 1000) * 65536;
2155 symb /= (i_params->mclk / 1000);
2156 stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
2157 stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
2159 symb = 10 * (coarse_srate / 13);
2160 symb = (symb / 1000) * 65536;
2161 symb /= (i_params->mclk / 1000);
2163 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
2164 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
2166 symb = (coarse_srate / 1000) * 65536;
2167 symb /= (i_params->mclk / 1000);
2168 stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
2169 stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
2171 symb = 13 * (coarse_srate / 10);
2172 symb = (symb / 100) * 65536;
2173 symb /= (i_params->mclk / 100);
2174 stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
2175 stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
2177 symb = 10 * (coarse_srate / 14);
2178 symb = (symb / 100) * 65536;
2179 symb /= (i_params->mclk / 100);
2180 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
2181 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
2183 symb = (coarse_srate / 100) * 65536;
2184 symb /= (i_params->mclk / 100);
2185 stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
2186 stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
2189 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20);
2190 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (coarse_freq >> 8) & 0xff);
2191 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, coarse_freq & 0xff);
2192 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
2195 case STV0900_DEMOD_2:
2196 coarse_freq = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8)
2197 | stv0900_read_reg(i_params, R0900_P2_CFR1);
2199 symb = 13 * (coarse_srate / 10);
2201 if (symb < i_params->dmd2_symbol_rate)
2204 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F);
2205 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
2206 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20);
2207 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0x00);
2208 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2);
2209 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
2211 if (i_params->chip_id >= 0x20)
2212 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
2214 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
2216 if (coarse_srate > 3000000) {
2217 symb = 13 * (coarse_srate / 10);
2218 symb = (symb / 1000) * 65536;
2219 symb /= (i_params->mclk / 1000);
2220 stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
2221 stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
2223 symb = 10 * (coarse_srate / 13);
2224 symb = (symb / 1000) * 65536;
2225 symb /= (i_params->mclk / 1000);
2227 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
2228 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
2230 symb = (coarse_srate / 1000) * 65536;
2231 symb /= (i_params->mclk / 1000);
2232 stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
2233 stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
2235 symb = 13 * (coarse_srate / 10);
2236 symb = (symb / 100) * 65536;
2237 symb /= (i_params->mclk / 100);
2238 stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
2239 stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
2241 symb = 10 * (coarse_srate / 14);
2242 symb = (symb / 100) * 65536;
2243 symb /= (i_params->mclk / 100);
2244 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
2245 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
2247 symb = (coarse_srate / 100) * 65536;
2248 symb /= (i_params->mclk / 100);
2249 stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
2250 stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
2253 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20);
2254 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (coarse_freq >> 8) & 0xff);
2255 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, coarse_freq & 0xff);
2256 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
2262 return coarse_srate;
2265 static int stv0900_blind_search_algo(struct dvb_frontend *fe)
2267 struct stv0900_state *state = fe->demodulator_priv;
2268 struct stv0900_internal *i_params = state->internal;
2269 enum fe_stv0900_demod_num demod = state->demod;
2270 u8 k_ref_tmg, k_ref_tmg_max, k_ref_tmg_min;
2272 int lock = FALSE, coarse_fail = FALSE;
2273 s32 demod_timeout = 500, fec_timeout = 50, kref_tmg_reg, fail_cpt, i, agc2_overflow;
2277 dprintk(KERN_INFO "%s\n", __func__);
2279 if (i_params->chip_id < 0x20) {
2280 k_ref_tmg_max = 233;
2281 k_ref_tmg_min = 143;
2283 k_ref_tmg_max = 120;
2287 agc2_integr = stv0900_blind_check_agc2_min_level(i_params, demod);
2289 if (agc2_integr > STV0900_BLIND_SEARCH_AGC2_TH) {
2294 case STV0900_DEMOD_1:
2296 if (i_params->chip_id == 0x10)
2297 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xAA);
2299 if (i_params->chip_id < 0x20)
2300 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
2302 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xC4);
2303 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
2305 if (i_params->chip_id >= 0x20) {
2306 stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
2307 stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
2308 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
2309 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
2312 kref_tmg_reg = R0900_P1_KREFTMG;
2314 case STV0900_DEMOD_2:
2315 if (i_params->chip_id == 0x10)
2316 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xAA);
2318 if (i_params->chip_id < 0x20)
2319 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
2321 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xC4);
2322 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
2324 if (i_params->chip_id >= 0x20) {
2325 stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41);
2326 stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
2327 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
2328 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
2331 kref_tmg_reg = R0900_P2_KREFTMG;
2335 k_ref_tmg = k_ref_tmg_max;
2338 stv0900_write_reg(i_params, kref_tmg_reg, k_ref_tmg);
2339 if (stv0900_search_srate_coarse(fe) != 0) {
2340 coarse_srate = stv0900_search_srate_fine(fe);
2342 if (coarse_srate != 0) {
2343 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, coarse_srate, STV0900_BLIND_SEARCH);
2344 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
2352 case STV0900_DEMOD_1:
2354 for (i = 0; i < 10; i++) {
2355 agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
2356 | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
2358 if (agc2_integr >= 0xff00)
2361 dstatus2 = stv0900_read_reg(i_params, R0900_P1_DSTATUS2);
2363 if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1))
2367 case STV0900_DEMOD_2:
2368 for (i = 0; i < 10; i++) {
2369 agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
2370 | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
2372 if (agc2_integr >= 0xff00)
2375 dstatus2 = stv0900_read_reg(i_params, R0900_P2_DSTATUS2);
2377 if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1))
2383 if ((fail_cpt > 7) || (agc2_overflow > 7))
2389 } while ((k_ref_tmg >= k_ref_tmg_min) && (lock == FALSE) && (coarse_fail == FALSE));
2395 static void stv0900_set_viterbi_acq(struct stv0900_internal *i_params,
2396 enum fe_stv0900_demod_num demod)
2400 dprintk(KERN_INFO "%s\n", __func__);
2402 dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12);
2404 stv0900_write_reg(i_params, vth_reg++, 0x96);
2405 stv0900_write_reg(i_params, vth_reg++, 0x64);
2406 stv0900_write_reg(i_params, vth_reg++, 0x36);
2407 stv0900_write_reg(i_params, vth_reg++, 0x23);
2408 stv0900_write_reg(i_params, vth_reg++, 0x1E);
2409 stv0900_write_reg(i_params, vth_reg++, 0x19);
2412 static void stv0900_set_search_standard(struct stv0900_internal *i_params,
2413 enum fe_stv0900_demod_num demod)
2418 dprintk(KERN_INFO "%s\n", __func__);
2420 sstndrd = i_params->dmd1_srch_standard;
2422 sstndrd = i_params->dmd2_srch_stndrd;
2425 case STV0900_SEARCH_DVBS1:
2426 dprintk("Search Standard = DVBS1\n");
2428 case STV0900_SEARCH_DSS:
2429 dprintk("Search Standard = DSS\n");
2430 case STV0900_SEARCH_DVBS2:
2432 dprintk("Search Standard = DVBS2\n");
2433 case STV0900_AUTO_SEARCH:
2435 dprintk("Search Standard = AUTO\n");
2440 case STV0900_DEMOD_1:
2442 switch (i_params->dmd1_srch_standard) {
2443 case STV0900_SEARCH_DVBS1:
2444 case STV0900_SEARCH_DSS:
2445 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
2446 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
2448 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0);
2449 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
2450 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
2451 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x22);
2453 stv0900_set_viterbi_acq(i_params, demod);
2454 stv0900_set_viterbi_standard(i_params,
2455 i_params->dmd1_srch_standard,
2456 i_params->dmd1_fec, demod);
2459 case STV0900_SEARCH_DVBS2:
2460 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
2461 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
2462 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
2463 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
2464 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 1);
2465 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
2466 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
2467 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
2468 if (i_params->demod_mode != STV0900_SINGLE) {
2469 if (i_params->chip_id <= 0x11)
2470 stv0900_stop_all_s2_modcod(i_params, demod);
2472 stv0900_activate_s2_modcode(i_params, demod);
2475 stv0900_activate_s2_modcode_single(i_params, demod);
2477 stv0900_set_viterbi_tracq(i_params, demod);
2480 case STV0900_AUTO_SEARCH:
2482 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
2483 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
2484 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
2485 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
2486 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0);
2487 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
2488 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
2489 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
2490 if (i_params->demod_mode != STV0900_SINGLE) {
2491 if (i_params->chip_id <= 0x11)
2492 stv0900_stop_all_s2_modcod(i_params, demod);
2494 stv0900_activate_s2_modcode(i_params, demod);
2497 stv0900_activate_s2_modcode_single(i_params, demod);
2499 if (i_params->dmd1_symbol_rate >= 2000000)
2500 stv0900_set_viterbi_acq(i_params, demod);
2502 stv0900_set_viterbi_tracq(i_params, demod);
2504 stv0900_set_viterbi_standard(i_params, i_params->dmd1_srch_standard, i_params->dmd1_fec, demod);
2509 case STV0900_DEMOD_2:
2510 switch (i_params->dmd2_srch_stndrd) {
2511 case STV0900_SEARCH_DVBS1:
2512 case STV0900_SEARCH_DSS:
2513 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
2514 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
2515 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0);
2516 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
2517 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
2518 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x22);
2519 stv0900_set_viterbi_acq(i_params, demod);
2520 stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod);
2522 case STV0900_SEARCH_DVBS2:
2523 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
2524 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
2525 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
2526 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
2527 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 1);
2528 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
2529 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
2530 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26);
2531 if (i_params->demod_mode != STV0900_SINGLE)
2532 stv0900_activate_s2_modcode(i_params, demod);
2534 stv0900_activate_s2_modcode_single(i_params, demod);
2536 stv0900_set_viterbi_tracq(i_params, demod);
2538 case STV0900_AUTO_SEARCH:
2540 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
2541 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
2542 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
2543 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
2544 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0);
2545 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
2546 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
2547 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26);
2548 if (i_params->demod_mode != STV0900_SINGLE)
2549 stv0900_activate_s2_modcode(i_params, demod);
2551 stv0900_activate_s2_modcode_single(i_params, demod);
2553 if (i_params->dmd2_symbol_rate >= 2000000)
2554 stv0900_set_viterbi_acq(i_params, demod);
2556 stv0900_set_viterbi_tracq(i_params, demod);
2558 stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod);
2567 enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
2569 struct stv0900_state *state = fe->demodulator_priv;
2570 struct stv0900_internal *i_params = state->internal;
2571 enum fe_stv0900_demod_num demod = state->demod;
2573 s32 demod_timeout = 500, fec_timeout = 50, stream_merger_field;
2575 int lock = FALSE, low_sr = FALSE;
2577 enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
2578 enum fe_stv0900_search_algo algo;
2579 int no_signal = FALSE;
2581 dprintk(KERN_INFO "%s\n", __func__);
2584 case STV0900_DEMOD_1:
2586 algo = i_params->dmd1_srch_algo;
2588 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1);
2589 stream_merger_field = F0900_P1_RST_HWARE;
2591 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C);
2593 if (i_params->chip_id >= 0x20)
2594 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x9e);
2596 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x88);
2598 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd1_symbol_rate, i_params->dmd1_srch_algo);
2600 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
2601 i_params->tuner1_bw = 2 * 36000000;
2603 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x00);
2604 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
2606 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
2608 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20);
2609 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
2611 if (i_params->dmd1_symbol_rate < 2000000)
2612 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x63);
2614 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
2616 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
2617 if (i_params->chip_id >= 0x20) {
2618 stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0x5a);
2620 if (i_params->dmd1_srch_algo == STV0900_COLD_START)
2621 i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
2622 else if (i_params->dmd1_srch_algo == STV0900_WARM_START)
2623 i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000;
2625 stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0xc1);
2626 i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
2629 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
2631 stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2632 stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2633 stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2634 if (i_params->dmd1_symbol_rate >= 10000000)
2641 stv0900_set_tuner(fe, i_params->tuner1_freq, i_params->tuner1_bw);
2643 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, i_params->dmd1_srch_iq_inv);
2644 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
2646 stv0900_set_search_standard(i_params, demod);
2648 if (i_params->dmd1_srch_algo != STV0900_BLIND_SEARCH)
2649 stv0900_start_search(i_params, demod);
2651 case STV0900_DEMOD_2:
2652 algo = i_params->dmd2_srch_algo;
2654 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1);
2656 stream_merger_field = F0900_P2_RST_HWARE;
2658 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C);
2660 if (i_params->chip_id >= 0x20)
2661 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x9e);
2663 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x88);
2665 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd2_symbol_rate, i_params->dmd2_srch_algo);
2667 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) {
2668 i_params->tuner2_bw = 2 * 36000000;
2670 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x00);
2671 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70);
2673 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
2675 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20);
2676 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2);
2678 if (i_params->dmd2_symbol_rate < 2000000)
2679 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x63);
2681 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70);
2683 if (i_params->dmd2_symbol_rate >= 10000000)
2684 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
2686 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x60);
2688 if (i_params->chip_id >= 0x20) {
2689 stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0x5a);
2691 if (i_params->dmd2_srch_algo == STV0900_COLD_START)
2692 i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
2693 i_params->rolloff) + 10000000)) / 10;
2694 else if (i_params->dmd2_srch_algo == STV0900_WARM_START)
2695 i_params->tuner2_bw = stv0900_carrier_width(i_params->dmd2_symbol_rate,
2696 i_params->rolloff) + 10000000;
2698 stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0xc1);
2699 i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
2700 i_params->rolloff) + 10000000)) / 10;
2703 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
2705 stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
2706 stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
2707 stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
2708 if (i_params->dmd2_symbol_rate >= 10000000)
2715 stv0900_set_tuner(fe, i_params->tuner2_freq, i_params->tuner2_bw);
2717 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, i_params->dmd2_srch_iq_inv);
2718 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
2720 stv0900_set_search_standard(i_params, demod);
2722 if (i_params->dmd2_srch_algo != STV0900_BLIND_SEARCH)
2723 stv0900_start_search(i_params, demod);
2727 if (i_params->chip_id == 0x12) {
2728 stv0900_write_bits(i_params, stream_merger_field, 0);
2730 stv0900_write_bits(i_params, stream_merger_field, 1);
2731 stv0900_write_bits(i_params, stream_merger_field, 0);
2734 if (algo == STV0900_BLIND_SEARCH)
2735 lock = stv0900_blind_search_algo(fe);
2736 else if (algo == STV0900_COLD_START)
2737 lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
2738 else if (algo == STV0900_WARM_START)
2739 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
2741 if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
2742 if (low_sr == FALSE) {
2743 if (stv0900_check_timing_lock(i_params, demod) == TRUE)
2744 lock = stv0900_sw_algo(i_params, demod);
2749 signal_type = stv0900_get_signal_params(fe);
2751 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
2752 stv0900_track_optimization(fe);
2753 if (i_params->chip_id <= 0x11) {
2754 if ((stv0900_get_standard(fe, STV0900_DEMOD_1) == STV0900_DVBS1_STANDARD) && (stv0900_get_standard(fe, STV0900_DEMOD_2) == STV0900_DVBS1_STANDARD)) {
2756 stv0900_write_bits(i_params, stream_merger_field, 0);
2758 stv0900_write_bits(i_params, stream_merger_field, 0);
2760 stv0900_write_bits(i_params, stream_merger_field, 1);
2761 stv0900_write_bits(i_params, stream_merger_field, 0);
2763 } else if (i_params->chip_id == 0x20) {
2764 stv0900_write_bits(i_params, stream_merger_field, 0);
2766 stv0900_write_bits(i_params, stream_merger_field, 1);
2767 stv0900_write_bits(i_params, stream_merger_field, 0);
2770 if (stv0900_wait_for_lock(i_params, demod, fec_timeout, fec_timeout) == TRUE) {
2773 case STV0900_DEMOD_1:
2775 i_params->dmd1_rslts.locked = TRUE;
2776 if (i_params->dmd1_rslts.standard == STV0900_DVBS2_STANDARD) {
2777 stv0900_set_dvbs2_rolloff(i_params, demod);
2778 stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0x40);
2779 stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0);
2780 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67);
2782 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
2785 stv0900_write_reg(i_params, R0900_P1_FBERCPT4, 0);
2786 stv0900_write_reg(i_params, R0900_P1_ERRCTRL2, 0xc1);
2788 case STV0900_DEMOD_2:
2789 i_params->dmd2_rslts.locked = TRUE;
2791 if (i_params->dmd2_rslts.standard == STV0900_DVBS2_STANDARD) {
2792 stv0900_set_dvbs2_rolloff(i_params, demod);
2793 stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x60);
2794 stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x20);
2795 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67);
2797 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
2800 stv0900_write_reg(i_params, R0900_P2_FBERCPT4, 0);
2802 stv0900_write_reg(i_params, R0900_P2_ERRCTRL2, 0xc1);
2807 signal_type = STV0900_NODATA;
2808 no_signal = stv0900_check_signal_presence(i_params, demod);
2811 case STV0900_DEMOD_1:
2813 i_params->dmd1_rslts.locked = FALSE;
2815 case STV0900_DEMOD_2:
2816 i_params->dmd2_rslts.locked = FALSE;
2822 if ((signal_type == STV0900_NODATA) && (no_signal == FALSE)) {
2824 case STV0900_DEMOD_1:
2826 if (i_params->chip_id <= 0x11) {
2827 if ((stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) &&
2828 (i_params->dmd1_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
2829 signal_type = stv0900_dvbs1_acq_workaround(fe);
2831 i_params->dmd1_rslts.locked = FALSE;
2834 case STV0900_DEMOD_2:
2835 if (i_params->chip_id <= 0x11) {
2836 if ((stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) &&
2837 (i_params->dmd2_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
2838 signal_type = stv0900_dvbs1_acq_workaround(fe);
2840 i_params->dmd2_rslts.locked = FALSE;