Merge branch 'topic/ca0106-resume' into topic/ca0106
[linux-2.6] / arch / blackfin / kernel / cplb-nompu / cplbinit.c
1 /*
2  * Blackfin CPLB initialization
3  *
4  *               Copyright 2004-2007 Analog Devices Inc.
5  *
6  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, see the file COPYING, or write
20  * to the Free Software Foundation, Inc.,
21  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
22  */
23 #include <linux/module.h>
24
25 #include <asm/blackfin.h>
26 #include <asm/cacheflush.h>
27 #include <asm/cplb.h>
28 #include <asm/cplbinit.h>
29
30 #define CPLB_MEM CONFIG_MAX_MEM_SIZE
31
32 /*
33 * Number of required data CPLB switchtable entries
34 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
35 * approx 16 for smaller 1MB page size CPLBs for allignment purposes
36 * 1 for L1 Data Memory
37 * possibly 1 for L2 Data Memory
38 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
39 * 1 for ASYNC Memory
40 */
41 #define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
42                                  + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
43
44 /*
45 * Number of required instruction CPLB switchtable entries
46 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
47 * approx 12 for smaller 1MB page size CPLBs for allignment purposes
48 * 1 for L1 Instruction Memory
49 * possibly 1 for L2 Instruction Memory
50 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
51 */
52 #define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
53
54
55 u_long icplb_table[MAX_CPLBS + 1];
56 u_long dcplb_table[MAX_CPLBS + 1];
57
58 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
59 # define PDT_ATTR __attribute__((l1_data))
60 #else
61 # define PDT_ATTR
62 #endif
63
64 u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
65 u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;
66
67 #ifdef CONFIG_CPLB_INFO
68 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
69 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
70 #endif
71
72 struct s_cplb {
73         struct cplb_tab init_i;
74         struct cplb_tab init_d;
75         struct cplb_tab switch_i;
76         struct cplb_tab switch_d;
77 };
78
79 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
80 static struct cplb_desc cplb_data[] = {
81         {
82                 .start = 0,
83                 .end = SIZE_1K,
84                 .psize = SIZE_1K,
85                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
86                 .i_conf = SDRAM_OOPS,
87                 .d_conf = SDRAM_OOPS,
88 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
89                 .valid = 1,
90 #else
91                 .valid = 0,
92 #endif
93                 .name = "Zero Pointer Guard Page",
94         },
95         {
96                 .start = L1_CODE_START,
97                 .end = L1_CODE_START + L1_CODE_LENGTH,
98                 .psize = SIZE_4M,
99                 .attr = INITIAL_T | SWITCH_T | I_CPLB,
100                 .i_conf = L1_IMEMORY,
101                 .d_conf = 0,
102                 .valid = 1,
103                 .name = "L1 I-Memory",
104         },
105         {
106                 .start = L1_DATA_A_START,
107                 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
108                 .psize = SIZE_4M,
109                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
110                 .i_conf = 0,
111                 .d_conf = L1_DMEMORY,
112 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
113                 .valid = 1,
114 #else
115                 .valid = 0,
116 #endif
117                 .name = "L1 D-Memory",
118         },
119         {
120                 .start = 0,
121                 .end = 0,  /* dynamic */
122                 .psize = 0,
123                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
124                 .i_conf = SDRAM_IGENERIC,
125                 .d_conf = SDRAM_DGENERIC,
126                 .valid = 1,
127                 .name = "Kernel Memory",
128         },
129         {
130                 .start = 0, /* dynamic */
131                 .end = 0, /* dynamic */
132                 .psize = 0,
133                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
134                 .i_conf = SDRAM_IGENERIC,
135                 .d_conf = SDRAM_DNON_CHBL,
136                 .valid = 1,
137                 .name = "uClinux MTD Memory",
138         },
139         {
140                 .start = 0, /* dynamic */
141                 .end = 0,   /* dynamic */
142                 .psize = SIZE_1M,
143                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
144                 .d_conf = SDRAM_DNON_CHBL,
145                 .valid = 1,
146                 .name = "Uncached DMA Zone",
147         },
148         {
149                 .start = 0, /* dynamic */
150                 .end = 0, /* dynamic */
151                 .psize = 0,
152                 .attr = SWITCH_T | D_CPLB,
153                 .i_conf = 0, /* dynamic */
154                 .d_conf = 0, /* dynamic */
155                 .valid = 1,
156                 .name = "Reserved Memory",
157         },
158         {
159                 .start = ASYNC_BANK0_BASE,
160                 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
161                 .psize = 0,
162                 .attr = SWITCH_T | D_CPLB,
163                 .d_conf = SDRAM_EBIU,
164                 .valid = 1,
165                 .name = "Asynchronous Memory Banks",
166         },
167         {
168                 .start = L2_START,
169                 .end = L2_START + L2_LENGTH,
170                 .psize = SIZE_1M,
171                 .attr = SWITCH_T | I_CPLB | D_CPLB,
172                 .i_conf = L2_IMEMORY,
173                 .d_conf = L2_DMEMORY,
174                 .valid = (L2_LENGTH > 0),
175                 .name = "L2 Memory",
176         },
177         {
178                 .start = BOOT_ROM_START,
179                 .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
180                 .psize = SIZE_1M,
181                 .attr = SWITCH_T | I_CPLB | D_CPLB,
182                 .i_conf = SDRAM_IGENERIC,
183                 .d_conf = SDRAM_DGENERIC,
184                 .valid = 1,
185                 .name = "On-Chip BootROM",
186         },
187 };
188
189 static u16 __init lock_kernel_check(u32 start, u32 end)
190 {
191         if (start >= (u32)_end || end <= (u32)_stext)
192                 return 0;
193
194         /* This cplb block overlapped with kernel area. */
195         return IN_KERNEL;
196 }
197
198 static unsigned short __init
199 fill_cplbtab(struct cplb_tab *table,
200              unsigned long start, unsigned long end,
201              unsigned long block_size, unsigned long cplb_data)
202 {
203         int i;
204
205         switch (block_size) {
206         case SIZE_4M:
207                 i = 3;
208                 break;
209         case SIZE_1M:
210                 i = 2;
211                 break;
212         case SIZE_4K:
213                 i = 1;
214                 break;
215         case SIZE_1K:
216         default:
217                 i = 0;
218                 break;
219         }
220
221         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
222
223         while ((start < end) && (table->pos < table->size)) {
224
225                 table->tab[table->pos++] = start;
226
227                 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
228                         table->tab[table->pos++] =
229                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
230                 else
231                         table->tab[table->pos++] = cplb_data;
232
233                 start += block_size;
234         }
235         return 0;
236 }
237
238 static unsigned short __init
239 close_cplbtab(struct cplb_tab *table)
240 {
241
242         while (table->pos < table->size) {
243
244                 table->tab[table->pos++] = 0;
245                 table->tab[table->pos++] = 0; /* !CPLB_VALID */
246         }
247         return 0;
248 }
249
250 /* helper function */
251 static void __init
252 __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
253 {
254         if (cplb_data[i].psize) {
255                 fill_cplbtab(t,
256                                 cplb_data[i].start,
257                                 cplb_data[i].end,
258                                 cplb_data[i].psize,
259                                 cplb_data[i].i_conf);
260         } else {
261 #if defined(CONFIG_BFIN_ICACHE)
262                 if (ANOMALY_05000263 && i == SDRAM_KERN) {
263                         fill_cplbtab(t,
264                                         cplb_data[i].start,
265                                         cplb_data[i].end,
266                                         SIZE_4M,
267                                         cplb_data[i].i_conf);
268                 } else
269 #endif
270                 {
271                         fill_cplbtab(t,
272                                         cplb_data[i].start,
273                                         a_start,
274                                         SIZE_1M,
275                                         cplb_data[i].i_conf);
276                         fill_cplbtab(t,
277                                         a_start,
278                                         a_end,
279                                         SIZE_4M,
280                                         cplb_data[i].i_conf);
281                         fill_cplbtab(t, a_end,
282                                         cplb_data[i].end,
283                                         SIZE_1M,
284                                         cplb_data[i].i_conf);
285                 }
286         }
287 }
288
289 static void __init
290 __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
291 {
292         if (cplb_data[i].psize) {
293                 fill_cplbtab(t,
294                                 cplb_data[i].start,
295                                 cplb_data[i].end,
296                                 cplb_data[i].psize,
297                                 cplb_data[i].d_conf);
298         } else {
299                 fill_cplbtab(t,
300                                 cplb_data[i].start,
301                                 a_start, SIZE_1M,
302                                 cplb_data[i].d_conf);
303                 fill_cplbtab(t, a_start,
304                                 a_end, SIZE_4M,
305                                 cplb_data[i].d_conf);
306                 fill_cplbtab(t, a_end,
307                                 cplb_data[i].end,
308                                 SIZE_1M,
309                                 cplb_data[i].d_conf);
310         }
311 }
312
313 void __init generate_cplb_tables(void)
314 {
315
316         u16 i, j, process;
317         u32 a_start, a_end, as, ae, as_1m;
318
319         struct cplb_tab *t_i = NULL;
320         struct cplb_tab *t_d = NULL;
321         struct s_cplb cplb;
322
323         printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n");
324
325         cplb.init_i.size = MAX_CPLBS;
326         cplb.init_d.size = MAX_CPLBS;
327         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
328         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
329
330         cplb.init_i.pos = 0;
331         cplb.init_d.pos = 0;
332         cplb.switch_i.pos = 0;
333         cplb.switch_d.pos = 0;
334
335         cplb.init_i.tab = icplb_table;
336         cplb.init_d.tab = dcplb_table;
337         cplb.switch_i.tab = ipdt_table;
338         cplb.switch_d.tab = dpdt_table;
339
340         cplb_data[SDRAM_KERN].end = memory_end;
341
342 #ifdef CONFIG_MTD_UCLINUX
343         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
344         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
345         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
346 # if defined(CONFIG_ROMFS_FS)
347         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
348
349         /*
350          * The ROMFS_FS size is often not multiple of 1MB.
351          * This can cause multiple CPLB sets covering the same memory area.
352          * This will then cause multiple CPLB hit exceptions.
353          * Workaround: We ensure a contiguous memory area by extending the kernel
354          * memory section over the mtd section.
355          * For ROMFS_FS memory must be covered with ICPLBs anyways.
356          * So there is no difference between kernel and mtd memory setup.
357          */
358
359         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
360         cplb_data[SDRAM_RAM_MTD].valid = 0;
361
362 # endif
363 #else
364         cplb_data[SDRAM_RAM_MTD].valid = 0;
365 #endif
366
367         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
368         cplb_data[SDRAM_DMAZ].end = _ramend;
369
370         cplb_data[RES_MEM].start = _ramend;
371         cplb_data[RES_MEM].end = physical_mem_end;
372
373         if (reserved_mem_dcache_on)
374                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
375         else
376                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
377
378         if (reserved_mem_icache_on)
379                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
380         else
381                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
382
383         for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
384                 if (!cplb_data[i].valid)
385                         continue;
386
387                 as_1m = cplb_data[i].start % SIZE_1M;
388
389                 /* We need to make sure all sections are properly 1M aligned
390                  * However between Kernel Memory and the Kernel mtd section, depending on the
391                  * rootfs size, there can be overlapping memory areas.
392                  */
393
394                 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
395 #ifdef CONFIG_MTD_UCLINUX
396                         if (i == SDRAM_RAM_MTD) {
397                                 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
398                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
399                                 else
400                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
401                         } else
402 #endif
403                                 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
404                                        cplb_data[i].name, cplb_data[i].start);
405                 }
406
407                 as = cplb_data[i].start % SIZE_4M;
408                 ae = cplb_data[i].end % SIZE_4M;
409
410                 if (as)
411                         a_start = cplb_data[i].start + (SIZE_4M - (as));
412                 else
413                         a_start = cplb_data[i].start;
414
415                 a_end = cplb_data[i].end - ae;
416
417                 for (j = INITIAL_T; j <= SWITCH_T; j++) {
418
419                         switch (j) {
420                         case INITIAL_T:
421                                 if (cplb_data[i].attr & INITIAL_T) {
422                                         t_i = &cplb.init_i;
423                                         t_d = &cplb.init_d;
424                                         process = 1;
425                                 } else
426                                         process = 0;
427                                 break;
428                         case SWITCH_T:
429                                 if (cplb_data[i].attr & SWITCH_T) {
430                                         t_i = &cplb.switch_i;
431                                         t_d = &cplb.switch_d;
432                                         process = 1;
433                                 } else
434                                         process = 0;
435                                 break;
436                         default:
437                                         process = 0;
438                                 break;
439                         }
440
441                         if (!process)
442                                 continue;
443                         if (cplb_data[i].attr & I_CPLB)
444                                 __fill_code_cplbtab(t_i, i, a_start, a_end);
445
446                         if (cplb_data[i].attr & D_CPLB)
447                                 __fill_data_cplbtab(t_d, i, a_start, a_end);
448                 }
449         }
450
451 /* close tables */
452
453         close_cplbtab(&cplb.init_i);
454         close_cplbtab(&cplb.init_d);
455
456         cplb.init_i.tab[cplb.init_i.pos] = -1;
457         cplb.init_d.tab[cplb.init_d.pos] = -1;
458         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
459         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
460
461 }
462
463 #endif
464