2 * pata_optidma.c - Opti DMA PATA for new ATA layer
4 * Alan Cox <alan@redhat.com>
6 * The Opti DMA controllers are related to the older PIO PCI controllers
7 * and indeed the VLB ones. The main differences are that the timing
8 * numbers are now based off PCI clocks not VLB and differ, and that
11 * This driver should support Viper-N+, FireStar, FireStar Plus.
13 * These devices support virtual DMA for read (aka the CS5520). Later
14 * chips support UDMA33, but only if the rest of the board logic does,
15 * so you have to get this right. We don't support the virtual DMA
16 * but we do handle UDMA.
18 * Bits that are worth knowing
19 * Most control registers are shadowed into I/O registers
20 * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
21 * Virtual DMA registers *move* between rev 0x02 and rev 0x10
22 * UDMA requires a 66MHz FSB
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/blkdev.h>
31 #include <linux/delay.h>
32 #include <scsi/scsi_host.h>
33 #include <linux/libata.h>
35 #define DRV_NAME "pata_optidma"
36 #define DRV_VERSION "0.3.2"
39 READ_REG = 0, /* index of Read cycle timing register */
40 WRITE_REG = 1, /* index of Write cycle timing register */
41 CNTRL_REG = 3, /* index of Control register */
42 STRAP_REG = 5, /* index of Strap register */
43 MISC_REG = 6 /* index of Miscellaneous register */
46 static int pci_clock; /* 0 = 33 1 = 25 */
49 * optidma_pre_reset - probe begin
51 * @deadline: deadline jiffies for the operation
53 * Set up cable type and use generic probe init
56 static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
58 struct ata_port *ap = link->ap;
59 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
60 static const struct pci_bits optidma_enable_bits = {
64 if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
67 return ata_std_prereset(link, deadline);
71 * optidma_probe_reset - probe reset
74 * Perform the ATA probe and bus reset sequence plus specific handling
75 * for this hardware. The Opti needs little handling - we have no UDMA66
76 * capability that needs cable detection. All we must do is check the port
80 static void optidma_error_handler(struct ata_port *ap)
82 ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
86 * optidma_unlock - unlock control registers
89 * Unlock the control register block for this adapter. Registers must not
90 * be unlocked in a situation where libata might look at them.
93 static void optidma_unlock(struct ata_port *ap)
95 void __iomem *regio = ap->ioaddr.cmd_addr;
97 /* These 3 unlock the control register access */
100 iowrite8(3, regio + 2);
104 * optidma_lock - issue temporary relock
107 * Re-lock the configuration register settings.
110 static void optidma_lock(struct ata_port *ap)
112 void __iomem *regio = ap->ioaddr.cmd_addr;
115 iowrite8(0x83, regio + 2);
119 * optidma_mode_setup - set mode data
124 * Called to do the DMA or PIO mode setup. Timing numbers are all
125 * pre computed to keep the code clean. There are two tables depending
126 * on the hardware clock speed.
128 * WARNING: While we do this the IDE registers vanish. If we take an
129 * IRQ here we depend on the host set locking to avoid catastrophe.
132 static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
134 struct ata_device *pair = ata_dev_pair(adev);
135 int pio = adev->pio_mode - XFER_PIO_0;
136 int dma = adev->dma_mode - XFER_MW_DMA_0;
137 void __iomem *regio = ap->ioaddr.cmd_addr;
140 /* Address table precomputed with a DCLK of 2 */
141 static const u8 addr_timing[2][5] = {
142 { 0x30, 0x20, 0x20, 0x10, 0x10 },
143 { 0x20, 0x20, 0x10, 0x10, 0x10 }
145 static const u8 data_rec_timing[2][5] = {
146 { 0x59, 0x46, 0x30, 0x20, 0x20 },
147 { 0x46, 0x32, 0x20, 0x20, 0x10 }
149 static const u8 dma_data_rec_timing[2][3] = {
150 { 0x76, 0x20, 0x20 },
154 /* Switch from IDE to control mode */
159 * As with many controllers the address setup time is shared
160 * and must suit both devices if present. FIXME: Check if we
161 * need to look at slowest of PIO/DMA mode of either device
164 if (mode >= XFER_MW_DMA_0)
167 addr = addr_timing[pci_clock][pio];
171 /* Hardware constraint */
175 pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
176 if (pair_addr > addr)
180 /* Commence primary programming sequence */
181 /* First we load the device number into the timing select */
182 iowrite8(adev->devno, regio + MISC_REG);
183 /* Now we load the data timings into read data/write data */
184 if (mode < XFER_MW_DMA_0) {
185 iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
186 iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
187 } else if (mode < XFER_UDMA_0) {
188 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
189 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
191 /* Finally we load the address setup into the misc register */
192 iowrite8(addr | adev->devno, regio + MISC_REG);
194 /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
195 iowrite8(0x85, regio + CNTRL_REG);
197 /* Switch back to IDE mode */
200 /* Note: at this point our programming is incomplete. We are
201 not supposed to program PCI 0x43 "things we hacked onto the chip"
202 until we've done both sets of PIO/DMA timings */
206 * optiplus_mode_setup - DMA setup for Firestar Plus
209 * @mode: desired mode
211 * The Firestar plus has additional UDMA functionality for UDMA0-2 and
212 * requires we do some additional work. Because the base work we must do
213 * is mostly shared we wrap the Firestar setup functionality in this
217 static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
219 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
222 int dev2 = 2 * adev->devno;
223 int unit = 2 * ap->port_no + adev->devno;
224 int udma = mode - XFER_UDMA_0;
226 pci_read_config_byte(pdev, 0x44, &udcfg);
227 if (mode <= XFER_UDMA_0) {
228 udcfg &= ~(1 << unit);
229 optidma_mode_setup(ap, adev, adev->dma_mode);
231 udcfg |= (1 << unit);
233 pci_read_config_byte(pdev, 0x45, &udslave);
234 udslave &= ~(0x03 << dev2);
235 udslave |= (udma << dev2);
236 pci_write_config_byte(pdev, 0x45, udslave);
238 udcfg &= ~(0x30 << dev2);
239 udcfg |= (udma << dev2);
242 pci_write_config_byte(pdev, 0x44, udcfg);
246 * optidma_set_pio_mode - PIO setup callback
250 * The libata core provides separate functions for handling PIO and
251 * DMA programming. The architecture of the Firestar makes it easier
252 * for us to have a common function so we provide wrappers
255 static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
257 optidma_mode_setup(ap, adev, adev->pio_mode);
261 * optidma_set_dma_mode - DMA setup callback
265 * The libata core provides separate functions for handling PIO and
266 * DMA programming. The architecture of the Firestar makes it easier
267 * for us to have a common function so we provide wrappers
270 static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
272 optidma_mode_setup(ap, adev, adev->dma_mode);
276 * optiplus_set_pio_mode - PIO setup callback
280 * The libata core provides separate functions for handling PIO and
281 * DMA programming. The architecture of the Firestar makes it easier
282 * for us to have a common function so we provide wrappers
285 static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
287 optiplus_mode_setup(ap, adev, adev->pio_mode);
291 * optiplus_set_dma_mode - DMA setup callback
295 * The libata core provides separate functions for handling PIO and
296 * DMA programming. The architecture of the Firestar makes it easier
297 * for us to have a common function so we provide wrappers
300 static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
302 optiplus_mode_setup(ap, adev, adev->dma_mode);
306 * optidma_make_bits - PCI setup helper
309 * Turn the ATA device setup into PCI configuration bits
310 * for register 0x43 and return the two bits needed.
313 static u8 optidma_make_bits43(struct ata_device *adev)
315 static const u8 bits43[5] = {
318 if (!ata_dev_enabled(adev))
321 return adev->dma_mode - XFER_MW_DMA_0;
322 return bits43[adev->pio_mode - XFER_PIO_0];
326 * optidma_set_mode - mode setup
327 * @link: link to set up
329 * Use the standard setup to tune the chipset and then finalise the
330 * configuration by writing the nibble of extra bits of data into
334 static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
336 struct ata_port *ap = link->ap;
338 int nybble = 4 * ap->port_no;
339 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
340 int rc = ata_do_set_mode(link, r_failed);
342 pci_read_config_byte(pdev, 0x43, &r);
344 r &= (0x0F << nybble);
345 r |= (optidma_make_bits43(&link->device[0]) +
346 (optidma_make_bits43(&link->device[0]) << 2)) << nybble;
347 pci_write_config_byte(pdev, 0x43, r);
352 static struct scsi_host_template optidma_sht = {
353 .module = THIS_MODULE,
355 .ioctl = ata_scsi_ioctl,
356 .queuecommand = ata_scsi_queuecmd,
357 .can_queue = ATA_DEF_QUEUE,
358 .this_id = ATA_SHT_THIS_ID,
359 .sg_tablesize = LIBATA_MAX_PRD,
360 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
361 .emulated = ATA_SHT_EMULATED,
362 .use_clustering = ATA_SHT_USE_CLUSTERING,
363 .proc_name = DRV_NAME,
364 .dma_boundary = ATA_DMA_BOUNDARY,
365 .slave_configure = ata_scsi_slave_config,
366 .slave_destroy = ata_scsi_slave_destroy,
367 .bios_param = ata_std_bios_param,
370 static struct ata_port_operations optidma_port_ops = {
371 .set_piomode = optidma_set_pio_mode,
372 .set_dmamode = optidma_set_dma_mode,
373 .mode_filter = ata_pci_default_filter,
375 .tf_load = ata_tf_load,
376 .tf_read = ata_tf_read,
377 .check_status = ata_check_status,
378 .exec_command = ata_exec_command,
379 .dev_select = ata_std_dev_select,
381 .freeze = ata_bmdma_freeze,
382 .thaw = ata_bmdma_thaw,
383 .post_internal_cmd = ata_bmdma_post_internal_cmd,
384 .error_handler = optidma_error_handler,
385 .set_mode = optidma_set_mode,
386 .cable_detect = ata_cable_40wire,
388 .bmdma_setup = ata_bmdma_setup,
389 .bmdma_start = ata_bmdma_start,
390 .bmdma_stop = ata_bmdma_stop,
391 .bmdma_status = ata_bmdma_status,
393 .qc_prep = ata_qc_prep,
394 .qc_issue = ata_qc_issue_prot,
396 .data_xfer = ata_data_xfer,
398 .irq_handler = ata_interrupt,
399 .irq_clear = ata_bmdma_irq_clear,
400 .irq_on = ata_irq_on,
402 .port_start = ata_sff_port_start,
405 static struct ata_port_operations optiplus_port_ops = {
406 .set_piomode = optiplus_set_pio_mode,
407 .set_dmamode = optiplus_set_dma_mode,
408 .mode_filter = ata_pci_default_filter,
410 .tf_load = ata_tf_load,
411 .tf_read = ata_tf_read,
412 .check_status = ata_check_status,
413 .exec_command = ata_exec_command,
414 .dev_select = ata_std_dev_select,
416 .freeze = ata_bmdma_freeze,
417 .thaw = ata_bmdma_thaw,
418 .post_internal_cmd = ata_bmdma_post_internal_cmd,
419 .error_handler = optidma_error_handler,
420 .set_mode = optidma_set_mode,
421 .cable_detect = ata_cable_40wire,
423 .bmdma_setup = ata_bmdma_setup,
424 .bmdma_start = ata_bmdma_start,
425 .bmdma_stop = ata_bmdma_stop,
426 .bmdma_status = ata_bmdma_status,
428 .qc_prep = ata_qc_prep,
429 .qc_issue = ata_qc_issue_prot,
431 .data_xfer = ata_data_xfer,
433 .irq_handler = ata_interrupt,
434 .irq_clear = ata_bmdma_irq_clear,
435 .irq_on = ata_irq_on,
437 .port_start = ata_sff_port_start,
441 * optiplus_with_udma - Look for UDMA capable setup
442 * @pdev; ATA controller
445 static int optiplus_with_udma(struct pci_dev *pdev)
450 struct pci_dev *dev1;
452 /* Find function 1 */
453 dev1 = pci_get_device(0x1045, 0xC701, NULL);
457 /* Rev must be >= 0x10 */
458 pci_read_config_byte(dev1, 0x08, &r);
461 /* Read the chipset system configuration to check our mode */
462 pci_read_config_byte(dev1, 0x5F, &r);
465 /* Must be 66Mhz sync */
466 if ((inb(ioport + 2) & 1) == 0)
469 /* Check the ATA arbitration/timing is suitable */
470 pci_read_config_byte(pdev, 0x42, &r);
471 if ((r & 0x36) != 0x36)
473 pci_read_config_byte(dev1, 0x52, &r);
474 if (r & 0x80) /* IDEDIR disabled */
477 printk(KERN_WARNING "UDMA not supported in this configuration.\n");
478 done_nomsg: /* Wrong chip revision */
483 static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
485 static const struct ata_port_info info_82c700 = {
487 .flags = ATA_FLAG_SLAVE_POSS,
490 .port_ops = &optidma_port_ops
492 static const struct ata_port_info info_82c700_udma = {
494 .flags = ATA_FLAG_SLAVE_POSS,
498 .port_ops = &optiplus_port_ops
500 const struct ata_port_info *ppi[] = { &info_82c700, NULL };
501 static int printed_version;
504 if (!printed_version++)
505 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
507 rc = pcim_enable_device(dev);
511 /* Fixed location chipset magic */
514 pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
516 if (optiplus_with_udma(dev))
517 ppi[0] = &info_82c700_udma;
519 return ata_pci_init_one(dev, ppi);
522 static const struct pci_device_id optidma[] = {
523 { PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */
528 static struct pci_driver optidma_pci_driver = {
531 .probe = optidma_init_one,
532 .remove = ata_pci_remove_one,
534 .suspend = ata_pci_device_suspend,
535 .resume = ata_pci_device_resume,
539 static int __init optidma_init(void)
541 return pci_register_driver(&optidma_pci_driver);
544 static void __exit optidma_exit(void)
546 pci_unregister_driver(&optidma_pci_driver);
549 MODULE_AUTHOR("Alan Cox");
550 MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
551 MODULE_LICENSE("GPL");
552 MODULE_DEVICE_TABLE(pci, optidma);
553 MODULE_VERSION(DRV_VERSION);
555 module_init(optidma_init);
556 module_exit(optidma_exit);