2 * This is based on both include/asm-sh/dma-mapping.h and
3 * include/asm-ppc/pci.h
5 #ifndef __ASM_PPC_DMA_MAPPING_H
6 #define __ASM_PPC_DMA_MAPPING_H
8 #include <linux/config.h>
9 /* need struct page definitions */
11 #include <asm/scatterlist.h>
14 #ifdef CONFIG_NOT_COHERENT_CACHE
16 * DMA-consistent mapping functions for PowerPCs that don't support
17 * cache snooping. These allocate/free a region of uncached mapped
18 * memory space for use with DMA devices. Alternatively, you could
19 * allocate the space "normally" and use the cache management functions
20 * to ensure it is consistent.
22 extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, int gfp);
23 extern void __dma_free_coherent(size_t size, void *vaddr);
24 extern void __dma_sync(void *vaddr, size_t size, int direction);
25 extern void __dma_sync_page(struct page *page, unsigned long offset,
26 size_t size, int direction);
27 #define dma_cache_inv(_start,_size) \
28 invalidate_dcache_range(_start, (_start + _size))
29 #define dma_cache_wback(_start,_size) \
30 clean_dcache_range(_start, (_start + _size))
31 #define dma_cache_wback_inv(_start,_size) \
32 flush_dcache_range(_start, (_start + _size))
34 #else /* ! CONFIG_NOT_COHERENT_CACHE */
36 * Cache coherent cores.
39 #define dma_cache_inv(_start,_size) do { } while (0)
40 #define dma_cache_wback(_start,_size) do { } while (0)
41 #define dma_cache_wback_inv(_start,_size) do { } while (0)
43 #define __dma_alloc_coherent(gfp, size, handle) NULL
44 #define __dma_free_coherent(size, addr) do { } while (0)
45 #define __dma_sync(addr, size, rw) do { } while (0)
46 #define __dma_sync_page(pg, off, sz, rw) do { } while (0)
48 #endif /* ! CONFIG_NOT_COHERENT_CACHE */
50 #define dma_supported(dev, mask) (1)
52 static inline int dma_set_mask(struct device *dev, u64 dma_mask)
54 if (!dev->dma_mask || !dma_supported(dev, mask))
57 *dev->dma_mask = dma_mask;
62 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
63 dma_addr_t * dma_handle, int gfp)
65 #ifdef CONFIG_NOT_COHERENT_CACHE
66 return __dma_alloc_coherent(size, dma_handle, gfp);
69 /* ignore region specifiers */
70 gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
72 if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
75 ret = (void *)__get_free_pages(gfp, get_order(size));
79 *dma_handle = virt_to_bus(ret);
87 dma_free_coherent(struct device *dev, size_t size, void *vaddr,
88 dma_addr_t dma_handle)
90 #ifdef CONFIG_NOT_COHERENT_CACHE
91 __dma_free_coherent(size, vaddr);
93 free_pages((unsigned long)vaddr, get_order(size));
97 static inline dma_addr_t
98 dma_map_single(struct device *dev, void *ptr, size_t size,
99 enum dma_data_direction direction)
101 BUG_ON(direction == DMA_NONE);
103 __dma_sync(ptr, size, direction);
105 return virt_to_bus(ptr);
109 #define dma_unmap_single(dev, addr, size, dir) do { } while (0)
111 static inline dma_addr_t
112 dma_map_page(struct device *dev, struct page *page,
113 unsigned long offset, size_t size,
114 enum dma_data_direction direction)
116 BUG_ON(direction == DMA_NONE);
118 __dma_sync_page(page, offset, size, direction);
120 return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset;
124 #define dma_unmap_page(dev, handle, size, dir) do { } while (0)
127 dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
128 enum dma_data_direction direction)
132 BUG_ON(direction == DMA_NONE);
134 for (i = 0; i < nents; i++, sg++) {
136 __dma_sync_page(sg->page, sg->offset, sg->length, direction);
137 sg->dma_address = page_to_bus(sg->page) + sg->offset;
143 /* We don't do anything here. */
144 #define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
147 dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
149 enum dma_data_direction direction)
151 BUG_ON(direction == DMA_NONE);
153 __dma_sync(bus_to_virt(dma_handle), size, direction);
157 dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
159 enum dma_data_direction direction)
161 BUG_ON(direction == DMA_NONE);
163 __dma_sync(bus_to_virt(dma_handle), size, direction);
167 dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
168 enum dma_data_direction direction)
172 BUG_ON(direction == DMA_NONE);
174 for (i = 0; i < nents; i++, sg++)
175 __dma_sync_page(sg->page, sg->offset, sg->length, direction);
179 dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
180 enum dma_data_direction direction)
184 BUG_ON(direction == DMA_NONE);
186 for (i = 0; i < nents; i++, sg++)
187 __dma_sync_page(sg->page, sg->offset, sg->length, direction);
190 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
191 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
192 #ifdef CONFIG_NOT_COHERENT_CACHE
193 #define dma_is_consistent(d) (0)
195 #define dma_is_consistent(d) (1)
198 static inline int dma_get_cache_alignment(void)
201 * Each processor family will define its own L1_CACHE_SHIFT,
202 * L1_CACHE_BYTES wraps to this, so this is always safe.
204 return L1_CACHE_BYTES;
208 dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
209 unsigned long offset, size_t size,
210 enum dma_data_direction direction)
212 /* just sync everything for now */
213 dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
217 dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
218 unsigned long offset, size_t size,
219 enum dma_data_direction direction)
221 /* just sync everything for now */
222 dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
225 static inline void dma_cache_sync(void *vaddr, size_t size,
226 enum dma_data_direction direction)
228 __dma_sync(vaddr, size, (int)direction);
231 static inline int dma_mapping_error(dma_addr_t dma_addr)
236 #endif /* __ASM_PPC_DMA_MAPPING_H */