2 * SPARC64 Huge TLB page support.
4 * Copyright (C) 2002, 2003 David S. Miller (davem@redhat.com)
7 #include <linux/config.h>
8 #include <linux/init.h>
9 #include <linux/module.h>
12 #include <linux/hugetlb.h>
13 #include <linux/pagemap.h>
14 #include <linux/smp_lock.h>
15 #include <linux/slab.h>
16 #include <linux/sysctl.h>
19 #include <asm/pgalloc.h>
21 #include <asm/tlbflush.h>
22 #include <asm/cacheflush.h>
23 #include <asm/mmu_context.h>
25 pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr)
32 pgd = pgd_offset(mm, addr);
34 pud = pud_offset(pgd, addr);
36 pmd = pmd_alloc(mm, pud, addr);
38 pte = pte_alloc_map(mm, pmd, addr);
44 pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
51 pgd = pgd_offset(mm, addr);
53 pud = pud_offset(pgd, addr);
55 pmd = pmd_offset(pud, addr);
57 pte = pte_offset_map(pmd, addr);
63 #define mk_pte_huge(entry) do { pte_val(entry) |= _PAGE_SZHUGE; } while (0)
65 void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
66 pte_t *ptep, pte_t entry)
70 for (i = 0; i < (1 << HUGETLB_PAGE_ORDER); i++) {
71 set_pte_at(mm, addr, ptep, entry);
74 pte_val(entry) += PAGE_SIZE;
78 pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
86 for (i = 0; i < (1 << HUGETLB_PAGE_ORDER); i++) {
87 pte_clear(mm, addr, ptep);
96 * This function checks for proper alignment of input addr and len parameters.
98 int is_aligned_hugepage_range(unsigned long addr, unsigned long len)
100 if (len & ~HPAGE_MASK)
102 if (addr & ~HPAGE_MASK)
107 struct page *follow_huge_addr(struct mm_struct *mm,
108 unsigned long address, int write)
110 return ERR_PTR(-EINVAL);
113 int pmd_huge(pmd_t pmd)
118 struct page *follow_huge_pmd(struct mm_struct *mm, unsigned long address,
119 pmd_t *pmd, int write)
124 static void context_reload(void *__data)
126 struct mm_struct *mm = __data;
128 if (mm == current->mm)
129 load_secondary_context(mm);
132 void hugetlb_prefault_arch_hook(struct mm_struct *mm)
134 /* On UltraSPARC-III+ and later, configure the second half of
135 * the Data-TLB for huge pages.
137 if (tlb_type == cheetah_plus) {
140 spin_lock(&ctx_alloc_lock);
141 ctx = mm->context.sparc64_ctx_val;
142 ctx &= ~CTX_PGSZ_MASK;
143 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
144 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
146 if (ctx != mm->context.sparc64_ctx_val) {
147 /* When changing the page size fields, we
148 * must perform a context flush so that no
149 * stale entries match. This flush must
150 * occur with the original context register
155 /* Reload the context register of all processors
156 * also executing in this address space.
158 mm->context.sparc64_ctx_val = ctx;
159 on_each_cpu(context_reload, mm, 0, 0);
161 spin_unlock(&ctx_alloc_lock);