1 /*****************************************************************************/
4 * head.S -- common startup code for ColdFire CPUs.
6 * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>.
9 /*****************************************************************************/
11 #include <linux/sys.h>
12 #include <linux/linkage.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/coldfire.h>
15 #include <asm/mcfcache.h>
16 #include <asm/mcfsim.h>
18 /*****************************************************************************/
21 * If we don't have a fixed memory size, then lets build in code
22 * to auto detect the DRAM size. Obviously this is the prefered
23 * method, and should work for most boards. It won't work for those
24 * that do not have their RAM starting at address 0, and it only
25 * works on SDRAM (not boards fitted with SRAM).
27 #if CONFIG_RAMSIZE != 0
29 movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */
32 #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
33 defined(CONFIG_M5249) || defined(CONFIG_M527x) || \
34 defined(CONFIG_M528x) || defined(CONFIG_M5307) || \
37 * Not all these devices have exactly the same DRAM controller,
38 * but the DCMR register is virtually identical - give or take
39 * a couple of bits. The only exception is the 5272 devices, their
40 * DRAM controller is quite different.
43 movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */
44 btst #0,%d0 /* check if region enabled */
48 addl #0x00040000,%d0 /* convert mask to size */
50 movel MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
51 btst #0,%d1 /* check if region enabled */
56 addl %d1,%d0 /* total mem size in d0 */
60 #elif defined(CONFIG_M5272)
62 movel MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
63 andil #0xfffff000,%d0 /* mask out chip select options */
64 negl %d0 /* negate bits */
67 #elif defined(CONFIG_M520x)
70 movel MCF_MBAR+MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
71 andl #0x1f, %d2 /* Get only the chip select size */
72 beq 3f /* Check if it is enabled */
73 addql #1, %d2 /* Form exponent */
75 lsll %d2, %d0 /* 2 ^ exponent */
77 movel MCF_MBAR+MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
78 andl #0x1f, %d2 /* Get only the chip select size */
79 beq 4f /* Check if it is enabled */
80 addql #1, %d2 /* Form exponent */
82 lsll %d2, %d1 /* 2 ^ exponent */
83 addl %d1, %d0 /* Total size of SDRAM in d0 */
88 #error "ERROR: I don't know how to probe your boards memory size?"
91 /*****************************************************************************/
94 * Boards and platforms can do specific early hardware setup if
95 * they need to. Most don't need this, define away if not required.
97 #ifndef PLATFORM_SETUP
98 #define PLATFORM_SETUP
101 /*****************************************************************************/
109 /*****************************************************************************/
114 * During startup we store away the RAM setup. These are not in the
115 * bss, since their values are determined and written before the bss
127 /*****************************************************************************/
132 * This is the codes first entry point. This is where it all
138 movew #0x2700, %sr /* no interrupts */
141 * Do any platform or board specific setup now. Most boards
142 * don't need anything. Those exceptions are define this in
143 * their board specific includes.
148 * Create basic memory configuration. Set VBR accordingly,
151 movel #CONFIG_VECTORBASE,%a7
152 movec %a7,%VBR /* set vectors addr */
155 movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */
158 GET_MEM_SIZE /* macro code determines size */
160 movel %d0,_ramend /* set end ram addr */
163 * Now that we know what the memory is, lets enable cache
164 * and get things moving. This is Coldfire CPU specific.
166 CACHE_ENABLE /* enable CPU cache */
169 #ifdef CONFIG_ROMFS_FS
171 * Move ROM filesystem above bss :-)
173 lea _sbss,%a0 /* get start of bss */
174 lea _ebss,%a1 /* set up destination */
175 movel %a0,%a2 /* copy of bss start */
177 movel 8(%a0),%d0 /* get size of ROMFS */
178 addql #8,%d0 /* allow for rounding */
179 andl #0xfffffffc, %d0 /* whole words */
181 addl %d0,%a0 /* copy from end */
182 addl %d0,%a1 /* copy from end */
183 movel %a1,_ramstart /* set start of ram */
186 movel -(%a0),%d0 /* copy dword */
188 cmpl %a0,%a2 /* check if at end */
191 #else /* CONFIG_ROMFS_FS */
194 #endif /* CONFIG_ROMFS_FS */
198 * Zero out the bss region.
200 lea _sbss,%a0 /* get start of bss */
201 lea _ebss,%a1 /* get end of bss */
202 clrl %d0 /* set value */
204 movel %d0,(%a0)+ /* clear each word */
205 cmpl %a0,%a1 /* check if at end */
209 * Load the current task pointer and stack.
211 lea init_thread_union,%a0
212 lea THREAD_SIZE(%a0),%sp
215 * Assember start up done, start code proper.
217 jsr start_kernel /* start Linux kernel */
220 jmp _exit /* should never get here */
222 /*****************************************************************************/