Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
[linux-2.6] / arch / arm / mach-versatile / core.c
1 /*
2  *  linux/arch/arm/mach-versatile/core.c
3  *
4  *  Copyright (C) 1999 - 2003 ARM Limited
5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21 #include <linux/config.h>
22 #include <linux/init.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27
28 #include <asm/system.h>
29 #include <asm/hardware.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <asm/leds.h>
33 #include <asm/mach-types.h>
34 #include <asm/hardware/amba.h>
35 #include <asm/hardware/amba_clcd.h>
36 #include <asm/hardware/arm_timer.h>
37 #include <asm/hardware/icst307.h>
38
39 #include <asm/mach/arch.h>
40 #include <asm/mach/flash.h>
41 #include <asm/mach/irq.h>
42 #include <asm/mach/time.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/mmc.h>
45
46 #include "core.h"
47 #include "clock.h"
48
49 /*
50  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
51  * is the (PA >> 12).
52  *
53  * Setup a VA for the Versatile Vectored Interrupt Controller.
54  */
55 #define __io_address(n)         __io(IO_ADDRESS(n))
56 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
57 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
58
59 static void vic_mask_irq(unsigned int irq)
60 {
61         irq -= IRQ_VIC_START;
62         writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
63 }
64
65 static void vic_unmask_irq(unsigned int irq)
66 {
67         irq -= IRQ_VIC_START;
68         writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
69 }
70
71 static struct irqchip vic_chip = {
72         .ack    = vic_mask_irq,
73         .mask   = vic_mask_irq,
74         .unmask = vic_unmask_irq,
75 };
76
77 static void sic_mask_irq(unsigned int irq)
78 {
79         irq -= IRQ_SIC_START;
80         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
81 }
82
83 static void sic_unmask_irq(unsigned int irq)
84 {
85         irq -= IRQ_SIC_START;
86         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
87 }
88
89 static struct irqchip sic_chip = {
90         .ack    = sic_mask_irq,
91         .mask   = sic_mask_irq,
92         .unmask = sic_unmask_irq,
93 };
94
95 static void
96 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
97 {
98         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
99
100         if (status == 0) {
101                 do_bad_IRQ(irq, desc, regs);
102                 return;
103         }
104
105         do {
106                 irq = ffs(status) - 1;
107                 status &= ~(1 << irq);
108
109                 irq += IRQ_SIC_START;
110
111                 desc = irq_desc + irq;
112                 desc_handle_irq(irq, desc, regs);
113         } while (status);
114 }
115
116 #if 1
117 #define IRQ_MMCI0A      IRQ_VICSOURCE22
118 #define IRQ_AACI        IRQ_VICSOURCE24
119 #define IRQ_ETH         IRQ_VICSOURCE25
120 #define PIC_MASK        0xFFD00000
121 #else
122 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
123 #define IRQ_AACI        IRQ_SIC_AACI
124 #define IRQ_ETH         IRQ_SIC_ETH
125 #define PIC_MASK        0
126 #endif
127
128 void __init versatile_init_irq(void)
129 {
130         unsigned int i, value;
131
132         /* Disable all interrupts initially. */
133
134         writel(0, VA_VIC_BASE + VIC_INT_SELECT);
135         writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
136         writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
137         writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
138         writel(0, VA_VIC_BASE + VIC_ITCR);
139         writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
140
141         /*
142          * Make sure we clear all existing interrupts
143          */
144         writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
145         for (i = 0; i < 19; i++) {
146                 value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
147                 writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
148         }
149
150         for (i = 0; i < 16; i++) {
151                 value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
152                 writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
153         }
154
155         writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
156
157         for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
158                 if (i != IRQ_VICSOURCE31) {
159                         set_irq_chip(i, &vic_chip);
160                         set_irq_handler(i, do_level_IRQ);
161                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
162                 }
163         }
164
165         set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
166         vic_unmask_irq(IRQ_VICSOURCE31);
167
168         /* Do second interrupt controller */
169         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
170
171         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
172                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
173                         set_irq_chip(i, &sic_chip);
174                         set_irq_handler(i, do_level_IRQ);
175                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
176                 }
177         }
178
179         /*
180          * Interrupts on secondary controller from 0 to 8 are routed to
181          * source 31 on PIC.
182          * Interrupts from 21 to 31 are routed directly to the VIC on
183          * the corresponding number on primary controller. This is controlled
184          * by setting PIC_ENABLEx.
185          */
186         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
187 }
188
189 static struct map_desc versatile_io_desc[] __initdata = {
190  { IO_ADDRESS(VERSATILE_SYS_BASE),   VERSATILE_SYS_BASE,   SZ_4K,      MT_DEVICE },
191  { IO_ADDRESS(VERSATILE_SIC_BASE),   VERSATILE_SIC_BASE,   SZ_4K,      MT_DEVICE },
192  { IO_ADDRESS(VERSATILE_VIC_BASE),   VERSATILE_VIC_BASE,   SZ_4K,      MT_DEVICE },
193  { IO_ADDRESS(VERSATILE_SCTL_BASE),  VERSATILE_SCTL_BASE,  SZ_4K * 9,  MT_DEVICE },
194 #ifdef CONFIG_MACH_VERSATILE_AB
195  { IO_ADDRESS(VERSATILE_GPIO0_BASE), VERSATILE_GPIO0_BASE, SZ_4K,      MT_DEVICE },
196  { IO_ADDRESS(VERSATILE_IB2_BASE),   VERSATILE_IB2_BASE,   SZ_64M,     MT_DEVICE },
197 #endif
198 #ifdef CONFIG_DEBUG_LL
199  { IO_ADDRESS(VERSATILE_UART0_BASE), VERSATILE_UART0_BASE, SZ_4K,      MT_DEVICE },
200 #endif
201 #ifdef CONFIG_PCI
202  { IO_ADDRESS(VERSATILE_PCI_CORE_BASE), VERSATILE_PCI_CORE_BASE, SZ_4K, MT_DEVICE },
203  { VERSATILE_PCI_VIRT_BASE,          VERSATILE_PCI_BASE,   VERSATILE_PCI_BASE_SIZE, MT_DEVICE },
204  { VERSATILE_PCI_CFG_VIRT_BASE,      VERSATILE_PCI_CFG_BASE, VERSATILE_PCI_CFG_BASE_SIZE, MT_DEVICE },
205 #if 0
206  { VERSATILE_PCI_VIRT_MEM_BASE0,     VERSATILE_PCI_MEM_BASE0, SZ_16M,  MT_DEVICE },
207  { VERSATILE_PCI_VIRT_MEM_BASE1,     VERSATILE_PCI_MEM_BASE1, SZ_16M,  MT_DEVICE },
208  { VERSATILE_PCI_VIRT_MEM_BASE2,     VERSATILE_PCI_MEM_BASE2, SZ_16M,  MT_DEVICE },
209 #endif
210 #endif
211 };
212
213 void __init versatile_map_io(void)
214 {
215         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
216 }
217
218 #define VERSATILE_REFCOUNTER    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
219
220 /*
221  * This is the Versatile sched_clock implementation.  This has
222  * a resolution of 41.7ns, and a maximum value of about 179s.
223  */
224 unsigned long long sched_clock(void)
225 {
226         unsigned long long v;
227
228         v = (unsigned long long)readl(VERSATILE_REFCOUNTER) * 125;
229         do_div(v, 3);
230
231         return v;
232 }
233
234
235 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
236
237 static int versatile_flash_init(void)
238 {
239         u32 val;
240
241         val = __raw_readl(VERSATILE_FLASHCTRL);
242         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
243         __raw_writel(val, VERSATILE_FLASHCTRL);
244
245         return 0;
246 }
247
248 static void versatile_flash_exit(void)
249 {
250         u32 val;
251
252         val = __raw_readl(VERSATILE_FLASHCTRL);
253         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
254         __raw_writel(val, VERSATILE_FLASHCTRL);
255 }
256
257 static void versatile_flash_set_vpp(int on)
258 {
259         u32 val;
260
261         val = __raw_readl(VERSATILE_FLASHCTRL);
262         if (on)
263                 val |= VERSATILE_FLASHPROG_FLVPPEN;
264         else
265                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
266         __raw_writel(val, VERSATILE_FLASHCTRL);
267 }
268
269 static struct flash_platform_data versatile_flash_data = {
270         .map_name               = "cfi_probe",
271         .width                  = 4,
272         .init                   = versatile_flash_init,
273         .exit                   = versatile_flash_exit,
274         .set_vpp                = versatile_flash_set_vpp,
275 };
276
277 static struct resource versatile_flash_resource = {
278         .start                  = VERSATILE_FLASH_BASE,
279         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE,
280         .flags                  = IORESOURCE_MEM,
281 };
282
283 static struct platform_device versatile_flash_device = {
284         .name                   = "armflash",
285         .id                     = 0,
286         .dev                    = {
287                 .platform_data  = &versatile_flash_data,
288         },
289         .num_resources          = 1,
290         .resource               = &versatile_flash_resource,
291 };
292
293 static struct resource smc91x_resources[] = {
294         [0] = {
295                 .start          = VERSATILE_ETH_BASE,
296                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
297                 .flags          = IORESOURCE_MEM,
298         },
299         [1] = {
300                 .start          = IRQ_ETH,
301                 .end            = IRQ_ETH,
302                 .flags          = IORESOURCE_IRQ,
303         },
304 };
305
306 static struct platform_device smc91x_device = {
307         .name           = "smc91x",
308         .id             = 0,
309         .num_resources  = ARRAY_SIZE(smc91x_resources),
310         .resource       = smc91x_resources,
311 };
312
313 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
314
315 unsigned int mmc_status(struct device *dev)
316 {
317         struct amba_device *adev = container_of(dev, struct amba_device, dev);
318         u32 mask;
319
320         if (adev->res.start == VERSATILE_MMCI0_BASE)
321                 mask = 1;
322         else
323                 mask = 2;
324
325         return readl(VERSATILE_SYSMCI) & mask;
326 }
327
328 static struct mmc_platform_data mmc0_plat_data = {
329         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
330         .status         = mmc_status,
331 };
332
333 /*
334  * Clock handling
335  */
336 static const struct icst307_params versatile_oscvco_params = {
337         .ref            = 24000,
338         .vco_max        = 200000,
339         .vd_min         = 4 + 8,
340         .vd_max         = 511 + 8,
341         .rd_min         = 1 + 2,
342         .rd_max         = 127 + 2,
343 };
344
345 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
346 {
347         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
348 #if defined(CONFIG_ARCH_VERSATILE_PB)
349         void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC4_OFFSET;
350 #elif defined(CONFIG_MACH_VERSATILE_AB)
351         void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSC1_OFFSET;
352 #endif
353         u32 val;
354
355         val = readl(sys_osc) & ~0x7ffff;
356         val |= vco.v | (vco.r << 9) | (vco.s << 16);
357
358         writel(0xa05f, sys_lock);
359         writel(val, sys_osc);
360         writel(0, sys_lock);
361 }
362
363 static struct clk versatile_clcd_clk = {
364         .name   = "CLCDCLK",
365         .params = &versatile_oscvco_params,
366         .setvco = versatile_oscvco_set,
367 };
368
369 /*
370  * CLCD support.
371  */
372 #define SYS_CLCD_MODE_MASK      (3 << 0)
373 #define SYS_CLCD_MODE_888       (0 << 0)
374 #define SYS_CLCD_MODE_5551      (1 << 0)
375 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
376 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
377 #define SYS_CLCD_NLCDIOON       (1 << 2)
378 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
379 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
380 #define SYS_CLCD_ID_MASK        (0x1f << 8)
381 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
382 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
383 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
384 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
385 #define SYS_CLCD_ID_VGA         (0x1f << 8)
386
387 static struct clcd_panel vga = {
388         .mode           = {
389                 .name           = "VGA",
390                 .refresh        = 60,
391                 .xres           = 640,
392                 .yres           = 480,
393                 .pixclock       = 39721,
394                 .left_margin    = 40,
395                 .right_margin   = 24,
396                 .upper_margin   = 32,
397                 .lower_margin   = 11,
398                 .hsync_len      = 96,
399                 .vsync_len      = 2,
400                 .sync           = 0,
401                 .vmode          = FB_VMODE_NONINTERLACED,
402         },
403         .width          = -1,
404         .height         = -1,
405         .tim2           = TIM2_BCD | TIM2_IPC,
406         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
407         .bpp            = 16,
408 };
409
410 static struct clcd_panel sanyo_3_8_in = {
411         .mode           = {
412                 .name           = "Sanyo QVGA",
413                 .refresh        = 116,
414                 .xres           = 320,
415                 .yres           = 240,
416                 .pixclock       = 100000,
417                 .left_margin    = 6,
418                 .right_margin   = 6,
419                 .upper_margin   = 5,
420                 .lower_margin   = 5,
421                 .hsync_len      = 6,
422                 .vsync_len      = 6,
423                 .sync           = 0,
424                 .vmode          = FB_VMODE_NONINTERLACED,
425         },
426         .width          = -1,
427         .height         = -1,
428         .tim2           = TIM2_BCD,
429         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
430         .bpp            = 16,
431 };
432
433 static struct clcd_panel sanyo_2_5_in = {
434         .mode           = {
435                 .name           = "Sanyo QVGA Portrait",
436                 .refresh        = 116,
437                 .xres           = 240,
438                 .yres           = 320,
439                 .pixclock       = 100000,
440                 .left_margin    = 20,
441                 .right_margin   = 10,
442                 .upper_margin   = 2,
443                 .lower_margin   = 2,
444                 .hsync_len      = 10,
445                 .vsync_len      = 2,
446                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
447                 .vmode          = FB_VMODE_NONINTERLACED,
448         },
449         .width          = -1,
450         .height         = -1,
451         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
452         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
453         .bpp            = 16,
454 };
455
456 static struct clcd_panel epson_2_2_in = {
457         .mode           = {
458                 .name           = "Epson QCIF",
459                 .refresh        = 390,
460                 .xres           = 176,
461                 .yres           = 220,
462                 .pixclock       = 62500,
463                 .left_margin    = 3,
464                 .right_margin   = 2,
465                 .upper_margin   = 1,
466                 .lower_margin   = 0,
467                 .hsync_len      = 3,
468                 .vsync_len      = 2,
469                 .sync           = 0,
470                 .vmode          = FB_VMODE_NONINTERLACED,
471         },
472         .width          = -1,
473         .height         = -1,
474         .tim2           = TIM2_BCD | TIM2_IPC,
475         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
476         .bpp            = 16,
477 };
478
479 /*
480  * Detect which LCD panel is connected, and return the appropriate
481  * clcd_panel structure.  Note: we do not have any information on
482  * the required timings for the 8.4in panel, so we presently assume
483  * VGA timings.
484  */
485 static struct clcd_panel *versatile_clcd_panel(void)
486 {
487         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
488         struct clcd_panel *panel = &vga;
489         u32 val;
490
491         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
492         if (val == SYS_CLCD_ID_SANYO_3_8)
493                 panel = &sanyo_3_8_in;
494         else if (val == SYS_CLCD_ID_SANYO_2_5)
495                 panel = &sanyo_2_5_in;
496         else if (val == SYS_CLCD_ID_EPSON_2_2)
497                 panel = &epson_2_2_in;
498         else if (val == SYS_CLCD_ID_VGA)
499                 panel = &vga;
500         else {
501                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
502                         val);
503                 panel = &vga;
504         }
505
506         return panel;
507 }
508
509 /*
510  * Disable all display connectors on the interface module.
511  */
512 static void versatile_clcd_disable(struct clcd_fb *fb)
513 {
514         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
515         u32 val;
516
517         val = readl(sys_clcd);
518         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
519         writel(val, sys_clcd);
520
521 #ifdef CONFIG_MACH_VERSATILE_AB
522         /*
523          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
524          */
525         if (fb->panel == &sanyo_2_5_in) {
526                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
527                 unsigned long ctrl;
528
529                 ctrl = readl(versatile_ib2_ctrl);
530                 ctrl &= ~0x01;
531                 writel(ctrl, versatile_ib2_ctrl);
532         }
533 #endif
534 }
535
536 /*
537  * Enable the relevant connector on the interface module.
538  */
539 static void versatile_clcd_enable(struct clcd_fb *fb)
540 {
541         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
542         u32 val;
543
544         val = readl(sys_clcd);
545         val &= ~SYS_CLCD_MODE_MASK;
546
547         switch (fb->fb.var.green.length) {
548         case 5:
549                 val |= SYS_CLCD_MODE_5551;
550                 break;
551         case 6:
552                 val |= SYS_CLCD_MODE_565_RLSB;
553                 break;
554         case 8:
555                 val |= SYS_CLCD_MODE_888;
556                 break;
557         }
558
559         /*
560          * Set the MUX
561          */
562         writel(val, sys_clcd);
563
564         /*
565          * And now enable the PSUs
566          */
567         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
568         writel(val, sys_clcd);
569
570 #ifdef CONFIG_MACH_VERSATILE_AB
571         /*
572          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
573          */
574         if (fb->panel == &sanyo_2_5_in) {
575                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
576                 unsigned long ctrl;
577
578                 ctrl = readl(versatile_ib2_ctrl);
579                 ctrl |= 0x01;
580                 writel(ctrl, versatile_ib2_ctrl);
581         }
582 #endif
583 }
584
585 static unsigned long framesize = SZ_1M;
586
587 static int versatile_clcd_setup(struct clcd_fb *fb)
588 {
589         dma_addr_t dma;
590
591         fb->panel               = versatile_clcd_panel();
592
593         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
594                                                     &dma, GFP_KERNEL);
595         if (!fb->fb.screen_base) {
596                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
597                 return -ENOMEM;
598         }
599
600         fb->fb.fix.smem_start   = dma;
601         fb->fb.fix.smem_len     = framesize;
602
603         return 0;
604 }
605
606 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
607 {
608         return dma_mmap_writecombine(&fb->dev->dev, vma,
609                                      fb->fb.screen_base,
610                                      fb->fb.fix.smem_start,
611                                      fb->fb.fix.smem_len);
612 }
613
614 static void versatile_clcd_remove(struct clcd_fb *fb)
615 {
616         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
617                               fb->fb.screen_base, fb->fb.fix.smem_start);
618 }
619
620 static struct clcd_board clcd_plat_data = {
621         .name           = "Versatile",
622         .check          = clcdfb_check,
623         .decode         = clcdfb_decode,
624         .disable        = versatile_clcd_disable,
625         .enable         = versatile_clcd_enable,
626         .setup          = versatile_clcd_setup,
627         .mmap           = versatile_clcd_mmap,
628         .remove         = versatile_clcd_remove,
629 };
630
631 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
632 #define AACI_DMA        { 0x80, 0x81 }
633 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
634 #define MMCI0_DMA       { 0x84, 0 }
635 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
636 #define KMI0_DMA        { 0, 0 }
637 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
638 #define KMI1_DMA        { 0, 0 }
639
640 /*
641  * These devices are connected directly to the multi-layer AHB switch
642  */
643 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
644 #define SMC_DMA         { 0, 0 }
645 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
646 #define MPMC_DMA        { 0, 0 }
647 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
648 #define CLCD_DMA        { 0, 0 }
649 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
650 #define DMAC_DMA        { 0, 0 }
651
652 /*
653  * These devices are connected via the core APB bridge
654  */
655 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
656 #define SCTL_DMA        { 0, 0 }
657 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
658 #define WATCHDOG_DMA    { 0, 0 }
659 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
660 #define GPIO0_DMA       { 0, 0 }
661 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
662 #define GPIO1_DMA       { 0, 0 }
663 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
664 #define RTC_DMA         { 0, 0 }
665
666 /*
667  * These devices are connected via the DMA APB bridge
668  */
669 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
670 #define SCI_DMA         { 7, 6 }
671 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
672 #define UART0_DMA       { 15, 14 }
673 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
674 #define UART1_DMA       { 13, 12 }
675 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
676 #define UART2_DMA       { 11, 10 }
677 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
678 #define SSP_DMA         { 9, 8 }
679
680 /* FPGA Primecells */
681 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
682 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
683 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
684 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
685
686 /* DevChip Primecells */
687 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
688 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
689 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
690 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
691 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
692 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
693 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
694 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
695 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
696 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
697 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
698 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
699 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
700 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
701
702 static struct amba_device *amba_devs[] __initdata = {
703         &dmac_device,
704         &uart0_device,
705         &uart1_device,
706         &uart2_device,
707         &smc_device,
708         &mpmc_device,
709         &clcd_device,
710         &sctl_device,
711         &wdog_device,
712         &gpio0_device,
713         &gpio1_device,
714         &rtc_device,
715         &sci0_device,
716         &ssp0_device,
717         &aaci_device,
718         &mmc0_device,
719         &kmi0_device,
720         &kmi1_device,
721 };
722
723 #ifdef CONFIG_LEDS
724 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
725
726 static void versatile_leds_event(led_event_t ledevt)
727 {
728         unsigned long flags;
729         u32 val;
730
731         local_irq_save(flags);
732         val = readl(VA_LEDS_BASE);
733
734         switch (ledevt) {
735         case led_idle_start:
736                 val = val & ~VERSATILE_SYS_LED0;
737                 break;
738
739         case led_idle_end:
740                 val = val | VERSATILE_SYS_LED0;
741                 break;
742
743         case led_timer:
744                 val = val ^ VERSATILE_SYS_LED1;
745                 break;
746
747         case led_halted:
748                 val = 0;
749                 break;
750
751         default:
752                 break;
753         }
754
755         writel(val, VA_LEDS_BASE);
756         local_irq_restore(flags);
757 }
758 #endif  /* CONFIG_LEDS */
759
760 void __init versatile_init(void)
761 {
762         int i;
763
764         clk_register(&versatile_clcd_clk);
765
766         platform_device_register(&versatile_flash_device);
767         platform_device_register(&smc91x_device);
768
769         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
770                 struct amba_device *d = amba_devs[i];
771                 amba_device_register(d, &iomem_resource);
772         }
773
774 #ifdef CONFIG_LEDS
775         leds_event = versatile_leds_event;
776 #endif
777 }
778
779 /*
780  * Where is the timer (VA)?
781  */
782 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
783 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
784 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
785 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
786 #define VA_IC_BASE               __io_address(VERSATILE_VIC_BASE) 
787
788 /*
789  * How long is the timer interval?
790  */
791 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
792 #if TIMER_INTERVAL >= 0x100000
793 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
794 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
795 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
796 #elif TIMER_INTERVAL >= 0x10000
797 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
798 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
799 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
800 #else
801 #define TIMER_RELOAD    (TIMER_INTERVAL)
802 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
803 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
804 #endif
805
806 /*
807  * Returns number of ms since last clock interrupt.  Note that interrupts
808  * will have been disabled by do_gettimeoffset()
809  */
810 static unsigned long versatile_gettimeoffset(void)
811 {
812         unsigned long ticks1, ticks2, status;
813
814         /*
815          * Get the current number of ticks.  Note that there is a race
816          * condition between us reading the timer and checking for
817          * an interrupt.  We get around this by ensuring that the
818          * counter has not reloaded between our two reads.
819          */
820         ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
821         do {
822                 ticks1 = ticks2;
823                 status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
824                 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
825         } while (ticks2 > ticks1);
826
827         /*
828          * Number of ticks since last interrupt.
829          */
830         ticks1 = TIMER_RELOAD - ticks2;
831
832         /*
833          * Interrupt pending?  If so, we've reloaded once already.
834          *
835          * FIXME: Need to check this is effectively timer 0 that expires
836          */
837         if (status & IRQMASK_TIMERINT0_1)
838                 ticks1 += TIMER_RELOAD;
839
840         /*
841          * Convert the ticks to usecs
842          */
843         return TICKS2USECS(ticks1);
844 }
845
846 /*
847  * IRQ handler for the timer
848  */
849 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
850 {
851         write_seqlock(&xtime_lock);
852
853         // ...clear the interrupt
854         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
855
856         timer_tick(regs);
857
858         write_sequnlock(&xtime_lock);
859
860         return IRQ_HANDLED;
861 }
862
863 static struct irqaction versatile_timer_irq = {
864         .name           = "Versatile Timer Tick",
865         .flags          = SA_INTERRUPT | SA_TIMER,
866         .handler        = versatile_timer_interrupt,
867 };
868
869 /*
870  * Set up timer interrupt, and return the current time in seconds.
871  */
872 static void __init versatile_timer_init(void)
873 {
874         u32 val;
875
876         /* 
877          * set clock frequency: 
878          *      VERSATILE_REFCLK is 32KHz
879          *      VERSATILE_TIMCLK is 1MHz
880          */
881         val = readl(__io_address(VERSATILE_SCTL_BASE));
882         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
883                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | 
884                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
885                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
886                __io_address(VERSATILE_SCTL_BASE));
887
888         /*
889          * Initialise to a known state (all timers off)
890          */
891         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
892         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
893         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
894         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
895
896         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
897         writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
898         writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
899                TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
900
901         /* 
902          * Make irqs happen for the system timer
903          */
904         setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
905 }
906
907 struct sys_timer versatile_timer = {
908         .init           = versatile_timer_init,
909         .offset         = versatile_gettimeoffset,
910 };