2 * RocketPort device driver for Linux
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Kernel Synchronization:
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
42 /****** Defines ******/
43 #define ROCKET_PARANOIA_CHECK
44 #define ROCKET_DISABLE_SIMUSAGE
46 #undef ROCKET_SOFT_FLOW
47 #undef ROCKET_DEBUG_OPEN
48 #undef ROCKET_DEBUG_INTR
49 #undef ROCKET_DEBUG_WRITE
50 #undef ROCKET_DEBUG_FLOW
51 #undef ROCKET_DEBUG_THROTTLE
52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53 #undef ROCKET_DEBUG_RECEIVE
54 #undef ROCKET_DEBUG_HANGUP
56 #undef ROCKET_DEBUG_IO
58 #define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
60 /****** Kernel includes ******/
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/major.h>
65 #include <linux/kernel.h>
66 #include <linux/signal.h>
67 #include <linux/slab.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/tty.h>
73 #include <linux/tty_driver.h>
74 #include <linux/tty_flip.h>
75 #include <linux/string.h>
76 #include <linux/fcntl.h>
77 #include <linux/ptrace.h>
78 #include <linux/mutex.h>
79 #include <linux/ioport.h>
80 #include <linux/delay.h>
81 #include <linux/completion.h>
82 #include <linux/wait.h>
83 #include <linux/pci.h>
84 #include <asm/uaccess.h>
85 #include <asm/atomic.h>
86 #include <linux/bitops.h>
87 #include <linux/spinlock.h>
88 #include <linux/init.h>
90 /****** RocketPort includes ******/
92 #include "rocket_int.h"
95 #define ROCKET_VERSION "2.09"
96 #define ROCKET_DATE "12-June-2003"
98 /****** RocketPort Local Variables ******/
100 static void rp_do_poll(unsigned long dummy);
102 static struct tty_driver *rocket_driver;
104 static struct rocket_version driver_version = {
105 ROCKET_VERSION, ROCKET_DATE
108 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
109 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
110 /* eg. Bit 0 indicates port 0 has xmit data, ... */
111 static atomic_t rp_num_ports_open; /* Number of serial ports open */
112 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
114 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
115 static unsigned long board2;
116 static unsigned long board3;
117 static unsigned long board4;
118 static unsigned long controller;
119 static int support_low_speed;
120 static unsigned long modem1;
121 static unsigned long modem2;
122 static unsigned long modem3;
123 static unsigned long modem4;
124 static unsigned long pc104_1[8];
125 static unsigned long pc104_2[8];
126 static unsigned long pc104_3[8];
127 static unsigned long pc104_4[8];
128 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
130 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
131 static unsigned long rcktpt_io_addr[NUM_BOARDS];
132 static int rcktpt_type[NUM_BOARDS];
133 static int is_PCI[NUM_BOARDS];
134 static rocketModel_t rocketModel[NUM_BOARDS];
135 static int max_board;
138 * The following arrays define the interrupt bits corresponding to each AIOP.
139 * These bits are different between the ISA and regular PCI boards and the
140 * Universal PCI boards.
143 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
150 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
151 UPCI_AIOP_INTR_BIT_0,
152 UPCI_AIOP_INTR_BIT_1,
153 UPCI_AIOP_INTR_BIT_2,
157 static Byte_t RData[RDATASIZE] = {
158 0x00, 0x09, 0xf6, 0x82,
159 0x02, 0x09, 0x86, 0xfb,
160 0x04, 0x09, 0x00, 0x0a,
161 0x06, 0x09, 0x01, 0x0a,
162 0x08, 0x09, 0x8a, 0x13,
163 0x0a, 0x09, 0xc5, 0x11,
164 0x0c, 0x09, 0x86, 0x85,
165 0x0e, 0x09, 0x20, 0x0a,
166 0x10, 0x09, 0x21, 0x0a,
167 0x12, 0x09, 0x41, 0xff,
168 0x14, 0x09, 0x82, 0x00,
169 0x16, 0x09, 0x82, 0x7b,
170 0x18, 0x09, 0x8a, 0x7d,
171 0x1a, 0x09, 0x88, 0x81,
172 0x1c, 0x09, 0x86, 0x7a,
173 0x1e, 0x09, 0x84, 0x81,
174 0x20, 0x09, 0x82, 0x7c,
175 0x22, 0x09, 0x0a, 0x0a
178 static Byte_t RRegData[RREGDATASIZE] = {
179 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
180 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
181 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
182 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
183 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
184 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
185 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
186 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
187 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
188 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
189 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
190 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
191 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
194 static CONTROLLER_T sController[CTL_SIZE] = {
195 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
196 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
197 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
198 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
199 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
200 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
201 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
202 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
205 static Byte_t sBitMapClrTbl[8] = {
206 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
209 static Byte_t sBitMapSetTbl[8] = {
210 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
213 static int sClockPrescale = 0x14;
216 * Line number is the ttySIx number (x), the Minor number. We
217 * assign them sequentially, starting at zero. The following
218 * array keeps track of the line number assigned to a given board/aiop/channel.
220 static unsigned char lineNumbers[MAX_RP_PORTS];
221 static unsigned long nextLineNumber;
223 /***** RocketPort Static Prototypes *********/
224 static int __init init_ISA(int i);
225 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
226 static void rp_flush_buffer(struct tty_struct *tty);
227 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
228 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
229 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
230 static void rp_start(struct tty_struct *tty);
231 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
233 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
234 static void sFlushRxFIFO(CHANNEL_T * ChP);
235 static void sFlushTxFIFO(CHANNEL_T * ChP);
236 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
237 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
238 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
239 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
240 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
241 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
242 ByteIO_t * AiopIOList, int AiopIOListSize,
243 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
244 int PeriodicOnly, int altChanRingIndicator,
246 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
247 ByteIO_t * AiopIOList, int AiopIOListSize,
248 int IRQNum, Byte_t Frequency, int PeriodicOnly);
249 static int sReadAiopID(ByteIO_t io);
250 static int sReadAiopNumChan(WordIO_t io);
252 MODULE_AUTHOR("Theodore Ts'o");
253 MODULE_DESCRIPTION("Comtrol RocketPort driver");
254 module_param(board1, ulong, 0);
255 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
256 module_param(board2, ulong, 0);
257 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
258 module_param(board3, ulong, 0);
259 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
260 module_param(board4, ulong, 0);
261 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
262 module_param(controller, ulong, 0);
263 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
264 module_param(support_low_speed, bool, 0);
265 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
266 module_param(modem1, ulong, 0);
267 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
268 module_param(modem2, ulong, 0);
269 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
270 module_param(modem3, ulong, 0);
271 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
272 module_param(modem4, ulong, 0);
273 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
274 module_param_array(pc104_1, ulong, NULL, 0);
275 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
276 module_param_array(pc104_2, ulong, NULL, 0);
277 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
278 module_param_array(pc104_3, ulong, NULL, 0);
279 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
280 module_param_array(pc104_4, ulong, NULL, 0);
281 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
283 static int rp_init(void);
284 static void rp_cleanup_module(void);
286 module_init(rp_init);
287 module_exit(rp_cleanup_module);
290 MODULE_LICENSE("Dual BSD/GPL");
292 /*************************************************************************/
293 /* Module code starts here */
295 static inline int rocket_paranoia_check(struct r_port *info,
298 #ifdef ROCKET_PARANOIA_CHECK
301 if (info->magic != RPORT_MAGIC) {
302 printk(KERN_WARNING "Warning: bad magic number for rocketport "
303 "struct in %s\n", routine);
311 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
312 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
315 static void rp_do_receive(struct r_port *info,
316 struct tty_struct *tty,
317 CHANNEL_t * cp, unsigned int ChanStatus)
319 unsigned int CharNStat;
320 int ToRecv, wRecv, space;
323 ToRecv = sGetRxCnt(cp);
324 #ifdef ROCKET_DEBUG_INTR
325 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
331 * if status indicates there are errored characters in the
332 * FIFO, then enter status mode (a word in FIFO holds
333 * character and status).
335 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
336 if (!(ChanStatus & STATMODE)) {
337 #ifdef ROCKET_DEBUG_RECEIVE
338 printk(KERN_INFO "Entering STATMODE...\n");
340 ChanStatus |= STATMODE;
346 * if we previously entered status mode, then read down the
347 * FIFO one word at a time, pulling apart the character and
348 * the status. Update error counters depending on status
350 if (ChanStatus & STATMODE) {
351 #ifdef ROCKET_DEBUG_RECEIVE
352 printk(KERN_INFO "Ignore %x, read %x...\n",
353 info->ignore_status_mask, info->read_status_mask);
358 CharNStat = sInW(sGetTxRxDataIO(cp));
359 #ifdef ROCKET_DEBUG_RECEIVE
360 printk(KERN_INFO "%x...\n", CharNStat);
362 if (CharNStat & STMBREAKH)
363 CharNStat &= ~(STMFRAMEH | STMPARITYH);
364 if (CharNStat & info->ignore_status_mask) {
368 CharNStat &= info->read_status_mask;
369 if (CharNStat & STMBREAKH)
371 else if (CharNStat & STMPARITYH)
373 else if (CharNStat & STMFRAMEH)
375 else if (CharNStat & STMRCVROVRH)
379 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
384 * after we've emptied the FIFO in status mode, turn
385 * status mode back off
387 if (sGetRxCnt(cp) == 0) {
388 #ifdef ROCKET_DEBUG_RECEIVE
389 printk(KERN_INFO "Status mode off.\n");
391 sDisRxStatusMode(cp);
395 * we aren't in status mode, so read down the FIFO two
396 * characters at time by doing repeated word IO
399 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
400 if (space < ToRecv) {
401 #ifdef ROCKET_DEBUG_RECEIVE
402 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
410 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
412 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
414 /* Push the data up to the tty layer */
415 tty_flip_buffer_push(tty);
419 * Serial port transmit data function. Called from the timer polling loop as a
420 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
421 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
422 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
424 static void rp_do_transmit(struct r_port *info)
427 CHANNEL_t *cp = &info->channel;
428 struct tty_struct *tty;
431 #ifdef ROCKET_DEBUG_INTR
432 printk(KERN_DEBUG "%s\n", __func__);
437 printk(KERN_WARNING "rp: WARNING %s called with "
438 "info->tty==NULL\n", __func__);
439 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
443 spin_lock_irqsave(&info->slock, flags);
445 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
447 /* Loop sending data to FIFO until done or FIFO full */
449 if (tty->stopped || tty->hw_stopped)
451 c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
452 if (c <= 0 || info->xmit_fifo_room <= 0)
454 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
456 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
457 info->xmit_tail += c;
458 info->xmit_tail &= XMIT_BUF_SIZE - 1;
460 info->xmit_fifo_room -= c;
461 #ifdef ROCKET_DEBUG_INTR
462 printk(KERN_INFO "tx %d chars...\n", c);
466 if (info->xmit_cnt == 0)
467 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
469 if (info->xmit_cnt < WAKEUP_CHARS) {
471 #ifdef ROCKETPORT_HAVE_POLL_WAIT
472 wake_up_interruptible(&tty->poll_wait);
476 spin_unlock_irqrestore(&info->slock, flags);
478 #ifdef ROCKET_DEBUG_INTR
479 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
480 info->xmit_tail, info->xmit_fifo_room);
485 * Called when a serial port signals it has read data in it's RX FIFO.
486 * It checks what interrupts are pending and services them, including
487 * receiving serial data.
489 static void rp_handle_port(struct r_port *info)
492 struct tty_struct *tty;
493 unsigned int IntMask, ChanStatus;
498 if ((info->flags & ROCKET_INITIALIZED) == 0) {
499 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
500 "info->flags & NOT_INIT\n");
504 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
505 "info->tty==NULL\n");
511 IntMask = sGetChanIntID(cp) & info->intmask;
512 #ifdef ROCKET_DEBUG_INTR
513 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
515 ChanStatus = sGetChanStatus(cp);
516 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
517 rp_do_receive(info, tty, cp, ChanStatus);
519 if (IntMask & DELTA_CD) { /* CD change */
520 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
521 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
522 (ChanStatus & CD_ACT) ? "on" : "off");
524 if (!(ChanStatus & CD_ACT) && info->cd_status) {
525 #ifdef ROCKET_DEBUG_HANGUP
526 printk(KERN_INFO "CD drop, calling hangup.\n");
530 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
531 wake_up_interruptible(&info->open_wait);
533 #ifdef ROCKET_DEBUG_INTR
534 if (IntMask & DELTA_CTS) { /* CTS change */
535 printk(KERN_INFO "CTS change...\n");
537 if (IntMask & DELTA_DSR) { /* DSR change */
538 printk(KERN_INFO "DSR change...\n");
544 * The top level polling routine. Repeats every 1/100 HZ (10ms).
546 static void rp_do_poll(unsigned long dummy)
549 int ctrl, aiop, ch, line;
550 unsigned int xmitmask, i;
551 unsigned int CtlMask;
552 unsigned char AiopMask;
555 /* Walk through all the boards (ctrl's) */
556 for (ctrl = 0; ctrl < max_board; ctrl++) {
557 if (rcktpt_io_addr[ctrl] <= 0)
560 /* Get a ptr to the board's control struct */
561 ctlp = sCtlNumToCtlPtr(ctrl);
563 /* Get the interrupt status from the board */
565 if (ctlp->BusType == isPCI)
566 CtlMask = sPCIGetControllerIntStatus(ctlp);
569 CtlMask = sGetControllerIntStatus(ctlp);
571 /* Check if any AIOP read bits are set */
572 for (aiop = 0; CtlMask; aiop++) {
573 bit = ctlp->AiopIntrBits[aiop];
576 AiopMask = sGetAiopIntStatus(ctlp, aiop);
578 /* Check if any port read bits are set */
579 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
582 /* Get the line number (/dev/ttyRx number). */
583 /* Read the data from the port. */
584 line = GetLineNumber(ctrl, aiop, ch);
585 rp_handle_port(rp_table[line]);
591 xmitmask = xmit_flags[ctrl];
594 * xmit_flags contains bit-significant flags, indicating there is data
595 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
596 * 1, ... (32 total possible). The variable i has the aiop and ch
597 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
600 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
601 if (xmitmask & (1 << i)) {
602 aiop = (i & 0x18) >> 3;
604 line = GetLineNumber(ctrl, aiop, ch);
605 rp_do_transmit(rp_table[line]);
612 * Reset the timer so we get called at the next clock tick (10ms).
614 if (atomic_read(&rp_num_ports_open))
615 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
619 * Initializes the r_port structure for a port, as well as enabling the port on
621 * Inputs: board, aiop, chan numbers
623 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
630 /* Get the next available line number */
631 line = SetLineNumber(board, aiop, chan);
633 ctlp = sCtlNumToCtlPtr(board);
635 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
636 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
638 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
643 info->magic = RPORT_MAGIC;
649 info->closing_wait = 3000;
650 info->close_delay = 50;
651 init_waitqueue_head(&info->open_wait);
652 init_completion(&info->close_wait);
653 info->flags &= ~ROCKET_MODE_MASK;
654 switch (pc104[board][line]) {
656 info->flags |= ROCKET_MODE_RS422;
659 info->flags |= ROCKET_MODE_RS485;
663 info->flags |= ROCKET_MODE_RS232;
667 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
668 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
669 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
675 rocketMode = info->flags & ROCKET_MODE_MASK;
677 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
678 sEnRTSToggle(&info->channel);
680 sDisRTSToggle(&info->channel);
682 if (ctlp->boardType == ROCKET_TYPE_PC104) {
683 switch (rocketMode) {
684 case ROCKET_MODE_RS485:
685 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
687 case ROCKET_MODE_RS422:
688 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
690 case ROCKET_MODE_RS232:
692 if (info->flags & ROCKET_RTS_TOGGLE)
693 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
695 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
699 spin_lock_init(&info->slock);
700 mutex_init(&info->write_mtx);
701 rp_table[line] = info;
702 tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
707 * Configures a rocketport port according to its termio settings. Called from
708 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
710 static void configure_r_port(struct r_port *info,
711 struct ktermios *old_termios)
716 int bits, baud, divisor;
718 struct ktermios *t = info->tty->termios;
723 /* Byte size and parity */
724 if ((cflag & CSIZE) == CS8) {
731 if (cflag & CSTOPB) {
738 if (cflag & PARENB) {
741 if (cflag & PARODD) {
751 baud = tty_get_baud_rate(info->tty);
754 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
755 if ((divisor >= 8192 || divisor < 0) && old_termios) {
756 baud = tty_termios_baud_rate(old_termios);
759 divisor = (rp_baud_base[info->board] / baud) - 1;
761 if (divisor >= 8192 || divisor < 0) {
763 divisor = (rp_baud_base[info->board] / baud) - 1;
765 info->cps = baud / bits;
766 sSetBaud(cp, divisor);
768 /* FIXME: Should really back compute a baud rate from the divisor */
769 tty_encode_baud_rate(info->tty, baud, baud);
771 if (cflag & CRTSCTS) {
772 info->intmask |= DELTA_CTS;
775 info->intmask &= ~DELTA_CTS;
778 if (cflag & CLOCAL) {
779 info->intmask &= ~DELTA_CD;
781 spin_lock_irqsave(&info->slock, flags);
782 if (sGetChanStatus(cp) & CD_ACT)
786 info->intmask |= DELTA_CD;
787 spin_unlock_irqrestore(&info->slock, flags);
791 * Handle software flow control in the board
793 #ifdef ROCKET_SOFT_FLOW
794 if (I_IXON(info->tty)) {
795 sEnTxSoftFlowCtl(cp);
796 if (I_IXANY(info->tty)) {
801 sSetTxXONChar(cp, START_CHAR(info->tty));
802 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
804 sDisTxSoftFlowCtl(cp);
811 * Set up ignore/read mask words
813 info->read_status_mask = STMRCVROVRH | 0xFF;
814 if (I_INPCK(info->tty))
815 info->read_status_mask |= STMFRAMEH | STMPARITYH;
816 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
817 info->read_status_mask |= STMBREAKH;
820 * Characters to ignore
822 info->ignore_status_mask = 0;
823 if (I_IGNPAR(info->tty))
824 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
825 if (I_IGNBRK(info->tty)) {
826 info->ignore_status_mask |= STMBREAKH;
828 * If we're ignoring parity and break indicators,
829 * ignore overruns too. (For real raw support).
831 if (I_IGNPAR(info->tty))
832 info->ignore_status_mask |= STMRCVROVRH;
835 rocketMode = info->flags & ROCKET_MODE_MASK;
837 if ((info->flags & ROCKET_RTS_TOGGLE)
838 || (rocketMode == ROCKET_MODE_RS485))
843 sSetRTS(&info->channel);
845 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
846 switch (rocketMode) {
847 case ROCKET_MODE_RS485:
848 sSetInterfaceMode(cp, InterfaceModeRS485);
850 case ROCKET_MODE_RS422:
851 sSetInterfaceMode(cp, InterfaceModeRS422);
853 case ROCKET_MODE_RS232:
855 if (info->flags & ROCKET_RTS_TOGGLE)
856 sSetInterfaceMode(cp, InterfaceModeRS232T);
858 sSetInterfaceMode(cp, InterfaceModeRS232);
864 /* info->count is considered critical, protected by spinlocks. */
865 static int block_til_ready(struct tty_struct *tty, struct file *filp,
868 DECLARE_WAITQUEUE(wait, current);
870 int do_clocal = 0, extra_count = 0;
874 * If the device is in the middle of being closed, then block
875 * until it's done, and then try again.
877 if (tty_hung_up_p(filp))
878 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
879 if (info->flags & ROCKET_CLOSING) {
880 if (wait_for_completion_interruptible(&info->close_wait))
882 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
886 * If non-blocking mode is set, or the port is not enabled,
887 * then make the check up front and then exit.
889 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
890 info->flags |= ROCKET_NORMAL_ACTIVE;
893 if (tty->termios->c_cflag & CLOCAL)
897 * Block waiting for the carrier detect and the line to become free. While we are in
898 * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
899 * We restore it upon exit, either normal or abnormal.
902 add_wait_queue(&info->open_wait, &wait);
903 #ifdef ROCKET_DEBUG_OPEN
904 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
906 spin_lock_irqsave(&info->slock, flags);
908 #ifdef ROCKET_DISABLE_SIMUSAGE
909 info->flags |= ROCKET_NORMAL_ACTIVE;
911 if (!tty_hung_up_p(filp)) {
916 info->blocked_open++;
918 spin_unlock_irqrestore(&info->slock, flags);
921 if (tty->termios->c_cflag & CBAUD) {
922 sSetDTR(&info->channel);
923 sSetRTS(&info->channel);
925 set_current_state(TASK_INTERRUPTIBLE);
926 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
927 if (info->flags & ROCKET_HUP_NOTIFY)
930 retval = -ERESTARTSYS;
933 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
935 if (signal_pending(current)) {
936 retval = -ERESTARTSYS;
939 #ifdef ROCKET_DEBUG_OPEN
940 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
941 info->line, info->count, info->flags);
943 schedule(); /* Don't hold spinlock here, will hang PC */
945 __set_current_state(TASK_RUNNING);
946 remove_wait_queue(&info->open_wait, &wait);
948 spin_lock_irqsave(&info->slock, flags);
952 info->blocked_open--;
954 spin_unlock_irqrestore(&info->slock, flags);
956 #ifdef ROCKET_DEBUG_OPEN
957 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
958 info->line, info->count);
962 info->flags |= ROCKET_NORMAL_ACTIVE;
967 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
968 * port's r_port struct. Initializes the port hardware.
970 static int rp_open(struct tty_struct *tty, struct file *filp)
973 int line = 0, retval;
978 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
981 page = __get_free_page(GFP_KERNEL);
985 if (info->flags & ROCKET_CLOSING) {
986 retval = wait_for_completion_interruptible(&info->close_wait);
990 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
994 * We must not sleep from here until the port is marked fully in use.
999 info->xmit_buf = (unsigned char *) page;
1001 tty->driver_data = info;
1004 if (info->count++ == 0) {
1005 atomic_inc(&rp_num_ports_open);
1007 #ifdef ROCKET_DEBUG_OPEN
1008 printk(KERN_INFO "rocket mod++ = %d...\n",
1009 atomic_read(&rp_num_ports_open));
1012 #ifdef ROCKET_DEBUG_OPEN
1013 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
1017 * Info->count is now 1; so it's safe to sleep now.
1019 if ((info->flags & ROCKET_INITIALIZED) == 0) {
1020 cp = &info->channel;
1021 sSetRxTrigger(cp, TRIG_1);
1022 if (sGetChanStatus(cp) & CD_ACT)
1023 info->cd_status = 1;
1025 info->cd_status = 0;
1026 sDisRxStatusMode(cp);
1030 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1031 sSetRxTrigger(cp, TRIG_1);
1034 sDisRxStatusMode(cp);
1038 sDisTxSoftFlowCtl(cp);
1043 info->flags |= ROCKET_INITIALIZED;
1046 * Set up the tty->alt_speed kludge
1048 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1049 info->tty->alt_speed = 57600;
1050 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1051 info->tty->alt_speed = 115200;
1052 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1053 info->tty->alt_speed = 230400;
1054 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1055 info->tty->alt_speed = 460800;
1057 configure_r_port(info, NULL);
1058 if (tty->termios->c_cflag & CBAUD) {
1063 /* Starts (or resets) the maint polling loop */
1064 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1066 retval = block_til_ready(tty, filp, info);
1068 #ifdef ROCKET_DEBUG_OPEN
1069 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1077 * Exception handler that closes a serial port. info->count is considered critical.
1079 static void rp_close(struct tty_struct *tty, struct file *filp)
1081 struct r_port *info = (struct r_port *) tty->driver_data;
1082 unsigned long flags;
1086 if (rocket_paranoia_check(info, "rp_close"))
1089 #ifdef ROCKET_DEBUG_OPEN
1090 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1093 if (tty_hung_up_p(filp))
1095 spin_lock_irqsave(&info->slock, flags);
1097 if ((tty->count == 1) && (info->count != 1)) {
1099 * Uh, oh. tty->count is 1, which means that the tty
1100 * structure will be freed. Info->count should always
1101 * be one in these conditions. If it's greater than
1102 * one, we've got real problems, since it means the
1103 * serial port won't be shutdown.
1105 printk(KERN_WARNING "rp_close: bad serial port count; "
1106 "tty->count is 1, info->count is %d\n", info->count);
1109 if (--info->count < 0) {
1110 printk(KERN_WARNING "rp_close: bad serial port count for "
1111 "ttyR%d: %d\n", info->line, info->count);
1115 spin_unlock_irqrestore(&info->slock, flags);
1118 info->flags |= ROCKET_CLOSING;
1119 spin_unlock_irqrestore(&info->slock, flags);
1121 cp = &info->channel;
1124 * Notify the line discpline to only process XON/XOFF characters
1129 * If transmission was throttled by the application request,
1130 * just flush the xmit buffer.
1132 if (tty->flow_stopped)
1133 rp_flush_buffer(tty);
1136 * Wait for the transmit buffer to clear
1138 if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1139 tty_wait_until_sent(tty, info->closing_wait);
1141 * Before we drop DTR, make sure the UART transmitter
1142 * has completely drained; this is especially
1143 * important if there is a transmit FIFO!
1145 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1148 rp_wait_until_sent(tty, timeout);
1149 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1152 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1154 sDisTxSoftFlowCtl(cp);
1162 rp_flush_buffer(tty);
1164 tty_ldisc_flush(tty);
1166 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1168 if (info->blocked_open) {
1169 if (info->close_delay) {
1170 msleep_interruptible(jiffies_to_msecs(info->close_delay));
1172 wake_up_interruptible(&info->open_wait);
1174 if (info->xmit_buf) {
1175 free_page((unsigned long) info->xmit_buf);
1176 info->xmit_buf = NULL;
1179 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1181 complete_all(&info->close_wait);
1182 atomic_dec(&rp_num_ports_open);
1184 #ifdef ROCKET_DEBUG_OPEN
1185 printk(KERN_INFO "rocket mod-- = %d...\n",
1186 atomic_read(&rp_num_ports_open));
1187 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1192 static void rp_set_termios(struct tty_struct *tty,
1193 struct ktermios *old_termios)
1195 struct r_port *info = (struct r_port *) tty->driver_data;
1199 if (rocket_paranoia_check(info, "rp_set_termios"))
1202 cflag = tty->termios->c_cflag;
1205 * This driver doesn't support CS5 or CS6
1207 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1208 tty->termios->c_cflag =
1209 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1211 tty->termios->c_cflag &= ~CMSPAR;
1213 configure_r_port(info, old_termios);
1215 cp = &info->channel;
1217 /* Handle transition to B0 status */
1218 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1223 /* Handle transition away from B0 status */
1224 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1225 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1230 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1231 tty->hw_stopped = 0;
1236 static void rp_break(struct tty_struct *tty, int break_state)
1238 struct r_port *info = (struct r_port *) tty->driver_data;
1239 unsigned long flags;
1241 if (rocket_paranoia_check(info, "rp_break"))
1244 spin_lock_irqsave(&info->slock, flags);
1245 if (break_state == -1)
1246 sSendBreak(&info->channel);
1248 sClrBreak(&info->channel);
1249 spin_unlock_irqrestore(&info->slock, flags);
1253 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1254 * the UPCI boards was added, it was decided to make this a function because
1255 * the macro was getting too complicated. All cases except the first one
1256 * (UPCIRingInd) are taken directly from the original macro.
1258 static int sGetChanRI(CHANNEL_T * ChP)
1260 CONTROLLER_t *CtlP = ChP->CtlP;
1261 int ChanNum = ChP->ChanNum;
1264 if (CtlP->UPCIRingInd)
1265 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1266 else if (CtlP->AltChanRingIndicator)
1267 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1268 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1269 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1274 /********************************************************************************************/
1275 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1278 * Returns the state of the serial modem control lines. These next 2 functions
1279 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1281 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1283 struct r_port *info = (struct r_port *)tty->driver_data;
1284 unsigned int control, result, ChanStatus;
1286 ChanStatus = sGetChanStatusLo(&info->channel);
1287 control = info->channel.TxControl[3];
1288 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1289 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1290 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1291 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1292 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1293 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1299 * Sets the modem control lines
1301 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1302 unsigned int set, unsigned int clear)
1304 struct r_port *info = (struct r_port *)tty->driver_data;
1306 if (set & TIOCM_RTS)
1307 info->channel.TxControl[3] |= SET_RTS;
1308 if (set & TIOCM_DTR)
1309 info->channel.TxControl[3] |= SET_DTR;
1310 if (clear & TIOCM_RTS)
1311 info->channel.TxControl[3] &= ~SET_RTS;
1312 if (clear & TIOCM_DTR)
1313 info->channel.TxControl[3] &= ~SET_DTR;
1315 sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0]));
1319 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1321 struct rocket_config tmp;
1325 memset(&tmp, 0, sizeof (tmp));
1326 tmp.line = info->line;
1327 tmp.flags = info->flags;
1328 tmp.close_delay = info->close_delay;
1329 tmp.closing_wait = info->closing_wait;
1330 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1332 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1337 static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1339 struct rocket_config new_serial;
1341 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1344 if (!capable(CAP_SYS_ADMIN))
1346 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1348 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1349 configure_r_port(info, NULL);
1353 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1354 info->close_delay = new_serial.close_delay;
1355 info->closing_wait = new_serial.closing_wait;
1357 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1358 info->tty->alt_speed = 57600;
1359 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1360 info->tty->alt_speed = 115200;
1361 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1362 info->tty->alt_speed = 230400;
1363 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1364 info->tty->alt_speed = 460800;
1366 configure_r_port(info, NULL);
1371 * This function fills in a rocket_ports struct with information
1372 * about what boards/ports are in the system. This info is passed
1373 * to user space. See setrocket.c where the info is used to create
1374 * the /dev/ttyRx ports.
1376 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1378 struct rocket_ports tmp;
1383 memset(&tmp, 0, sizeof (tmp));
1384 tmp.tty_major = rocket_driver->major;
1386 for (board = 0; board < 4; board++) {
1387 tmp.rocketModel[board].model = rocketModel[board].model;
1388 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1389 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1390 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1391 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1393 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1398 static int reset_rm2(struct r_port *info, void __user *arg)
1402 if (copy_from_user(&reset, arg, sizeof (int)))
1407 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1408 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1411 if (info->ctlp->BusType == isISA)
1412 sModemReset(info->ctlp, info->chan, reset);
1414 sPCIModemReset(info->ctlp, info->chan, reset);
1419 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1421 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1426 /* IOCTL call handler into the driver */
1427 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1428 unsigned int cmd, unsigned long arg)
1430 struct r_port *info = (struct r_port *) tty->driver_data;
1431 void __user *argp = (void __user *)arg;
1433 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1437 case RCKP_GET_STRUCT:
1438 if (copy_to_user(argp, info, sizeof (struct r_port)))
1441 case RCKP_GET_CONFIG:
1442 return get_config(info, argp);
1443 case RCKP_SET_CONFIG:
1444 return set_config(info, argp);
1445 case RCKP_GET_PORTS:
1446 return get_ports(info, argp);
1447 case RCKP_RESET_RM2:
1448 return reset_rm2(info, argp);
1449 case RCKP_GET_VERSION:
1450 return get_version(info, argp);
1452 return -ENOIOCTLCMD;
1457 static void rp_send_xchar(struct tty_struct *tty, char ch)
1459 struct r_port *info = (struct r_port *) tty->driver_data;
1462 if (rocket_paranoia_check(info, "rp_send_xchar"))
1465 cp = &info->channel;
1467 sWriteTxPrioByte(cp, ch);
1469 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1472 static void rp_throttle(struct tty_struct *tty)
1474 struct r_port *info = (struct r_port *) tty->driver_data;
1477 #ifdef ROCKET_DEBUG_THROTTLE
1478 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1479 tty->ldisc.chars_in_buffer(tty));
1482 if (rocket_paranoia_check(info, "rp_throttle"))
1485 cp = &info->channel;
1487 rp_send_xchar(tty, STOP_CHAR(tty));
1489 sClrRTS(&info->channel);
1492 static void rp_unthrottle(struct tty_struct *tty)
1494 struct r_port *info = (struct r_port *) tty->driver_data;
1496 #ifdef ROCKET_DEBUG_THROTTLE
1497 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1498 tty->ldisc.chars_in_buffer(tty));
1501 if (rocket_paranoia_check(info, "rp_throttle"))
1504 cp = &info->channel;
1506 rp_send_xchar(tty, START_CHAR(tty));
1508 sSetRTS(&info->channel);
1512 * ------------------------------------------------------------
1513 * rp_stop() and rp_start()
1515 * This routines are called before setting or resetting tty->stopped.
1516 * They enable or disable transmitter interrupts, as necessary.
1517 * ------------------------------------------------------------
1519 static void rp_stop(struct tty_struct *tty)
1521 struct r_port *info = (struct r_port *) tty->driver_data;
1523 #ifdef ROCKET_DEBUG_FLOW
1524 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1525 info->xmit_cnt, info->xmit_fifo_room);
1528 if (rocket_paranoia_check(info, "rp_stop"))
1531 if (sGetTxCnt(&info->channel))
1532 sDisTransmit(&info->channel);
1535 static void rp_start(struct tty_struct *tty)
1537 struct r_port *info = (struct r_port *) tty->driver_data;
1539 #ifdef ROCKET_DEBUG_FLOW
1540 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1541 info->xmit_cnt, info->xmit_fifo_room);
1544 if (rocket_paranoia_check(info, "rp_stop"))
1547 sEnTransmit(&info->channel);
1548 set_bit((info->aiop * 8) + info->chan,
1549 (void *) &xmit_flags[info->board]);
1553 * rp_wait_until_sent() --- wait until the transmitter is empty
1555 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1557 struct r_port *info = (struct r_port *) tty->driver_data;
1559 unsigned long orig_jiffies;
1560 int check_time, exit_time;
1563 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1566 cp = &info->channel;
1568 orig_jiffies = jiffies;
1569 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1570 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1572 printk(KERN_INFO "cps=%d...\n", info->cps);
1575 txcnt = sGetTxCnt(cp);
1577 if (sGetChanStatusLo(cp) & TXSHRMT)
1579 check_time = (HZ / info->cps) / 5;
1581 check_time = HZ * txcnt / info->cps;
1584 exit_time = orig_jiffies + timeout - jiffies;
1587 if (exit_time < check_time)
1588 check_time = exit_time;
1590 if (check_time == 0)
1592 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1593 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1594 jiffies, check_time);
1596 msleep_interruptible(jiffies_to_msecs(check_time));
1597 if (signal_pending(current))
1600 __set_current_state(TASK_RUNNING);
1601 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1602 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1607 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1609 static void rp_hangup(struct tty_struct *tty)
1612 struct r_port *info = (struct r_port *) tty->driver_data;
1614 if (rocket_paranoia_check(info, "rp_hangup"))
1617 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1618 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1620 rp_flush_buffer(tty);
1621 if (info->flags & ROCKET_CLOSING)
1624 atomic_dec(&rp_num_ports_open);
1625 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1628 info->flags &= ~ROCKET_NORMAL_ACTIVE;
1631 cp = &info->channel;
1634 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1636 sDisTxSoftFlowCtl(cp);
1638 info->flags &= ~ROCKET_INITIALIZED;
1640 wake_up_interruptible(&info->open_wait);
1644 * Exception handler - write char routine. The RocketPort driver uses a
1645 * double-buffering strategy, with the twist that if the in-memory CPU
1646 * buffer is empty, and there's space in the transmit FIFO, the
1647 * writing routines will write directly to transmit FIFO.
1648 * Write buffer and counters protected by spinlocks
1650 static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1652 struct r_port *info = (struct r_port *) tty->driver_data;
1654 unsigned long flags;
1656 if (rocket_paranoia_check(info, "rp_put_char"))
1660 * Grab the port write mutex, locking out other processes that try to
1661 * write to this port
1663 mutex_lock(&info->write_mtx);
1665 #ifdef ROCKET_DEBUG_WRITE
1666 printk(KERN_INFO "rp_put_char %c...\n", ch);
1669 spin_lock_irqsave(&info->slock, flags);
1670 cp = &info->channel;
1672 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1673 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1675 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1676 info->xmit_buf[info->xmit_head++] = ch;
1677 info->xmit_head &= XMIT_BUF_SIZE - 1;
1679 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1681 sOutB(sGetTxRxDataIO(cp), ch);
1682 info->xmit_fifo_room--;
1684 spin_unlock_irqrestore(&info->slock, flags);
1685 mutex_unlock(&info->write_mtx);
1689 * Exception handler - write routine, called when user app writes to the device.
1690 * A per port write mutex is used to protect from another process writing to
1691 * this port at the same time. This other process could be running on the other CPU
1692 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1693 * Spinlocks protect the info xmit members.
1695 static int rp_write(struct tty_struct *tty,
1696 const unsigned char *buf, int count)
1698 struct r_port *info = (struct r_port *) tty->driver_data;
1700 const unsigned char *b;
1702 unsigned long flags;
1704 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1707 if (mutex_lock_interruptible(&info->write_mtx))
1708 return -ERESTARTSYS;
1710 #ifdef ROCKET_DEBUG_WRITE
1711 printk(KERN_INFO "rp_write %d chars...\n", count);
1713 cp = &info->channel;
1715 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1716 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1719 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1720 * into FIFO. Use the write queue for temp storage.
1722 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1723 c = min(count, info->xmit_fifo_room);
1726 /* Push data into FIFO, 2 bytes at a time */
1727 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1729 /* If there is a byte remaining, write it */
1731 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1737 spin_lock_irqsave(&info->slock, flags);
1738 info->xmit_fifo_room -= c;
1739 spin_unlock_irqrestore(&info->slock, flags);
1742 /* If count is zero, we wrote it all and are done */
1746 /* Write remaining data into the port's xmit_buf */
1748 if (info->tty == 0) /* Seemingly obligatory check... */
1751 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1756 memcpy(info->xmit_buf + info->xmit_head, b, c);
1758 spin_lock_irqsave(&info->slock, flags);
1760 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1761 info->xmit_cnt += c;
1762 spin_unlock_irqrestore(&info->slock, flags);
1769 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1770 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1773 if (info->xmit_cnt < WAKEUP_CHARS) {
1775 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1776 wake_up_interruptible(&tty->poll_wait);
1779 mutex_unlock(&info->write_mtx);
1784 * Return the number of characters that can be sent. We estimate
1785 * only using the in-memory transmit buffer only, and ignore the
1786 * potential space in the transmit FIFO.
1788 static int rp_write_room(struct tty_struct *tty)
1790 struct r_port *info = (struct r_port *) tty->driver_data;
1793 if (rocket_paranoia_check(info, "rp_write_room"))
1796 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1799 #ifdef ROCKET_DEBUG_WRITE
1800 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1806 * Return the number of characters in the buffer. Again, this only
1807 * counts those characters in the in-memory transmit buffer.
1809 static int rp_chars_in_buffer(struct tty_struct *tty)
1811 struct r_port *info = (struct r_port *) tty->driver_data;
1814 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1817 cp = &info->channel;
1819 #ifdef ROCKET_DEBUG_WRITE
1820 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1822 return info->xmit_cnt;
1826 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1827 * r_port struct for the port. Note that spinlock are used to protect info members,
1828 * do not call this function if the spinlock is already held.
1830 static void rp_flush_buffer(struct tty_struct *tty)
1832 struct r_port *info = (struct r_port *) tty->driver_data;
1834 unsigned long flags;
1836 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1839 spin_lock_irqsave(&info->slock, flags);
1840 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1841 spin_unlock_irqrestore(&info->slock, flags);
1843 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1844 wake_up_interruptible(&tty->poll_wait);
1848 cp = &info->channel;
1854 static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1855 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1858 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1861 * Called when a PCI card is found. Retrieves and stores model information,
1862 * init's aiopic and serial port hardware.
1863 * Inputs: i is the board number (0-n)
1865 static __init int register_PCI(int i, struct pci_dev *dev)
1867 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1868 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1869 char *str, *board_type;
1873 int altChanRingIndicator = 0;
1874 int ports_per_aiop = 8;
1875 WordIO_t ConfigIO = 0;
1876 ByteIO_t UPCIRingInd = 0;
1878 if (!dev || pci_enable_device(dev))
1881 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1883 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1884 rocketModel[i].loadrm2 = 0;
1885 rocketModel[i].startingPortNumber = nextLineNumber;
1887 /* Depending on the model, set up some config variables */
1888 switch (dev->device) {
1889 case PCI_DEVICE_ID_RP4QUAD:
1893 rocketModel[i].model = MODEL_RP4QUAD;
1894 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1895 rocketModel[i].numPorts = 4;
1897 case PCI_DEVICE_ID_RP8OCTA:
1900 rocketModel[i].model = MODEL_RP8OCTA;
1901 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1902 rocketModel[i].numPorts = 8;
1904 case PCI_DEVICE_ID_URP8OCTA:
1907 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1908 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1909 rocketModel[i].numPorts = 8;
1911 case PCI_DEVICE_ID_RP8INTF:
1914 rocketModel[i].model = MODEL_RP8INTF;
1915 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1916 rocketModel[i].numPorts = 8;
1918 case PCI_DEVICE_ID_URP8INTF:
1921 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1922 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1923 rocketModel[i].numPorts = 8;
1925 case PCI_DEVICE_ID_RP8J:
1928 rocketModel[i].model = MODEL_RP8J;
1929 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1930 rocketModel[i].numPorts = 8;
1932 case PCI_DEVICE_ID_RP4J:
1936 rocketModel[i].model = MODEL_RP4J;
1937 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1938 rocketModel[i].numPorts = 4;
1940 case PCI_DEVICE_ID_RP8SNI:
1941 str = "8 (DB78 Custom)";
1943 rocketModel[i].model = MODEL_RP8SNI;
1944 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1945 rocketModel[i].numPorts = 8;
1947 case PCI_DEVICE_ID_RP16SNI:
1948 str = "16 (DB78 Custom)";
1950 rocketModel[i].model = MODEL_RP16SNI;
1951 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1952 rocketModel[i].numPorts = 16;
1954 case PCI_DEVICE_ID_RP16INTF:
1957 rocketModel[i].model = MODEL_RP16INTF;
1958 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1959 rocketModel[i].numPorts = 16;
1961 case PCI_DEVICE_ID_URP16INTF:
1964 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1965 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1966 rocketModel[i].numPorts = 16;
1968 case PCI_DEVICE_ID_CRP16INTF:
1971 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1972 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1973 rocketModel[i].numPorts = 16;
1975 case PCI_DEVICE_ID_RP32INTF:
1978 rocketModel[i].model = MODEL_RP32INTF;
1979 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1980 rocketModel[i].numPorts = 32;
1982 case PCI_DEVICE_ID_URP32INTF:
1985 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1986 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1987 rocketModel[i].numPorts = 32;
1989 case PCI_DEVICE_ID_RPP4:
1990 str = "Plus Quadcable";
1993 altChanRingIndicator++;
1995 rocketModel[i].model = MODEL_RPP4;
1996 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1997 rocketModel[i].numPorts = 4;
1999 case PCI_DEVICE_ID_RPP8:
2000 str = "Plus Octacable";
2003 altChanRingIndicator++;
2005 rocketModel[i].model = MODEL_RPP8;
2006 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2007 rocketModel[i].numPorts = 8;
2009 case PCI_DEVICE_ID_RP2_232:
2010 str = "Plus 2 (RS-232)";
2013 altChanRingIndicator++;
2015 rocketModel[i].model = MODEL_RP2_232;
2016 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2017 rocketModel[i].numPorts = 2;
2019 case PCI_DEVICE_ID_RP2_422:
2020 str = "Plus 2 (RS-422)";
2023 altChanRingIndicator++;
2025 rocketModel[i].model = MODEL_RP2_422;
2026 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2027 rocketModel[i].numPorts = 2;
2029 case PCI_DEVICE_ID_RP6M:
2035 /* If revision is 1, the rocketmodem flash must be loaded.
2036 * If it is 2 it is a "socketed" version. */
2037 if (dev->revision == 1) {
2038 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2039 rocketModel[i].loadrm2 = 1;
2041 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2044 rocketModel[i].model = MODEL_RP6M;
2045 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2046 rocketModel[i].numPorts = 6;
2048 case PCI_DEVICE_ID_RP4M:
2052 if (dev->revision == 1) {
2053 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2054 rocketModel[i].loadrm2 = 1;
2056 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2059 rocketModel[i].model = MODEL_RP4M;
2060 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2061 rocketModel[i].numPorts = 4;
2064 str = "(unknown/unsupported)";
2070 * Check for UPCI boards.
2073 switch (dev->device) {
2074 case PCI_DEVICE_ID_URP32INTF:
2075 case PCI_DEVICE_ID_URP8INTF:
2076 case PCI_DEVICE_ID_URP16INTF:
2077 case PCI_DEVICE_ID_CRP16INTF:
2078 case PCI_DEVICE_ID_URP8OCTA:
2079 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2080 ConfigIO = pci_resource_start(dev, 1);
2081 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2082 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2085 * Check for octa or quad cable.
2088 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2089 PCI_GPIO_CTRL_8PORT)) {
2092 rocketModel[i].numPorts = 4;
2096 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2099 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2100 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2101 rocketModel[i].numPorts = 8;
2102 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2103 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2104 ConfigIO = pci_resource_start(dev, 1);
2105 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2107 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2110 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2111 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2112 rocketModel[i].numPorts = 4;
2113 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2114 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2115 ConfigIO = pci_resource_start(dev, 1);
2116 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2122 switch (rcktpt_type[i]) {
2123 case ROCKET_TYPE_MODEM:
2124 board_type = "RocketModem";
2126 case ROCKET_TYPE_MODEMII:
2127 board_type = "RocketModem II";
2129 case ROCKET_TYPE_MODEMIII:
2130 board_type = "RocketModem III";
2133 board_type = "RocketPort";
2138 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2139 rp_baud_base[i] = 921600;
2142 * If support_low_speed is set, use the slow clock
2143 * prescale, which supports 50 bps
2145 if (support_low_speed) {
2146 /* mod 9 (divide by 10) prescale */
2147 sClockPrescale = 0x19;
2148 rp_baud_base[i] = 230400;
2150 /* mod 4 (devide by 5) prescale */
2151 sClockPrescale = 0x14;
2152 rp_baud_base[i] = 460800;
2156 for (aiop = 0; aiop < max_num_aiops; aiop++)
2157 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2158 ctlp = sCtlNumToCtlPtr(i);
2159 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2160 for (aiop = 0; aiop < max_num_aiops; aiop++)
2161 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2163 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2164 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2165 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2166 rocketModel[i].startingPortNumber,
2167 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2169 if (num_aiops <= 0) {
2170 rcktpt_io_addr[i] = 0;
2175 /* Reset the AIOPIC, init the serial ports */
2176 for (aiop = 0; aiop < num_aiops; aiop++) {
2177 sResetAiopByNum(ctlp, aiop);
2178 num_chan = ports_per_aiop;
2179 for (chan = 0; chan < num_chan; chan++)
2180 init_r_port(i, aiop, chan, dev);
2183 /* Rocket modems must be reset */
2184 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2185 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2186 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2187 num_chan = ports_per_aiop;
2188 for (chan = 0; chan < num_chan; chan++)
2189 sPCIModemReset(ctlp, chan, 1);
2191 for (chan = 0; chan < num_chan; chan++)
2192 sPCIModemReset(ctlp, chan, 0);
2194 rmSpeakerReset(ctlp, rocketModel[i].model);
2200 * Probes for PCI cards, inits them if found
2201 * Input: board_found = number of ISA boards already found, or the
2202 * starting board number
2203 * Returns: Number of PCI boards found
2205 static int __init init_PCI(int boards_found)
2207 struct pci_dev *dev = NULL;
2210 /* Work through the PCI device list, pulling out ours */
2211 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2212 if (register_PCI(count + boards_found, dev))
2218 #endif /* CONFIG_PCI */
2221 * Probes for ISA cards
2222 * Input: i = the board number to look for
2223 * Returns: 1 if board found, 0 else
2225 static int __init init_ISA(int i)
2227 int num_aiops, num_chan = 0, total_num_chan = 0;
2229 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2233 /* If io_addr is zero, no board configured */
2234 if (rcktpt_io_addr[i] == 0)
2237 /* Reserve the IO region */
2238 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2239 printk(KERN_ERR "Unable to reserve IO region for configured "
2240 "ISA RocketPort at address 0x%lx, board not "
2241 "installed...\n", rcktpt_io_addr[i]);
2242 rcktpt_io_addr[i] = 0;
2246 ctlp = sCtlNumToCtlPtr(i);
2248 ctlp->boardType = rcktpt_type[i];
2250 switch (rcktpt_type[i]) {
2251 case ROCKET_TYPE_PC104:
2252 type_string = "(PC104)";
2254 case ROCKET_TYPE_MODEM:
2255 type_string = "(RocketModem)";
2257 case ROCKET_TYPE_MODEMII:
2258 type_string = "(RocketModem II)";
2266 * If support_low_speed is set, use the slow clock prescale,
2267 * which supports 50 bps
2269 if (support_low_speed) {
2270 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2271 rp_baud_base[i] = 230400;
2273 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2274 rp_baud_base[i] = 460800;
2277 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2278 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2280 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2282 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2283 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2284 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2287 /* If something went wrong initing the AIOP's release the ISA IO memory */
2288 if (num_aiops <= 0) {
2289 release_region(rcktpt_io_addr[i], 64);
2290 rcktpt_io_addr[i] = 0;
2294 rocketModel[i].startingPortNumber = nextLineNumber;
2296 for (aiop = 0; aiop < num_aiops; aiop++) {
2297 sResetAiopByNum(ctlp, aiop);
2298 sEnAiop(ctlp, aiop);
2299 num_chan = sGetAiopNumChan(ctlp, aiop);
2300 total_num_chan += num_chan;
2301 for (chan = 0; chan < num_chan; chan++)
2302 init_r_port(i, aiop, chan, NULL);
2305 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2306 num_chan = sGetAiopNumChan(ctlp, 0);
2307 total_num_chan = num_chan;
2308 for (chan = 0; chan < num_chan; chan++)
2309 sModemReset(ctlp, chan, 1);
2311 for (chan = 0; chan < num_chan; chan++)
2312 sModemReset(ctlp, chan, 0);
2314 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2316 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2318 rocketModel[i].numPorts = total_num_chan;
2319 rocketModel[i].model = MODEL_ISA;
2321 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2322 i, rcktpt_io_addr[i], num_aiops, type_string);
2324 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2325 rocketModel[i].modelString,
2326 rocketModel[i].startingPortNumber,
2327 rocketModel[i].startingPortNumber +
2328 rocketModel[i].numPorts - 1);
2333 static const struct tty_operations rocket_ops = {
2337 .put_char = rp_put_char,
2338 .write_room = rp_write_room,
2339 .chars_in_buffer = rp_chars_in_buffer,
2340 .flush_buffer = rp_flush_buffer,
2342 .throttle = rp_throttle,
2343 .unthrottle = rp_unthrottle,
2344 .set_termios = rp_set_termios,
2347 .hangup = rp_hangup,
2348 .break_ctl = rp_break,
2349 .send_xchar = rp_send_xchar,
2350 .wait_until_sent = rp_wait_until_sent,
2351 .tiocmget = rp_tiocmget,
2352 .tiocmset = rp_tiocmset,
2356 * The module "startup" routine; it's run when the module is loaded.
2358 static int __init rp_init(void)
2360 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2362 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2363 ROCKET_VERSION, ROCKET_DATE);
2365 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2370 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2371 * zero, use the default controller IO address of board1 + 0x40.
2374 if (controller == 0)
2375 controller = board1 + 0x40;
2377 controller = 0; /* Used as a flag, meaning no ISA boards */
2380 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2381 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2382 printk(KERN_ERR "Unable to reserve IO region for first "
2383 "configured ISA RocketPort controller 0x%lx. "
2384 "Driver exiting\n", controller);
2389 /* Store ISA variable retrieved from command line or .conf file. */
2390 rcktpt_io_addr[0] = board1;
2391 rcktpt_io_addr[1] = board2;
2392 rcktpt_io_addr[2] = board3;
2393 rcktpt_io_addr[3] = board4;
2395 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2396 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2397 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2398 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2399 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2400 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2401 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2402 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2405 * Set up the tty driver structure and then register this
2406 * driver with the tty layer.
2409 rocket_driver->owner = THIS_MODULE;
2410 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2411 rocket_driver->name = "ttyR";
2412 rocket_driver->driver_name = "Comtrol RocketPort";
2413 rocket_driver->major = TTY_ROCKET_MAJOR;
2414 rocket_driver->minor_start = 0;
2415 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2416 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2417 rocket_driver->init_termios = tty_std_termios;
2418 rocket_driver->init_termios.c_cflag =
2419 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2420 rocket_driver->init_termios.c_ispeed = 9600;
2421 rocket_driver->init_termios.c_ospeed = 9600;
2422 #ifdef ROCKET_SOFT_FLOW
2423 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2425 tty_set_operations(rocket_driver, &rocket_ops);
2427 ret = tty_register_driver(rocket_driver);
2429 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2433 #ifdef ROCKET_DEBUG_OPEN
2434 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2438 * OK, let's probe each of the controllers looking for boards. Any boards found
2439 * will be initialized here.
2441 isa_boards_found = 0;
2442 pci_boards_found = 0;
2444 for (i = 0; i < NUM_BOARDS; i++) {
2450 if (isa_boards_found < NUM_BOARDS)
2451 pci_boards_found = init_PCI(isa_boards_found);
2454 max_board = pci_boards_found + isa_boards_found;
2456 if (max_board == 0) {
2457 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2464 tty_unregister_driver(rocket_driver);
2466 put_tty_driver(rocket_driver);
2472 static void rp_cleanup_module(void)
2477 del_timer_sync(&rocket_timer);
2479 retval = tty_unregister_driver(rocket_driver);
2481 printk(KERN_ERR "Error %d while trying to unregister "
2482 "rocketport driver\n", -retval);
2484 for (i = 0; i < MAX_RP_PORTS; i++)
2486 tty_unregister_device(rocket_driver, i);
2490 put_tty_driver(rocket_driver);
2492 for (i = 0; i < NUM_BOARDS; i++) {
2493 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2495 release_region(rcktpt_io_addr[i], 64);
2498 release_region(controller, 4);
2501 /***************************************************************************
2502 Function: sInitController
2503 Purpose: Initialization of controller global registers and controller
2505 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2506 IRQNum,Frequency,PeriodicOnly)
2507 CONTROLLER_T *CtlP; Ptr to controller structure
2508 int CtlNum; Controller number
2509 ByteIO_t MudbacIO; Mudbac base I/O address.
2510 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2511 This list must be in the order the AIOPs will be found on the
2512 controller. Once an AIOP in the list is not found, it is
2513 assumed that there are no more AIOPs on the controller.
2514 int AiopIOListSize; Number of addresses in AiopIOList
2515 int IRQNum; Interrupt Request number. Can be any of the following:
2516 0: Disable global interrupts
2525 Byte_t Frequency: A flag identifying the frequency
2526 of the periodic interrupt, can be any one of the following:
2527 FREQ_DIS - periodic interrupt disabled
2528 FREQ_137HZ - 137 Hertz
2529 FREQ_69HZ - 69 Hertz
2530 FREQ_34HZ - 34 Hertz
2531 FREQ_17HZ - 17 Hertz
2534 If IRQNum is set to 0 the Frequency parameter is
2535 overidden, it is forced to a value of FREQ_DIS.
2536 int PeriodicOnly: 1 if all interrupts except the periodic
2537 interrupt are to be blocked.
2538 0 is both the periodic interrupt and
2539 other channel interrupts are allowed.
2540 If IRQNum is set to 0 the PeriodicOnly parameter is
2541 overidden, it is forced to a value of 0.
2542 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2543 initialization failed.
2546 If periodic interrupts are to be disabled but AIOP interrupts
2547 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2549 If interrupts are to be completely disabled set IRQNum to 0.
2551 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2552 invalid combination.
2554 This function performs initialization of global interrupt modes,
2555 but it does not actually enable global interrupts. To enable
2556 and disable global interrupts use functions sEnGlobalInt() and
2557 sDisGlobalInt(). Enabling of global interrupts is normally not
2558 done until all other initializations are complete.
2560 Even if interrupts are globally enabled, they must also be
2561 individually enabled for each channel that is to generate
2564 Warnings: No range checking on any of the parameters is done.
2566 No context switches are allowed while executing this function.
2568 After this function all AIOPs on the controller are disabled,
2569 they can be enabled with sEnAiop().
2571 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2572 ByteIO_t * AiopIOList, int AiopIOListSize,
2573 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2579 CtlP->AiopIntrBits = aiop_intr_bits;
2580 CtlP->AltChanRingIndicator = 0;
2581 CtlP->CtlNum = CtlNum;
2582 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2583 CtlP->BusType = isISA;
2584 CtlP->MBaseIO = MudbacIO;
2585 CtlP->MReg1IO = MudbacIO + 1;
2586 CtlP->MReg2IO = MudbacIO + 2;
2587 CtlP->MReg3IO = MudbacIO + 3;
2589 CtlP->MReg2 = 0; /* interrupt disable */
2590 CtlP->MReg3 = 0; /* no periodic interrupts */
2592 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2593 CtlP->MReg2 = 0; /* interrupt disable */
2594 CtlP->MReg3 = 0; /* no periodic interrupts */
2596 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2597 CtlP->MReg3 = Frequency; /* set frequency */
2598 if (PeriodicOnly) { /* periodic interrupt only */
2599 CtlP->MReg3 |= PERIODIC_ONLY;
2603 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2604 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2605 sControllerEOI(CtlP); /* clear EOI if warm init */
2608 for (i = done = 0; i < AiopIOListSize; i++) {
2610 CtlP->AiopIO[i] = (WordIO_t) io;
2611 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2612 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2613 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2616 sEnAiop(CtlP, i); /* enable the AIOP */
2617 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2618 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2619 done = 1; /* done looking for AIOPs */
2621 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2622 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2623 sOutB(io + _INDX_DATA, sClockPrescale);
2624 CtlP->NumAiop++; /* bump count of AIOPs */
2626 sDisAiop(CtlP, i); /* disable AIOP */
2629 if (CtlP->NumAiop == 0)
2632 return (CtlP->NumAiop);
2635 /***************************************************************************
2636 Function: sPCIInitController
2637 Purpose: Initialization of controller global registers and controller
2639 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2640 IRQNum,Frequency,PeriodicOnly)
2641 CONTROLLER_T *CtlP; Ptr to controller structure
2642 int CtlNum; Controller number
2643 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2644 This list must be in the order the AIOPs will be found on the
2645 controller. Once an AIOP in the list is not found, it is
2646 assumed that there are no more AIOPs on the controller.
2647 int AiopIOListSize; Number of addresses in AiopIOList
2648 int IRQNum; Interrupt Request number. Can be any of the following:
2649 0: Disable global interrupts
2658 Byte_t Frequency: A flag identifying the frequency
2659 of the periodic interrupt, can be any one of the following:
2660 FREQ_DIS - periodic interrupt disabled
2661 FREQ_137HZ - 137 Hertz
2662 FREQ_69HZ - 69 Hertz
2663 FREQ_34HZ - 34 Hertz
2664 FREQ_17HZ - 17 Hertz
2667 If IRQNum is set to 0 the Frequency parameter is
2668 overidden, it is forced to a value of FREQ_DIS.
2669 int PeriodicOnly: 1 if all interrupts except the periodic
2670 interrupt are to be blocked.
2671 0 is both the periodic interrupt and
2672 other channel interrupts are allowed.
2673 If IRQNum is set to 0 the PeriodicOnly parameter is
2674 overidden, it is forced to a value of 0.
2675 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2676 initialization failed.
2679 If periodic interrupts are to be disabled but AIOP interrupts
2680 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2682 If interrupts are to be completely disabled set IRQNum to 0.
2684 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2685 invalid combination.
2687 This function performs initialization of global interrupt modes,
2688 but it does not actually enable global interrupts. To enable
2689 and disable global interrupts use functions sEnGlobalInt() and
2690 sDisGlobalInt(). Enabling of global interrupts is normally not
2691 done until all other initializations are complete.
2693 Even if interrupts are globally enabled, they must also be
2694 individually enabled for each channel that is to generate
2697 Warnings: No range checking on any of the parameters is done.
2699 No context switches are allowed while executing this function.
2701 After this function all AIOPs on the controller are disabled,
2702 they can be enabled with sEnAiop().
2704 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2705 ByteIO_t * AiopIOList, int AiopIOListSize,
2706 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2707 int PeriodicOnly, int altChanRingIndicator,
2713 CtlP->AltChanRingIndicator = altChanRingIndicator;
2714 CtlP->UPCIRingInd = UPCIRingInd;
2715 CtlP->CtlNum = CtlNum;
2716 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2717 CtlP->BusType = isPCI; /* controller release 1 */
2721 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2722 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2723 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2727 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2728 CtlP->AiopIntrBits = aiop_intr_bits;
2731 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2734 for (i = 0; i < AiopIOListSize; i++) {
2736 CtlP->AiopIO[i] = (WordIO_t) io;
2737 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2739 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2740 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2741 break; /* done looking for AIOPs */
2743 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2744 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2745 sOutB(io + _INDX_DATA, sClockPrescale);
2746 CtlP->NumAiop++; /* bump count of AIOPs */
2749 if (CtlP->NumAiop == 0)
2752 return (CtlP->NumAiop);
2755 /***************************************************************************
2756 Function: sReadAiopID
2757 Purpose: Read the AIOP idenfication number directly from an AIOP.
2758 Call: sReadAiopID(io)
2759 ByteIO_t io: AIOP base I/O address
2760 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2761 is replace by an identifying number.
2762 Flag AIOPID_NULL if no valid AIOP is found
2763 Warnings: No context switches are allowed while executing this function.
2766 static int sReadAiopID(ByteIO_t io)
2768 Byte_t AiopID; /* ID byte from AIOP */
2770 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2771 sOutB(io + _CMD_REG, 0x0);
2772 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2775 else /* AIOP does not exist */
2779 /***************************************************************************
2780 Function: sReadAiopNumChan
2781 Purpose: Read the number of channels available in an AIOP directly from
2783 Call: sReadAiopNumChan(io)
2784 WordIO_t io: AIOP base I/O address
2785 Return: int: The number of channels available
2786 Comments: The number of channels is determined by write/reads from identical
2787 offsets within the SRAM address spaces for channels 0 and 4.
2788 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2789 AIOP, otherwise it is an 8 channel.
2790 Warnings: No context switches are allowed while executing this function.
2792 static int sReadAiopNumChan(WordIO_t io)
2795 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2797 /* write to chan 0 SRAM */
2798 sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0]));
2799 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2800 x = sInW(io + _INDX_DATA);
2801 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2802 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2808 /***************************************************************************
2810 Purpose: Initialization of a channel and channel structure
2811 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2812 CONTROLLER_T *CtlP; Ptr to controller structure
2813 CHANNEL_T *ChP; Ptr to channel structure
2814 int AiopNum; AIOP number within controller
2815 int ChanNum; Channel number within AIOP
2816 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2817 number exceeds number of channels available in AIOP.
2818 Comments: This function must be called before a channel can be used.
2819 Warnings: No range checking on any of the parameters is done.
2821 No context switches are allowed while executing this function.
2823 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2834 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2835 return 0; /* exceeds num chans in AIOP */
2837 /* Channel, AIOP, and controller identifiers */
2839 ChP->ChanID = CtlP->AiopID[AiopNum];
2840 ChP->AiopNum = AiopNum;
2841 ChP->ChanNum = ChanNum;
2843 /* Global direct addresses */
2844 AiopIO = CtlP->AiopIO[AiopNum];
2845 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2846 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2847 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2848 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2849 ChP->IndexData = AiopIO + _INDX_DATA;
2851 /* Channel direct addresses */
2852 ChIOOff = AiopIO + ChP->ChanNum * 2;
2853 ChP->TxRxData = ChIOOff + _TD0;
2854 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2855 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2856 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2858 /* Initialize the channel from the RData array */
2859 for (i = 0; i < RDATASIZE; i += 4) {
2861 R[1] = RData[i + 1] + 0x10 * ChanNum;
2862 R[2] = RData[i + 2];
2863 R[3] = RData[i + 3];
2864 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0]));
2868 for (i = 0; i < RREGDATASIZE; i += 4) {
2869 ChR[i] = RRegData[i];
2870 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2871 ChR[i + 2] = RRegData[i + 2];
2872 ChR[i + 3] = RRegData[i + 3];
2875 /* Indexed registers */
2876 ChOff = (Word_t) ChanNum *0x1000;
2878 if (sClockPrescale == 0x14)
2883 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2884 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2885 ChP->BaudDiv[2] = (Byte_t) brd9600;
2886 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2887 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]);
2889 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2890 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2891 ChP->TxControl[2] = 0;
2892 ChP->TxControl[3] = 0;
2893 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
2895 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2896 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2897 ChP->RxControl[2] = 0;
2898 ChP->RxControl[3] = 0;
2899 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
2901 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2902 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2903 ChP->TxEnables[2] = 0;
2904 ChP->TxEnables[3] = 0;
2905 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]);
2907 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2908 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2909 ChP->TxCompare[2] = 0;
2910 ChP->TxCompare[3] = 0;
2911 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]);
2913 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2914 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2915 ChP->TxReplace1[2] = 0;
2916 ChP->TxReplace1[3] = 0;
2917 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]);
2919 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2920 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2921 ChP->TxReplace2[2] = 0;
2922 ChP->TxReplace2[3] = 0;
2923 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]);
2925 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2926 ChP->TxFIFO = ChOff + _TX_FIFO;
2928 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2929 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2930 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2931 sOutW(ChP->IndexData, 0);
2932 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2933 ChP->RxFIFO = ChOff + _RX_FIFO;
2935 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2936 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2937 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2938 sOutW(ChP->IndexData, 0);
2939 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2940 sOutW(ChP->IndexData, 0);
2941 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2942 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2943 sOutB(ChP->IndexData, 0);
2944 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2945 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2946 sOutB(ChP->IndexData, 0);
2947 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2948 sEnRxProcessor(ChP); /* start the Rx processor */
2953 /***************************************************************************
2954 Function: sStopRxProcessor
2955 Purpose: Stop the receive processor from processing a channel.
2956 Call: sStopRxProcessor(ChP)
2957 CHANNEL_T *ChP; Ptr to channel structure
2959 Comments: The receive processor can be started again with sStartRxProcessor().
2960 This function causes the receive processor to skip over the
2961 stopped channel. It does not stop it from processing other channels.
2963 Warnings: No context switches are allowed while executing this function.
2965 Do not leave the receive processor stopped for more than one
2968 After calling this function a delay of 4 uS is required to ensure
2969 that the receive processor is no longer processing this channel.
2971 static void sStopRxProcessor(CHANNEL_T * ChP)
2979 sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]);
2982 /***************************************************************************
2983 Function: sFlushRxFIFO
2984 Purpose: Flush the Rx FIFO
2985 Call: sFlushRxFIFO(ChP)
2986 CHANNEL_T *ChP; Ptr to channel structure
2988 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2989 while it is being flushed the receive processor is stopped
2990 and the transmitter is disabled. After these operations a
2991 4 uS delay is done before clearing the pointers to allow
2992 the receive processor to stop. These items are handled inside
2994 Warnings: No context switches are allowed while executing this function.
2996 static void sFlushRxFIFO(CHANNEL_T * ChP)
2999 Byte_t Ch; /* channel number within AIOP */
3000 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
3002 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3003 return; /* don't need to flush */
3006 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
3008 sDisRxFIFO(ChP); /* disable it */
3009 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3010 sInB(ChP->IntChan); /* depends on bus i/o timing */
3012 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3013 Ch = (Byte_t) sGetChanNum(ChP);
3014 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3015 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3016 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3017 sOutW(ChP->IndexData, 0);
3018 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3019 sOutW(ChP->IndexData, 0);
3021 sEnRxFIFO(ChP); /* enable Rx FIFO */
3024 /***************************************************************************
3025 Function: sFlushTxFIFO
3026 Purpose: Flush the Tx FIFO
3027 Call: sFlushTxFIFO(ChP)
3028 CHANNEL_T *ChP; Ptr to channel structure
3030 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3031 while it is being flushed the receive processor is stopped
3032 and the transmitter is disabled. After these operations a
3033 4 uS delay is done before clearing the pointers to allow
3034 the receive processor to stop. These items are handled inside
3036 Warnings: No context switches are allowed while executing this function.
3038 static void sFlushTxFIFO(CHANNEL_T * ChP)
3041 Byte_t Ch; /* channel number within AIOP */
3042 int TxEnabled; /* 1 if transmitter enabled */
3044 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3045 return; /* don't need to flush */
3048 if (ChP->TxControl[3] & TX_ENABLE) {
3050 sDisTransmit(ChP); /* disable transmitter */
3052 sStopRxProcessor(ChP); /* stop Rx processor */
3053 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3054 sInB(ChP->IntChan); /* depends on bus i/o timing */
3055 Ch = (Byte_t) sGetChanNum(ChP);
3056 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3057 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3058 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3059 sOutW(ChP->IndexData, 0);
3061 sEnTransmit(ChP); /* enable transmitter */
3062 sStartRxProcessor(ChP); /* restart Rx processor */
3065 /***************************************************************************
3066 Function: sWriteTxPrioByte
3067 Purpose: Write a byte of priority transmit data to a channel
3068 Call: sWriteTxPrioByte(ChP,Data)
3069 CHANNEL_T *ChP; Ptr to channel structure
3070 Byte_t Data; The transmit data byte
3072 Return: int: 1 if the bytes is successfully written, otherwise 0.
3074 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3076 Warnings: No context switches are allowed while executing this function.
3078 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3080 Byte_t DWBuf[4]; /* buffer for double word writes */
3081 Word_t *WordPtr; /* must be far because Win SS != DS */
3082 register DWordIO_t IndexAddr;
3084 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3085 IndexAddr = ChP->IndexAddr;
3086 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3087 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3088 return (0); /* nothing sent */
3090 WordPtr = (Word_t *) (&DWBuf[0]);
3091 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3093 DWBuf[2] = Data; /* data byte value */
3094 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3096 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3098 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3099 DWBuf[3] = 0; /* priority buffer pointer */
3100 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3101 } else { /* write it to Tx FIFO */
3103 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3105 return (1); /* 1 byte sent */
3108 /***************************************************************************
3109 Function: sEnInterrupts
3110 Purpose: Enable one or more interrupts for a channel
3111 Call: sEnInterrupts(ChP,Flags)
3112 CHANNEL_T *ChP; Ptr to channel structure
3113 Word_t Flags: Interrupt enable flags, can be any combination
3114 of the following flags:
3115 TXINT_EN: Interrupt on Tx FIFO empty
3116 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3118 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3119 MCINT_EN: Interrupt on modem input change
3120 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3121 Interrupt Channel Register.
3123 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3124 enabled. If an interrupt enable flag is not set in Flags, that
3125 interrupt will not be changed. Interrupts can be disabled with
3126 function sDisInterrupts().
3128 This function sets the appropriate bit for the channel in the AIOP's
3129 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3130 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3132 Interrupts must also be globally enabled before channel interrupts
3133 will be passed on to the host. This is done with function
3136 In some cases it may be desirable to disable interrupts globally but
3137 enable channel interrupts. This would allow the global interrupt
3138 status register to be used to determine which AIOPs need service.
3140 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3142 Byte_t Mask; /* Interrupt Mask Register */
3144 ChP->RxControl[2] |=
3145 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3147 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3149 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3151 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3153 if (Flags & CHANINT_EN) {
3154 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3155 sOutB(ChP->IntMask, Mask);
3159 /***************************************************************************
3160 Function: sDisInterrupts
3161 Purpose: Disable one or more interrupts for a channel
3162 Call: sDisInterrupts(ChP,Flags)
3163 CHANNEL_T *ChP; Ptr to channel structure
3164 Word_t Flags: Interrupt flags, can be any combination
3165 of the following flags:
3166 TXINT_EN: Interrupt on Tx FIFO empty
3167 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3169 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3170 MCINT_EN: Interrupt on modem input change
3171 CHANINT_EN: Disable channel interrupt signal to the
3172 AIOP's Interrupt Channel Register.
3174 Comments: If an interrupt flag is set in Flags, that interrupt will be
3175 disabled. If an interrupt flag is not set in Flags, that
3176 interrupt will not be changed. Interrupts can be enabled with
3177 function sEnInterrupts().
3179 This function clears the appropriate bit for the channel in the AIOP's
3180 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3181 this channel's bit from being set in the AIOP's Interrupt Channel
3184 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3186 Byte_t Mask; /* Interrupt Mask Register */
3188 ChP->RxControl[2] &=
3189 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3190 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3191 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3192 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3194 if (Flags & CHANINT_EN) {
3195 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3196 sOutB(ChP->IntMask, Mask);
3200 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3202 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3206 * Not an official SSCI function, but how to reset RocketModems.
3209 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3214 addr = CtlP->AiopIO[0] + 0x400;
3215 val = sInB(CtlP->MReg3IO);
3216 /* if AIOP[1] is not enabled, enable it */
3217 if ((val & 2) == 0) {
3218 val = sInB(CtlP->MReg2IO);
3219 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3220 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3226 sOutB(addr + chan, 0); /* apply or remove reset */
3231 * Not an official SSCI function, but how to reset RocketModems.
3234 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3238 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3241 sOutB(addr + chan, 0); /* apply or remove reset */
3244 /* Resets the speaker controller on RocketModem II and III devices */
3245 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3249 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3250 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3251 addr = CtlP->AiopIO[0] + 0x4F;
3255 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3256 if ((model == MODEL_UPCI_RM3_8PORT)
3257 || (model == MODEL_UPCI_RM3_4PORT)) {
3258 addr = CtlP->AiopIO[0] + 0x88;
3263 /* Returns the line number given the controller (board), aiop and channel number */
3264 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3266 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3270 * Stores the line number associated with a given controller (board), aiop
3271 * and channel number.
3272 * Returns: The line number assigned
3274 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3276 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3277 return (nextLineNumber - 1);