git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39 #include <net/mac80211.h>
  40
  41 #include "iwl-fh.h"
  42 #include "iwl-3945-fh.h"
  43 #include "iwl-commands.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-3945.h"
  46 #include "iwl-eeprom.h"
  47 #include "iwl-helpers.h"
  48 #include "iwl-core.h"
  49 #include "iwl-agn-rs.h"
  50
  51 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  52         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  53                                     IWL_RATE_##r##M_IEEE,   \
  54                                     IWL_RATE_##ip##M_INDEX, \
  55                                     IWL_RATE_##in##M_INDEX, \
  56                                     IWL_RATE_##rp##M_INDEX, \
  57                                     IWL_RATE_##rn##M_INDEX, \
  58                                     IWL_RATE_##pp##M_INDEX, \
  59                                     IWL_RATE_##np##M_INDEX, \
  60                                     IWL_RATE_##r##M_INDEX_TABLE, \
  61                                     IWL_RATE_##ip##M_INDEX_TABLE }
  62
  63 /*
  64  * Parameter order:
  65  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  66  *
  67  * If there isn't a valid next or previous rate then INV is used which
  68  * maps to IWL_RATE_INVALID
  69  *
  70  */
  71 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  72         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  73         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  74         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  75         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  76         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  77         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  78         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  79         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  80         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  81         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  82         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  83         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  84 };
  85
  86 /* 1 = enable the iwl3945_disable_events() function */
  87 #define IWL_EVT_DISABLE (0)
  88 #define IWL_EVT_DISABLE_SIZE (1532/32)
  89
  90 /**
  91  * iwl3945_disable_events - Disable selected events in uCode event log
  92  *
  93  * Disable an event by writing "1"s into "disable"
  94  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  95  *   Default values of 0 enable uCode events to be logged.
  96  * Use for only special debugging.  This function is just a placeholder as-is,
  97  *   you'll need to provide the special bits! ...
  98  *   ... and set IWL_EVT_DISABLE to 1. */
  99 void iwl3945_disable_events(struct iwl_priv *priv)
 100 {
 101         int ret;
 102         int i;
 103         u32 base;               /* SRAM address of event log header */
 104         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 105         u32 array_size;         /* # of u32 entries in array */
 106         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 107                 0x00000000,     /*   31 -    0  Event id numbers */
 108                 0x00000000,     /*   63 -   32 */
 109                 0x00000000,     /*   95 -   64 */
 110                 0x00000000,     /*  127 -   96 */
 111                 0x00000000,     /*  159 -  128 */
 112                 0x00000000,     /*  191 -  160 */
 113                 0x00000000,     /*  223 -  192 */
 114                 0x00000000,     /*  255 -  224 */
 115                 0x00000000,     /*  287 -  256 */
 116                 0x00000000,     /*  319 -  288 */
 117                 0x00000000,     /*  351 -  320 */
 118                 0x00000000,     /*  383 -  352 */
 119                 0x00000000,     /*  415 -  384 */
 120                 0x00000000,     /*  447 -  416 */
 121                 0x00000000,     /*  479 -  448 */
 122                 0x00000000,     /*  511 -  480 */
 123                 0x00000000,     /*  543 -  512 */
 124                 0x00000000,     /*  575 -  544 */
 125                 0x00000000,     /*  607 -  576 */
 126                 0x00000000,     /*  639 -  608 */
 127                 0x00000000,     /*  671 -  640 */
 128                 0x00000000,     /*  703 -  672 */
 129                 0x00000000,     /*  735 -  704 */
 130                 0x00000000,     /*  767 -  736 */
 131                 0x00000000,     /*  799 -  768 */
 132                 0x00000000,     /*  831 -  800 */
 133                 0x00000000,     /*  863 -  832 */
 134                 0x00000000,     /*  895 -  864 */
 135                 0x00000000,     /*  927 -  896 */
 136                 0x00000000,     /*  959 -  928 */
 137                 0x00000000,     /*  991 -  960 */
 138                 0x00000000,     /* 1023 -  992 */
 139                 0x00000000,     /* 1055 - 1024 */
 140                 0x00000000,     /* 1087 - 1056 */
 141                 0x00000000,     /* 1119 - 1088 */
 142                 0x00000000,     /* 1151 - 1120 */
 143                 0x00000000,     /* 1183 - 1152 */
 144                 0x00000000,     /* 1215 - 1184 */
 145                 0x00000000,     /* 1247 - 1216 */
 146                 0x00000000,     /* 1279 - 1248 */
 147                 0x00000000,     /* 1311 - 1280 */
 148                 0x00000000,     /* 1343 - 1312 */
 149                 0x00000000,     /* 1375 - 1344 */
 150                 0x00000000,     /* 1407 - 1376 */
 151                 0x00000000,     /* 1439 - 1408 */
 152                 0x00000000,     /* 1471 - 1440 */
 153                 0x00000000,     /* 1503 - 1472 */
 154         };
 155
 156         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 157         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 158                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 159                 return;
 160         }
 161
 162         ret = iwl_grab_nic_access(priv);
 163         if (ret) {
 164                 IWL_WARN(priv, "Can not read from adapter at this time.\n");
 165                 return;
 166         }
 167
 168         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 169         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 170         iwl_release_nic_access(priv);
 171
 172         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 173                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 174                                disable_ptr);
 175                 ret = iwl_grab_nic_access(priv);
 176                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 177                         iwl_write_targ_mem(priv,
 178                                            disable_ptr + (i * sizeof(u32)),
 179                                            evt_disable[i]);
 180
 181                 iwl_release_nic_access(priv);
 182         } else {
 183                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 184                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 185                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 186                                disable_ptr, array_size);
 187         }
 188
 189 }
 190
 191 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 192 {
 193         int idx;
 194
 195         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
 196                 if (iwl3945_rates[idx].plcp == plcp)
 197                         return idx;
 198         return -1;
 199 }
 200
 201 #ifdef CONFIG_IWLWIFI_DEBUG
 202 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
 203
 204 static const char *iwl3945_get_tx_fail_reason(u32 status)
 205 {
 206         switch (status & TX_STATUS_MSK) {
 207         case TX_STATUS_SUCCESS:
 208                 return "SUCCESS";
 209                 TX_STATUS_ENTRY(SHORT_LIMIT);
 210                 TX_STATUS_ENTRY(LONG_LIMIT);
 211                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 212                 TX_STATUS_ENTRY(MGMNT_ABORT);
 213                 TX_STATUS_ENTRY(NEXT_FRAG);
 214                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 215                 TX_STATUS_ENTRY(DEST_PS);
 216                 TX_STATUS_ENTRY(ABORTED);
 217                 TX_STATUS_ENTRY(BT_RETRY);
 218                 TX_STATUS_ENTRY(STA_INVALID);
 219                 TX_STATUS_ENTRY(FRAG_DROPPED);
 220                 TX_STATUS_ENTRY(TID_DISABLE);
 221                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 222                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 223                 TX_STATUS_ENTRY(TX_LOCKED);
 224                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 225         }
 226
 227         return "UNKNOWN";
 228 }
 229 #else
 230 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 231 {
 232         return "";
 233 }
 234 #endif
 235
 236 /*
 237  * get ieee prev rate from rate scale table.
 238  * for A and B mode we need to overright prev
 239  * value
 240  */
 241 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 242 {
 243         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 244
 245         switch (priv->band) {
 246         case IEEE80211_BAND_5GHZ:
 247                 if (rate == IWL_RATE_12M_INDEX)
 248                         next_rate = IWL_RATE_9M_INDEX;
 249                 else if (rate == IWL_RATE_6M_INDEX)
 250                         next_rate = IWL_RATE_6M_INDEX;
 251                 break;
 252         case IEEE80211_BAND_2GHZ:
 253                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 254                     iwl_is_associated(priv)) {
 255                         if (rate == IWL_RATE_11M_INDEX)
 256                                 next_rate = IWL_RATE_5M_INDEX;
 257                 }
 258                 break;
 259
 260         default:
 261                 break;
 262         }
 263
 264         return next_rate;
 265 }
 266
 267
 268 /**
 269  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 270  *
 271  * When FW advances 'R' index, all entries between old and new 'R' index
 272  * need to be reclaimed. As result, some free space forms. If there is
 273  * enough free space (> low mark), wake the stack that feeds us.
 274  */
 275 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 276                                      int txq_id, int index)
 277 {
 278         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 279         struct iwl_queue *q = &txq->q;
 280         struct iwl_tx_info *tx_info;
 281
 282         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 283
 284         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 285                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 286
 287                 tx_info = &txq->txb[txq->q.read_ptr];
 288                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 289                 tx_info->skb[0] = NULL;
 290                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 291         }
 292
 293         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 294                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 295                         priv->mac80211_registered)
 296                 ieee80211_wake_queue(priv->hw, txq_id);
 297 }
 298
 299 /**
 300  * iwl3945_rx_reply_tx - Handle Tx response
 301  */
 302 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 303                             struct iwl_rx_mem_buffer *rxb)
 304 {
 305         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 306         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 307         int txq_id = SEQ_TO_QUEUE(sequence);
 308         int index = SEQ_TO_INDEX(sequence);
 309         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 310         struct ieee80211_tx_info *info;
 311         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 312         u32  status = le32_to_cpu(tx_resp->status);
 313         int rate_idx;
 314         int fail;
 315
 316         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 317                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 318                           "is out of range [0-%d] %d %d\n", txq_id,
 319                           index, txq->q.n_bd, txq->q.write_ptr,
 320                           txq->q.read_ptr);
 321                 return;
 322         }
 323
 324         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 325         ieee80211_tx_info_clear_status(info);
 326
 327         /* Fill the MRR chain with some info about on-chip retransmissions */
 328         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 329         if (info->band == IEEE80211_BAND_5GHZ)
 330                 rate_idx -= IWL_FIRST_OFDM_RATE;
 331
 332         fail = tx_resp->failure_frame;
 333
 334         info->status.rates[0].idx = rate_idx;
 335         info->status.rates[0].count = fail + 1; /* add final attempt */
 336
 337         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 338         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 339                                 IEEE80211_TX_STAT_ACK : 0;
 340
 341         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 342                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 343                         tx_resp->rate, tx_resp->failure_frame);
 344
 345         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 346         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 347
 348         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 349                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 350 }
 351
 352
 353
 354 /*****************************************************************************
 355  *
 356  * Intel PRO/Wireless 3945ABG/BG Network Connection
 357  *
 358  *  RX handler implementations
 359  *
 360  *****************************************************************************/
 361
 362 void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
 363 {
 364         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 365         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 366                      (int)sizeof(struct iwl3945_notif_statistics),
 367                      le32_to_cpu(pkt->len));
 368
 369         memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
 370
 371         iwl3945_led_background(priv);
 372
 373         priv->last_statistics_time = jiffies;
 374 }
 375
 376 /******************************************************************************
 377  *
 378  * Misc. internal state and helper functions
 379  *
 380  ******************************************************************************/
 381 #ifdef CONFIG_IWLWIFI_DEBUG
 382
 383 /**
 384  * iwl3945_report_frame - dump frame to syslog during debug sessions
 385  *
 386  * You may hack this function to show different aspects of received frames,
 387  * including selective frame dumps.
 388  * group100 parameter selects whether to show 1 out of 100 good frames.
 389  */
 390 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
 391                       struct iwl_rx_packet *pkt,
 392                       struct ieee80211_hdr *header, int group100)
 393 {
 394         u32 to_us;
 395         u32 print_summary = 0;
 396         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 397         u32 hundred = 0;
 398         u32 dataframe = 0;
 399         __le16 fc;
 400         u16 seq_ctl;
 401         u16 channel;
 402         u16 phy_flags;
 403         u16 length;
 404         u16 status;
 405         u16 bcn_tmr;
 406         u32 tsf_low;
 407         u64 tsf;
 408         u8 rssi;
 409         u8 agc;
 410         u16 sig_avg;
 411         u16 noise_diff;
 412         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 413         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 414         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 415         u8 *data = IWL_RX_DATA(pkt);
 416
 417         /* MAC header */
 418         fc = header->frame_control;
 419         seq_ctl = le16_to_cpu(header->seq_ctrl);
 420
 421         /* metadata */
 422         channel = le16_to_cpu(rx_hdr->channel);
 423         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 424         length = le16_to_cpu(rx_hdr->len);
 425
 426         /* end-of-frame status and timestamp */
 427         status = le32_to_cpu(rx_end->status);
 428         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 429         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 430         tsf = le64_to_cpu(rx_end->timestamp);
 431
 432         /* signal statistics */
 433         rssi = rx_stats->rssi;
 434         agc = rx_stats->agc;
 435         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 436         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 437
 438         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 439
 440         /* if data frame is to us and all is good,
 441          *   (optionally) print summary for only 1 out of every 100 */
 442         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 443             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 444                 dataframe = 1;
 445                 if (!group100)
 446                         print_summary = 1;      /* print each frame */
 447                 else if (priv->framecnt_to_us < 100) {
 448                         priv->framecnt_to_us++;
 449                         print_summary = 0;
 450                 } else {
 451                         priv->framecnt_to_us = 0;
 452                         print_summary = 1;
 453                         hundred = 1;
 454                 }
 455         } else {
 456                 /* print summary for all other frames */
 457                 print_summary = 1;
 458         }
 459
 460         if (print_summary) {
 461                 char *title;
 462                 int rate;
 463
 464                 if (hundred)
 465                         title = "100Frames";
 466                 else if (ieee80211_has_retry(fc))
 467                         title = "Retry";
 468                 else if (ieee80211_is_assoc_resp(fc))
 469                         title = "AscRsp";
 470                 else if (ieee80211_is_reassoc_resp(fc))
 471                         title = "RasRsp";
 472                 else if (ieee80211_is_probe_resp(fc)) {
 473                         title = "PrbRsp";
 474                         print_dump = 1; /* dump frame contents */
 475                 } else if (ieee80211_is_beacon(fc)) {
 476                         title = "Beacon";
 477                         print_dump = 1; /* dump frame contents */
 478                 } else if (ieee80211_is_atim(fc))
 479                         title = "ATIM";
 480                 else if (ieee80211_is_auth(fc))
 481                         title = "Auth";
 482                 else if (ieee80211_is_deauth(fc))
 483                         title = "DeAuth";
 484                 else if (ieee80211_is_disassoc(fc))
 485                         title = "DisAssoc";
 486                 else
 487                         title = "Frame";
 488
 489                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 490                 if (rate == -1)
 491                         rate = 0;
 492                 else
 493                         rate = iwl3945_rates[rate].ieee / 2;
 494
 495                 /* print frame summary.
 496                  * MAC addresses show just the last byte (for brevity),
 497                  *    but you can hack it to show more, if you'd like to. */
 498                 if (dataframe)
 499                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
 500                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
 501                                      title, le16_to_cpu(fc), header->addr1[5],
 502                                      length, rssi, channel, rate);
 503                 else {
 504                         /* src/dst addresses assume managed mode */
 505                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
 506                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 507                                      "phy=0x%02x, chnl=%d\n",
 508                                      title, le16_to_cpu(fc), header->addr1[5],
 509                                      header->addr3[5], rssi,
 510                                      tsf_low - priv->scan_start_tsf,
 511                                      phy_flags, channel);
 512                 }
 513         }
 514         if (print_dump)
 515                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
 516 }
 517
 518 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 519                       struct iwl_rx_packet *pkt,
 520                       struct ieee80211_hdr *header, int group100)
 521 {
 522         if (priv->debug_level & IWL_DL_RX)
 523                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
 524 }
 525
 526 #else
 527 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 528                       struct iwl_rx_packet *pkt,
 529                       struct ieee80211_hdr *header, int group100)
 530 {
 531 }
 532 #endif
 533
 534 /* This is necessary only for a number of statistics, see the caller. */
 535 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 536                 struct ieee80211_hdr *header)
 537 {
 538         /* Filter incoming packets to determine if they are targeted toward
 539          * this network, discarding packets coming from ourselves */
 540         switch (priv->iw_mode) {
 541         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 542                 /* packets to our IBSS update information */
 543                 return !compare_ether_addr(header->addr3, priv->bssid);
 544         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 545                 /* packets to our IBSS update information */
 546                 return !compare_ether_addr(header->addr2, priv->bssid);
 547         default:
 548                 return 1;
 549         }
 550 }
 551
 552 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 553                                    struct iwl_rx_mem_buffer *rxb,
 554                                    struct ieee80211_rx_status *stats)
 555 {
 556         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
 557 #ifdef CONFIG_IWLWIFI_LEDS
 558         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 559 #endif
 560         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 561         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 562         short len = le16_to_cpu(rx_hdr->len);
 563
 564         /* We received data from the HW, so stop the watchdog */
 565         if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
 566                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 567                 return;
 568         }
 569
 570         /* We only process data packets if the interface is open */
 571         if (unlikely(!priv->is_open)) {
 572                 IWL_DEBUG_DROP_LIMIT(priv,
 573                         "Dropping packet while interface is not open.\n");
 574                 return;
 575         }
 576
 577         skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
 578         /* Set the size of the skb to the size of the frame */
 579         skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
 580
 581         if (!iwl3945_mod_params.sw_crypto)
 582                 iwl_set_decrypted_flag(priv,
 583                                        (struct ieee80211_hdr *)rxb->skb->data,
 584                                        le32_to_cpu(rx_end->status), stats);
 585
 586 #ifdef CONFIG_IWLWIFI_LEDS
 587         if (ieee80211_is_data(hdr->frame_control))
 588                 priv->rxtxpackets += len;
 589 #endif
 590         ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
 591         rxb->skb = NULL;
 592 }
 593
 594 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 595
 596 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 597                                 struct iwl_rx_mem_buffer *rxb)
 598 {
 599         struct ieee80211_hdr *header;
 600         struct ieee80211_rx_status rx_status;
 601         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 602         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 603         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 604         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 605         int snr;
 606         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
 607         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
 608         u8 network_packet;
 609
 610         rx_status.flag = 0;
 611         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 612         rx_status.freq =
 613                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 614         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 615                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 616
 617         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 618         if (rx_status.band == IEEE80211_BAND_5GHZ)
 619                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 620
 621         rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
 622                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 623
 624         /* set the preamble flag if appropriate */
 625         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 626                 rx_status.flag |= RX_FLAG_SHORTPRE;
 627
 628         if ((unlikely(rx_stats->phy_count > 20))) {
 629                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 630                                 rx_stats->phy_count);
 631                 return;
 632         }
 633
 634         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 635             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 636                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 637                 return;
 638         }
 639
 640
 641
 642         /* Convert 3945's rssi indicator to dBm */
 643         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 644
 645         /* Set default noise value to -127 */
 646         if (priv->last_rx_noise == 0)
 647                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
 648
 649         /* 3945 provides noise info for OFDM frames only.
 650          * sig_avg and noise_diff are measured by the 3945's digital signal
 651          *   processor (DSP), and indicate linear levels of signal level and
 652          *   distortion/noise within the packet preamble after
 653          *   automatic gain control (AGC).  sig_avg should stay fairly
 654          *   constant if the radio's AGC is working well.
 655          * Since these values are linear (not dB or dBm), linear
 656          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
 657          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
 658          *   to obtain noise level in dBm.
 659          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
 660         if (rx_stats_noise_diff) {
 661                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
 662                 rx_status.noise = rx_status.signal -
 663                                         iwl3945_calc_db_from_ratio(snr);
 664                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
 665                                                          rx_status.noise);
 666
 667         /* If noise info not available, calculate signal quality indicator (%)
 668          *   using just the dBm signal level. */
 669         } else {
 670                 rx_status.noise = priv->last_rx_noise;
 671                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
 672         }
 673
 674
 675         IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
 676                         rx_status.signal, rx_status.noise, rx_status.qual,
 677                         rx_stats_sig_avg, rx_stats_noise_diff);
 678
 679         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 680
 681         network_packet = iwl3945_is_network_packet(priv, header);
 682
 683         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
 684                               network_packet ? '*' : ' ',
 685                               le16_to_cpu(rx_hdr->channel),
 686                               rx_status.signal, rx_status.signal,
 687                               rx_status.noise, rx_status.rate_idx);
 688
 689         /* Set "1" to report good data frames in groups of 100 */
 690         iwl3945_dbg_report_frame(priv, pkt, header, 1);
 691
 692         if (network_packet) {
 693                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
 694                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
 695                 priv->last_rx_rssi = rx_status.signal;
 696                 priv->last_rx_noise = rx_status.noise;
 697         }
 698
 699         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 700 }
 701
 702 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 703                                      struct iwl_tx_queue *txq,
 704                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 705 {
 706         int count;
 707         struct iwl_queue *q;
 708         struct iwl3945_tfd *tfd, *tfd_tmp;
 709
 710         q = &txq->q;
 711         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 712         tfd = &tfd_tmp[q->write_ptr];
 713
 714         if (reset)
 715                 memset(tfd, 0, sizeof(*tfd));
 716
 717         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 718
 719         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 720                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 721                           NUM_TFD_CHUNKS);
 722                 return -EINVAL;
 723         }
 724
 725         tfd->tbs[count].addr = cpu_to_le32(addr);
 726         tfd->tbs[count].len = cpu_to_le32(len);
 727
 728         count++;
 729
 730         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 731                                          TFD_CTL_PAD_SET(pad));
 732
 733         return 0;
 734 }
 735
 736 /**
 737  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 738  *
 739  * Does NOT advance any indexes
 740  */
 741 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 742 {
 743         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 744         int index = txq->q.read_ptr;
 745         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 746         struct pci_dev *dev = priv->pci_dev;
 747         int i;
 748         int counter;
 749
 750         /* classify bd */
 751         if (txq->q.id == IWL_CMD_QUEUE_NUM)
 752                 /* nothing to cleanup after for host commands */
 753                 return;
 754
 755         /* sanity check */
 756         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 757         if (counter > NUM_TFD_CHUNKS) {
 758                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 759                 /* @todo issue fatal error, it is quite serious situation */
 760                 return;
 761         }
 762
 763         /* Unmap tx_cmd */
 764         if (counter)
 765                 pci_unmap_single(dev,
 766                                 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
 767                                 pci_unmap_len(&txq->cmd[index]->meta, len),
 768                                 PCI_DMA_TODEVICE);
 769
 770         /* unmap chunks if any */
 771
 772         for (i = 1; i < counter; i++) {
 773                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 774                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 775                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 776                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 777                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 778                                 /* Can be called from interrupt context */
 779                                 dev_kfree_skb_any(skb);
 780                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 781                         }
 782                 }
 783         }
 784         return ;
 785 }
 786
 787 u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
 788 {
 789         int i, start = IWL_AP_ID;
 790         int ret = IWL_INVALID_STATION;
 791         unsigned long flags;
 792
 793         if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
 794             (priv->iw_mode == NL80211_IFTYPE_AP))
 795                 start = IWL_STA_ID;
 796
 797         if (is_broadcast_ether_addr(addr))
 798                 return priv->hw_params.bcast_sta_id;
 799
 800         spin_lock_irqsave(&priv->sta_lock, flags);
 801         for (i = start; i < priv->hw_params.max_stations; i++)
 802                 if ((priv->stations_39[i].used) &&
 803                     (!compare_ether_addr
 804                      (priv->stations_39[i].sta.sta.addr, addr))) {
 805                         ret = i;
 806                         goto out;
 807                 }
 808
 809         IWL_DEBUG_INFO(priv, "can not find STA %pM (total %d)\n",
 810                        addr, priv->num_stations);
 811  out:
 812         spin_unlock_irqrestore(&priv->sta_lock, flags);
 813         return ret;
 814 }
 815
 816 /**
 817  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 818  *
 819 */
 820 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
 821                               struct ieee80211_tx_info *info,
 822                               struct ieee80211_hdr *hdr, int sta_id, int tx_id)
 823 {
 824         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 825         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
 826         u16 rate_mask;
 827         int rate;
 828         u8 rts_retry_limit;
 829         u8 data_retry_limit;
 830         __le32 tx_flags;
 831         __le16 fc = hdr->frame_control;
 832         struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 833
 834         rate = iwl3945_rates[rate_index].plcp;
 835         tx_flags = tx->tx_flags;
 836
 837         /* We need to figure out how to get the sta->supp_rates while
 838          * in this running context */
 839         rate_mask = IWL_RATES_MASK;
 840
 841         if (tx_id >= IWL_CMD_QUEUE_NUM)
 842                 rts_retry_limit = 3;
 843         else
 844                 rts_retry_limit = 7;
 845
 846         if (ieee80211_is_probe_resp(fc)) {
 847                 data_retry_limit = 3;
 848                 if (data_retry_limit < rts_retry_limit)
 849                         rts_retry_limit = data_retry_limit;
 850         } else
 851                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 852
 853         if (priv->data_retry_limit != -1)
 854                 data_retry_limit = priv->data_retry_limit;
 855
 856         if (ieee80211_is_mgmt(fc)) {
 857                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 858                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 859                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 860                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 861                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 862                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 863                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 864                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 865                         }
 866                         break;
 867                 default:
 868                         break;
 869                 }
 870         }
 871
 872         tx->rts_retry_limit = rts_retry_limit;
 873         tx->data_retry_limit = data_retry_limit;
 874         tx->rate = rate;
 875         tx->tx_flags = tx_flags;
 876
 877         /* OFDM */
 878         tx->supp_rates[0] =
 879            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 880
 881         /* CCK */
 882         tx->supp_rates[1] = (rate_mask & 0xF);
 883
 884         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 885                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 886                        tx->rate, le32_to_cpu(tx->tx_flags),
 887                        tx->supp_rates[1], tx->supp_rates[0]);
 888 }
 889
 890 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 891 {
 892         unsigned long flags_spin;
 893         struct iwl3945_station_entry *station;
 894
 895         if (sta_id == IWL_INVALID_STATION)
 896                 return IWL_INVALID_STATION;
 897
 898         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 899         station = &priv->stations_39[sta_id];
 900
 901         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 902         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 903         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 904
 905         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 906
 907         iwl_send_add_sta(priv,
 908                          (struct iwl_addsta_cmd *)&station->sta, flags);
 909         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 910                         sta_id, tx_rate);
 911         return sta_id;
 912 }
 913
 914 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 915 {
 916         int ret;
 917         unsigned long flags;
 918
 919         spin_lock_irqsave(&priv->lock, flags);
 920         ret = iwl_grab_nic_access(priv);
 921         if (ret) {
 922                 spin_unlock_irqrestore(&priv->lock, flags);
 923                 return ret;
 924         }
 925
 926         if (src == IWL_PWR_SRC_VAUX) {
 927                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 928                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 929                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 930                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 931                         iwl_release_nic_access(priv);
 932
 933                         iwl_poll_bit(priv, CSR_GPIO_IN,
 934                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 935                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 936                 } else {
 937                         iwl_release_nic_access(priv);
 938                 }
 939         } else {
 940                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 941                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 942                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 943
 944                 iwl_release_nic_access(priv);
 945                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 946                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 947         }
 948         spin_unlock_irqrestore(&priv->lock, flags);
 949
 950         return ret;
 951 }
 952
 953 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 954 {
 955         int rc;
 956         unsigned long flags;
 957
 958         spin_lock_irqsave(&priv->lock, flags);
 959         rc = iwl_grab_nic_access(priv);
 960         if (rc) {
 961                 spin_unlock_irqrestore(&priv->lock, flags);
 962                 return rc;
 963         }
 964
 965         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 966         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 967         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 968         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 969                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 970                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 971                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 972                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 973                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 974                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 975                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 976                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 977
 978         /* fake read to flush all prev I/O */
 979         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 980
 981         iwl_release_nic_access(priv);
 982         spin_unlock_irqrestore(&priv->lock, flags);
 983
 984         return 0;
 985 }
 986
 987 static int iwl3945_tx_reset(struct iwl_priv *priv)
 988 {
 989         int rc;
 990         unsigned long flags;
 991
 992         spin_lock_irqsave(&priv->lock, flags);
 993         rc = iwl_grab_nic_access(priv);
 994         if (rc) {
 995                 spin_unlock_irqrestore(&priv->lock, flags);
 996                 return rc;
 997         }
 998
 999         /* bypass mode */
1000         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
1001
1002         /* RA 0 is active */
1003         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
1004
1005         /* all 6 fifo are active */
1006         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
1007
1008         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1009         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1010         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1011         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1012
1013         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
1014                              priv->shared_phys);
1015
1016         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
1017                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1018                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1019                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1020                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1021                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1022                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1023                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1024
1025         iwl_release_nic_access(priv);
1026         spin_unlock_irqrestore(&priv->lock, flags);
1027
1028         return 0;
1029 }
1030
1031 /**
1032  * iwl3945_txq_ctx_reset - Reset TX queue context
1033  *
1034  * Destroys all DMA structures and initialize them again
1035  */
1036 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
1037 {
1038         int rc;
1039         int txq_id, slots_num;
1040
1041         iwl3945_hw_txq_ctx_free(priv);
1042
1043         /* Tx CMD queue */
1044         rc = iwl3945_tx_reset(priv);
1045         if (rc)
1046                 goto error;
1047
1048         /* Tx queue(s) */
1049         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1050                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1051                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1052                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1053                                        txq_id);
1054                 if (rc) {
1055                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1056                         goto error;
1057                 }
1058         }
1059
1060         return rc;
1061
1062  error:
1063         iwl3945_hw_txq_ctx_free(priv);
1064         return rc;
1065 }
1066
1067 static int iwl3945_apm_init(struct iwl_priv *priv)
1068 {
1069         int ret = 0;
1070
1071         iwl_power_initialize(priv);
1072
1073         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1074                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1075
1076         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1077         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1078                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1079
1080         /* set "initialization complete" bit to move adapter
1081         * D0U* --> D0A* state */
1082         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1083
1084         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1085                             CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1086         if (ret < 0) {
1087                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1088                 goto out;
1089         }
1090
1091         ret = iwl_grab_nic_access(priv);
1092         if (ret)
1093                 goto out;
1094
1095         /* enable DMA */
1096         iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1097                                                 APMG_CLK_VAL_BSM_CLK_RQT);
1098
1099         udelay(20);
1100
1101         /* disable L1-Active */
1102         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1103                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1104
1105         iwl_release_nic_access(priv);
1106 out:
1107         return ret;
1108 }
1109
1110 static void iwl3945_nic_config(struct iwl_priv *priv)
1111 {
1112         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1113         unsigned long flags;
1114         u8 rev_id = 0;
1115
1116         spin_lock_irqsave(&priv->lock, flags);
1117
1118         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1119                 IWL_DEBUG_INFO(priv, "RTP type \n");
1120         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1121                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1122                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1123                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1124         } else {
1125                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1126                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1127                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1128         }
1129
1130         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1131                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1132                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1133                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1134         } else
1135                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1136
1137         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1138                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1139                                eeprom->board_revision);
1140                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1141                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1142         } else {
1143                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1144                                eeprom->board_revision);
1145                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1146                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1147         }
1148
1149         if (eeprom->almgor_m_version <= 1) {
1150                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1151                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1152                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1153                                eeprom->almgor_m_version);
1154         } else {
1155                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1156                                eeprom->almgor_m_version);
1157                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1158                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1159         }
1160         spin_unlock_irqrestore(&priv->lock, flags);
1161
1162         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1163                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1164
1165         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1166                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1167 }
1168
1169 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1170 {
1171         u8 rev_id;
1172         int rc;
1173         unsigned long flags;
1174         struct iwl_rx_queue *rxq = &priv->rxq;
1175
1176         spin_lock_irqsave(&priv->lock, flags);
1177         priv->cfg->ops->lib->apm_ops.init(priv);
1178         spin_unlock_irqrestore(&priv->lock, flags);
1179
1180         /* Determine HW type */
1181         rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1182         if (rc)
1183                 return rc;
1184         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1185
1186         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1187         if(rc)
1188                 return rc;
1189
1190         priv->cfg->ops->lib->apm_ops.config(priv);
1191
1192         /* Allocate the RX queue, or reset if it is already allocated */
1193         if (!rxq->bd) {
1194                 rc = iwl_rx_queue_alloc(priv);
1195                 if (rc) {
1196                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1197                         return -ENOMEM;
1198                 }
1199         } else
1200                 iwl_rx_queue_reset(priv, rxq);
1201
1202         iwl3945_rx_replenish(priv);
1203
1204         iwl3945_rx_init(priv, rxq);
1205
1206         spin_lock_irqsave(&priv->lock, flags);
1207
1208         /* Look at using this instead:
1209         rxq->need_update = 1;
1210         iwl_rx_queue_update_write_ptr(priv, rxq);
1211         */
1212
1213         rc = iwl_grab_nic_access(priv);
1214         if (rc) {
1215                 spin_unlock_irqrestore(&priv->lock, flags);
1216                 return rc;
1217         }
1218         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1219         iwl_release_nic_access(priv);
1220
1221         spin_unlock_irqrestore(&priv->lock, flags);
1222
1223         rc = iwl3945_txq_ctx_reset(priv);
1224         if (rc)
1225                 return rc;
1226
1227         set_bit(STATUS_INIT, &priv->status);
1228
1229         return 0;
1230 }
1231
1232 /**
1233  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1234  *
1235  * Destroy all TX DMA queues and structures
1236  */
1237 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1238 {
1239         int txq_id;
1240
1241         /* Tx queues */
1242         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1243                 iwl_tx_queue_free(priv, txq_id);
1244 }
1245
1246 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1247 {
1248         int txq_id;
1249         unsigned long flags;
1250
1251         spin_lock_irqsave(&priv->lock, flags);
1252         if (iwl_grab_nic_access(priv)) {
1253                 spin_unlock_irqrestore(&priv->lock, flags);
1254                 iwl3945_hw_txq_ctx_free(priv);
1255                 return;
1256         }
1257
1258         /* stop SCD */
1259         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1260
1261         /* reset TFD queues */
1262         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1263                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1264                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1265                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1266                                 1000);
1267         }
1268
1269         iwl_release_nic_access(priv);
1270         spin_unlock_irqrestore(&priv->lock, flags);
1271
1272         iwl3945_hw_txq_ctx_free(priv);
1273 }
1274
1275 static int iwl3945_apm_stop_master(struct iwl_priv *priv)
1276 {
1277         int ret = 0;
1278         unsigned long flags;
1279
1280         spin_lock_irqsave(&priv->lock, flags);
1281
1282         /* set stop master bit */
1283         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1284
1285         iwl_poll_direct_bit(priv, CSR_RESET,
1286                             CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1287
1288         if (ret < 0)
1289                 goto out;
1290
1291 out:
1292         spin_unlock_irqrestore(&priv->lock, flags);
1293         IWL_DEBUG_INFO(priv, "stop master\n");
1294
1295         return ret;
1296 }
1297
1298 static void iwl3945_apm_stop(struct iwl_priv *priv)
1299 {
1300         unsigned long flags;
1301
1302         iwl3945_apm_stop_master(priv);
1303
1304         spin_lock_irqsave(&priv->lock, flags);
1305
1306         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1307
1308         udelay(10);
1309         /* clear "init complete"  move adapter D0A* --> D0U state */
1310         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1311         spin_unlock_irqrestore(&priv->lock, flags);
1312 }
1313
1314 static int iwl3945_apm_reset(struct iwl_priv *priv)
1315 {
1316         int rc;
1317         unsigned long flags;
1318
1319         iwl3945_apm_stop_master(priv);
1320
1321         spin_lock_irqsave(&priv->lock, flags);
1322
1323         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1324         udelay(10);
1325
1326         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1327
1328         iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1329                          CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1330
1331         rc = iwl_grab_nic_access(priv);
1332         if (!rc) {
1333                 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1334                                          APMG_CLK_VAL_BSM_CLK_RQT);
1335
1336                 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1337                 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1338                                         0xFFFFFFFF);
1339
1340                 /* enable DMA */
1341                 iwl_write_prph(priv, APMG_CLK_EN_REG,
1342                                          APMG_CLK_VAL_DMA_CLK_RQT |
1343                                          APMG_CLK_VAL_BSM_CLK_RQT);
1344                 udelay(10);
1345
1346                 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1347                                 APMG_PS_CTRL_VAL_RESET_REQ);
1348                 udelay(5);
1349                 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1350                                 APMG_PS_CTRL_VAL_RESET_REQ);
1351                 iwl_release_nic_access(priv);
1352         }
1353
1354         /* Clear the 'host command active' bit... */
1355         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1356
1357         wake_up_interruptible(&priv->wait_command_queue);
1358         spin_unlock_irqrestore(&priv->lock, flags);
1359
1360         return rc;
1361 }
1362
1363 /**
1364  * iwl3945_hw_reg_adjust_power_by_temp
1365  * return index delta into power gain settings table
1366 */
1367 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1368 {
1369         return (new_reading - old_reading) * (-11) / 100;
1370 }
1371
1372 /**
1373  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1374  */
1375 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1376 {
1377         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1378 }
1379
1380 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1381 {
1382         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1383 }
1384
1385 /**
1386  * iwl3945_hw_reg_txpower_get_temperature
1387  * get the current temperature by reading from NIC
1388 */
1389 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1390 {
1391         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1392         int temperature;
1393
1394         temperature = iwl3945_hw_get_temperature(priv);
1395
1396         /* driver's okay range is -260 to +25.
1397          *   human readable okay range is 0 to +285 */
1398         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1399
1400         /* handle insane temp reading */
1401         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1402                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1403
1404                 /* if really really hot(?),
1405                  *   substitute the 3rd band/group's temp measured at factory */
1406                 if (priv->last_temperature > 100)
1407                         temperature = eeprom->groups[2].temperature;
1408                 else /* else use most recent "sane" value from driver */
1409                         temperature = priv->last_temperature;
1410         }
1411
1412         return temperature;     /* raw, not "human readable" */
1413 }
1414
1415 /* Adjust Txpower only if temperature variance is greater than threshold.
1416  *
1417  * Both are lower than older versions' 9 degrees */
1418 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1419
1420 /**
1421  * is_temp_calib_needed - determines if new calibration is needed
1422  *
1423  * records new temperature in tx_mgr->temperature.
1424  * replaces tx_mgr->last_temperature *only* if calib needed
1425  *    (assumes caller will actually do the calibration!). */
1426 static int is_temp_calib_needed(struct iwl_priv *priv)
1427 {
1428         int temp_diff;
1429
1430         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1431         temp_diff = priv->temperature - priv->last_temperature;
1432
1433         /* get absolute value */
1434         if (temp_diff < 0) {
1435                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1436                 temp_diff = -temp_diff;
1437         } else if (temp_diff == 0)
1438                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1439         else
1440                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1441
1442         /* if we don't need calibration, *don't* update last_temperature */
1443         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1444                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1445                 return 0;
1446         }
1447
1448         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1449
1450         /* assume that caller will actually do calib ...
1451          *   update the "last temperature" value */
1452         priv->last_temperature = priv->temperature;
1453         return 1;
1454 }
1455
1456 #define IWL_MAX_GAIN_ENTRIES 78
1457 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1458 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1459
1460 /* radio and DSP power table, each step is 1/2 dB.
1461  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1462 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1463         {
1464          {251, 127},            /* 2.4 GHz, highest power */
1465          {251, 127},
1466          {251, 127},
1467          {251, 127},
1468          {251, 125},
1469          {251, 110},
1470          {251, 105},
1471          {251, 98},
1472          {187, 125},
1473          {187, 115},
1474          {187, 108},
1475          {187, 99},
1476          {243, 119},
1477          {243, 111},
1478          {243, 105},
1479          {243, 97},
1480          {243, 92},
1481          {211, 106},
1482          {211, 100},
1483          {179, 120},
1484          {179, 113},
1485          {179, 107},
1486          {147, 125},
1487          {147, 119},
1488          {147, 112},
1489          {147, 106},
1490          {147, 101},
1491          {147, 97},
1492          {147, 91},
1493          {115, 107},
1494          {235, 121},
1495          {235, 115},
1496          {235, 109},
1497          {203, 127},
1498          {203, 121},
1499          {203, 115},
1500          {203, 108},
1501          {203, 102},
1502          {203, 96},
1503          {203, 92},
1504          {171, 110},
1505          {171, 104},
1506          {171, 98},
1507          {139, 116},
1508          {227, 125},
1509          {227, 119},
1510          {227, 113},
1511          {227, 107},
1512          {227, 101},
1513          {227, 96},
1514          {195, 113},
1515          {195, 106},
1516          {195, 102},
1517          {195, 95},
1518          {163, 113},
1519          {163, 106},
1520          {163, 102},
1521          {163, 95},
1522          {131, 113},
1523          {131, 106},
1524          {131, 102},
1525          {131, 95},
1526          {99, 113},
1527          {99, 106},
1528          {99, 102},
1529          {99, 95},
1530          {67, 113},
1531          {67, 106},
1532          {67, 102},
1533          {67, 95},
1534          {35, 113},
1535          {35, 106},
1536          {35, 102},
1537          {35, 95},
1538          {3, 113},
1539          {3, 106},
1540          {3, 102},
1541          {3, 95} },             /* 2.4 GHz, lowest power */
1542         {
1543          {251, 127},            /* 5.x GHz, highest power */
1544          {251, 120},
1545          {251, 114},
1546          {219, 119},
1547          {219, 101},
1548          {187, 113},
1549          {187, 102},
1550          {155, 114},
1551          {155, 103},
1552          {123, 117},
1553          {123, 107},
1554          {123, 99},
1555          {123, 92},
1556          {91, 108},
1557          {59, 125},
1558          {59, 118},
1559          {59, 109},
1560          {59, 102},
1561          {59, 96},
1562          {59, 90},
1563          {27, 104},
1564          {27, 98},
1565          {27, 92},
1566          {115, 118},
1567          {115, 111},
1568          {115, 104},
1569          {83, 126},
1570          {83, 121},
1571          {83, 113},
1572          {83, 105},
1573          {83, 99},
1574          {51, 118},
1575          {51, 111},
1576          {51, 104},
1577          {51, 98},
1578          {19, 116},
1579          {19, 109},
1580          {19, 102},
1581          {19, 98},
1582          {19, 93},
1583          {171, 113},
1584          {171, 107},
1585          {171, 99},
1586          {139, 120},
1587          {139, 113},
1588          {139, 107},
1589          {139, 99},
1590          {107, 120},
1591          {107, 113},
1592          {107, 107},
1593          {107, 99},
1594          {75, 120},
1595          {75, 113},
1596          {75, 107},
1597          {75, 99},
1598          {43, 120},
1599          {43, 113},
1600          {43, 107},
1601          {43, 99},
1602          {11, 120},
1603          {11, 113},
1604          {11, 107},
1605          {11, 99},
1606          {131, 107},
1607          {131, 99},
1608          {99, 120},
1609          {99, 113},
1610          {99, 107},
1611          {99, 99},
1612          {67, 120},
1613          {67, 113},
1614          {67, 107},
1615          {67, 99},
1616          {35, 120},
1617          {35, 113},
1618          {35, 107},
1619          {35, 99},
1620          {3, 120} }             /* 5.x GHz, lowest power */
1621 };
1622
1623 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1624 {
1625         if (index < 0)
1626                 return 0;
1627         if (index >= IWL_MAX_GAIN_ENTRIES)
1628                 return IWL_MAX_GAIN_ENTRIES - 1;
1629         return (u8) index;
1630 }
1631
1632 /* Kick off thermal recalibration check every 60 seconds */
1633 #define REG_RECALIB_PERIOD (60)
1634
1635 /**
1636  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1637  *
1638  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1639  * or 6 Mbit (OFDM) rates.
1640  */
1641 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1642                                s32 rate_index, const s8 *clip_pwrs,
1643                                struct iwl_channel_info *ch_info,
1644                                int band_index)
1645 {
1646         struct iwl3945_scan_power_info *scan_power_info;
1647         s8 power;
1648         u8 power_index;
1649
1650         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1651
1652         /* use this channel group's 6Mbit clipping/saturation pwr,
1653          *   but cap at regulatory scan power restriction (set during init
1654          *   based on eeprom channel data) for this channel.  */
1655         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1656
1657         /* further limit to user's max power preference.
1658          * FIXME:  Other spectrum management power limitations do not
1659          *   seem to apply?? */
1660         power = min(power, priv->tx_power_user_lmt);
1661         scan_power_info->requested_power = power;
1662
1663         /* find difference between new scan *power* and current "normal"
1664          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1665          *   current "normal" temperature-compensated Tx power *index* for
1666          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1667          *   *index*. */
1668         power_index = ch_info->power_info[rate_index].power_table_index
1669             - (power - ch_info->power_info
1670                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1671
1672         /* store reference index that we use when adjusting *all* scan
1673          *   powers.  So we can accommodate user (all channel) or spectrum
1674          *   management (single channel) power changes "between" temperature
1675          *   feedback compensation procedures.
1676          * don't force fit this reference index into gain table; it may be a
1677          *   negative number.  This will help avoid errors when we're at
1678          *   the lower bounds (highest gains, for warmest temperatures)
1679          *   of the table. */
1680
1681         /* don't exceed table bounds for "real" setting */
1682         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1683
1684         scan_power_info->power_table_index = power_index;
1685         scan_power_info->tpc.tx_gain =
1686             power_gain_table[band_index][power_index].tx_gain;
1687         scan_power_info->tpc.dsp_atten =
1688             power_gain_table[band_index][power_index].dsp_atten;
1689 }
1690
1691 /**
1692  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1693  *
1694  * Configures power settings for all rates for the current channel,
1695  * using values from channel info struct, and send to NIC
1696  */
1697 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1698 {
1699         int rate_idx, i;
1700         const struct iwl_channel_info *ch_info = NULL;
1701         struct iwl3945_txpowertable_cmd txpower = {
1702                 .channel = priv->active_rxon.channel,
1703         };
1704
1705         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1706         ch_info = iwl_get_channel_info(priv,
1707                                        priv->band,
1708                                        le16_to_cpu(priv->active_rxon.channel));
1709         if (!ch_info) {
1710                 IWL_ERR(priv,
1711                         "Failed to get channel info for channel %d [%d]\n",
1712                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1713                 return -EINVAL;
1714         }
1715
1716         if (!is_channel_valid(ch_info)) {
1717                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1718                                 "non-Tx channel.\n");
1719                 return 0;
1720         }
1721
1722         /* fill cmd with power settings for all rates for current channel */
1723         /* Fill OFDM rate */
1724         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1725              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1726
1727                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1728                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1729
1730                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1731                                 le16_to_cpu(txpower.channel),
1732                                 txpower.band,
1733                                 txpower.power[i].tpc.tx_gain,
1734                                 txpower.power[i].tpc.dsp_atten,
1735                                 txpower.power[i].rate);
1736         }
1737         /* Fill CCK rates */
1738         for (rate_idx = IWL_FIRST_CCK_RATE;
1739              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1740                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1741                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1742
1743                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1744                                 le16_to_cpu(txpower.channel),
1745                                 txpower.band,
1746                                 txpower.power[i].tpc.tx_gain,
1747                                 txpower.power[i].tpc.dsp_atten,
1748                                 txpower.power[i].rate);
1749         }
1750
1751         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1752                                 sizeof(struct iwl3945_txpowertable_cmd),
1753                                 &txpower);
1754
1755 }
1756
1757 /**
1758  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1759  * @ch_info: Channel to update.  Uses power_info.requested_power.
1760  *
1761  * Replace requested_power and base_power_index ch_info fields for
1762  * one channel.
1763  *
1764  * Called if user or spectrum management changes power preferences.
1765  * Takes into account h/w and modulation limitations (clip power).
1766  *
1767  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1768  *
1769  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1770  *       properly fill out the scan powers, and actual h/w gain settings,
1771  *       and send changes to NIC
1772  */
1773 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1774                              struct iwl_channel_info *ch_info)
1775 {
1776         struct iwl3945_channel_power_info *power_info;
1777         int power_changed = 0;
1778         int i;
1779         const s8 *clip_pwrs;
1780         int power;
1781
1782         /* Get this chnlgrp's rate-to-max/clip-powers table */
1783         clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1784
1785         /* Get this channel's rate-to-current-power settings table */
1786         power_info = ch_info->power_info;
1787
1788         /* update OFDM Txpower settings */
1789         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1790              i++, ++power_info) {
1791                 int delta_idx;
1792
1793                 /* limit new power to be no more than h/w capability */
1794                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1795                 if (power == power_info->requested_power)
1796                         continue;
1797
1798                 /* find difference between old and new requested powers,
1799                  *    update base (non-temp-compensated) power index */
1800                 delta_idx = (power - power_info->requested_power) * 2;
1801                 power_info->base_power_index -= delta_idx;
1802
1803                 /* save new requested power value */
1804                 power_info->requested_power = power;
1805
1806                 power_changed = 1;
1807         }
1808
1809         /* update CCK Txpower settings, based on OFDM 12M setting ...
1810          *    ... all CCK power settings for a given channel are the *same*. */
1811         if (power_changed) {
1812                 power =
1813                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1814                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1815
1816                 /* do all CCK rates' iwl3945_channel_power_info structures */
1817                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1818                         power_info->requested_power = power;
1819                         power_info->base_power_index =
1820                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1821                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1822                         ++power_info;
1823                 }
1824         }
1825
1826         return 0;
1827 }
1828
1829 /**
1830  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1831  *
1832  * NOTE: Returned power limit may be less (but not more) than requested,
1833  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1834  *       (no consideration for h/w clipping limitations).
1835  */
1836 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1837 {
1838         s8 max_power;
1839
1840 #if 0
1841         /* if we're using TGd limits, use lower of TGd or EEPROM */
1842         if (ch_info->tgd_data.max_power != 0)
1843                 max_power = min(ch_info->tgd_data.max_power,
1844                                 ch_info->eeprom.max_power_avg);
1845
1846         /* else just use EEPROM limits */
1847         else
1848 #endif
1849                 max_power = ch_info->eeprom.max_power_avg;
1850
1851         return min(max_power, ch_info->max_power_avg);
1852 }
1853
1854 /**
1855  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1856  *
1857  * Compensate txpower settings of *all* channels for temperature.
1858  * This only accounts for the difference between current temperature
1859  *   and the factory calibration temperatures, and bases the new settings
1860  *   on the channel's base_power_index.
1861  *
1862  * If RxOn is "associated", this sends the new Txpower to NIC!
1863  */
1864 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1865 {
1866         struct iwl_channel_info *ch_info = NULL;
1867         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1868         int delta_index;
1869         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1870         u8 a_band;
1871         u8 rate_index;
1872         u8 scan_tbl_index;
1873         u8 i;
1874         int ref_temp;
1875         int temperature = priv->temperature;
1876
1877         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1878         for (i = 0; i < priv->channel_count; i++) {
1879                 ch_info = &priv->channel_info[i];
1880                 a_band = is_channel_a_band(ch_info);
1881
1882                 /* Get this chnlgrp's factory calibration temperature */
1883                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1884                     temperature;
1885
1886                 /* get power index adjustment based on current and factory
1887                  * temps */
1888                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1889                                                               ref_temp);
1890
1891                 /* set tx power value for all rates, OFDM and CCK */
1892                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1893                      rate_index++) {
1894                         int power_idx =
1895                             ch_info->power_info[rate_index].base_power_index;
1896
1897                         /* temperature compensate */
1898                         power_idx += delta_index;
1899
1900                         /* stay within table range */
1901                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1902                         ch_info->power_info[rate_index].
1903                             power_table_index = (u8) power_idx;
1904                         ch_info->power_info[rate_index].tpc =
1905                             power_gain_table[a_band][power_idx];
1906                 }
1907
1908                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1909                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1910
1911                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1912                 for (scan_tbl_index = 0;
1913                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1914                         s32 actual_index = (scan_tbl_index == 0) ?
1915                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1916                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1917                                            actual_index, clip_pwrs,
1918                                            ch_info, a_band);
1919                 }
1920         }
1921
1922         /* send Txpower command for current channel to ucode */
1923         return priv->cfg->ops->lib->send_tx_power(priv);
1924 }
1925
1926 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1927 {
1928         struct iwl_channel_info *ch_info;
1929         s8 max_power;
1930         u8 a_band;
1931         u8 i;
1932
1933         if (priv->tx_power_user_lmt == power) {
1934                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1935                                 "limit: %ddBm.\n", power);
1936                 return 0;
1937         }
1938
1939         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1940         priv->tx_power_user_lmt = power;
1941
1942         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1943
1944         for (i = 0; i < priv->channel_count; i++) {
1945                 ch_info = &priv->channel_info[i];
1946                 a_band = is_channel_a_band(ch_info);
1947
1948                 /* find minimum power of all user and regulatory constraints
1949                  *    (does not consider h/w clipping limitations) */
1950                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1951                 max_power = min(power, max_power);
1952                 if (max_power != ch_info->curr_txpow) {
1953                         ch_info->curr_txpow = max_power;
1954
1955                         /* this considers the h/w clipping limitations */
1956                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1957                 }
1958         }
1959
1960         /* update txpower settings for all channels,
1961          *   send to NIC if associated. */
1962         is_temp_calib_needed(priv);
1963         iwl3945_hw_reg_comp_txpower_temp(priv);
1964
1965         return 0;
1966 }
1967
1968 /* will add 3945 channel switch cmd handling later */
1969 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1970 {
1971         return 0;
1972 }
1973
1974 /**
1975  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1976  *
1977  * -- reset periodic timer
1978  * -- see if temp has changed enough to warrant re-calibration ... if so:
1979  *     -- correct coeffs for temp (can reset temp timer)
1980  *     -- save this temp as "last",
1981  *     -- send new set of gain settings to NIC
1982  * NOTE:  This should continue working, even when we're not associated,
1983  *   so we can keep our internal table of scan powers current. */
1984 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1985 {
1986         /* This will kick in the "brute force"
1987          * iwl3945_hw_reg_comp_txpower_temp() below */
1988         if (!is_temp_calib_needed(priv))
1989                 goto reschedule;
1990
1991         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1992          * This is based *only* on current temperature,
1993          * ignoring any previous power measurements */
1994         iwl3945_hw_reg_comp_txpower_temp(priv);
1995
1996  reschedule:
1997         queue_delayed_work(priv->workqueue,
1998                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1999 }
2000
2001 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2002 {
2003         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2004                                              thermal_periodic.work);
2005
2006         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2007                 return;
2008
2009         mutex_lock(&priv->mutex);
2010         iwl3945_reg_txpower_periodic(priv);
2011         mutex_unlock(&priv->mutex);
2012 }
2013
2014 /**
2015  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2016  *                                 for the channel.
2017  *
2018  * This function is used when initializing channel-info structs.
2019  *
2020  * NOTE: These channel groups do *NOT* match the bands above!
2021  *       These channel groups are based on factory-tested channels;
2022  *       on A-band, EEPROM's "group frequency" entries represent the top
2023  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2024  */
2025 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2026                                        const struct iwl_channel_info *ch_info)
2027 {
2028         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2029         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2030         u8 group;
2031         u16 group_index = 0;    /* based on factory calib frequencies */
2032         u8 grp_channel;
2033
2034         /* Find the group index for the channel ... don't use index 1(?) */
2035         if (is_channel_a_band(ch_info)) {
2036                 for (group = 1; group < 5; group++) {
2037                         grp_channel = ch_grp[group].group_channel;
2038                         if (ch_info->channel <= grp_channel) {
2039                                 group_index = group;
2040                                 break;
2041                         }
2042                 }
2043                 /* group 4 has a few channels *above* its factory cal freq */
2044                 if (group == 5)
2045                         group_index = 4;
2046         } else
2047                 group_index = 0;        /* 2.4 GHz, group 0 */
2048
2049         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2050                         group_index);
2051         return group_index;
2052 }
2053
2054 /**
2055  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2056  *
2057  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2058  *   into radio/DSP gain settings table for requested power.
2059  */
2060 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2061                                        s8 requested_power,
2062                                        s32 setting_index, s32 *new_index)
2063 {
2064         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2065         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2066         s32 index0, index1;
2067         s32 power = 2 * requested_power;
2068         s32 i;
2069         const struct iwl3945_eeprom_txpower_sample *samples;
2070         s32 gains0, gains1;
2071         s32 res;
2072         s32 denominator;
2073
2074         chnl_grp = &eeprom->groups[setting_index];
2075         samples = chnl_grp->samples;
2076         for (i = 0; i < 5; i++) {
2077                 if (power == samples[i].power) {
2078                         *new_index = samples[i].gain_index;
2079                         return 0;
2080                 }
2081         }
2082
2083         if (power > samples[1].power) {
2084                 index0 = 0;
2085                 index1 = 1;
2086         } else if (power > samples[2].power) {
2087                 index0 = 1;
2088                 index1 = 2;
2089         } else if (power > samples[3].power) {
2090                 index0 = 2;
2091                 index1 = 3;
2092         } else {
2093                 index0 = 3;
2094                 index1 = 4;
2095         }
2096
2097         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2098         if (denominator == 0)
2099                 return -EINVAL;
2100         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2101         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2102         res = gains0 + (gains1 - gains0) *
2103             ((s32) power - (s32) samples[index0].power) / denominator +
2104             (1 << 18);
2105         *new_index = res >> 19;
2106         return 0;
2107 }
2108
2109 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2110 {
2111         u32 i;
2112         s32 rate_index;
2113         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2114         const struct iwl3945_eeprom_txpower_group *group;
2115
2116         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2117
2118         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2119                 s8 *clip_pwrs;  /* table of power levels for each rate */
2120                 s8 satur_pwr;   /* saturation power for each chnl group */
2121                 group = &eeprom->groups[i];
2122
2123                 /* sanity check on factory saturation power value */
2124                 if (group->saturation_power < 40) {
2125                         IWL_WARN(priv, "Error: saturation power is %d, "
2126                                     "less than minimum expected 40\n",
2127                                     group->saturation_power);
2128                         return;
2129                 }
2130
2131                 /*
2132                  * Derive requested power levels for each rate, based on
2133                  *   hardware capabilities (saturation power for band).
2134                  * Basic value is 3dB down from saturation, with further
2135                  *   power reductions for highest 3 data rates.  These
2136                  *   backoffs provide headroom for high rate modulation
2137                  *   power peaks, without too much distortion (clipping).
2138                  */
2139                 /* we'll fill in this array with h/w max power levels */
2140                 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2141
2142                 /* divide factory saturation power by 2 to find -3dB level */
2143                 satur_pwr = (s8) (group->saturation_power >> 1);
2144
2145                 /* fill in channel group's nominal powers for each rate */
2146                 for (rate_index = 0;
2147                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2148                         switch (rate_index) {
2149                         case IWL_RATE_36M_INDEX_TABLE:
2150                                 if (i == 0)     /* B/G */
2151                                         *clip_pwrs = satur_pwr;
2152                                 else    /* A */
2153                                         *clip_pwrs = satur_pwr - 5;
2154                                 break;
2155                         case IWL_RATE_48M_INDEX_TABLE:
2156                                 if (i == 0)
2157                                         *clip_pwrs = satur_pwr - 7;
2158                                 else
2159                                         *clip_pwrs = satur_pwr - 10;
2160                                 break;
2161                         case IWL_RATE_54M_INDEX_TABLE:
2162                                 if (i == 0)
2163                                         *clip_pwrs = satur_pwr - 9;
2164                                 else
2165                                         *clip_pwrs = satur_pwr - 12;
2166                                 break;
2167                         default:
2168                                 *clip_pwrs = satur_pwr;
2169                                 break;
2170                         }
2171                 }
2172         }
2173 }
2174
2175 /**
2176  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2177  *
2178  * Second pass (during init) to set up priv->channel_info
2179  *
2180  * Set up Tx-power settings in our channel info database for each VALID
2181  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2182  * and current temperature.
2183  *
2184  * Since this is based on current temperature (at init time), these values may
2185  * not be valid for very long, but it gives us a starting/default point,
2186  * and allows us to active (i.e. using Tx) scan.
2187  *
2188  * This does *not* write values to NIC, just sets up our internal table.
2189  */
2190 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2191 {
2192         struct iwl_channel_info *ch_info = NULL;
2193         struct iwl3945_channel_power_info *pwr_info;
2194         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2195         int delta_index;
2196         u8 rate_index;
2197         u8 scan_tbl_index;
2198         const s8 *clip_pwrs;    /* array of power levels for each rate */
2199         u8 gain, dsp_atten;
2200         s8 power;
2201         u8 pwr_index, base_pwr_index, a_band;
2202         u8 i;
2203         int temperature;
2204
2205         /* save temperature reference,
2206          *   so we can determine next time to calibrate */
2207         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2208         priv->last_temperature = temperature;
2209
2210         iwl3945_hw_reg_init_channel_groups(priv);
2211
2212         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2213         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2214              i++, ch_info++) {
2215                 a_band = is_channel_a_band(ch_info);
2216                 if (!is_channel_valid(ch_info))
2217                         continue;
2218
2219                 /* find this channel's channel group (*not* "band") index */
2220                 ch_info->group_index =
2221                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2222
2223                 /* Get this chnlgrp's rate->max/clip-powers table */
2224                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2225
2226                 /* calculate power index *adjustment* value according to
2227                  *  diff between current temperature and factory temperature */
2228                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2229                                 eeprom->groups[ch_info->group_index].
2230                                 temperature);
2231
2232                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2233                                 ch_info->channel, delta_index, temperature +
2234                                 IWL_TEMP_CONVERT);
2235
2236                 /* set tx power value for all OFDM rates */
2237                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2238                      rate_index++) {
2239                         s32 uninitialized_var(power_idx);
2240                         int rc;
2241
2242                         /* use channel group's clip-power table,
2243                          *   but don't exceed channel's max power */
2244                         s8 pwr = min(ch_info->max_power_avg,
2245                                      clip_pwrs[rate_index]);
2246
2247                         pwr_info = &ch_info->power_info[rate_index];
2248
2249                         /* get base (i.e. at factory-measured temperature)
2250                          *    power table index for this rate's power */
2251                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2252                                                          ch_info->group_index,
2253                                                          &power_idx);
2254                         if (rc) {
2255                                 IWL_ERR(priv, "Invalid power index\n");
2256                                 return rc;
2257                         }
2258                         pwr_info->base_power_index = (u8) power_idx;
2259
2260                         /* temperature compensate */
2261                         power_idx += delta_index;
2262
2263                         /* stay within range of gain table */
2264                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2265
2266                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2267                         pwr_info->requested_power = pwr;
2268                         pwr_info->power_table_index = (u8) power_idx;
2269                         pwr_info->tpc.tx_gain =
2270                             power_gain_table[a_band][power_idx].tx_gain;
2271                         pwr_info->tpc.dsp_atten =
2272                             power_gain_table[a_band][power_idx].dsp_atten;
2273                 }
2274
2275                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2276                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2277                 power = pwr_info->requested_power +
2278                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2279                 pwr_index = pwr_info->power_table_index +
2280                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2281                 base_pwr_index = pwr_info->base_power_index +
2282                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2283
2284                 /* stay within table range */
2285                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2286                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2287                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2288
2289                 /* fill each CCK rate's iwl3945_channel_power_info structure
2290                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2291                  * NOTE:  CCK rates start at end of OFDM rates! */
2292                 for (rate_index = 0;
2293                      rate_index < IWL_CCK_RATES; rate_index++) {
2294                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2295                         pwr_info->requested_power = power;
2296                         pwr_info->power_table_index = pwr_index;
2297                         pwr_info->base_power_index = base_pwr_index;
2298                         pwr_info->tpc.tx_gain = gain;
2299                         pwr_info->tpc.dsp_atten = dsp_atten;
2300                 }
2301
2302                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2303                 for (scan_tbl_index = 0;
2304                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2305                         s32 actual_index = (scan_tbl_index == 0) ?
2306                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2307                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2308                                 actual_index, clip_pwrs, ch_info, a_band);
2309                 }
2310         }
2311
2312         return 0;
2313 }
2314
2315 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2316 {
2317         int rc;
2318         unsigned long flags;
2319
2320         spin_lock_irqsave(&priv->lock, flags);
2321         rc = iwl_grab_nic_access(priv);
2322         if (rc) {
2323                 spin_unlock_irqrestore(&priv->lock, flags);
2324                 return rc;
2325         }
2326
2327         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2328         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2329                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2330         if (rc < 0)
2331                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2332
2333         iwl_release_nic_access(priv);
2334         spin_unlock_irqrestore(&priv->lock, flags);
2335
2336         return 0;
2337 }
2338
2339 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2340 {
2341         int rc;
2342         unsigned long flags;
2343         int txq_id = txq->q.id;
2344
2345         struct iwl3945_shared *shared_data = priv->shared_virt;
2346
2347         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2348
2349         spin_lock_irqsave(&priv->lock, flags);
2350         rc = iwl_grab_nic_access(priv);
2351         if (rc) {
2352                 spin_unlock_irqrestore(&priv->lock, flags);
2353                 return rc;
2354         }
2355         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2356         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2357
2358         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2359                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2360                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2361                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2362                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2363                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2364         iwl_release_nic_access(priv);
2365
2366         /* fake read to flush all prev. writes */
2367         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2368         spin_unlock_irqrestore(&priv->lock, flags);
2369
2370         return 0;
2371 }
2372
2373 /*
2374  * HCMD utils
2375  */
2376 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2377 {
2378         switch (cmd_id) {
2379         case REPLY_RXON:
2380                 return sizeof(struct iwl3945_rxon_cmd);
2381         case POWER_TABLE_CMD:
2382                 return sizeof(struct iwl3945_powertable_cmd);
2383         default:
2384                 return len;
2385         }
2386 }
2387
2388 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2389 {
2390         u16 size = (u16)sizeof(struct iwl3945_addsta_cmd);
2391         memcpy(data, cmd, size);
2392         return size;
2393 }
2394
2395 /**
2396  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2397  */
2398 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2399 {
2400         int rc, i, index, prev_index;
2401         struct iwl3945_rate_scaling_cmd rate_cmd = {
2402                 .reserved = {0, 0, 0},
2403         };
2404         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2405
2406         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2407                 index = iwl3945_rates[i].table_rs_index;
2408
2409                 table[index].rate_n_flags =
2410                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2411                 table[index].try_cnt = priv->retry_rate;
2412                 prev_index = iwl3945_get_prev_ieee_rate(i);
2413                 table[index].next_rate_index =
2414                                 iwl3945_rates[prev_index].table_rs_index;
2415         }
2416
2417         switch (priv->band) {
2418         case IEEE80211_BAND_5GHZ:
2419                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2420                 /* If one of the following CCK rates is used,
2421                  * have it fall back to the 6M OFDM rate */
2422                 for (i = IWL_RATE_1M_INDEX_TABLE;
2423                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2424                         table[i].next_rate_index =
2425                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2426
2427                 /* Don't fall back to CCK rates */
2428                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2429                                                 IWL_RATE_9M_INDEX_TABLE;
2430
2431                 /* Don't drop out of OFDM rates */
2432                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2433                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2434                 break;
2435
2436         case IEEE80211_BAND_2GHZ:
2437                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2438                 /* If an OFDM rate is used, have it fall back to the
2439                  * 1M CCK rates */
2440
2441                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2442                     iwl_is_associated(priv)) {
2443
2444                         index = IWL_FIRST_CCK_RATE;
2445                         for (i = IWL_RATE_6M_INDEX_TABLE;
2446                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2447                                 table[i].next_rate_index =
2448                                         iwl3945_rates[index].table_rs_index;
2449
2450                         index = IWL_RATE_11M_INDEX_TABLE;
2451                         /* CCK shouldn't fall back to OFDM... */
2452                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2453                 }
2454                 break;
2455
2456         default:
2457                 WARN_ON(1);
2458                 break;
2459         }
2460
2461         /* Update the rate scaling for control frame Tx */
2462         rate_cmd.table_id = 0;
2463         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2464                               &rate_cmd);
2465         if (rc)
2466                 return rc;
2467
2468         /* Update the rate scaling for data frame Tx */
2469         rate_cmd.table_id = 1;
2470         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2471                                 &rate_cmd);
2472 }
2473
2474 /* Called when initializing driver */
2475 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2476 {
2477         memset((void *)&priv->hw_params, 0,
2478                sizeof(struct iwl_hw_params));
2479
2480         priv->shared_virt =
2481             pci_alloc_consistent(priv->pci_dev,
2482                                  sizeof(struct iwl3945_shared),
2483                                  &priv->shared_phys);
2484
2485         if (!priv->shared_virt) {
2486                 IWL_ERR(priv, "failed to allocate pci memory\n");
2487                 mutex_unlock(&priv->mutex);
2488                 return -ENOMEM;
2489         }
2490
2491         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2492         priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2493         priv->hw_params.max_pkt_size = 2342;
2494         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2495         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2496         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2497         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2498
2499         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2500
2501         return 0;
2502 }
2503
2504 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2505                           struct iwl3945_frame *frame, u8 rate)
2506 {
2507         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2508         unsigned int frame_size;
2509
2510         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2511         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2512
2513         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2514         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2515
2516         frame_size = iwl3945_fill_beacon_frame(priv,
2517                                 tx_beacon_cmd->frame,
2518                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2519
2520         BUG_ON(frame_size > MAX_MPDU_SIZE);
2521         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2522
2523         tx_beacon_cmd->tx.rate = rate;
2524         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2525                                       TX_CMD_FLG_TSF_MSK);
2526
2527         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2528         tx_beacon_cmd->tx.supp_rates[0] =
2529                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2530
2531         tx_beacon_cmd->tx.supp_rates[1] =
2532                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2533
2534         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2535 }
2536
2537 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2538 {
2539         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2540         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2541 }
2542
2543 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2544 {
2545         INIT_DELAYED_WORK(&priv->thermal_periodic,
2546                           iwl3945_bg_reg_txpower_periodic);
2547 }
2548
2549 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2550 {
2551         cancel_delayed_work(&priv->thermal_periodic);
2552 }
2553
2554 /* check contents of special bootstrap uCode SRAM */
2555 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2556  {
2557         __le32 *image = priv->ucode_boot.v_addr;
2558         u32 len = priv->ucode_boot.len;
2559         u32 reg;
2560         u32 val;
2561
2562         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2563
2564         /* verify BSM SRAM contents */
2565         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2566         for (reg = BSM_SRAM_LOWER_BOUND;
2567              reg < BSM_SRAM_LOWER_BOUND + len;
2568              reg += sizeof(u32), image++) {
2569                 val = iwl_read_prph(priv, reg);
2570                 if (val != le32_to_cpu(*image)) {
2571                         IWL_ERR(priv, "BSM uCode verification failed at "
2572                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2573                                   BSM_SRAM_LOWER_BOUND,
2574                                   reg - BSM_SRAM_LOWER_BOUND, len,
2575                                   val, le32_to_cpu(*image));
2576                         return -EIO;
2577                 }
2578         }
2579
2580         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2581
2582         return 0;
2583 }
2584
2585
2586 /******************************************************************************
2587  *
2588  * EEPROM related functions
2589  *
2590  ******************************************************************************/
2591
2592 /*
2593  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2594  * embedded controller) as EEPROM reader; each read is a series of pulses
2595  * to/from the EEPROM chip, not a single event, so even reads could conflict
2596  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2597  * simply claims ownership, which should be safe when this function is called
2598  * (i.e. before loading uCode!).
2599  */
2600 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2601 {
2602         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2603         return 0;
2604 }
2605
2606
2607 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2608 {
2609         return;
2610 }
2611
2612  /**
2613   * iwl3945_load_bsm - Load bootstrap instructions
2614   *
2615   * BSM operation:
2616   *
2617   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2618   * in special SRAM that does not power down during RFKILL.  When powering back
2619   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2620   * the bootstrap program into the on-board processor, and starts it.
2621   *
2622   * The bootstrap program loads (via DMA) instructions and data for a new
2623   * program from host DRAM locations indicated by the host driver in the
2624   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2625   * automatically.
2626   *
2627   * When initializing the NIC, the host driver points the BSM to the
2628   * "initialize" uCode image.  This uCode sets up some internal data, then
2629   * notifies host via "initialize alive" that it is complete.
2630   *
2631   * The host then replaces the BSM_DRAM_* pointer values to point to the
2632   * normal runtime uCode instructions and a backup uCode data cache buffer
2633   * (filled initially with starting data values for the on-board processor),
2634   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2635   * which begins normal operation.
2636   *
2637   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2638   * the backup data cache in DRAM before SRAM is powered down.
2639   *
2640   * When powering back up, the BSM loads the bootstrap program.  This reloads
2641   * the runtime uCode instructions and the backup data cache into SRAM,
2642   * and re-launches the runtime uCode from where it left off.
2643   */
2644 static int iwl3945_load_bsm(struct iwl_priv *priv)
2645 {
2646         __le32 *image = priv->ucode_boot.v_addr;
2647         u32 len = priv->ucode_boot.len;
2648         dma_addr_t pinst;
2649         dma_addr_t pdata;
2650         u32 inst_len;
2651         u32 data_len;
2652         int rc;
2653         int i;
2654         u32 done;
2655         u32 reg_offset;
2656
2657         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2658
2659         /* make sure bootstrap program is no larger than BSM's SRAM size */
2660         if (len > IWL39_MAX_BSM_SIZE)
2661                 return -EINVAL;
2662
2663         /* Tell bootstrap uCode where to find the "Initialize" uCode
2664         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2665         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2666         *        after the "initialize" uCode has run, to point to
2667         *        runtime/protocol instructions and backup data cache. */
2668         pinst = priv->ucode_init.p_addr;
2669         pdata = priv->ucode_init_data.p_addr;
2670         inst_len = priv->ucode_init.len;
2671         data_len = priv->ucode_init_data.len;
2672
2673         rc = iwl_grab_nic_access(priv);
2674         if (rc)
2675                 return rc;
2676
2677         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2678         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2679         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2680         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2681
2682         /* Fill BSM memory with bootstrap instructions */
2683         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2684              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2685              reg_offset += sizeof(u32), image++)
2686                 _iwl_write_prph(priv, reg_offset,
2687                                           le32_to_cpu(*image));
2688
2689         rc = iwl3945_verify_bsm(priv);
2690         if (rc) {
2691                 iwl_release_nic_access(priv);
2692                 return rc;
2693         }
2694
2695         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2696         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2697         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2698                                  IWL39_RTC_INST_LOWER_BOUND);
2699         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2700
2701         /* Load bootstrap code into instruction SRAM now,
2702          *   to prepare to load "initialize" uCode */
2703         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2704                 BSM_WR_CTRL_REG_BIT_START);
2705
2706         /* Wait for load of bootstrap uCode to finish */
2707         for (i = 0; i < 100; i++) {
2708                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2709                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2710                         break;
2711                 udelay(10);
2712         }
2713         if (i < 100)
2714                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2715         else {
2716                 IWL_ERR(priv, "BSM write did not complete!\n");
2717                 return -EIO;
2718         }
2719
2720         /* Enable future boot loads whenever power management unit triggers it
2721          *   (e.g. when powering back up after power-save shutdown) */
2722         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2723                 BSM_WR_CTRL_REG_BIT_START_EN);
2724
2725         iwl_release_nic_access(priv);
2726
2727         return 0;
2728 }
2729
2730 static struct iwl_lib_ops iwl3945_lib = {
2731         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2732         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2733         .txq_init = iwl3945_hw_tx_queue_init,
2734         .load_ucode = iwl3945_load_bsm,
2735         .apm_ops = {
2736                 .init = iwl3945_apm_init,
2737                 .reset = iwl3945_apm_reset,
2738                 .stop = iwl3945_apm_stop,
2739                 .config = iwl3945_nic_config,
2740                 .set_pwr_src = iwl3945_set_pwr_src,
2741         },
2742         .eeprom_ops = {
2743                 .regulatory_bands = {
2744                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2745                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2746                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2747                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2748                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2749                         EEPROM_REGULATORY_BAND_NO_FAT,
2750                         EEPROM_REGULATORY_BAND_NO_FAT,
2751                 },
2752                 .verify_signature  = iwlcore_eeprom_verify_signature,
2753                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2754                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2755                 .query_addr = iwlcore_eeprom_query_addr,
2756         },
2757         .send_tx_power  = iwl3945_send_tx_power,
2758         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2759 };
2760
2761 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2762         .get_hcmd_size = iwl3945_get_hcmd_size,
2763         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2764 };
2765
2766 static struct iwl_ops iwl3945_ops = {
2767         .lib = &iwl3945_lib,
2768         .utils = &iwl3945_hcmd_utils,
2769 };
2770
2771 static struct iwl_cfg iwl3945_bg_cfg = {
2772         .name = "3945BG",
2773         .fw_name_pre = IWL3945_FW_PRE,
2774         .ucode_api_max = IWL3945_UCODE_API_MAX,
2775         .ucode_api_min = IWL3945_UCODE_API_MIN,
2776         .sku = IWL_SKU_G,
2777         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2778         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2779         .ops = &iwl3945_ops,
2780         .mod_params = &iwl3945_mod_params
2781 };
2782
2783 static struct iwl_cfg iwl3945_abg_cfg = {
2784         .name = "3945ABG",
2785         .fw_name_pre = IWL3945_FW_PRE,
2786         .ucode_api_max = IWL3945_UCODE_API_MAX,
2787         .ucode_api_min = IWL3945_UCODE_API_MIN,
2788         .sku = IWL_SKU_A|IWL_SKU_G,
2789         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2790         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2791         .ops = &iwl3945_ops,
2792         .mod_params = &iwl3945_mod_params
2793 };
2794
2795 struct pci_device_id iwl3945_hw_card_ids[] = {
2796         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2797         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2798         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2799         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2800         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2801         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2802         {0}
2803 };
2804
2805 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);