Merge git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux-2.6-for-linus
[linux-2.6] / arch / powerpc / boot / dts / mpc8610_hpcd.dts
1 /*
2  * MPC8610 HPCD Device Tree Source
3  *
4  * Copyright 2007-2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under the terms of the GNU General Public License Version 2 as published
8  * by the Free Software Foundation.
9  */
10
11 /dts-v1/;
12
13 / {
14         model = "MPC8610HPCD";
15         compatible = "fsl,MPC8610HPCD";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         aliases {
20                 serial0 = &serial0;
21                 serial1 = &serial1;
22                 pci0 = &pci0;
23                 pci1 = &pci1;
24                 pci2 = &pci2;
25         };
26
27         cpus {
28                 #address-cells = <1>;
29                 #size-cells = <0>;
30
31                 PowerPC,8610@0 {
32                         device_type = "cpu";
33                         reg = <0>;
34                         d-cache-line-size = <32>;
35                         i-cache-line-size = <32>;
36                         d-cache-size = <32768>;         // L1
37                         i-cache-size = <32768>;         // L1
38                         timebase-frequency = <0>;       // From uboot
39                         bus-frequency = <0>;            // From uboot
40                         clock-frequency = <0>;          // From uboot
41                 };
42         };
43
44         memory {
45                 device_type = "memory";
46                 reg = <0x00000000 0x20000000>;  // 512M at 0x0
47         };
48
49         localbus@e0005000 {
50                 #address-cells = <2>;
51                 #size-cells = <1>;
52                 compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
53                 reg = <0xe0005000 0x1000>;
54                 interrupts = <19 2>;
55                 interrupt-parent = <&mpic>;
56                 ranges = <0 0 0xf8000000 0x08000000
57                           1 0 0xf0000000 0x08000000
58                           2 0 0xe8400000 0x00008000
59                           4 0 0xe8440000 0x00008000
60                           5 0 0xe8480000 0x00008000
61                           6 0 0xe84c0000 0x00008000
62                           3 0 0xe8000000 0x00000020>;
63
64                 flash@0,0 {
65                         compatible = "cfi-flash";
66                         reg = <0 0 0x8000000>;
67                         bank-width = <2>;
68                         device-width = <1>;
69                 };
70
71                 flash@1,0 {
72                         compatible = "cfi-flash";
73                         reg = <1 0 0x8000000>;
74                         bank-width = <2>;
75                         device-width = <1>;
76                 };
77
78                 flash@2,0 {
79                         compatible = "fsl,mpc8610-fcm-nand",
80                                      "fsl,elbc-fcm-nand";
81                         reg = <2 0 0x8000>;
82                 };
83
84                 flash@4,0 {
85                         compatible = "fsl,mpc8610-fcm-nand",
86                                      "fsl,elbc-fcm-nand";
87                         reg = <4 0 0x8000>;
88                 };
89
90                 flash@5,0 {
91                         compatible = "fsl,mpc8610-fcm-nand",
92                                      "fsl,elbc-fcm-nand";
93                         reg = <5 0 0x8000>;
94                 };
95
96                 flash@6,0 {
97                         compatible = "fsl,mpc8610-fcm-nand",
98                                      "fsl,elbc-fcm-nand";
99                         reg = <6 0 0x8000>;
100                 };
101
102                 board-control@3,0 {
103                         compatible = "fsl,fpga-pixis";
104                         reg = <3 0 0x20>;
105                 };
106         };
107
108         soc@e0000000 {
109                 #address-cells = <1>;
110                 #size-cells = <1>;
111                 #interrupt-cells = <2>;
112                 device_type = "soc";
113                 compatible = "fsl,mpc8610-immr", "simple-bus";
114                 ranges = <0x0 0xe0000000 0x00100000>;
115                 reg = <0xe0000000 0x1000>;
116                 bus-frequency = <0>;
117
118                 i2c@3000 {
119                         #address-cells = <1>;
120                         #size-cells = <0>;
121                         cell-index = <0>;
122                         compatible = "fsl-i2c";
123                         reg = <0x3000 0x100>;
124                         interrupts = <43 2>;
125                         interrupt-parent = <&mpic>;
126                         dfsrr;
127
128                         cs4270:codec@4f {
129                                 compatible = "cirrus,cs4270";
130                                 reg = <0x4f>;
131                                 /* MCLK source is a stand-alone oscillator */
132                                 clock-frequency = <12288000>;
133                         };
134                 };
135
136                 i2c@3100 {
137                         #address-cells = <1>;
138                         #size-cells = <0>;
139                         cell-index = <1>;
140                         compatible = "fsl-i2c";
141                         reg = <0x3100 0x100>;
142                         interrupts = <43 2>;
143                         interrupt-parent = <&mpic>;
144                         dfsrr;
145                 };
146
147                 serial0: serial@4500 {
148                         cell-index = <0>;
149                         device_type = "serial";
150                         compatible = "ns16550";
151                         reg = <0x4500 0x100>;
152                         clock-frequency = <0>;
153                         interrupts = <42 2>;
154                         interrupt-parent = <&mpic>;
155                 };
156
157                 serial1: serial@4600 {
158                         cell-index = <1>;
159                         device_type = "serial";
160                         compatible = "ns16550";
161                         reg = <0x4600 0x100>;
162                         clock-frequency = <0>;
163                         interrupts = <42 2>;
164                         interrupt-parent = <&mpic>;
165                 };
166
167                 display@2c000 {
168                         compatible = "fsl,diu";
169                         reg = <0x2c000 100>;
170                         interrupts = <72 2>;
171                         interrupt-parent = <&mpic>;
172                 };
173
174                 mpic: interrupt-controller@40000 {
175                         interrupt-controller;
176                         #address-cells = <0>;
177                         #interrupt-cells = <2>;
178                         reg = <0x40000 0x40000>;
179                         compatible = "chrp,open-pic";
180                         device_type = "open-pic";
181                 };
182
183                 msi@41600 {
184                         compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
185                         reg = <0x41600 0x80>;
186                         msi-available-ranges = <0 0x100>;
187                         interrupts = <
188                                 0xe0 0
189                                 0xe1 0
190                                 0xe2 0
191                                 0xe3 0
192                                 0xe4 0
193                                 0xe5 0
194                                 0xe6 0
195                                 0xe7 0>;
196                         interrupt-parent = <&mpic>;
197                 };
198
199                 global-utilities@e0000 {
200                         compatible = "fsl,mpc8610-guts";
201                         reg = <0xe0000 0x1000>;
202                         fsl,has-rstcr;
203                 };
204
205                 i2s@16000 {
206                         compatible = "fsl,mpc8610-ssi";
207                         cell-index = <0>;
208                         reg = <0x16000 0x100>;
209                         interrupt-parent = <&mpic>;
210                         interrupts = <62 2>;
211                         fsl,mode = "i2s-slave";
212                         codec-handle = <&cs4270>;
213                 };
214
215                 ssi@16100 {
216                         compatible = "fsl,mpc8610-ssi";
217                         cell-index = <1>;
218                         reg = <0x16100 0x100>;
219                         interrupt-parent = <&mpic>;
220                         interrupts = <63 2>;
221                 };
222
223                 dma@21300 {
224                         #address-cells = <1>;
225                         #size-cells = <1>;
226                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
227                         cell-index = <0>;
228                         reg = <0x21300 0x4>; /* DMA general status register */
229                         ranges = <0x0 0x21100 0x200>;
230
231                         dma-channel@0 {
232                                 compatible = "fsl,mpc8610-dma-channel",
233                                         "fsl,eloplus-dma-channel";
234                                 cell-index = <0>;
235                                 reg = <0x0 0x80>;
236                                 interrupt-parent = <&mpic>;
237                                 interrupts = <20 2>;
238                         };
239                         dma-channel@1 {
240                                 compatible = "fsl,mpc8610-dma-channel",
241                                         "fsl,eloplus-dma-channel";
242                                 cell-index = <1>;
243                                 reg = <0x80 0x80>;
244                                 interrupt-parent = <&mpic>;
245                                 interrupts = <21 2>;
246                         };
247                         dma-channel@2 {
248                                 compatible = "fsl,mpc8610-dma-channel",
249                                         "fsl,eloplus-dma-channel";
250                                 cell-index = <2>;
251                                 reg = <0x100 0x80>;
252                                 interrupt-parent = <&mpic>;
253                                 interrupts = <22 2>;
254                         };
255                         dma-channel@3 {
256                                 compatible = "fsl,mpc8610-dma-channel",
257                                         "fsl,eloplus-dma-channel";
258                                 cell-index = <3>;
259                                 reg = <0x180 0x80>;
260                                 interrupt-parent = <&mpic>;
261                                 interrupts = <23 2>;
262                         };
263                 };
264
265                 dma@c300 {
266                         #address-cells = <1>;
267                         #size-cells = <1>;
268                         compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
269                         cell-index = <1>;
270                         reg = <0xc300 0x4>; /* DMA general status register */
271                         ranges = <0x0 0xc100 0x200>;
272
273                         dma-channel@0 {
274                                 compatible = "fsl,mpc8610-dma-channel",
275                                         "fsl,eloplus-dma-channel";
276                                 cell-index = <0>;
277                                 reg = <0x0 0x80>;
278                                 interrupt-parent = <&mpic>;
279                                 interrupts = <60 2>;
280                         };
281                         dma-channel@1 {
282                                 compatible = "fsl,mpc8610-dma-channel",
283                                         "fsl,eloplus-dma-channel";
284                                 cell-index = <1>;
285                                 reg = <0x80 0x80>;
286                                 interrupt-parent = <&mpic>;
287                                 interrupts = <61 2>;
288                         };
289                         dma-channel@2 {
290                                 compatible = "fsl,mpc8610-dma-channel",
291                                         "fsl,eloplus-dma-channel";
292                                 cell-index = <2>;
293                                 reg = <0x100 0x80>;
294                                 interrupt-parent = <&mpic>;
295                                 interrupts = <62 2>;
296                         };
297                         dma-channel@3 {
298                                 compatible = "fsl,mpc8610-dma-channel",
299                                         "fsl,eloplus-dma-channel";
300                                 cell-index = <3>;
301                                 reg = <0x180 0x80>;
302                                 interrupt-parent = <&mpic>;
303                                 interrupts = <63 2>;
304                         };
305                 };
306
307         };
308
309         pci0: pci@e0008000 {
310                 cell-index = <0>;
311                 compatible = "fsl,mpc8610-pci";
312                 device_type = "pci";
313                 #interrupt-cells = <1>;
314                 #size-cells = <2>;
315                 #address-cells = <3>;
316                 reg = <0xe0008000 0x1000>;
317                 bus-range = <0 0>;
318                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
319                           0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
320                 clock-frequency = <33333333>;
321                 interrupt-parent = <&mpic>;
322                 interrupts = <24 2>;
323                 interrupt-map-mask = <0xf800 0 0 7>;
324                 interrupt-map = <
325                         /* IDSEL 0x11 */
326                         0x8800 0 0 1 &mpic 4 1
327                         0x8800 0 0 2 &mpic 5 1
328                         0x8800 0 0 3 &mpic 6 1
329                         0x8800 0 0 4 &mpic 7 1
330
331                         /* IDSEL 0x12 */
332                         0x9000 0 0 1 &mpic 5 1
333                         0x9000 0 0 2 &mpic 6 1
334                         0x9000 0 0 3 &mpic 7 1
335                         0x9000 0 0 4 &mpic 4 1
336                         >;
337         };
338
339         pci1: pcie@e000a000 {
340                 cell-index = <1>;
341                 compatible = "fsl,mpc8641-pcie";
342                 device_type = "pci";
343                 #interrupt-cells = <1>;
344                 #size-cells = <2>;
345                 #address-cells = <3>;
346                 reg = <0xe000a000 0x1000>;
347                 bus-range = <1 3>;
348                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
349                           0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
350                 clock-frequency = <33333333>;
351                 interrupt-parent = <&mpic>;
352                 interrupts = <26 2>;
353                 interrupt-map-mask = <0xf800 0 0 7>;
354
355                 interrupt-map = <
356                         /* IDSEL 0x1b */
357                         0xd800 0 0 1 &mpic 2 1
358
359                         /* IDSEL 0x1c*/
360                         0xe000 0 0 1 &mpic 1 1
361                         0xe000 0 0 2 &mpic 1 1
362                         0xe000 0 0 3 &mpic 1 1
363                         0xe000 0 0 4 &mpic 1 1
364
365                         /* IDSEL 0x1f */
366                         0xf800 0 0 1 &mpic 3 2
367                         0xf800 0 0 2 &mpic 0 1
368                 >;
369
370                 pcie@0 {
371                         reg = <0 0 0 0 0>;
372                         #size-cells = <2>;
373                         #address-cells = <3>;
374                         device_type = "pci";
375                         ranges = <0x02000000 0x0 0xa0000000
376                                   0x02000000 0x0 0xa0000000
377                                   0x0 0x10000000
378                                   0x01000000 0x0 0x00000000
379                                   0x01000000 0x0 0x00000000
380                                   0x0 0x00100000>;
381                         uli1575@0 {
382                                 reg = <0 0 0 0 0>;
383                                 #size-cells = <2>;
384                                 #address-cells = <3>;
385                                 ranges = <0x02000000 0x0 0xa0000000
386                                           0x02000000 0x0 0xa0000000
387                                           0x0 0x10000000
388                                           0x01000000 0x0 0x00000000
389                                           0x01000000 0x0 0x00000000
390                                           0x0 0x00100000>;
391
392                                 isa@1e {
393                                         device_type = "isa";
394                                         #size-cells = <1>;
395                                         #address-cells = <2>;
396                                         reg = <0xf000 0 0 0 0>;
397                                         ranges = <1 0 0x01000000 0 0
398                                                   0x00001000>;
399
400                                         rtc@70 {
401                                                 compatible = "pnpPNP,b00";
402                                                 reg = <1 0x70 2>;
403                                         };
404                                 };
405                         };
406                 };
407         };
408
409         pci2: pcie@e0009000 {
410                 #address-cells = <3>;
411                 #size-cells = <2>;
412                 #interrupt-cells = <1>;
413                 device_type = "pci";
414                 compatible = "fsl,mpc8641-pcie";
415                 reg = <0xe0009000 0x00001000>;
416                 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
417                           0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
418                 bus-range = <0 255>;
419                 interrupt-map-mask = <0xf800 0 0 7>;
420                 interrupt-map = <0x0000 0 0 1 &mpic 4 1
421                                  0x0000 0 0 2 &mpic 5 1
422                                  0x0000 0 0 3 &mpic 6 1
423                                  0x0000 0 0 4 &mpic 7 1>;
424                 interrupt-parent = <&mpic>;
425                 interrupts = <25 2>;
426                 clock-frequency = <33333333>;
427         };
428 };