2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/errno.h>
15 #include <linux/string.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22 #include <linux/console.h>
23 #include <linux/backlight.h>
29 #include <asm/pci-bridge.h>
31 #ifdef CONFIG_BOOTX_TEXT
32 #include <asm/btext.h>
40 #undef CONFIG_FB_NVIDIA_DEBUG
41 #ifdef CONFIG_FB_NVIDIA_DEBUG
42 #define NVTRACE printk
44 #define NVTRACE if (0) printk
47 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
48 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
50 #ifdef CONFIG_FB_NVIDIA_DEBUG
51 #define assert(expr) \
53 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
54 #expr,__FILE__,__FUNCTION__,__LINE__); \
61 #define PFX "nvidiafb: "
63 /* HW cursor parameters */
66 static struct pci_device_id nvidiafb_pci_tbl[] = {
67 {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
68 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0},
71 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
73 /* command line data, set in nvidiafb_setup() */
74 static int flatpanel __devinitdata = -1; /* Autodetect later */
75 static int fpdither __devinitdata = -1;
76 static int forceCRTC __devinitdata = -1;
77 static int hwcur __devinitdata = 0;
78 static int noaccel __devinitdata = 0;
79 static int noscale __devinitdata = 0;
80 static int paneltweak __devinitdata = 0;
81 static int vram __devinitdata = 0;
82 static int bpp __devinitdata = 8;
84 static int nomtrr __devinitdata = 0;
86 #ifdef CONFIG_PMAC_BACKLIGHT
87 static int backlight __devinitdata = 1;
89 static int backlight __devinitdata = 0;
92 static char *mode_option __devinitdata = NULL;
94 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
95 .type = FB_TYPE_PACKED_PIXELS,
100 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
110 .activate = FB_ACTIVATE_NOW,
120 .vmode = FB_VMODE_NONINTERLACED
123 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
124 u16 bg, u16 fg, u32 w, u32 h)
126 u32 *data = (u32 *) data8;
132 for (i = 0; i < h; i++) {
136 for (j = 0; j < w / 2; j++) {
138 #if defined (__BIG_ENDIAN)
139 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
141 tmp |= (b & (1 << 31)) ? fg : bg;
144 tmp = (b & 1) ? fg : bg;
146 tmp |= (b & 1) ? fg << 16 : bg << 16;
149 NV_WR32(&par->CURSOR[k++], 0, tmp);
151 k += (MAX_CURS - w) / 2;
155 static void nvidia_write_clut(struct nvidia_par *par,
156 u8 regnum, u8 red, u8 green, u8 blue)
158 NVWriteDacMask(par, 0xff);
159 NVWriteDacWriteAddr(par, regnum);
160 NVWriteDacData(par, red);
161 NVWriteDacData(par, green);
162 NVWriteDacData(par, blue);
165 static void nvidia_read_clut(struct nvidia_par *par,
166 u8 regnum, u8 * red, u8 * green, u8 * blue)
168 NVWriteDacMask(par, 0xff);
169 NVWriteDacReadAddr(par, regnum);
170 *red = NVReadDacData(par);
171 *green = NVReadDacData(par);
172 *blue = NVReadDacData(par);
175 static int nvidia_panel_tweak(struct nvidia_par *par,
176 struct _riva_hw_state *state)
180 if (par->paneltweak) {
181 tweak = par->paneltweak;
183 /* begin flat panel hacks */
184 /* This is unfortunate, but some chips need this register
185 tweaked or else you get artifacts where adjacent pixels are
186 swapped. There are no hard rules for what to set here so all
187 we can do is experiment and apply hacks. */
189 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
190 /* At least one NV34 laptop needs this workaround. */
194 if((par->Chipset & 0xfff0) == 0x0310) {
197 /* end flat panel hacks */
203 static void nvidia_screen_off(struct nvidia_par *par, int on)
209 * Turn off screen and disable sequencer.
211 tmp = NVReadSeq(par, 0x01);
213 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
214 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
217 * Reenable sequencer, then turn on screen.
220 tmp = NVReadSeq(par, 0x01);
222 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
223 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
227 static void nvidia_save_vga(struct nvidia_par *par,
228 struct _riva_hw_state *state)
233 NVLockUnlock(par, 0);
235 NVUnloadStateExt(par, state);
237 state->misc_output = NVReadMiscOut(par);
239 for (i = 0; i < NUM_CRT_REGS; i++)
240 state->crtc[i] = NVReadCrtc(par, i);
242 for (i = 0; i < NUM_ATC_REGS; i++)
243 state->attr[i] = NVReadAttr(par, i);
245 for (i = 0; i < NUM_GRC_REGS; i++)
246 state->gra[i] = NVReadGr(par, i);
248 for (i = 0; i < NUM_SEQ_REGS; i++)
249 state->seq[i] = NVReadSeq(par, i);
255 static void nvidia_write_regs(struct nvidia_par *par,
256 struct _riva_hw_state *state)
262 NVLoadStateExt(par, state);
264 NVWriteMiscOut(par, state->misc_output);
266 for (i = 1; i < NUM_SEQ_REGS; i++) {
268 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
270 NVWriteSeq(par, i, state->seq[i]);
273 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
274 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
276 for (i = 0; i < NUM_CRT_REGS; i++) {
283 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
285 NVWriteCrtc(par, i, state->crtc[i]);
289 for (i = 0; i < NUM_GRC_REGS; i++) {
291 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
293 NVWriteGr(par, i, state->gra[i]);
296 for (i = 0; i < NUM_ATC_REGS; i++) {
298 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
300 NVWriteAttr(par, i, state->attr[i]);
306 static int nvidia_calc_regs(struct fb_info *info)
308 struct nvidia_par *par = info->par;
309 struct _riva_hw_state *state = &par->ModeReg;
310 int i, depth = fb_get_color_depth(&info->var, &info->fix);
311 int h_display = info->var.xres / 8 - 1;
312 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
313 int h_end = (info->var.xres + info->var.right_margin +
314 info->var.hsync_len) / 8 - 1;
315 int h_total = (info->var.xres + info->var.right_margin +
316 info->var.hsync_len + info->var.left_margin) / 8 - 5;
317 int h_blank_s = h_display;
318 int h_blank_e = h_total + 4;
319 int v_display = info->var.yres - 1;
320 int v_start = info->var.yres + info->var.lower_margin - 1;
321 int v_end = (info->var.yres + info->var.lower_margin +
322 info->var.vsync_len) - 1;
323 int v_total = (info->var.yres + info->var.lower_margin +
324 info->var.vsync_len + info->var.upper_margin) - 2;
325 int v_blank_s = v_display;
326 int v_blank_e = v_total + 1;
329 * Set all CRTC values.
332 if (info->var.vmode & FB_VMODE_INTERLACED)
335 if (par->FlatPanel == 1) {
336 v_start = v_total - 3;
339 h_start = h_total - 5;
341 h_blank_e = h_total + 4;
344 state->crtc[0x0] = Set8Bits(h_total);
345 state->crtc[0x1] = Set8Bits(h_display);
346 state->crtc[0x2] = Set8Bits(h_blank_s);
347 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
349 state->crtc[0x4] = Set8Bits(h_start);
350 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
351 | SetBitField(h_end, 4: 0, 4:0);
352 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
353 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
354 | SetBitField(v_display, 8: 8, 1:1)
355 | SetBitField(v_start, 8: 8, 2:2)
356 | SetBitField(v_blank_s, 8: 8, 3:3)
358 | SetBitField(v_total, 9: 9, 5:5)
359 | SetBitField(v_display, 9: 9, 6:6)
360 | SetBitField(v_start, 9: 9, 7:7);
361 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
363 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
364 state->crtc[0x10] = Set8Bits(v_start);
365 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
366 state->crtc[0x12] = Set8Bits(v_display);
367 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
368 (info->var.bits_per_pixel / 8));
369 state->crtc[0x15] = Set8Bits(v_blank_s);
370 state->crtc[0x16] = Set8Bits(v_blank_e);
372 state->attr[0x10] = 0x01;
375 state->attr[0x11] = 0x00;
377 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
378 | SetBitField(v_blank_s, 10: 10, 3:3)
379 | SetBitField(v_start, 10: 10, 2:2)
380 | SetBitField(v_display, 10: 10, 1:1)
381 | SetBitField(v_total, 10: 10, 0:0);
383 state->horiz = SetBitField(h_total, 8: 8, 0:0)
384 | SetBitField(h_display, 8: 8, 1:1)
385 | SetBitField(h_blank_s, 8: 8, 2:2)
386 | SetBitField(h_start, 8: 8, 3:3);
388 state->extra = SetBitField(v_total, 11: 11, 0:0)
389 | SetBitField(v_display, 11: 11, 2:2)
390 | SetBitField(v_start, 11: 11, 4:4)
391 | SetBitField(v_blank_s, 11: 11, 6:6);
393 if (info->var.vmode & FB_VMODE_INTERLACED) {
394 h_total = (h_total >> 1) & ~1;
395 state->interlace = Set8Bits(h_total);
396 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
398 state->interlace = 0xff; /* interlace off */
402 * Calculate the extended registers.
410 if (par->Architecture >= NV_ARCH_10)
411 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
414 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
415 state->misc_output &= ~0x40;
417 state->misc_output |= 0x40;
418 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
419 state->misc_output &= ~0x80;
421 state->misc_output |= 0x80;
423 NVCalcStateExt(par, state, i, info->var.xres_virtual,
424 info->var.xres, info->var.yres_virtual,
425 1000000000 / info->var.pixclock, info->var.vmode);
427 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
428 if (par->FlatPanel == 1) {
429 state->pixel |= (1 << 7);
431 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
432 || (par->fpHeight <= info->var.yres)) {
433 state->scale |= (1 << 8);
436 if (!par->crtcSync_read) {
437 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
438 par->crtcSync_read = 1;
441 par->PanelTweak = nvidia_panel_tweak(par, state);
444 state->vpll = state->pll;
445 state->vpll2 = state->pll;
446 state->vpllB = state->pllB;
447 state->vpll2B = state->pllB;
449 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
450 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
452 if (par->CRTCnumber) {
453 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
454 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
455 state->crtcOwner = 3;
456 state->pllsel |= 0x20000800;
457 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
458 if (par->twoStagePLL)
459 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
460 } else if (par->twoHeads) {
461 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
462 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
463 state->crtcOwner = 0;
464 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
465 if (par->twoStagePLL)
466 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
469 state->cursorConfig = 0x00000100;
471 if (info->var.vmode & FB_VMODE_DOUBLE)
472 state->cursorConfig |= (1 << 4);
474 if (par->alphaCursor) {
475 if ((par->Chipset & 0x0ff0) != 0x0110)
476 state->cursorConfig |= 0x04011000;
478 state->cursorConfig |= 0x14011000;
479 state->general |= (1 << 29);
481 state->cursorConfig |= 0x02000000;
484 if ((par->Chipset & 0x0ff0) == 0x0110) {
485 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
488 state->dither |= 0x00010000;
490 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
498 state->displayV = info->var.xres;
503 static void nvidia_init_vga(struct fb_info *info)
505 struct nvidia_par *par = info->par;
506 struct _riva_hw_state *state = &par->ModeReg;
509 for (i = 0; i < 0x10; i++)
511 state->attr[0x10] = 0x41;
512 state->attr[0x11] = 0xff;
513 state->attr[0x12] = 0x0f;
514 state->attr[0x13] = 0x00;
515 state->attr[0x14] = 0x00;
517 memset(state->crtc, 0x00, NUM_CRT_REGS);
518 state->crtc[0x0a] = 0x20;
519 state->crtc[0x17] = 0xe3;
520 state->crtc[0x18] = 0xff;
521 state->crtc[0x28] = 0x40;
523 memset(state->gra, 0x00, NUM_GRC_REGS);
524 state->gra[0x05] = 0x40;
525 state->gra[0x06] = 0x05;
526 state->gra[0x07] = 0x0f;
527 state->gra[0x08] = 0xff;
529 state->seq[0x00] = 0x03;
530 state->seq[0x01] = 0x01;
531 state->seq[0x02] = 0x0f;
532 state->seq[0x03] = 0x00;
533 state->seq[0x04] = 0x0e;
535 state->misc_output = 0xeb;
538 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
540 struct nvidia_par *par = info->par;
541 u8 data[MAX_CURS * MAX_CURS / 8];
542 int i, set = cursor->set;
545 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
548 NVShowHideCursor(par, 0);
550 if (par->cursor_reset) {
552 par->cursor_reset = 0;
555 if (set & FB_CUR_SETSIZE)
556 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
558 if (set & FB_CUR_SETPOS) {
561 yy = cursor->image.dy - info->var.yoffset;
562 xx = cursor->image.dx - info->var.xoffset;
566 NV_WR32(par->PRAMDAC, 0x0000300, temp);
569 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
570 u32 bg_idx = cursor->image.bg_color;
571 u32 fg_idx = cursor->image.fg_color;
572 u32 s_pitch = (cursor->image.width + 7) >> 3;
573 u32 d_pitch = MAX_CURS / 8;
574 u8 *dat = (u8 *) cursor->image.data;
575 u8 *msk = (u8 *) cursor->mask;
578 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
581 switch (cursor->rop) {
583 for (i = 0; i < s_pitch * cursor->image.height; i++)
584 src[i] = dat[i] ^ msk[i];
588 for (i = 0; i < s_pitch * cursor->image.height; i++)
589 src[i] = dat[i] & msk[i];
593 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
594 cursor->image.height);
596 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
597 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
598 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
600 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
601 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
602 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
604 NVLockUnlock(par, 0);
606 nvidiafb_load_cursor_image(par, data, bg, fg,
608 cursor->image.height);
614 NVShowHideCursor(par, 1);
619 static int nvidiafb_set_par(struct fb_info *info)
621 struct nvidia_par *par = info->par;
625 NVLockUnlock(par, 1);
626 if (!par->FlatPanel || !par->twoHeads)
629 if (par->FPDither < 0) {
630 if ((par->Chipset & 0x0ff0) == 0x0110)
631 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
634 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
635 printk(KERN_INFO PFX "Flat panel dithering %s\n",
636 par->FPDither ? "enabled" : "disabled");
639 info->fix.visual = (info->var.bits_per_pixel == 8) ?
640 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
642 nvidia_init_vga(info);
643 nvidia_calc_regs(info);
645 NVLockUnlock(par, 0);
647 VGA_WR08(par->PCIO, 0x03D4, 0x44);
648 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
649 NVLockUnlock(par, 0);
652 nvidia_screen_off(par, 1);
654 nvidia_write_regs(par, &par->ModeReg);
655 NVSetStartAddress(par, 0);
657 #if defined (__BIG_ENDIAN)
658 /* turn on LFB swapping */
662 VGA_WR08(par->PCIO, 0x3d4, 0x46);
663 tmp = VGA_RD08(par->PCIO, 0x3d5);
665 VGA_WR08(par->PCIO, 0x3d5, tmp);
669 info->fix.line_length = (info->var.xres_virtual *
670 info->var.bits_per_pixel) >> 3;
671 if (info->var.accel_flags) {
672 info->fbops->fb_imageblit = nvidiafb_imageblit;
673 info->fbops->fb_fillrect = nvidiafb_fillrect;
674 info->fbops->fb_copyarea = nvidiafb_copyarea;
675 info->fbops->fb_sync = nvidiafb_sync;
676 info->pixmap.scan_align = 4;
677 info->flags &= ~FBINFO_HWACCEL_DISABLED;
678 NVResetGraphics(info);
680 info->fbops->fb_imageblit = cfb_imageblit;
681 info->fbops->fb_fillrect = cfb_fillrect;
682 info->fbops->fb_copyarea = cfb_copyarea;
683 info->fbops->fb_sync = NULL;
684 info->pixmap.scan_align = 1;
685 info->flags |= FBINFO_HWACCEL_DISABLED;
688 par->cursor_reset = 1;
690 nvidia_screen_off(par, 0);
692 #ifdef CONFIG_BOOTX_TEXT
693 /* Update debug text engine */
694 btext_update_display(info->fix.smem_start,
695 info->var.xres, info->var.yres,
696 info->var.bits_per_pixel, info->fix.line_length);
699 NVLockUnlock(par, 0);
704 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
705 unsigned blue, unsigned transp,
706 struct fb_info *info)
708 struct nvidia_par *par = info->par;
712 if (regno >= (1 << info->var.green.length))
715 if (info->var.grayscale) {
716 /* gray = 0.30*R + 0.59*G + 0.11*B */
717 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
720 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
721 ((u32 *) info->pseudo_palette)[regno] =
722 (regno << info->var.red.offset) |
723 (regno << info->var.green.offset) |
724 (regno << info->var.blue.offset);
727 switch (info->var.bits_per_pixel) {
729 /* "transparent" stuff is completely ignored. */
730 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
733 if (info->var.green.length == 5) {
734 for (i = 0; i < 8; i++) {
735 nvidia_write_clut(par, regno * 8 + i, red >> 8,
736 green >> 8, blue >> 8);
742 for (i = 0; i < 8; i++) {
743 nvidia_write_clut(par, regno * 8 + i,
744 red >> 8, green >> 8,
749 nvidia_read_clut(par, regno * 4, &r, &g, &b);
751 for (i = 0; i < 4; i++)
752 nvidia_write_clut(par, regno * 4 + i, r,
757 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
768 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
769 struct fb_info *info)
771 struct nvidia_par *par = info->par;
772 int memlen, vramlen, mode_valid = 0;
777 var->transp.offset = 0;
778 var->transp.length = 0;
782 if (var->bits_per_pixel <= 8)
783 var->bits_per_pixel = 8;
784 else if (var->bits_per_pixel <= 16)
785 var->bits_per_pixel = 16;
787 var->bits_per_pixel = 32;
789 switch (var->bits_per_pixel) {
793 var->green.offset = 0;
794 var->green.length = 8;
795 var->blue.offset = 0;
796 var->blue.length = 8;
797 var->transp.offset = 0;
798 var->transp.length = 0;
801 var->green.length = (var->green.length < 6) ? 5 : 6;
803 var->blue.length = 5;
804 var->transp.length = 6 - var->green.length;
805 var->blue.offset = 0;
806 var->green.offset = 5;
807 var->red.offset = 5 + var->green.length;
808 var->transp.offset = (5 + var->red.offset) & 15;
810 case 32: /* RGBA 8888 */
811 var->red.offset = 16;
813 var->green.offset = 8;
814 var->green.length = 8;
815 var->blue.offset = 0;
816 var->blue.length = 8;
817 var->transp.length = 8;
818 var->transp.offset = 24;
822 var->red.msb_right = 0;
823 var->green.msb_right = 0;
824 var->blue.msb_right = 0;
825 var->transp.msb_right = 0;
827 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
828 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
831 /* calculate modeline if supported by monitor */
832 if (!mode_valid && info->monspecs.gtf) {
833 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
838 const struct fb_videomode *mode;
840 mode = fb_find_best_mode(var, &info->modelist);
842 fb_videomode_to_var(var, mode);
847 if (!mode_valid && info->monspecs.modedb_len)
850 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
851 par->fpHeight < var->yres))
854 if (var->yres_virtual < var->yres)
855 var->yres_virtual = var->yres;
857 if (var->xres_virtual < var->xres)
858 var->xres_virtual = var->xres;
860 var->xres_virtual = (var->xres_virtual + 63) & ~63;
862 vramlen = info->screen_size;
863 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
864 memlen = pitch * var->yres_virtual;
866 if (memlen > vramlen) {
867 var->yres_virtual = vramlen / pitch;
869 if (var->yres_virtual < var->yres) {
870 var->yres_virtual = var->yres;
871 var->xres_virtual = vramlen / var->yres_virtual;
872 var->xres_virtual /= var->bits_per_pixel / 8;
873 var->xres_virtual &= ~63;
874 pitch = (var->xres_virtual *
875 var->bits_per_pixel + 7) / 8;
876 memlen = pitch * var->yres;
878 if (var->xres_virtual < var->xres) {
879 printk("nvidiafb: required video memory, "
880 "%d bytes, for %dx%d-%d (virtual) "
882 memlen, var->xres_virtual,
883 var->yres_virtual, var->bits_per_pixel);
889 if (var->accel_flags) {
890 if (var->yres_virtual > 0x7fff)
891 var->yres_virtual = 0x7fff;
892 if (var->xres_virtual > 0x7fff)
893 var->xres_virtual = 0x7fff;
896 var->xres_virtual &= ~63;
903 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
904 struct fb_info *info)
906 struct nvidia_par *par = info->par;
909 total = var->yoffset * info->fix.line_length + var->xoffset;
911 NVSetStartAddress(par, total);
916 static int nvidiafb_blank(int blank, struct fb_info *info)
918 struct nvidia_par *par = info->par;
919 unsigned char tmp, vesa;
921 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
922 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
930 case FB_BLANK_UNBLANK:
931 case FB_BLANK_NORMAL:
933 case FB_BLANK_VSYNC_SUSPEND:
936 case FB_BLANK_HSYNC_SUSPEND:
939 case FB_BLANK_POWERDOWN:
944 NVWriteSeq(par, 0x01, tmp);
945 NVWriteCrtc(par, 0x1a, vesa);
953 * Because the VGA registers are not mapped linearly in its MMIO space,
954 * restrict VGA register saving and restore to x86 only, where legacy VGA IO
955 * access is legal. Consequently, we must also check if the device is the
959 static void save_vga_x86(struct nvidia_par *par)
961 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
963 if (res && res->flags & IORESOURCE_ROM_SHADOW) {
964 memset(&par->vgastate, 0, sizeof(par->vgastate));
965 par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS |
967 save_vga(&par->vgastate);
971 static void restore_vga_x86(struct nvidia_par *par)
973 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
975 if (res && res->flags & IORESOURCE_ROM_SHADOW)
976 restore_vga(&par->vgastate);
979 #define save_vga_x86(x) do {} while (0)
980 #define restore_vga_x86(x) do {} while (0)
983 static int nvidiafb_open(struct fb_info *info, int user)
985 struct nvidia_par *par = info->par;
987 mutex_lock(&par->open_lock);
989 if (!par->open_count) {
991 nvidia_save_vga(par, &par->initial_state);
995 mutex_unlock(&par->open_lock);
999 static int nvidiafb_release(struct fb_info *info, int user)
1001 struct nvidia_par *par = info->par;
1004 mutex_lock(&par->open_lock);
1006 if (!par->open_count) {
1011 if (par->open_count == 1) {
1012 nvidia_write_regs(par, &par->initial_state);
1013 restore_vga_x86(par);
1018 mutex_unlock(&par->open_lock);
1022 static struct fb_ops nvidia_fb_ops = {
1023 .owner = THIS_MODULE,
1024 .fb_open = nvidiafb_open,
1025 .fb_release = nvidiafb_release,
1026 .fb_check_var = nvidiafb_check_var,
1027 .fb_set_par = nvidiafb_set_par,
1028 .fb_setcolreg = nvidiafb_setcolreg,
1029 .fb_pan_display = nvidiafb_pan_display,
1030 .fb_blank = nvidiafb_blank,
1031 .fb_fillrect = nvidiafb_fillrect,
1032 .fb_copyarea = nvidiafb_copyarea,
1033 .fb_imageblit = nvidiafb_imageblit,
1034 .fb_cursor = nvidiafb_cursor,
1035 .fb_sync = nvidiafb_sync,
1039 static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t mesg)
1041 struct fb_info *info = pci_get_drvdata(dev);
1042 struct nvidia_par *par = info->par;
1044 if (mesg.event == PM_EVENT_PRETHAW)
1045 mesg.event = PM_EVENT_FREEZE;
1046 acquire_console_sem();
1047 par->pm_state = mesg.event;
1049 if (mesg.event == PM_EVENT_SUSPEND) {
1050 fb_set_suspend(info, 1);
1051 nvidiafb_blank(FB_BLANK_POWERDOWN, info);
1052 nvidia_write_regs(par, &par->SavedReg);
1053 pci_save_state(dev);
1054 pci_disable_device(dev);
1055 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1057 dev->dev.power.power_state = mesg;
1059 release_console_sem();
1063 static int nvidiafb_resume(struct pci_dev *dev)
1065 struct fb_info *info = pci_get_drvdata(dev);
1066 struct nvidia_par *par = info->par;
1068 acquire_console_sem();
1069 pci_set_power_state(dev, PCI_D0);
1071 if (par->pm_state != PM_EVENT_FREEZE) {
1072 pci_restore_state(dev);
1074 if (pci_enable_device(dev))
1077 pci_set_master(dev);
1080 par->pm_state = PM_EVENT_ON;
1081 nvidiafb_set_par(info);
1082 fb_set_suspend (info, 0);
1083 nvidiafb_blank(FB_BLANK_UNBLANK, info);
1086 release_console_sem();
1090 #define nvidiafb_suspend NULL
1091 #define nvidiafb_resume NULL
1094 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1096 struct fb_monspecs *specs = &info->monspecs;
1097 struct fb_videomode modedb;
1098 struct nvidia_par *par = info->par;
1102 info->flags = FBINFO_DEFAULT
1103 | FBINFO_HWACCEL_IMAGEBLIT
1104 | FBINFO_HWACCEL_FILLRECT
1105 | FBINFO_HWACCEL_COPYAREA
1106 | FBINFO_HWACCEL_YPAN;
1108 fb_videomode_to_modelist(info->monspecs.modedb,
1109 info->monspecs.modedb_len, &info->modelist);
1110 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1124 if (specs->modedb != NULL) {
1125 const struct fb_videomode *mode;
1127 mode = fb_find_best_display(specs, &info->modelist);
1128 fb_videomode_to_var(&nvidiafb_default_var, mode);
1129 nvidiafb_default_var.bits_per_pixel = bpp;
1130 } else if (par->fpWidth && par->fpHeight) {
1134 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1135 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1136 specs->modedb_len, &modedb, bpp);
1140 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1141 specs->modedb, specs->modedb_len, &modedb, bpp);
1143 info->var = nvidiafb_default_var;
1144 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1145 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1146 info->pseudo_palette = par->pseudo_palette;
1147 fb_alloc_cmap(&info->cmap, 256, 0);
1148 fb_destroy_modedb(info->monspecs.modedb);
1149 info->monspecs.modedb = NULL;
1151 /* maximize virtual vertical length */
1152 lpitch = info->var.xres_virtual *
1153 ((info->var.bits_per_pixel + 7) >> 3);
1154 info->var.yres_virtual = info->screen_size / lpitch;
1156 info->pixmap.scan_align = 4;
1157 info->pixmap.buf_align = 4;
1158 info->pixmap.access_align = 32;
1159 info->pixmap.size = 8 * 1024;
1160 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1163 info->fbops->fb_cursor = NULL;
1165 info->var.accel_flags = (!noaccel);
1167 switch (par->Architecture) {
1169 info->fix.accel = FB_ACCEL_NV4;
1172 info->fix.accel = FB_ACCEL_NV_10;
1175 info->fix.accel = FB_ACCEL_NV_20;
1178 info->fix.accel = FB_ACCEL_NV_30;
1181 info->fix.accel = FB_ACCEL_NV_40;
1187 return nvidiafb_check_var(&info->var, info);
1190 static u32 __devinit nvidia_get_chipset(struct fb_info *info)
1192 struct nvidia_par *par = info->par;
1193 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1195 printk(KERN_INFO PFX "Device ID: %x \n", id);
1197 if ((id & 0xfff0) == 0x00f0) {
1199 id = NV_RD32(par->REGS, 0x1800);
1201 if ((id & 0x0000ffff) == 0x000010DE)
1202 id = 0x10DE0000 | (id >> 16);
1203 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1204 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1205 ((id >> 8) & 0x000000ff);
1206 printk(KERN_INFO PFX "Subsystem ID: %x \n", id);
1212 static u32 __devinit nvidia_get_arch(struct fb_info *info)
1214 struct nvidia_par *par = info->par;
1217 switch (par->Chipset & 0x0ff0) {
1218 case 0x0100: /* GeForce 256 */
1219 case 0x0110: /* GeForce2 MX */
1220 case 0x0150: /* GeForce2 */
1221 case 0x0170: /* GeForce4 MX */
1222 case 0x0180: /* GeForce4 MX (8x AGP) */
1223 case 0x01A0: /* nForce */
1224 case 0x01F0: /* nForce2 */
1227 case 0x0200: /* GeForce3 */
1228 case 0x0250: /* GeForce4 Ti */
1229 case 0x0280: /* GeForce4 Ti (8x AGP) */
1232 case 0x0300: /* GeForceFX 5800 */
1233 case 0x0310: /* GeForceFX 5600 */
1234 case 0x0320: /* GeForceFX 5200 */
1235 case 0x0330: /* GeForceFX 5900 */
1236 case 0x0340: /* GeForceFX 5700 */
1239 case 0x0040: /* GeForce 6800 */
1240 case 0x00C0: /* GeForce 6800 */
1241 case 0x0120: /* GeForce 6800 */
1243 case 0x0140: /* GeForce 6600 */
1244 case 0x0160: /* GeForce 6200 */
1245 case 0x01D0: /* GeForce 7200, 7300, 7400 */
1246 case 0x0090: /* GeForce 7800 */
1247 case 0x0210: /* GeForce 6800 */
1248 case 0x0220: /* GeForce 6200 */
1250 case 0x0240: /* GeForce 6100 */
1251 case 0x0290: /* GeForce 7900 */
1252 case 0x0390: /* GeForce 7600 */
1255 case 0x0020: /* TNT, TNT2 */
1258 default: /* unknown architecture */
1265 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1266 const struct pci_device_id *ent)
1268 struct nvidia_par *par;
1269 struct fb_info *info;
1276 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1283 mutex_init(&par->open_lock);
1284 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1286 if (info->pixmap.addr == NULL)
1289 if (pci_enable_device(pd)) {
1290 printk(KERN_ERR PFX "cannot enable PCI device\n");
1291 goto err_out_enable;
1294 if (pci_request_regions(pd, "nvidiafb")) {
1295 printk(KERN_ERR PFX "cannot request PCI regions\n");
1296 goto err_out_enable;
1299 par->FlatPanel = flatpanel;
1301 printk(KERN_INFO PFX "flatpanel support enabled\n");
1302 par->FPDither = fpdither;
1304 par->CRTCnumber = forceCRTC;
1305 par->FpScale = (!noscale);
1306 par->paneltweak = paneltweak;
1308 /* enable IO and mem if not already done */
1309 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1310 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1311 pci_write_config_word(pd, PCI_COMMAND, cmd);
1313 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1314 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1315 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1317 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1320 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1321 goto err_out_free_base0;
1324 par->Chipset = nvidia_get_chipset(info);
1325 par->Architecture = nvidia_get_arch(info);
1327 if (par->Architecture == 0) {
1328 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1332 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1334 if (NVCommonSetup(info))
1337 par->FbAddress = nvidiafb_fix.smem_start;
1338 par->FbMapSize = par->RamAmountKBytes * 1024;
1339 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1340 par->FbMapSize = vram * 1024 * 1024;
1342 /* Limit amount of vram to 64 MB */
1343 if (par->FbMapSize > 64 * 1024 * 1024)
1344 par->FbMapSize = 64 * 1024 * 1024;
1346 if(par->Architecture >= NV_ARCH_40)
1347 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1349 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1350 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1352 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1353 par->CursorStart = par->FbUsableSize + (32 * 1024);
1355 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1356 info->screen_size = par->FbUsableSize;
1357 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1359 if (!info->screen_base) {
1360 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1361 goto err_out_free_base1;
1364 par->FbStart = info->screen_base;
1368 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1369 par->RamAmountKBytes * 1024,
1370 MTRR_TYPE_WRCOMB, 1);
1371 if (par->mtrr.vram < 0) {
1372 printk(KERN_ERR PFX "unable to setup MTRR\n");
1374 par->mtrr.vram_valid = 1;
1375 /* let there be speed */
1376 printk(KERN_INFO PFX "MTRR set to ON\n");
1379 #endif /* CONFIG_MTRR */
1381 info->fbops = &nvidia_fb_ops;
1382 info->fix = nvidiafb_fix;
1384 if (nvidia_set_fbinfo(info) < 0) {
1385 printk(KERN_ERR PFX "error setting initial video mode\n");
1386 goto err_out_iounmap_fb;
1389 nvidia_save_vga(par, &par->SavedReg);
1391 pci_set_drvdata(pd, info);
1394 nvidia_bl_init(par);
1396 if (register_framebuffer(info) < 0) {
1397 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1398 goto err_out_iounmap_fb;
1402 printk(KERN_INFO PFX
1403 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1405 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1411 iounmap(info->screen_base);
1413 fb_destroy_modedb(info->monspecs.modedb);
1414 nvidia_delete_i2c_busses(par);
1418 pci_release_regions(pd);
1420 kfree(info->pixmap.addr);
1422 framebuffer_release(info);
1427 static void __devexit nvidiafb_remove(struct pci_dev *pd)
1429 struct fb_info *info = pci_get_drvdata(pd);
1430 struct nvidia_par *par = info->par;
1434 unregister_framebuffer(info);
1436 nvidia_bl_exit(par);
1439 if (par->mtrr.vram_valid)
1440 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1441 info->fix.smem_len);
1442 #endif /* CONFIG_MTRR */
1444 iounmap(info->screen_base);
1445 fb_destroy_modedb(info->monspecs.modedb);
1446 nvidia_delete_i2c_busses(par);
1448 pci_release_regions(pd);
1449 kfree(info->pixmap.addr);
1450 framebuffer_release(info);
1451 pci_set_drvdata(pd, NULL);
1455 /* ------------------------------------------------------------------------- *
1459 * ------------------------------------------------------------------------- */
1462 static int __devinit nvidiafb_setup(char *options)
1467 if (!options || !*options)
1470 while ((this_opt = strsep(&options, ",")) != NULL) {
1471 if (!strncmp(this_opt, "forceCRTC", 9)) {
1477 forceCRTC = *p - '0';
1478 if (forceCRTC < 0 || forceCRTC > 1)
1480 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1482 } else if (!strncmp(this_opt, "hwcur", 5)) {
1484 } else if (!strncmp(this_opt, "noaccel", 6)) {
1486 } else if (!strncmp(this_opt, "noscale", 7)) {
1488 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1489 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1490 } else if (!strncmp(this_opt, "vram:", 5)) {
1491 vram = simple_strtoul(this_opt+5, NULL, 0);
1492 } else if (!strncmp(this_opt, "backlight:", 10)) {
1493 backlight = simple_strtoul(this_opt+10, NULL, 0);
1495 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1498 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1499 fpdither = simple_strtol(this_opt+9, NULL, 0);
1500 } else if (!strncmp(this_opt, "bpp:", 4)) {
1501 bpp = simple_strtoul(this_opt+4, NULL, 0);
1503 mode_option = this_opt;
1508 #endif /* !MODULE */
1510 static struct pci_driver nvidiafb_driver = {
1512 .id_table = nvidiafb_pci_tbl,
1513 .probe = nvidiafb_probe,
1514 .suspend = nvidiafb_suspend,
1515 .resume = nvidiafb_resume,
1516 .remove = __devexit_p(nvidiafb_remove),
1519 /* ------------------------------------------------------------------------- *
1523 * ------------------------------------------------------------------------- */
1525 static int __devinit nvidiafb_init(void)
1528 char *option = NULL;
1530 if (fb_get_options("nvidiafb", &option))
1532 nvidiafb_setup(option);
1534 return pci_register_driver(&nvidiafb_driver);
1537 module_init(nvidiafb_init);
1540 static void __exit nvidiafb_exit(void)
1542 pci_unregister_driver(&nvidiafb_driver);
1545 module_exit(nvidiafb_exit);
1547 module_param(flatpanel, int, 0);
1548 MODULE_PARM_DESC(flatpanel,
1549 "Enables experimental flat panel support for some chipsets. "
1550 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1551 module_param(fpdither, int, 0);
1552 MODULE_PARM_DESC(fpdither,
1553 "Enables dithering of flat panel for 6 bits panels. "
1554 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1555 module_param(hwcur, int, 0);
1556 MODULE_PARM_DESC(hwcur,
1557 "Enables hardware cursor implementation. (0 or 1=enabled) "
1559 module_param(noaccel, int, 0);
1560 MODULE_PARM_DESC(noaccel,
1561 "Disables hardware acceleration. (0 or 1=disable) "
1563 module_param(noscale, int, 0);
1564 MODULE_PARM_DESC(noscale,
1565 "Disables screen scaleing. (0 or 1=disable) "
1566 "(default=0, do scaling)");
1567 module_param(paneltweak, int, 0);
1568 MODULE_PARM_DESC(paneltweak,
1569 "Tweak display settings for flatpanels. "
1570 "(default=0, no tweaks)");
1571 module_param(forceCRTC, int, 0);
1572 MODULE_PARM_DESC(forceCRTC,
1573 "Forces usage of a particular CRTC in case autodetection "
1574 "fails. (0 or 1) (default=autodetect)");
1575 module_param(vram, int, 0);
1576 MODULE_PARM_DESC(vram,
1577 "amount of framebuffer memory to remap in MiB"
1578 "(default=0 - remap entire memory)");
1579 module_param(mode_option, charp, 0);
1580 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1581 module_param(bpp, int, 0);
1582 MODULE_PARM_DESC(bpp, "pixel width in bits"
1585 module_param(nomtrr, bool, 0);
1586 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1590 MODULE_AUTHOR("Antonino Daplas");
1591 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1592 MODULE_LICENSE("GPL");