2 * Frame buffer driver for Trident Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
19 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <video/trident.h>
27 #define VERSION "0.7.9-NEWAPI"
29 struct tridentfb_par {
30 void __iomem *io_virt; /* iospace virtual memory address */
36 static unsigned char eng_oper; /* engine operation... */
37 static struct fb_ops tridentfb_ops;
39 static struct fb_fix_screeninfo tridentfb_fix = {
41 .type = FB_TYPE_PACKED_PIXELS,
43 .visual = FB_VISUAL_PSEUDOCOLOR,
44 .accel = FB_ACCEL_NONE,
47 /* defaults which are normally overriden by user values */
50 static char *mode_option __devinitdata = "640x480";
51 static int bpp __devinitdata = 8;
53 static int noaccel __devinitdata;
58 static int fp __devinitdata;
59 static int crt __devinitdata;
61 static int memsize __devinitdata;
62 static int memdiff __devinitdata;
65 module_param(mode_option, charp, 0);
66 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
67 module_param_named(mode, mode_option, charp, 0);
68 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
69 module_param(bpp, int, 0);
70 module_param(center, int, 0);
71 module_param(stretch, int, 0);
72 module_param(noaccel, int, 0);
73 module_param(memsize, int, 0);
74 module_param(memdiff, int, 0);
75 module_param(nativex, int, 0);
76 module_param(fp, int, 0);
77 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
78 module_param(crt, int, 0);
79 MODULE_PARM_DESC(crt, "Define if CRT is connected");
81 static int is3Dchip(int id)
83 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
84 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
85 (id == CYBER9397) || (id == CYBER9397DVD) ||
86 (id == CYBER9520) || (id == CYBER9525DVD) ||
87 (id == IMAGE975) || (id == IMAGE985) ||
88 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
89 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
90 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
91 (id == CYBERBLADEXPAi1));
94 static int iscyber(int id)
110 case CYBERBLADEXPAi1:
118 case CYBERBLADEi7: /* VIA MPV4 integrated version */
121 /* case CYBERBLDAEXPm8: Strange */
122 /* case CYBERBLDAEXPm16: Strange */
127 #define CRT 0x3D0 /* CRTC registers offset for color display */
129 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
131 fb_writeb(val, p->io_virt + reg);
134 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
136 return fb_readb(p->io_virt + reg);
139 static struct accel_switch {
140 void (*init_accel) (struct tridentfb_par *, int, int);
141 void (*wait_engine) (struct tridentfb_par *);
143 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
145 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
148 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
150 fb_writel(v, par->io_virt + r);
153 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
155 return fb_readl(par->io_virt + r);
159 * Blade specific acceleration.
162 #define point(x, y) ((y) << 16 | (x))
174 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
176 int v1 = (pitch >> 3) << 20;
193 v2 = v1 | (tmp << 29);
194 writemmr(par, 0x21C0, v2);
195 writemmr(par, 0x21C4, v2);
196 writemmr(par, 0x21B8, v2);
197 writemmr(par, 0x21BC, v2);
198 writemmr(par, 0x21D0, v1);
199 writemmr(par, 0x21D4, v1);
200 writemmr(par, 0x21C8, v1);
201 writemmr(par, 0x21CC, v1);
202 writemmr(par, 0x216C, 0);
205 static void blade_wait_engine(struct tridentfb_par *par)
207 while (readmmr(par, STA) & 0xFA800000) ;
210 static void blade_fill_rect(struct tridentfb_par *par,
211 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
213 writemmr(par, CLR, c);
214 writemmr(par, ROP, rop ? 0x66 : ROP_S);
215 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
217 writemmr(par, DR1, point(x, y));
218 writemmr(par, DR2, point(x + w - 1, y + h - 1));
221 static void blade_copy_rect(struct tridentfb_par *par,
222 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
227 s2 = point(x1 + w - 1, y1 + h - 1);
229 d2 = point(x2 + w - 1, y2 + h - 1);
231 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
234 writemmr(par, ROP, ROP_S);
235 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
237 writemmr(par, SR1, direction ? s2 : s1);
238 writemmr(par, SR2, direction ? s1 : s2);
239 writemmr(par, DR1, direction ? d2 : d1);
240 writemmr(par, DR2, direction ? d1 : d2);
243 static struct accel_switch accel_blade = {
251 * BladeXP specific acceleration functions
255 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
257 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
277 switch (pitch << (bpp >> 3)) {
293 t_outb(par, x, 0x2125);
313 writemmr(par, 0x2154, v1);
314 writemmr(par, 0x2150, v1);
315 t_outb(par, 3, 0x2126);
318 static void xp_wait_engine(struct tridentfb_par *par)
326 busy = t_inb(par, STA) & 0x80;
330 if (count == 10000000) {
336 t_outb(par, 0x00, 0x2120);
343 static void xp_fill_rect(struct tridentfb_par *par,
344 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
346 writemmr(par, 0x2127, ROP_P);
347 writemmr(par, 0x2158, c);
348 writemmr(par, 0x2128, 0x4000);
349 writemmr(par, 0x2140, masked_point(h, w));
350 writemmr(par, 0x2138, masked_point(y, x));
351 t_outb(par, 0x01, 0x2124);
352 t_outb(par, eng_oper, 0x2125);
355 static void xp_copy_rect(struct tridentfb_par *par,
356 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
359 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
363 if ((x1 < x2) && (y1 == y2)) {
381 writemmr(par, 0x2128, direction);
382 t_outb(par, ROP_S, 0x2127);
383 writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp));
384 writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp));
385 writemmr(par, 0x2140, masked_point(h, w));
386 t_outb(par, 0x01, 0x2124);
389 static struct accel_switch accel_xp = {
397 * Image specific acceleration functions
399 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
417 writemmr(par, 0x2120, 0xF0000000);
418 writemmr(par, 0x2120, 0x40000000 | tmp);
419 writemmr(par, 0x2120, 0x80000000);
420 writemmr(par, 0x2144, 0x00000000);
421 writemmr(par, 0x2148, 0x00000000);
422 writemmr(par, 0x2150, 0x00000000);
423 writemmr(par, 0x2154, 0x00000000);
424 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
425 writemmr(par, 0x216C, 0x00000000);
426 writemmr(par, 0x2170, 0x00000000);
427 writemmr(par, 0x217C, 0x00000000);
428 writemmr(par, 0x2120, 0x10000000);
429 writemmr(par, 0x2130, (2047 << 16) | 2047);
432 static void image_wait_engine(struct tridentfb_par *par)
434 while (readmmr(par, 0x2164) & 0xF0000000) ;
437 static void image_fill_rect(struct tridentfb_par *par,
438 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
440 writemmr(par, 0x2120, 0x80000000);
441 writemmr(par, 0x2120, 0x90000000 | ROP_S);
443 writemmr(par, 0x2144, c);
445 writemmr(par, DR1, point(x, y));
446 writemmr(par, DR2, point(x + w - 1, y + h - 1));
448 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
451 static void image_copy_rect(struct tridentfb_par *par,
452 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
457 s2 = point(x1 + w - 1, y1 + h - 1);
459 d2 = point(x2 + w - 1, y2 + h - 1);
461 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
464 writemmr(par, 0x2120, 0x80000000);
465 writemmr(par, 0x2120, 0x90000000 | ROP_S);
467 writemmr(par, SR1, direction ? s2 : s1);
468 writemmr(par, SR2, direction ? s1 : s2);
469 writemmr(par, DR1, direction ? d2 : d1);
470 writemmr(par, DR2, direction ? d1 : d2);
471 writemmr(par, 0x2124,
472 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
475 static struct accel_switch accel_image = {
483 * Accel functions called by the upper layers
485 #ifdef CONFIG_FB_TRIDENT_ACCEL
486 static void tridentfb_fillrect(struct fb_info *info,
487 const struct fb_fillrect *fr)
489 struct tridentfb_par *par = info->par;
490 int bpp = info->var.bits_per_pixel;
501 col = ((u32 *)(info->pseudo_palette))[fr->color];
504 col = ((u32 *)(info->pseudo_palette))[fr->color];
508 acc->fill_rect(par, fr->dx, fr->dy, fr->width,
509 fr->height, col, fr->rop);
510 acc->wait_engine(par);
512 static void tridentfb_copyarea(struct fb_info *info,
513 const struct fb_copyarea *ca)
515 struct tridentfb_par *par = info->par;
517 acc->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
518 ca->width, ca->height);
519 acc->wait_engine(par);
521 #else /* !CONFIG_FB_TRIDENT_ACCEL */
522 #define tridentfb_fillrect cfb_fillrect
523 #define tridentfb_copyarea cfb_copyarea
524 #endif /* CONFIG_FB_TRIDENT_ACCEL */
528 * Hardware access functions
531 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
533 writeb(reg, par->io_virt + CRT + 4);
534 return readb(par->io_virt + CRT + 5);
537 static inline void write3X4(struct tridentfb_par *par, int reg,
540 writeb(reg, par->io_virt + CRT + 4);
541 writeb(val, par->io_virt + CRT + 5);
544 static inline unsigned char read3C4(struct tridentfb_par *par, int reg)
546 t_outb(par, reg, 0x3C4);
547 return t_inb(par, 0x3C5);
550 static inline void write3C4(struct tridentfb_par *par, int reg,
553 t_outb(par, reg, 0x3C4);
554 t_outb(par, val, 0x3C5);
557 static inline unsigned char read3CE(struct tridentfb_par *par, int reg)
559 t_outb(par, reg, 0x3CE);
560 return t_inb(par, 0x3CF);
563 static inline void writeAttr(struct tridentfb_par *par, int reg,
566 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
567 t_outb(par, reg, 0x3C0);
568 t_outb(par, val, 0x3C0);
571 static inline void write3CE(struct tridentfb_par *par, int reg,
574 t_outb(par, reg, 0x3CE);
575 t_outb(par, val, 0x3CF);
578 static void enable_mmio(void)
584 /* Unprotect registers */
585 outb(NewMode1, 0x3C4);
590 outb(inb(0x3D5) | 0x01, 0x3D5);
593 static void disable_mmio(struct tridentfb_par *par)
596 t_outb(par, 0x0B, 0x3C4);
599 /* Unprotect registers */
600 t_outb(par, NewMode1, 0x3C4);
601 t_outb(par, 0x80, 0x3C5);
604 t_outb(par, PCIReg, 0x3D4);
605 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
608 static void crtc_unlock(struct tridentfb_par *par)
610 write3X4(par, CRTVSyncEnd, read3X4(par, CRTVSyncEnd) & 0x7F);
613 /* Return flat panel's maximum x resolution */
614 static int __devinit get_nativex(struct tridentfb_par *par)
621 tmp = (read3CE(par, VertStretch) >> 4) & 3;
642 output("%dx%d flat panel found\n", x, y);
647 static void set_lwidth(struct tridentfb_par *par, int width)
649 write3X4(par, Offset, width & 0xFF);
650 write3X4(par, AddColReg,
651 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
654 /* For resolutions smaller than FP resolution stretch */
655 static void screen_stretch(struct tridentfb_par *par)
657 if (par->chip_id != CYBERBLADEXPAi1)
658 write3CE(par, BiosReg, 0);
660 write3CE(par, BiosReg, 8);
661 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
662 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
665 /* For resolutions smaller than FP resolution center */
666 static void screen_center(struct tridentfb_par *par)
668 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
669 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
672 /* Address of first shown pixel in display memory */
673 static void set_screen_start(struct tridentfb_par *par, int base)
676 write3X4(par, StartAddrLow, base & 0xFF);
677 write3X4(par, StartAddrHigh, (base & 0xFF00) >> 8);
678 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
679 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
680 tmp = read3X4(par, CRTHiOrd) & 0xF8;
681 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
684 /* Set dotclock frequency */
685 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
688 unsigned long f, fi, d, di;
689 unsigned char lo = 0, hi = 0;
692 for (k = 2; k >= 0; k--)
693 for (m = 0; m < 63; m++)
694 for (n = 0; n < 128; n++) {
695 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
696 if ((di = abs(fi - freq)) < d) {
705 if (is3Dchip(par->chip_id)) {
706 write3C4(par, ClockHigh, hi);
707 write3C4(par, ClockLow, lo);
712 debug("VCLK = %X %X\n", hi, lo);
715 /* Set number of lines for flat panels*/
716 static void set_number_of_lines(struct tridentfb_par *par, int lines)
718 int tmp = read3CE(par, CyberEnhance) & 0x8F;
721 else if (lines > 768)
723 else if (lines > 600)
725 else if (lines > 480)
727 write3CE(par, CyberEnhance, tmp);
731 * If we see that FP is active we assume we have one.
732 * Otherwise we have a CRT display. User can override.
734 static int __devinit is_flatpanel(struct tridentfb_par *par)
738 if (crt || !iscyber(par->chip_id))
740 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
743 /* Try detecting the video memory size */
744 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
746 unsigned char tmp, tmp2;
749 /* If memory size provided by user */
753 switch (par->chip_id) {
758 tmp = read3X4(par, SPR) & 0x0F;
774 k = 10 * Mb; /* XP */
780 k = 12 * Mb; /* XP */
783 k = 14 * Mb; /* XP */
786 k = 16 * Mb; /* XP */
790 tmp2 = read3C4(par, 0xC1);
820 output("framebuffer size = %d Kb\n", k / Kb);
824 /* See if we can handle the video mode described in var */
825 static int tridentfb_check_var(struct fb_var_screeninfo *var,
826 struct fb_info *info)
828 struct tridentfb_par *par = info->par;
829 int bpp = var->bits_per_pixel;
832 /* check color depth */
834 bpp = var->bits_per_pixel = 32;
835 /* check whether resolution fits on panel and in memory */
836 if (par->flatpanel && nativex && var->xres > nativex)
838 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
844 var->green.offset = 0;
845 var->blue.offset = 0;
847 var->green.length = 6;
848 var->blue.length = 6;
851 var->red.offset = 11;
852 var->green.offset = 5;
853 var->blue.offset = 0;
855 var->green.length = 6;
856 var->blue.length = 5;
859 var->red.offset = 16;
860 var->green.offset = 8;
861 var->blue.offset = 0;
863 var->green.length = 8;
864 var->blue.length = 8;
875 /* Pan the display */
876 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
877 struct fb_info *info)
879 struct tridentfb_par *par = info->par;
883 offset = (var->xoffset + (var->yoffset * var->xres))
884 * var->bits_per_pixel / 32;
885 info->var.xoffset = var->xoffset;
886 info->var.yoffset = var->yoffset;
887 set_screen_start(par, offset);
892 static void shadowmode_on(struct tridentfb_par *par)
894 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
897 static void shadowmode_off(struct tridentfb_par *par)
899 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
902 /* Set the hardware to the requested video mode */
903 static int tridentfb_set_par(struct fb_info *info)
905 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
906 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
907 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
908 struct fb_var_screeninfo *var = &info->var;
909 int bpp = var->bits_per_pixel;
914 hdispend = var->xres / 8 - 1;
915 hsyncstart = (var->xres + var->right_margin) / 8;
916 hsyncend = var->hsync_len / 8;
918 (var->xres + var->left_margin + var->right_margin +
919 var->hsync_len) / 8 - 10;
920 hblankstart = hdispend + 1;
921 hblankend = htotal + 5;
923 vdispend = var->yres - 1;
924 vsyncstart = var->yres + var->lower_margin;
925 vsyncend = var->vsync_len;
926 vtotal = var->upper_margin + vsyncstart + vsyncend - 2;
927 vblankstart = var->yres;
928 vblankend = vtotal + 2;
931 write3CE(par, CyberControl, 8);
933 if (par->flatpanel && var->xres < nativex) {
935 * on flat panels with native size larger
936 * than requested resolution decide whether
937 * we stretch or center
939 t_outb(par, 0xEB, 0x3C2);
949 t_outb(par, 0x2B, 0x3C2);
950 write3CE(par, CyberControl, 8);
953 /* vertical timing values */
954 write3X4(par, CRTVTotal, vtotal & 0xFF);
955 write3X4(par, CRTVDispEnd, vdispend & 0xFF);
956 write3X4(par, CRTVSyncStart, vsyncstart & 0xFF);
957 write3X4(par, CRTVSyncEnd, (vsyncend & 0x0F));
958 write3X4(par, CRTVBlankStart, vblankstart & 0xFF);
959 write3X4(par, CRTVBlankEnd, 0 /* p->vblankend & 0xFF */);
961 /* horizontal timing values */
962 write3X4(par, CRTHTotal, htotal & 0xFF);
963 write3X4(par, CRTHDispEnd, hdispend & 0xFF);
964 write3X4(par, CRTHSyncStart, hsyncstart & 0xFF);
965 write3X4(par, CRTHSyncEnd,
966 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
967 write3X4(par, CRTHBlankStart, hblankstart & 0xFF);
968 write3X4(par, CRTHBlankEnd, 0 /* (p->hblankend & 0x1F) */);
970 /* higher bits of vertical timing values */
972 if (vtotal & 0x100) tmp |= 0x01;
973 if (vdispend & 0x100) tmp |= 0x02;
974 if (vsyncstart & 0x100) tmp |= 0x04;
975 if (vblankstart & 0x100) tmp |= 0x08;
977 if (vtotal & 0x200) tmp |= 0x20;
978 if (vdispend & 0x200) tmp |= 0x40;
979 if (vsyncstart & 0x200) tmp |= 0x80;
980 write3X4(par, CRTOverflow, tmp);
982 tmp = read3X4(par, CRTHiOrd) | 0x08; /* line compare bit 10 */
983 if (vtotal & 0x400) tmp |= 0x80;
984 if (vblankstart & 0x400) tmp |= 0x40;
985 if (vsyncstart & 0x400) tmp |= 0x20;
986 if (vdispend & 0x400) tmp |= 0x10;
987 write3X4(par, CRTHiOrd, tmp);
990 if (htotal & 0x800) tmp |= 0x800 >> 11;
991 if (hblankstart & 0x800) tmp |= 0x800 >> 7;
992 write3X4(par, HorizOverflow, tmp);
995 if (vblankstart & 0x200) tmp |= 0x20;
996 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
997 write3X4(par, CRTMaxScanLine, tmp);
999 write3X4(par, CRTLineCompare, 0xFF);
1000 write3X4(par, CRTPRowScan, 0);
1001 write3X4(par, CRTModeControl, 0xC3);
1003 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1005 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1006 /* enable access extended memory */
1007 write3X4(par, CRTCModuleTest, tmp);
1009 /* enable GE for text acceleration */
1010 write3X4(par, GraphEngReg, 0x80);
1012 #ifdef CONFIG_FB_TRIDENT_ACCEL
1013 acc->init_accel(par, info->var.xres, bpp);
1031 write3X4(par, PixelBusReg, tmp);
1034 if (iscyber(par->chip_id))
1036 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1038 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1039 write3X4(par, Performance, 0x92);
1040 /* MMIO & PCI read and write burst enable */
1041 write3X4(par, PCIReg, 0x07);
1043 /* convert from picoseconds to kHz */
1044 vclk = PICOS2KHZ(info->var.pixclock);
1047 set_vclk(par, vclk);
1049 write3C4(par, 0, 3);
1050 write3C4(par, 1, 1); /* set char clock 8 dots wide */
1051 /* enable 4 maps because needed in chain4 mode */
1052 write3C4(par, 2, 0x0F);
1053 write3C4(par, 3, 0);
1054 write3C4(par, 4, 0x0E); /* memory mode enable bitmaps ?? */
1056 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1057 write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
1058 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1059 write3CE(par, 0x6, 0x05); /* graphics mode */
1060 write3CE(par, 0x7, 0x0F); /* planes? */
1062 if (par->chip_id == CYBERBLADEXPAi1) {
1063 /* This fixes snow-effect in 32 bpp */
1064 write3X4(par, CRTHSyncStart, 0x84);
1067 /* graphics mode and support 256 color modes */
1068 writeAttr(par, 0x10, 0x41);
1069 writeAttr(par, 0x12, 0x0F); /* planes */
1070 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1073 for (tmp = 0; tmp < 0x10; tmp++)
1074 writeAttr(par, tmp, tmp);
1075 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
1076 t_outb(par, 0x20, 0x3C0); /* enable attr */
1099 t_outb(par, tmp, 0x3C6);
1103 set_number_of_lines(par, info->var.yres);
1104 set_lwidth(par, info->var.xres * bpp / (4 * 16));
1105 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1106 info->fix.line_length = info->var.xres * (bpp >> 3);
1107 info->cmap.len = (bpp == 8) ? 256 : 16;
1112 /* Set one color register */
1113 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1114 unsigned blue, unsigned transp,
1115 struct fb_info *info)
1117 int bpp = info->var.bits_per_pixel;
1118 struct tridentfb_par *par = info->par;
1120 if (regno >= info->cmap.len)
1124 t_outb(par, 0xFF, 0x3C6);
1125 t_outb(par, regno, 0x3C8);
1127 t_outb(par, red >> 10, 0x3C9);
1128 t_outb(par, green >> 10, 0x3C9);
1129 t_outb(par, blue >> 10, 0x3C9);
1131 } else if (regno < 16) {
1132 if (bpp == 16) { /* RGB 565 */
1135 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1136 ((blue & 0xF800) >> 11);
1138 ((u32 *)(info->pseudo_palette))[regno] = col;
1139 } else if (bpp == 32) /* ARGB 8888 */
1140 ((u32*)info->pseudo_palette)[regno] =
1141 ((transp & 0xFF00) << 16) |
1142 ((red & 0xFF00) << 8) |
1143 ((green & 0xFF00)) |
1144 ((blue & 0xFF00) >> 8);
1147 /* debug("exit\n"); */
1151 /* Try blanking the screen.For flat panels it does nothing */
1152 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1154 unsigned char PMCont, DPMSCont;
1155 struct tridentfb_par *par = info->par;
1160 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1161 PMCont = t_inb(par, 0x83C6) & 0xFC;
1162 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1163 switch (blank_mode) {
1164 case FB_BLANK_UNBLANK:
1165 /* Screen: On, HSync: On, VSync: On */
1166 case FB_BLANK_NORMAL:
1167 /* Screen: Off, HSync: On, VSync: On */
1171 case FB_BLANK_HSYNC_SUSPEND:
1172 /* Screen: Off, HSync: Off, VSync: On */
1176 case FB_BLANK_VSYNC_SUSPEND:
1177 /* Screen: Off, HSync: On, VSync: Off */
1181 case FB_BLANK_POWERDOWN:
1182 /* Screen: Off, HSync: Off, VSync: Off */
1188 write3CE(par, PowerStatus, DPMSCont);
1189 t_outb(par, 4, 0x83C8);
1190 t_outb(par, PMCont, 0x83C6);
1194 /* let fbcon do a softblank for us */
1195 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1198 static struct fb_ops tridentfb_ops = {
1199 .owner = THIS_MODULE,
1200 .fb_setcolreg = tridentfb_setcolreg,
1201 .fb_pan_display = tridentfb_pan_display,
1202 .fb_blank = tridentfb_blank,
1203 .fb_check_var = tridentfb_check_var,
1204 .fb_set_par = tridentfb_set_par,
1205 .fb_fillrect = tridentfb_fillrect,
1206 .fb_copyarea = tridentfb_copyarea,
1207 .fb_imageblit = cfb_imageblit,
1210 static int __devinit trident_pci_probe(struct pci_dev *dev,
1211 const struct pci_device_id *id)
1214 unsigned char revision;
1215 struct fb_info *info;
1216 struct tridentfb_par *default_par;
1221 err = pci_enable_device(dev);
1225 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1228 default_par = info->par;
1230 chip_id = id->device;
1232 if (chip_id == CYBERBLADEi1)
1233 output("*** Please do use cyblafb, Cyberblade/i1 support "
1234 "will soon be removed from tridentfb!\n");
1237 /* If PCI id is 0x9660 then further detect chip type */
1239 if (chip_id == TGUI9660) {
1240 outb(RevisionID, 0x3C4);
1241 revision = inb(0x3C5);
1246 chip_id = CYBER9397;
1249 chip_id = CYBER9397DVD;
1258 chip_id = CYBER9385;
1261 chip_id = CYBER9382;
1264 chip_id = CYBER9388;
1271 chip3D = is3Dchip(chip_id);
1273 if (is_xp(chip_id)) {
1275 } else if (is_blade(chip_id)) {
1281 default_par->chip_id = chip_id;
1283 /* acceleration is on by default for 3D chips */
1284 defaultaccel = chip3D && !noaccel;
1286 /* setup MMIO region */
1287 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1288 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1290 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1291 debug("request_region failed!\n");
1295 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1296 tridentfb_fix.mmio_len);
1298 if (!default_par->io_virt) {
1299 debug("ioremap failed\n");
1306 /* setup framebuffer memory */
1307 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1308 tridentfb_fix.smem_len = get_memsize(default_par);
1310 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1311 debug("request_mem_region failed!\n");
1312 disable_mmio(info->par);
1317 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1318 tridentfb_fix.smem_len);
1320 if (!info->screen_base) {
1321 debug("ioremap failed\n");
1326 output("%s board found\n", pci_name(dev));
1327 default_par->flatpanel = is_flatpanel(default_par);
1329 if (default_par->flatpanel)
1330 nativex = get_nativex(default_par);
1332 info->fix = tridentfb_fix;
1333 info->fbops = &tridentfb_ops;
1336 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1337 #ifdef CONFIG_FB_TRIDENT_ACCEL
1338 info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1340 if (!fb_find_mode(&info->var, info,
1341 mode_option, NULL, 0, NULL, bpp)) {
1345 err = fb_alloc_cmap(&info->cmap, 256, 0);
1349 if (defaultaccel && acc)
1350 info->var.accel_flags |= FB_ACCELF_TEXT;
1352 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1353 info->var.activate |= FB_ACTIVATE_NOW;
1354 info->device = &dev->dev;
1355 if (register_framebuffer(info) < 0) {
1356 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1357 fb_dealloc_cmap(&info->cmap);
1361 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1362 info->node, info->fix.id, info->var.xres,
1363 info->var.yres, info->var.bits_per_pixel);
1365 pci_set_drvdata(dev, info);
1369 if (info->screen_base)
1370 iounmap(info->screen_base);
1371 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1372 disable_mmio(info->par);
1374 if (default_par->io_virt)
1375 iounmap(default_par->io_virt);
1376 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1377 framebuffer_release(info);
1381 static void __devexit trident_pci_remove(struct pci_dev *dev)
1383 struct fb_info *info = pci_get_drvdata(dev);
1384 struct tridentfb_par *par = info->par;
1386 unregister_framebuffer(info);
1387 iounmap(par->io_virt);
1388 iounmap(info->screen_base);
1389 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1390 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1391 pci_set_drvdata(dev, NULL);
1392 framebuffer_release(info);
1395 /* List of boards that we are trying to support */
1396 static struct pci_device_id trident_devices[] = {
1397 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1398 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1399 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1400 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1401 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1402 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1403 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1404 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1405 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1406 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1407 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1408 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1409 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1410 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1411 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1412 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1413 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1414 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1415 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1416 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1420 MODULE_DEVICE_TABLE(pci, trident_devices);
1422 static struct pci_driver tridentfb_pci_driver = {
1423 .name = "tridentfb",
1424 .id_table = trident_devices,
1425 .probe = trident_pci_probe,
1426 .remove = __devexit_p(trident_pci_remove)
1430 * Parse user specified options (`video=trident:')
1432 * video=trident:800x600,bpp=16,noaccel
1435 static int __init tridentfb_setup(char *options)
1438 if (!options || !*options)
1440 while ((opt = strsep(&options, ",")) != NULL) {
1443 if (!strncmp(opt, "noaccel", 7))
1445 else if (!strncmp(opt, "fp", 2))
1447 else if (!strncmp(opt, "crt", 3))
1449 else if (!strncmp(opt, "bpp=", 4))
1450 bpp = simple_strtoul(opt + 4, NULL, 0);
1451 else if (!strncmp(opt, "center", 6))
1453 else if (!strncmp(opt, "stretch", 7))
1455 else if (!strncmp(opt, "memsize=", 8))
1456 memsize = simple_strtoul(opt + 8, NULL, 0);
1457 else if (!strncmp(opt, "memdiff=", 8))
1458 memdiff = simple_strtoul(opt + 8, NULL, 0);
1459 else if (!strncmp(opt, "nativex=", 8))
1460 nativex = simple_strtoul(opt + 8, NULL, 0);
1468 static int __init tridentfb_init(void)
1471 char *option = NULL;
1473 if (fb_get_options("tridentfb", &option))
1475 tridentfb_setup(option);
1477 output("Trident framebuffer %s initializing\n", VERSION);
1478 return pci_register_driver(&tridentfb_pci_driver);
1481 static void __exit tridentfb_exit(void)
1483 pci_unregister_driver(&tridentfb_pci_driver);
1486 module_init(tridentfb_init);
1487 module_exit(tridentfb_exit);
1489 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1490 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1491 MODULE_LICENSE("GPL");