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   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <asm/iommu.h>
  39 #include <asm/calgary.h>
  40 #include <asm/tce.h>
  41 #include <asm/pci-direct.h>
  42 #include <asm/system.h>
  43 #include <asm/dma.h>
  44 #include <asm/rio.h>
  45
  46 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  47 int use_calgary __read_mostly = 1;
  48 #else
  49 int use_calgary __read_mostly = 0;
  50 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  51
  52 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  53 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  54
  55 /* register offsets inside the host bridge space */
  56 #define CALGARY_CONFIG_REG      0x0108
  57 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  58 #define PHB_PLSSR_OFFSET        0x0120
  59 #define PHB_CONFIG_RW_OFFSET    0x0160
  60 #define PHB_IOBASE_BAR_LOW      0x0170
  61 #define PHB_IOBASE_BAR_HIGH     0x0180
  62 #define PHB_MEM_1_LOW           0x0190
  63 #define PHB_MEM_1_HIGH          0x01A0
  64 #define PHB_IO_ADDR_SIZE        0x01B0
  65 #define PHB_MEM_1_SIZE          0x01C0
  66 #define PHB_MEM_ST_OFFSET       0x01D0
  67 #define PHB_AER_OFFSET          0x0200
  68 #define PHB_CONFIG_0_HIGH       0x0220
  69 #define PHB_CONFIG_0_LOW        0x0230
  70 #define PHB_CONFIG_0_END        0x0240
  71 #define PHB_MEM_2_LOW           0x02B0
  72 #define PHB_MEM_2_HIGH          0x02C0
  73 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  74 #define PHB_MEM_2_SIZE_LOW      0x02E0
  75 #define PHB_DOSHOLE_OFFSET      0x08E0
  76
  77 /* CalIOC2 specific */
  78 #define PHB_SAVIOR_L2           0x0DB0
  79 #define PHB_PAGE_MIG_CTRL       0x0DA8
  80 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  81 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  82
  83 /* PHB_CONFIG_RW */
  84 #define PHB_TCE_ENABLE          0x20000000
  85 #define PHB_SLOT_DISABLE        0x1C000000
  86 #define PHB_DAC_DISABLE         0x01000000
  87 #define PHB_MEM2_ENABLE         0x00400000
  88 #define PHB_MCSR_ENABLE         0x00100000
  89 /* TAR (Table Address Register) */
  90 #define TAR_SW_BITS             0x0000ffffffff800fUL
  91 #define TAR_VALID               0x0000000000000008UL
  92 /* CSR (Channel/DMA Status Register) */
  93 #define CSR_AGENT_MASK          0xffe0ffff
  94 /* CCR (Calgary Configuration Register) */
  95 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  96 /* PMCR/PMDR (Page Migration Control/Debug Registers */
  97 #define PMR_SOFTSTOP            0x80000000
  98 #define PMR_SOFTSTOPFAULT       0x40000000
  99 #define PMR_HARDSTOP            0x20000000
 100
 101 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 102 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 103 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 104 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 105 #define PHBS_PER_CALGARY        4
 106
 107 /* register offsets in Calgary's internal register space */
 108 static const unsigned long tar_offsets[] = {
 109         0x0580 /* TAR0 */,
 110         0x0588 /* TAR1 */,
 111         0x0590 /* TAR2 */,
 112         0x0598 /* TAR3 */
 113 };
 114
 115 static const unsigned long split_queue_offsets[] = {
 116         0x4870 /* SPLIT QUEUE 0 */,
 117         0x5870 /* SPLIT QUEUE 1 */,
 118         0x6870 /* SPLIT QUEUE 2 */,
 119         0x7870 /* SPLIT QUEUE 3 */
 120 };
 121
 122 static const unsigned long phb_offsets[] = {
 123         0x8000 /* PHB0 */,
 124         0x9000 /* PHB1 */,
 125         0xA000 /* PHB2 */,
 126         0xB000 /* PHB3 */
 127 };
 128
 129 /* PHB debug registers */
 130
 131 static const unsigned long phb_debug_offsets[] = {
 132         0x4000  /* PHB 0 DEBUG */,
 133         0x5000  /* PHB 1 DEBUG */,
 134         0x6000  /* PHB 2 DEBUG */,
 135         0x7000  /* PHB 3 DEBUG */
 136 };
 137
 138 /*
 139  * STUFF register for each debug PHB,
 140  * byte 1 = start bus number, byte 2 = end bus number
 141  */
 142
 143 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 144
 145 #define EMERGENCY_PAGES 32 /* = 128KB */
 146
 147 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 148 static int translate_empty_slots __read_mostly = 0;
 149 static int calgary_detected __read_mostly = 0;
 150
 151 static struct rio_table_hdr     *rio_table_hdr __initdata;
 152 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 153 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 154
 155 struct calgary_bus_info {
 156         void *tce_space;
 157         unsigned char translation_disabled;
 158         signed char phbid;
 159         void __iomem *bbar;
 160 };
 161
 162 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 163 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 164 static void calgary_dump_error_regs(struct iommu_table *tbl);
 165 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 166 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 167 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 168
 169 static struct cal_chipset_ops calgary_chip_ops = {
 170         .handle_quirks = calgary_handle_quirks,
 171         .tce_cache_blast = calgary_tce_cache_blast,
 172         .dump_error_regs = calgary_dump_error_regs
 173 };
 174
 175 static struct cal_chipset_ops calioc2_chip_ops = {
 176         .handle_quirks = calioc2_handle_quirks,
 177         .tce_cache_blast = calioc2_tce_cache_blast,
 178         .dump_error_regs = calioc2_dump_error_regs
 179 };
 180
 181 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 182
 183 /* enable this to stress test the chip's TCE cache */
 184 #ifdef CONFIG_IOMMU_DEBUG
 185 int debugging __read_mostly = 1;
 186
 187 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 188         int expected, unsigned long start, unsigned long end)
 189 {
 190         unsigned long idx = start;
 191
 192         BUG_ON(start >= end);
 193
 194         while (idx < end) {
 195                 if (!!test_bit(idx, bitmap) != expected)
 196                         return idx;
 197                 ++idx;
 198         }
 199
 200         /* all bits have the expected value */
 201         return ~0UL;
 202 }
 203 #else /* debugging is disabled */
 204 int debugging __read_mostly = 0;
 205
 206 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 207         int expected, unsigned long start, unsigned long end)
 208 {
 209         return ~0UL;
 210 }
 211
 212 #endif /* CONFIG_IOMMU_DEBUG */
 213
 214 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 215 {
 216         unsigned int npages;
 217
 218         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 219         npages >>= PAGE_SHIFT;
 220
 221         return npages;
 222 }
 223
 224 static inline int translate_phb(struct pci_dev* dev)
 225 {
 226         int disabled = bus_info[dev->bus->number].translation_disabled;
 227         return !disabled;
 228 }
 229
 230 static void iommu_range_reserve(struct iommu_table *tbl,
 231         unsigned long start_addr, unsigned int npages)
 232 {
 233         unsigned long index;
 234         unsigned long end;
 235         unsigned long badbit;
 236         unsigned long flags;
 237
 238         index = start_addr >> PAGE_SHIFT;
 239
 240         /* bail out if we're asked to reserve a region we don't cover */
 241         if (index >= tbl->it_size)
 242                 return;
 243
 244         end = index + npages;
 245         if (end > tbl->it_size) /* don't go off the table */
 246                 end = tbl->it_size;
 247
 248         spin_lock_irqsave(&tbl->it_lock, flags);
 249
 250         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 251         if (badbit != ~0UL) {
 252                 if (printk_ratelimit())
 253                         printk(KERN_ERR "Calgary: entry already allocated at "
 254                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 255                                badbit, tbl, start_addr, npages);
 256         }
 257
 258         set_bit_string(tbl->it_map, index, npages);
 259
 260         spin_unlock_irqrestore(&tbl->it_lock, flags);
 261 }
 262
 263 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 264         unsigned int npages)
 265 {
 266         unsigned long flags;
 267         unsigned long offset;
 268
 269         BUG_ON(npages == 0);
 270
 271         spin_lock_irqsave(&tbl->it_lock, flags);
 272
 273         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 274                                        tbl->it_size, npages);
 275         if (offset == ~0UL) {
 276                 tbl->chip_ops->tce_cache_blast(tbl);
 277                 offset = find_next_zero_string(tbl->it_map, 0,
 278                                                tbl->it_size, npages);
 279                 if (offset == ~0UL) {
 280                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 281                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 282                         if (panic_on_overflow)
 283                                 panic("Calgary: fix the allocator.\n");
 284                         else
 285                                 return bad_dma_address;
 286                 }
 287         }
 288
 289         set_bit_string(tbl->it_map, offset, npages);
 290         tbl->it_hint = offset + npages;
 291         BUG_ON(tbl->it_hint > tbl->it_size);
 292
 293         spin_unlock_irqrestore(&tbl->it_lock, flags);
 294
 295         return offset;
 296 }
 297
 298 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 299         unsigned int npages, int direction)
 300 {
 301         unsigned long entry;
 302         dma_addr_t ret = bad_dma_address;
 303
 304         entry = iommu_range_alloc(tbl, npages);
 305
 306         if (unlikely(entry == bad_dma_address))
 307                 goto error;
 308
 309         /* set the return dma address */
 310         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 311
 312         /* put the TCEs in the HW table */
 313         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 314                   direction);
 315
 316         return ret;
 317
 318 error:
 319         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 320                "iommu %p\n", npages, tbl);
 321         return bad_dma_address;
 322 }
 323
 324 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 325         unsigned int npages)
 326 {
 327         unsigned long entry;
 328         unsigned long badbit;
 329         unsigned long badend;
 330         unsigned long flags;
 331
 332         /* were we called with bad_dma_address? */
 333         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 334         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 335                 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
 336                        "address 0x%Lx\n", dma_addr);
 337                 WARN_ON(1);
 338                 return;
 339         }
 340
 341         entry = dma_addr >> PAGE_SHIFT;
 342
 343         BUG_ON(entry + npages > tbl->it_size);
 344
 345         tce_free(tbl, entry, npages);
 346
 347         spin_lock_irqsave(&tbl->it_lock, flags);
 348
 349         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 350         if (badbit != ~0UL) {
 351                 if (printk_ratelimit())
 352                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 353                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 354                                badbit, tbl, dma_addr, entry, npages);
 355         }
 356
 357         __clear_bit_string(tbl->it_map, entry, npages);
 358
 359         spin_unlock_irqrestore(&tbl->it_lock, flags);
 360 }
 361
 362 static inline struct iommu_table *find_iommu_table(struct device *dev)
 363 {
 364         struct pci_dev *pdev;
 365         struct pci_bus *pbus;
 366         struct iommu_table *tbl;
 367
 368         pdev = to_pci_dev(dev);
 369
 370         pbus = pdev->bus;
 371
 372         /* is the device behind a bridge? Look for the root bus */
 373         while (pbus->parent)
 374                 pbus = pbus->parent;
 375
 376         tbl = pci_iommu(pbus);
 377
 378         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 379
 380         return tbl;
 381 }
 382
 383 static void calgary_unmap_sg(struct device *dev,
 384         struct scatterlist *sglist, int nelems, int direction)
 385 {
 386         struct iommu_table *tbl = find_iommu_table(dev);
 387
 388         if (!translate_phb(to_pci_dev(dev)))
 389                 return;
 390
 391         while (nelems--) {
 392                 unsigned int npages;
 393                 dma_addr_t dma = sglist->dma_address;
 394                 unsigned int dmalen = sglist->dma_length;
 395
 396                 if (dmalen == 0)
 397                         break;
 398
 399                 npages = num_dma_pages(dma, dmalen);
 400                 iommu_free(tbl, dma, npages);
 401                 sglist++;
 402         }
 403 }
 404
 405 static int calgary_nontranslate_map_sg(struct device* dev,
 406         struct scatterlist *sg, int nelems, int direction)
 407 {
 408         int i;
 409
 410         for (i = 0; i < nelems; i++ ) {
 411                 struct scatterlist *s = &sg[i];
 412                 BUG_ON(!s->page);
 413                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 414                 s->dma_length = s->length;
 415         }
 416         return nelems;
 417 }
 418
 419 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 420         int nelems, int direction)
 421 {
 422         struct iommu_table *tbl = find_iommu_table(dev);
 423         unsigned long vaddr;
 424         unsigned int npages;
 425         unsigned long entry;
 426         int i;
 427
 428         if (!translate_phb(to_pci_dev(dev)))
 429                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 430
 431         for (i = 0; i < nelems; i++ ) {
 432                 struct scatterlist *s = &sg[i];
 433                 BUG_ON(!s->page);
 434
 435                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 436                 npages = num_dma_pages(vaddr, s->length);
 437
 438                 entry = iommu_range_alloc(tbl, npages);
 439                 if (entry == bad_dma_address) {
 440                         /* makes sure unmap knows to stop */
 441                         s->dma_length = 0;
 442                         goto error;
 443                 }
 444
 445                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 446
 447                 /* insert into HW table */
 448                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 449                           direction);
 450
 451                 s->dma_length = s->length;
 452         }
 453
 454         return nelems;
 455 error:
 456         calgary_unmap_sg(dev, sg, nelems, direction);
 457         for (i = 0; i < nelems; i++) {
 458                 sg[i].dma_address = bad_dma_address;
 459                 sg[i].dma_length = 0;
 460         }
 461         return 0;
 462 }
 463
 464 static dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 465         size_t size, int direction)
 466 {
 467         dma_addr_t dma_handle = bad_dma_address;
 468         unsigned long uaddr;
 469         unsigned int npages;
 470         struct iommu_table *tbl = find_iommu_table(dev);
 471
 472         uaddr = (unsigned long)vaddr;
 473         npages = num_dma_pages(uaddr, size);
 474
 475         if (translate_phb(to_pci_dev(dev)))
 476                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 477         else
 478                 dma_handle = virt_to_bus(vaddr);
 479
 480         return dma_handle;
 481 }
 482
 483 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 484         size_t size, int direction)
 485 {
 486         struct iommu_table *tbl = find_iommu_table(dev);
 487         unsigned int npages;
 488
 489         if (!translate_phb(to_pci_dev(dev)))
 490                 return;
 491
 492         npages = num_dma_pages(dma_handle, size);
 493         iommu_free(tbl, dma_handle, npages);
 494 }
 495
 496 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 497         dma_addr_t *dma_handle, gfp_t flag)
 498 {
 499         void *ret = NULL;
 500         dma_addr_t mapping;
 501         unsigned int npages, order;
 502         struct iommu_table *tbl = find_iommu_table(dev);
 503
 504         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 505         npages = size >> PAGE_SHIFT;
 506         order = get_order(size);
 507
 508         /* alloc enough pages (and possibly more) */
 509         ret = (void *)__get_free_pages(flag, order);
 510         if (!ret)
 511                 goto error;
 512         memset(ret, 0, size);
 513
 514         if (translate_phb(to_pci_dev(dev))) {
 515                 /* set up tces to cover the allocated range */
 516                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 517                 if (mapping == bad_dma_address)
 518                         goto free;
 519
 520                 *dma_handle = mapping;
 521         } else /* non translated slot */
 522                 *dma_handle = virt_to_bus(ret);
 523
 524         return ret;
 525
 526 free:
 527         free_pages((unsigned long)ret, get_order(size));
 528         ret = NULL;
 529 error:
 530         return ret;
 531 }
 532
 533 static const struct dma_mapping_ops calgary_dma_ops = {
 534         .alloc_coherent = calgary_alloc_coherent,
 535         .map_single = calgary_map_single,
 536         .unmap_single = calgary_unmap_single,
 537         .map_sg = calgary_map_sg,
 538         .unmap_sg = calgary_unmap_sg,
 539 };
 540
 541 static inline void __iomem * busno_to_bbar(unsigned char num)
 542 {
 543         return bus_info[num].bbar;
 544 }
 545
 546 static inline int busno_to_phbid(unsigned char num)
 547 {
 548         return bus_info[num].phbid;
 549 }
 550
 551 static inline unsigned long split_queue_offset(unsigned char num)
 552 {
 553         size_t idx = busno_to_phbid(num);
 554
 555         return split_queue_offsets[idx];
 556 }
 557
 558 static inline unsigned long tar_offset(unsigned char num)
 559 {
 560         size_t idx = busno_to_phbid(num);
 561
 562         return tar_offsets[idx];
 563 }
 564
 565 static inline unsigned long phb_offset(unsigned char num)
 566 {
 567         size_t idx = busno_to_phbid(num);
 568
 569         return phb_offsets[idx];
 570 }
 571
 572 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 573 {
 574         unsigned long target = ((unsigned long)bar) | offset;
 575         return (void __iomem*)target;
 576 }
 577
 578 static inline int is_calioc2(unsigned short device)
 579 {
 580         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 581 }
 582
 583 static inline int is_calgary(unsigned short device)
 584 {
 585         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 586 }
 587
 588 static inline int is_cal_pci_dev(unsigned short device)
 589 {
 590         return (is_calgary(device) || is_calioc2(device));
 591 }
 592
 593 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 594 {
 595         u64 val;
 596         u32 aer;
 597         int i = 0;
 598         void __iomem *bbar = tbl->bbar;
 599         void __iomem *target;
 600
 601         /* disable arbitration on the bus */
 602         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 603         aer = readl(target);
 604         writel(0, target);
 605
 606         /* read plssr to ensure it got there */
 607         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 608         val = readl(target);
 609
 610         /* poll split queues until all DMA activity is done */
 611         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 612         do {
 613                 val = readq(target);
 614                 i++;
 615         } while ((val & 0xff) != 0xff && i < 100);
 616         if (i == 100)
 617                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 618                        "continuing anyway\n");
 619
 620         /* invalidate TCE cache */
 621         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 622         writeq(tbl->tar_val, target);
 623
 624         /* enable arbitration */
 625         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 626         writel(aer, target);
 627         (void)readl(target); /* flush */
 628 }
 629
 630 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 631 {
 632         void __iomem *bbar = tbl->bbar;
 633         void __iomem *target;
 634         u64 val64;
 635         u32 val;
 636         int i = 0;
 637         int count = 1;
 638         unsigned char bus = tbl->it_busno;
 639
 640 begin:
 641         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 642                "sequence - count %d\n", bus, count);
 643
 644         /* 1. using the Page Migration Control reg set SoftStop */
 645         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 646         val = be32_to_cpu(readl(target));
 647         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 648         val |= PMR_SOFTSTOP;
 649         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 650         writel(cpu_to_be32(val), target);
 651
 652         /* 2. poll split queues until all DMA activity is done */
 653         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 654         target = calgary_reg(bbar, split_queue_offset(bus));
 655         do {
 656                 val64 = readq(target);
 657                 i++;
 658         } while ((val64 & 0xff) != 0xff && i < 100);
 659         if (i == 100)
 660                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 661                        "continuing anyway\n");
 662
 663         /* 3. poll Page Migration DEBUG for SoftStopFault */
 664         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 665         val = be32_to_cpu(readl(target));
 666         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 667
 668         /* 4. if SoftStopFault - goto (1) */
 669         if (val & PMR_SOFTSTOPFAULT) {
 670                 if (++count < 100)
 671                         goto begin;
 672                 else {
 673                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 674                                "aborting TCE cache flush sequence!\n");
 675                         return; /* pray for the best */
 676                 }
 677         }
 678
 679         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 680         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 681         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 682         val = be32_to_cpu(readl(target));
 683         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 684         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 685         val = be32_to_cpu(readl(target));
 686         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 687
 688         /* 6. invalidate TCE cache */
 689         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 690         target = calgary_reg(bbar, tar_offset(bus));
 691         writeq(tbl->tar_val, target);
 692
 693         /* 7. Re-read PMCR */
 694         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 695         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 696         val = be32_to_cpu(readl(target));
 697         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 698
 699         /* 8. Remove HardStop */
 700         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 701         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 702         val = 0;
 703         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 704         writel(cpu_to_be32(val), target);
 705         val = be32_to_cpu(readl(target));
 706         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 707 }
 708
 709 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 710         u64 limit)
 711 {
 712         unsigned int numpages;
 713
 714         limit = limit | 0xfffff;
 715         limit++;
 716
 717         numpages = ((limit - start) >> PAGE_SHIFT);
 718         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 719 }
 720
 721 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 722 {
 723         void __iomem *target;
 724         u64 low, high, sizelow;
 725         u64 start, limit;
 726         struct iommu_table *tbl = pci_iommu(dev->bus);
 727         unsigned char busnum = dev->bus->number;
 728         void __iomem *bbar = tbl->bbar;
 729
 730         /* peripheral MEM_1 region */
 731         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 732         low = be32_to_cpu(readl(target));
 733         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 734         high = be32_to_cpu(readl(target));
 735         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 736         sizelow = be32_to_cpu(readl(target));
 737
 738         start = (high << 32) | low;
 739         limit = sizelow;
 740
 741         calgary_reserve_mem_region(dev, start, limit);
 742 }
 743
 744 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 745 {
 746         void __iomem *target;
 747         u32 val32;
 748         u64 low, high, sizelow, sizehigh;
 749         u64 start, limit;
 750         struct iommu_table *tbl = pci_iommu(dev->bus);
 751         unsigned char busnum = dev->bus->number;
 752         void __iomem *bbar = tbl->bbar;
 753
 754         /* is it enabled? */
 755         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 756         val32 = be32_to_cpu(readl(target));
 757         if (!(val32 & PHB_MEM2_ENABLE))
 758                 return;
 759
 760         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 761         low = be32_to_cpu(readl(target));
 762         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 763         high = be32_to_cpu(readl(target));
 764         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 765         sizelow = be32_to_cpu(readl(target));
 766         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 767         sizehigh = be32_to_cpu(readl(target));
 768
 769         start = (high << 32) | low;
 770         limit = (sizehigh << 32) | sizelow;
 771
 772         calgary_reserve_mem_region(dev, start, limit);
 773 }
 774
 775 /*
 776  * some regions of the IO address space do not get translated, so we
 777  * must not give devices IO addresses in those regions. The regions
 778  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 779  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 780  * later.
 781  */
 782 static void __init calgary_reserve_regions(struct pci_dev *dev)
 783 {
 784         unsigned int npages;
 785         u64 start;
 786         struct iommu_table *tbl = pci_iommu(dev->bus);
 787
 788         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 789         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 790
 791         /* avoid the BIOS/VGA first 640KB-1MB region */
 792         /* for CalIOC2 - avoid the entire first MB */
 793         if (is_calgary(dev->device)) {
 794                 start = (640 * 1024);
 795                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 796         } else { /* calioc2 */
 797                 start = 0;
 798                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 799         }
 800         iommu_range_reserve(tbl, start, npages);
 801
 802         /* reserve the two PCI peripheral memory regions in IO space */
 803         calgary_reserve_peripheral_mem_1(dev);
 804         calgary_reserve_peripheral_mem_2(dev);
 805 }
 806
 807 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 808 {
 809         u64 val64;
 810         u64 table_phys;
 811         void __iomem *target;
 812         int ret;
 813         struct iommu_table *tbl;
 814
 815         /* build TCE tables for each PHB */
 816         ret = build_tce_table(dev, bbar);
 817         if (ret)
 818                 return ret;
 819
 820         tbl = pci_iommu(dev->bus);
 821         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 822         tce_free(tbl, 0, tbl->it_size);
 823
 824         if (is_calgary(dev->device))
 825                 tbl->chip_ops = &calgary_chip_ops;
 826         else if (is_calioc2(dev->device))
 827                 tbl->chip_ops = &calioc2_chip_ops;
 828         else
 829                 BUG();
 830
 831         calgary_reserve_regions(dev);
 832
 833         /* set TARs for each PHB */
 834         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 835         val64 = be64_to_cpu(readq(target));
 836
 837         /* zero out all TAR bits under sw control */
 838         val64 &= ~TAR_SW_BITS;
 839         table_phys = (u64)__pa(tbl->it_base);
 840
 841         val64 |= table_phys;
 842
 843         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 844         val64 |= (u64) specified_table_size;
 845
 846         tbl->tar_val = cpu_to_be64(val64);
 847
 848         writeq(tbl->tar_val, target);
 849         readq(target); /* flush */
 850
 851         return 0;
 852 }
 853
 854 static void __init calgary_free_bus(struct pci_dev *dev)
 855 {
 856         u64 val64;
 857         struct iommu_table *tbl = pci_iommu(dev->bus);
 858         void __iomem *target;
 859         unsigned int bitmapsz;
 860
 861         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 862         val64 = be64_to_cpu(readq(target));
 863         val64 &= ~TAR_SW_BITS;
 864         writeq(cpu_to_be64(val64), target);
 865         readq(target); /* flush */
 866
 867         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 868         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 869         tbl->it_map = NULL;
 870
 871         kfree(tbl);
 872
 873         set_pci_iommu(dev->bus, NULL);
 874
 875         /* Can't free bootmem allocated memory after system is up :-( */
 876         bus_info[dev->bus->number].tce_space = NULL;
 877 }
 878
 879 static void calgary_dump_error_regs(struct iommu_table *tbl)
 880 {
 881         void __iomem *bbar = tbl->bbar;
 882         void __iomem *target;
 883         u32 csr, plssr;
 884
 885         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 886         csr = be32_to_cpu(readl(target));
 887
 888         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 889         plssr = be32_to_cpu(readl(target));
 890
 891         /* If no error, the agent ID in the CSR is not valid */
 892         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 893                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 894 }
 895
 896 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 897 {
 898         void __iomem *bbar = tbl->bbar;
 899         u32 csr, csmr, plssr, mck, rcstat;
 900         void __iomem *target;
 901         unsigned long phboff = phb_offset(tbl->it_busno);
 902         unsigned long erroff;
 903         u32 errregs[7];
 904         int i;
 905
 906         /* dump CSR */
 907         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 908         csr = be32_to_cpu(readl(target));
 909         /* dump PLSSR */
 910         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 911         plssr = be32_to_cpu(readl(target));
 912         /* dump CSMR */
 913         target = calgary_reg(bbar, phboff | 0x290);
 914         csmr = be32_to_cpu(readl(target));
 915         /* dump mck */
 916         target = calgary_reg(bbar, phboff | 0x800);
 917         mck = be32_to_cpu(readl(target));
 918
 919         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 920                tbl->it_busno);
 921
 922         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 923                csr, plssr, csmr, mck);
 924
 925         /* dump rest of error regs */
 926         printk(KERN_EMERG "Calgary: ");
 927         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 928                 /* err regs are at 0x810 - 0x870 */
 929                 erroff = (0x810 + (i * 0x10));
 930                 target = calgary_reg(bbar, phboff | erroff);
 931                 errregs[i] = be32_to_cpu(readl(target));
 932                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 933         }
 934         printk("\n");
 935
 936         /* root complex status */
 937         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 938         rcstat = be32_to_cpu(readl(target));
 939         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 940                PHB_ROOT_COMPLEX_STATUS);
 941 }
 942
 943 static void calgary_watchdog(unsigned long data)
 944 {
 945         struct pci_dev *dev = (struct pci_dev *)data;
 946         struct iommu_table *tbl = pci_iommu(dev->bus);
 947         void __iomem *bbar = tbl->bbar;
 948         u32 val32;
 949         void __iomem *target;
 950
 951         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 952         val32 = be32_to_cpu(readl(target));
 953
 954         /* If no error, the agent ID in the CSR is not valid */
 955         if (val32 & CSR_AGENT_MASK) {
 956                 tbl->chip_ops->dump_error_regs(tbl);
 957
 958                 /* reset error */
 959                 writel(0, target);
 960
 961                 /* Disable bus that caused the error */
 962                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 963                                      PHB_CONFIG_RW_OFFSET);
 964                 val32 = be32_to_cpu(readl(target));
 965                 val32 |= PHB_SLOT_DISABLE;
 966                 writel(cpu_to_be32(val32), target);
 967                 readl(target); /* flush */
 968         } else {
 969                 /* Reset the timer */
 970                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 971         }
 972 }
 973
 974 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 975         unsigned char busnum, unsigned long timeout)
 976 {
 977         u64 val64;
 978         void __iomem *target;
 979         unsigned int phb_shift = ~0; /* silence gcc */
 980         u64 mask;
 981
 982         switch (busno_to_phbid(busnum)) {
 983         case 0: phb_shift = (63 - 19);
 984                 break;
 985         case 1: phb_shift = (63 - 23);
 986                 break;
 987         case 2: phb_shift = (63 - 27);
 988                 break;
 989         case 3: phb_shift = (63 - 35);
 990                 break;
 991         default:
 992                 BUG_ON(busno_to_phbid(busnum));
 993         }
 994
 995         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 996         val64 = be64_to_cpu(readq(target));
 997
 998         /* zero out this PHB's timer bits */
 999         mask = ~(0xFUL << phb_shift);
1000         val64 &= mask;
1001         val64 |= (timeout << phb_shift);
1002         writeq(cpu_to_be64(val64), target);
1003         readq(target); /* flush */
1004 }
1005
1006 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1007 {
1008         unsigned char busnum = dev->bus->number;
1009         void __iomem *bbar = tbl->bbar;
1010         void __iomem *target;
1011         u32 val;
1012
1013         /*
1014          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1015          */
1016         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1017         val = cpu_to_be32(readl(target));
1018         val |= 0x00800000;
1019         writel(cpu_to_be32(val), target);
1020 }
1021
1022 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1023 {
1024         unsigned char busnum = dev->bus->number;
1025
1026         /*
1027          * Give split completion a longer timeout on bus 1 for aic94xx
1028          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1029          */
1030         if (is_calgary(dev->device) && (busnum == 1))
1031                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1032                                                      CCR_2SEC_TIMEOUT);
1033 }
1034
1035 static void __init calgary_enable_translation(struct pci_dev *dev)
1036 {
1037         u32 val32;
1038         unsigned char busnum;
1039         void __iomem *target;
1040         void __iomem *bbar;
1041         struct iommu_table *tbl;
1042
1043         busnum = dev->bus->number;
1044         tbl = pci_iommu(dev->bus);
1045         bbar = tbl->bbar;
1046
1047         /* enable TCE in PHB Config Register */
1048         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1049         val32 = be32_to_cpu(readl(target));
1050         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1051
1052         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1053                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1054                "Calgary" : "CalIOC2", busnum);
1055         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1056                "bus.\n");
1057
1058         writel(cpu_to_be32(val32), target);
1059         readl(target); /* flush */
1060
1061         init_timer(&tbl->watchdog_timer);
1062         tbl->watchdog_timer.function = &calgary_watchdog;
1063         tbl->watchdog_timer.data = (unsigned long)dev;
1064         mod_timer(&tbl->watchdog_timer, jiffies);
1065 }
1066
1067 static void __init calgary_disable_translation(struct pci_dev *dev)
1068 {
1069         u32 val32;
1070         unsigned char busnum;
1071         void __iomem *target;
1072         void __iomem *bbar;
1073         struct iommu_table *tbl;
1074
1075         busnum = dev->bus->number;
1076         tbl = pci_iommu(dev->bus);
1077         bbar = tbl->bbar;
1078
1079         /* disable TCE in PHB Config Register */
1080         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1081         val32 = be32_to_cpu(readl(target));
1082         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1083
1084         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1085         writel(cpu_to_be32(val32), target);
1086         readl(target); /* flush */
1087
1088         del_timer_sync(&tbl->watchdog_timer);
1089 }
1090
1091 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1092 {
1093         pci_dev_get(dev);
1094         set_pci_iommu(dev->bus, NULL);
1095
1096         /* is the device behind a bridge? */
1097         if (dev->bus->parent)
1098                 dev->bus->parent->self = dev;
1099         else
1100                 dev->bus->self = dev;
1101 }
1102
1103 static int __init calgary_init_one(struct pci_dev *dev)
1104 {
1105         void __iomem *bbar;
1106         struct iommu_table *tbl;
1107         int ret;
1108
1109         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1110
1111         bbar = busno_to_bbar(dev->bus->number);
1112         ret = calgary_setup_tar(dev, bbar);
1113         if (ret)
1114                 goto done;
1115
1116         pci_dev_get(dev);
1117
1118         if (dev->bus->parent) {
1119                 if (dev->bus->parent->self)
1120                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1121                                "bus->parent->self!\n", dev);
1122                 dev->bus->parent->self = dev;
1123         } else
1124                 dev->bus->self = dev;
1125
1126         tbl = pci_iommu(dev->bus);
1127         tbl->chip_ops->handle_quirks(tbl, dev);
1128
1129         calgary_enable_translation(dev);
1130
1131         return 0;
1132
1133 done:
1134         return ret;
1135 }
1136
1137 static int __init calgary_locate_bbars(void)
1138 {
1139         int ret;
1140         int rioidx, phb, bus;
1141         void __iomem *bbar;
1142         void __iomem *target;
1143         unsigned long offset;
1144         u8 start_bus, end_bus;
1145         u32 val;
1146
1147         ret = -ENODATA;
1148         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1149                 struct rio_detail *rio = rio_devs[rioidx];
1150
1151                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1152                         continue;
1153
1154                 /* map entire 1MB of Calgary config space */
1155                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1156                 if (!bbar)
1157                         goto error;
1158
1159                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1160                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1161                         target = calgary_reg(bbar, offset);
1162
1163                         val = be32_to_cpu(readl(target));
1164
1165                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1166                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1167
1168                         if (end_bus) {
1169                                 for (bus = start_bus; bus <= end_bus; bus++) {
1170                                         bus_info[bus].bbar = bbar;
1171                                         bus_info[bus].phbid = phb;
1172                                 }
1173                         } else {
1174                                 bus_info[start_bus].bbar = bbar;
1175                                 bus_info[start_bus].phbid = phb;
1176                         }
1177                 }
1178         }
1179
1180         return 0;
1181
1182 error:
1183         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1184         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1185                 if (bus_info[bus].bbar)
1186                         iounmap(bus_info[bus].bbar);
1187
1188         return ret;
1189 }
1190
1191 static int __init calgary_init(void)
1192 {
1193         int ret;
1194         struct pci_dev *dev = NULL;
1195         void *tce_space;
1196
1197         ret = calgary_locate_bbars();
1198         if (ret)
1199                 return ret;
1200
1201         do {
1202                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1203                 if (!dev)
1204                         break;
1205                 if (!is_cal_pci_dev(dev->device))
1206                         continue;
1207                 if (!translate_phb(dev)) {
1208                         calgary_init_one_nontraslated(dev);
1209                         continue;
1210                 }
1211                 tce_space = bus_info[dev->bus->number].tce_space;
1212                 if (!tce_space && !translate_empty_slots)
1213                         continue;
1214
1215                 ret = calgary_init_one(dev);
1216                 if (ret)
1217                         goto error;
1218         } while (1);
1219
1220         return ret;
1221
1222 error:
1223         do {
1224                 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
1225                                              PCI_ANY_ID, dev);
1226                 if (!dev)
1227                         break;
1228                 if (!is_cal_pci_dev(dev->device))
1229                         continue;
1230                 if (!translate_phb(dev)) {
1231                         pci_dev_put(dev);
1232                         continue;
1233                 }
1234                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
1235                         continue;
1236
1237                 calgary_disable_translation(dev);
1238                 calgary_free_bus(dev);
1239                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1240         } while (1);
1241
1242         return ret;
1243 }
1244
1245 static inline int __init determine_tce_table_size(u64 ram)
1246 {
1247         int ret;
1248
1249         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1250                 return specified_table_size;
1251
1252         /*
1253          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1254          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1255          * larger table size has twice as many entries, so shift the
1256          * max ram address by 13 to divide by 8K and then look at the
1257          * order of the result to choose between 0-7.
1258          */
1259         ret = get_order(ram >> 13);
1260         if (ret > TCE_TABLE_SIZE_8M)
1261                 ret = TCE_TABLE_SIZE_8M;
1262
1263         return ret;
1264 }
1265
1266 static int __init build_detail_arrays(void)
1267 {
1268         unsigned long ptr;
1269         int i, scal_detail_size, rio_detail_size;
1270
1271         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1272                 printk(KERN_WARNING
1273                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1274                         "but system has %d nodes.\n",
1275                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1276                 return -ENODEV;
1277         }
1278
1279         switch (rio_table_hdr->version){
1280         case 2:
1281                 scal_detail_size = 11;
1282                 rio_detail_size = 13;
1283                 break;
1284         case 3:
1285                 scal_detail_size = 12;
1286                 rio_detail_size = 15;
1287                 break;
1288         default:
1289                 printk(KERN_WARNING
1290                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1291                        rio_table_hdr->version);
1292                 return -EPROTO;
1293         }
1294
1295         ptr = ((unsigned long)rio_table_hdr) + 3;
1296         for (i = 0; i < rio_table_hdr->num_scal_dev;
1297                     i++, ptr += scal_detail_size)
1298                 scal_devs[i] = (struct scal_detail *)ptr;
1299
1300         for (i = 0; i < rio_table_hdr->num_rio_dev;
1301                     i++, ptr += rio_detail_size)
1302                 rio_devs[i] = (struct rio_detail *)ptr;
1303
1304         return 0;
1305 }
1306
1307 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1308 {
1309         int dev;
1310         u32 val;
1311
1312         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1313                 /*
1314                  * FIXME: properly scan for devices accross the
1315                  * PCI-to-PCI bridge on every CalIOC2 port.
1316                  */
1317                 return 1;
1318         }
1319
1320         for (dev = 1; dev < 8; dev++) {
1321                 val = read_pci_config(bus, dev, 0, 0);
1322                 if (val != 0xffffffff)
1323                         break;
1324         }
1325         return (val != 0xffffffff);
1326 }
1327
1328 void __init detect_calgary(void)
1329 {
1330         int bus;
1331         void *tbl;
1332         int calgary_found = 0;
1333         unsigned long ptr;
1334         unsigned int offset, prev_offset;
1335         int ret;
1336
1337         /*
1338          * if the user specified iommu=off or iommu=soft or we found
1339          * another HW IOMMU already, bail out.
1340          */
1341         if (swiotlb || no_iommu || iommu_detected)
1342                 return;
1343
1344         if (!use_calgary)
1345                 return;
1346
1347         if (!early_pci_allowed())
1348                 return;
1349
1350         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1351
1352         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1353
1354         rio_table_hdr = NULL;
1355         prev_offset = 0;
1356         offset = 0x180;
1357         /*
1358          * The next offset is stored in the 1st word.
1359          * Only parse up until the offset increases:
1360          */
1361         while (offset > prev_offset) {
1362                 /* The block id is stored in the 2nd word */
1363                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1364                         /* set the pointer past the offset & block id */
1365                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1366                         break;
1367                 }
1368                 prev_offset = offset;
1369                 offset = *((unsigned short *)(ptr + offset));
1370         }
1371         if (!rio_table_hdr) {
1372                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1373                        "in EBDA - bailing!\n");
1374                 return;
1375         }
1376
1377         ret = build_detail_arrays();
1378         if (ret) {
1379                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1380                 return;
1381         }
1382
1383         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1384
1385         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1386                 struct calgary_bus_info *info = &bus_info[bus];
1387                 unsigned short pci_device;
1388                 u32 val;
1389
1390                 val = read_pci_config(bus, 0, 0, 0);
1391                 pci_device = (val & 0xFFFF0000) >> 16;
1392
1393                 if (!is_cal_pci_dev(pci_device))
1394                         continue;
1395
1396                 if (info->translation_disabled)
1397                         continue;
1398
1399                 if (calgary_bus_has_devices(bus, pci_device) ||
1400                     translate_empty_slots) {
1401                         tbl = alloc_tce_table();
1402                         if (!tbl)
1403                                 goto cleanup;
1404                         info->tce_space = tbl;
1405                         calgary_found = 1;
1406                 }
1407         }
1408
1409         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1410                calgary_found ? "found" : "not found");
1411
1412         if (calgary_found) {
1413                 iommu_detected = 1;
1414                 calgary_detected = 1;
1415                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1416                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1417                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1418                        debugging ? "enabled" : "disabled");
1419         }
1420         return;
1421
1422 cleanup:
1423         for (--bus; bus >= 0; --bus) {
1424                 struct calgary_bus_info *info = &bus_info[bus];
1425
1426                 if (info->tce_space)
1427                         free_tce_table(info->tce_space);
1428         }
1429 }
1430
1431 int __init calgary_iommu_init(void)
1432 {
1433         int ret;
1434
1435         if (no_iommu || swiotlb)
1436                 return -ENODEV;
1437
1438         if (!calgary_detected)
1439                 return -ENODEV;
1440
1441         /* ok, we're trying to use Calgary - let's roll */
1442         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1443
1444         ret = calgary_init();
1445         if (ret) {
1446                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1447                        "falling back to no_iommu\n", ret);
1448                 if (end_pfn > MAX_DMA32_PFN)
1449                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1450                                         "32bit PCI may malfunction.\n");
1451                 return ret;
1452         }
1453
1454         force_iommu = 1;
1455         bad_dma_address = 0x0;
1456         dma_ops = &calgary_dma_ops;
1457
1458         return 0;
1459 }
1460
1461 static int __init calgary_parse_options(char *p)
1462 {
1463         unsigned int bridge;
1464         size_t len;
1465         char* endp;
1466
1467         while (*p) {
1468                 if (!strncmp(p, "64k", 3))
1469                         specified_table_size = TCE_TABLE_SIZE_64K;
1470                 else if (!strncmp(p, "128k", 4))
1471                         specified_table_size = TCE_TABLE_SIZE_128K;
1472                 else if (!strncmp(p, "256k", 4))
1473                         specified_table_size = TCE_TABLE_SIZE_256K;
1474                 else if (!strncmp(p, "512k", 4))
1475                         specified_table_size = TCE_TABLE_SIZE_512K;
1476                 else if (!strncmp(p, "1M", 2))
1477                         specified_table_size = TCE_TABLE_SIZE_1M;
1478                 else if (!strncmp(p, "2M", 2))
1479                         specified_table_size = TCE_TABLE_SIZE_2M;
1480                 else if (!strncmp(p, "4M", 2))
1481                         specified_table_size = TCE_TABLE_SIZE_4M;
1482                 else if (!strncmp(p, "8M", 2))
1483                         specified_table_size = TCE_TABLE_SIZE_8M;
1484
1485                 len = strlen("translate_empty_slots");
1486                 if (!strncmp(p, "translate_empty_slots", len))
1487                         translate_empty_slots = 1;
1488
1489                 len = strlen("disable");
1490                 if (!strncmp(p, "disable", len)) {
1491                         p += len;
1492                         if (*p == '=')
1493                                 ++p;
1494                         if (*p == '\0')
1495                                 break;
1496                         bridge = simple_strtol(p, &endp, 0);
1497                         if (p == endp)
1498                                 break;
1499
1500                         if (bridge < MAX_PHB_BUS_NUM) {
1501                                 printk(KERN_INFO "Calgary: disabling "
1502                                        "translation for PHB %#x\n", bridge);
1503                                 bus_info[bridge].translation_disabled = 1;
1504                         }
1505                 }
1506
1507                 p = strpbrk(p, ",");
1508                 if (!p)
1509                         break;
1510
1511                 p++; /* skip ',' */
1512         }
1513         return 1;
1514 }
1515 __setup("calgary=", calgary_parse_options);
1516
1517 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1518 {
1519         struct iommu_table *tbl;
1520         unsigned int npages;
1521         int i;
1522
1523         tbl = pci_iommu(dev->bus);
1524
1525         for (i = 0; i < 4; i++) {
1526                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1527
1528                 /* Don't give out TCEs that map MEM resources */
1529                 if (!(r->flags & IORESOURCE_MEM))
1530                         continue;
1531
1532                 /* 0-based? we reserve the whole 1st MB anyway */
1533                 if (!r->start)
1534                         continue;
1535
1536                 /* cover the whole region */
1537                 npages = (r->end - r->start) >> PAGE_SHIFT;
1538                 npages++;
1539
1540                 iommu_range_reserve(tbl, r->start, npages);
1541         }
1542 }
1543
1544 static int __init calgary_fixup_tce_spaces(void)
1545 {
1546         struct pci_dev *dev = NULL;
1547         void *tce_space;
1548
1549         if (no_iommu || swiotlb || !calgary_detected)
1550                 return -ENODEV;
1551
1552         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1553
1554         do {
1555                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1556                 if (!dev)
1557                         break;
1558                 if (!is_cal_pci_dev(dev->device))
1559                         continue;
1560                 if (!translate_phb(dev))
1561                         continue;
1562
1563                 tce_space = bus_info[dev->bus->number].tce_space;
1564                 if (!tce_space)
1565                         continue;
1566
1567                 calgary_fixup_one_tce_space(dev);
1568
1569         } while (1);
1570
1571         return 0;
1572 }
1573
1574 /*
1575  * We need to be call after pcibios_assign_resources (fs_initcall level)
1576  * and before device_initcall.
1577  */
1578 rootfs_initcall(calgary_fixup_tce_spaces);