2 * arch/sh/mm/cache-sh4.c
4 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
5 * Copyright (C) 2001 - 2006 Paul Mundt
6 * Copyright (C) 2003 Richard Curnow
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/init.h>
14 #include <asm/addrspace.h>
15 #include <asm/pgtable.h>
16 #include <asm/processor.h>
17 #include <asm/cache.h>
19 #include <asm/pgalloc.h>
20 #include <asm/mmu_context.h>
21 #include <asm/cacheflush.h>
24 * The maximum number of pages we support up to when doing ranged dcache
25 * flushing. Anything exceeding this will simply flush the dcache in its
28 #define MAX_DCACHE_PAGES 64 /* XXX: Tune for ways */
30 static void __flush_dcache_segment_1way(unsigned long start,
31 unsigned long extent);
32 static void __flush_dcache_segment_2way(unsigned long start,
33 unsigned long extent);
34 static void __flush_dcache_segment_4way(unsigned long start,
35 unsigned long extent);
37 static void __flush_cache_4096(unsigned long addr, unsigned long phys,
38 unsigned long exec_offset);
41 * This is initialised here to ensure that it is not placed in the BSS. If
42 * that were to happen, note that cache_init gets called before the BSS is
43 * cleared, so this would get nulled out which would be hopeless.
45 static void (*__flush_dcache_segment_fn)(unsigned long, unsigned long) =
46 (void (*)(unsigned long, unsigned long))0xdeadbeef;
48 static void compute_alias(struct cache_info *c)
50 c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
51 c->n_aliases = (c->alias_mask >> PAGE_SHIFT) + 1;
54 static void __init emit_cache_params(void)
56 printk("PVR=%08x CVR=%08x PRR=%08x\n",
60 printk("I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
61 cpu_data->icache.ways,
62 cpu_data->icache.sets,
63 cpu_data->icache.way_incr);
64 printk("I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
65 cpu_data->icache.entry_mask,
66 cpu_data->icache.alias_mask,
67 cpu_data->icache.n_aliases);
68 printk("D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
69 cpu_data->dcache.ways,
70 cpu_data->dcache.sets,
71 cpu_data->dcache.way_incr);
72 printk("D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
73 cpu_data->dcache.entry_mask,
74 cpu_data->dcache.alias_mask,
75 cpu_data->dcache.n_aliases);
77 if (!__flush_dcache_segment_fn)
78 panic("unknown number of cache ways\n");
82 * SH-4 has virtually indexed and physically tagged cache.
85 /* Worst case assumed to be 64k cache, direct-mapped i.e. 4 synonym bits. */
86 #define MAX_P3_SEMAPHORES 16
88 struct semaphore p3map_sem[MAX_P3_SEMAPHORES];
90 void __init p3_cache_init(void)
94 compute_alias(&cpu_data->icache);
95 compute_alias(&cpu_data->dcache);
97 switch (cpu_data->dcache.ways) {
99 __flush_dcache_segment_fn = __flush_dcache_segment_1way;
102 __flush_dcache_segment_fn = __flush_dcache_segment_2way;
105 __flush_dcache_segment_fn = __flush_dcache_segment_4way;
108 __flush_dcache_segment_fn = NULL;
114 if (remap_area_pages(P3SEG, 0, PAGE_SIZE * 4, _PAGE_CACHABLE))
115 panic("%s failed.", __FUNCTION__);
117 for (i = 0; i < cpu_data->dcache.n_aliases; i++)
118 sema_init(&p3map_sem[i], 1);
122 * Write back the dirty D-caches, but not invalidate them.
124 * START: Virtual Address (U0, P1, or P3)
125 * SIZE: Size of the region.
127 void __flush_wback_region(void *start, int size)
130 unsigned long begin, end;
132 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
133 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
134 & ~(L1_CACHE_BYTES-1);
135 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
136 asm volatile("ocbwb %0"
143 * Write back the dirty D-caches and invalidate them.
145 * START: Virtual Address (U0, P1, or P3)
146 * SIZE: Size of the region.
148 void __flush_purge_region(void *start, int size)
151 unsigned long begin, end;
153 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
154 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
155 & ~(L1_CACHE_BYTES-1);
156 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
157 asm volatile("ocbp %0"
164 * No write back please
166 void __flush_invalidate_region(void *start, int size)
169 unsigned long begin, end;
171 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
172 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
173 & ~(L1_CACHE_BYTES-1);
174 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
175 asm volatile("ocbi %0"
182 * Write back the range of D-cache, and purge the I-cache.
184 * Called from kernel/module.c:sys_init_module and routine for a.out format.
186 void flush_icache_range(unsigned long start, unsigned long end)
192 * Write back the D-cache and purge the I-cache for signal trampoline.
193 * .. which happens to be the same behavior as flush_icache_range().
194 * So, we simply flush out a line.
196 void flush_cache_sigtramp(unsigned long addr)
198 unsigned long v, index;
202 v = addr & ~(L1_CACHE_BYTES-1);
203 asm volatile("ocbwb %0"
207 index = CACHE_IC_ADDRESS_ARRAY | (v & cpu_data->icache.entry_mask);
209 local_irq_save(flags);
212 for (i = 0; i < cpu_data->icache.ways;
213 i++, index += cpu_data->icache.way_incr)
214 ctrl_outl(0, index); /* Clear out Valid-bit */
218 local_irq_restore(flags);
221 static inline void flush_cache_4096(unsigned long start,
224 unsigned long flags, exec_offset = 0;
227 * All types of SH-4 require PC to be in P2 to operate on the I-cache.
228 * Some types of SH-4 require PC to be in P2 to operate on the D-cache.
230 if ((cpu_data->flags & CPU_HAS_P2_FLUSH_BUG) ||
231 (start < CACHE_OC_ADDRESS_ARRAY))
232 exec_offset = 0x20000000;
234 local_irq_save(flags);
235 __flush_cache_4096(start | SH_CACHE_ASSOC,
236 P1SEGADDR(phys), exec_offset);
237 local_irq_restore(flags);
241 * Write back & invalidate the D-cache of the page.
242 * (To avoid "alias" issues)
244 void flush_dcache_page(struct page *page)
246 if (test_bit(PG_mapped, &page->flags)) {
247 unsigned long phys = PHYSADDR(page_address(page));
248 unsigned long addr = CACHE_OC_ADDRESS_ARRAY;
251 /* Loop all the D-cache */
252 n = cpu_data->dcache.n_aliases;
253 for (i = 0; i < n; i++, addr += PAGE_SIZE)
254 flush_cache_4096(addr, phys);
260 /* TODO: Selective icache invalidation through IC address array.. */
261 static inline void flush_icache_all(void)
263 unsigned long flags, ccr;
265 local_irq_save(flags);
270 ccr |= CCR_CACHE_ICI;
274 * back_to_P1() will take care of the barrier for us, don't add
279 local_irq_restore(flags);
282 void flush_dcache_all(void)
284 (*__flush_dcache_segment_fn)(0UL, cpu_data->dcache.way_size);
288 void flush_cache_all(void)
294 static void __flush_cache_mm(struct mm_struct *mm, unsigned long start,
297 unsigned long d = 0, p = start & PAGE_MASK;
298 unsigned long alias_mask = cpu_data->dcache.alias_mask;
299 unsigned long n_aliases = cpu_data->dcache.n_aliases;
300 unsigned long select_bit;
301 unsigned long all_aliases_mask;
302 unsigned long addr_offset;
309 dir = pgd_offset(mm, p);
310 pud = pud_offset(dir, p);
311 pmd = pmd_offset(pud, p);
312 end = PAGE_ALIGN(end);
314 all_aliases_mask = (1 << n_aliases) - 1;
317 if (pmd_none(*pmd) || unlikely(pmd_bad(*pmd))) {
325 pte = pte_offset_kernel(pmd, p);
331 if (!(pte_val(entry) & _PAGE_PRESENT)) {
337 phys = pte_val(entry) & PTE_PHYS_MASK;
339 if ((p ^ phys) & alias_mask) {
340 d |= 1 << ((p & alias_mask) >> PAGE_SHIFT);
341 d |= 1 << ((phys & alias_mask) >> PAGE_SHIFT);
343 if (d == all_aliases_mask)
349 } while (p < end && ((unsigned long)pte & ~PAGE_MASK));
357 for (i = 0; i < n_aliases; i++) {
358 if (d & select_bit) {
359 (*__flush_dcache_segment_fn)(addr_offset, PAGE_SIZE);
364 addr_offset += PAGE_SIZE;
369 * Note : (RPC) since the caches are physically tagged, the only point
370 * of flush_cache_mm for SH-4 is to get rid of aliases from the
371 * D-cache. The assumption elsewhere, e.g. flush_cache_range, is that
372 * lines can stay resident so long as the virtual address they were
373 * accessed with (hence cache set) is in accord with the physical
374 * address (i.e. tag). It's no different here. So I reckon we don't
375 * need to flush the I-cache, since aliases don't matter for that. We
378 * Caller takes mm->mmap_sem.
380 void flush_cache_mm(struct mm_struct *mm)
383 * If cache is only 4k-per-way, there are never any 'aliases'. Since
384 * the cache is physically tagged, the data can just be left in there.
386 if (cpu_data->dcache.n_aliases == 0)
390 * Don't bother groveling around the dcache for the VMA ranges
391 * if there are too many PTEs to make it worthwhile.
393 if (mm->nr_ptes >= MAX_DCACHE_PAGES)
396 struct vm_area_struct *vma;
399 * In this case there are reasonably sized ranges to flush,
400 * iterate through the VMA list and take care of any aliases.
402 for (vma = mm->mmap; vma; vma = vma->vm_next)
403 __flush_cache_mm(mm, vma->vm_start, vma->vm_end);
406 /* Only touch the icache if one of the VMAs has VM_EXEC set. */
412 * Write back and invalidate I/D-caches for the page.
414 * ADDR: Virtual Address (U0 address)
415 * PFN: Physical page number
417 void flush_cache_page(struct vm_area_struct *vma, unsigned long address,
420 unsigned long phys = pfn << PAGE_SHIFT;
421 unsigned int alias_mask;
423 alias_mask = cpu_data->dcache.alias_mask;
425 /* We only need to flush D-cache when we have alias */
426 if ((address^phys) & alias_mask) {
427 /* Loop 4K of the D-cache */
429 CACHE_OC_ADDRESS_ARRAY | (address & alias_mask),
431 /* Loop another 4K of the D-cache */
433 CACHE_OC_ADDRESS_ARRAY | (phys & alias_mask),
437 alias_mask = cpu_data->icache.alias_mask;
438 if (vma->vm_flags & VM_EXEC) {
440 * Evict entries from the portion of the cache from which code
441 * may have been executed at this address (virtual). There's
442 * no need to evict from the portion corresponding to the
443 * physical address as for the D-cache, because we know the
444 * kernel has never executed the code through its identity
448 CACHE_IC_ADDRESS_ARRAY | (address & alias_mask),
454 * Write back and invalidate D-caches.
456 * START, END: Virtual Address (U0 address)
458 * NOTE: We need to flush the _physical_ page entry.
459 * Flushing the cache lines for U0 only isn't enough.
460 * We need to flush for P1 too, which may contain aliases.
462 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
466 * If cache is only 4k-per-way, there are never any 'aliases'. Since
467 * the cache is physically tagged, the data can just be left in there.
469 if (cpu_data->dcache.n_aliases == 0)
473 * Don't bother with the lookup and alias check if we have a
474 * wide range to cover, just blow away the dcache in its
475 * entirety instead. -- PFM.
477 if (((end - start) >> PAGE_SHIFT) >= MAX_DCACHE_PAGES)
480 __flush_cache_mm(vma->vm_mm, start, end);
482 if (vma->vm_flags & VM_EXEC) {
484 * TODO: Is this required??? Need to look at how I-cache
485 * coherency is assured when new programs are loaded to see if
493 * flush_icache_user_range
494 * @vma: VMA of the process
497 * @len: length of the range (< page size)
499 void flush_icache_user_range(struct vm_area_struct *vma,
500 struct page *page, unsigned long addr, int len)
502 flush_cache_page(vma, addr, page_to_pfn(page));
509 * @addr: address in memory mapped cache array
510 * @phys: P1 address to flush (has to match tags if addr has 'A' bit
511 * set i.e. associative write)
512 * @exec_offset: set to 0x20000000 if flush has to be executed from P2
515 * The offset into the cache array implied by 'addr' selects the
516 * 'colour' of the virtual address range that will be flushed. The
517 * operation (purge/write-back) is selected by the lower 2 bits of
520 static void __flush_cache_4096(unsigned long addr, unsigned long phys,
521 unsigned long exec_offset)
524 unsigned long base_addr = addr;
525 struct cache_info *dcache;
526 unsigned long way_incr;
527 unsigned long a, ea, p;
528 unsigned long temp_pc;
530 dcache = &cpu_data->dcache;
531 /* Write this way for better assembly. */
532 way_count = dcache->ways;
533 way_incr = dcache->way_incr;
536 * Apply exec_offset (i.e. branch to P2 if required.).
540 * If I write "=r" for the (temp_pc), it puts this in r6 hence
541 * trashing exec_offset before it's been added on - why? Hence
542 * "=&r" as a 'workaround'
544 asm volatile("mov.l 1f, %0\n\t"
550 "2:\n" : "=&r" (temp_pc) : "r" (exec_offset));
553 * We know there will be >=1 iteration, so write as do-while to avoid
554 * pointless nead-of-loop check for 0 iterations.
557 ea = base_addr + PAGE_SIZE;
562 *(volatile unsigned long *)a = p;
564 * Next line: intentionally not p+32, saves an add, p
565 * will do since only the cache tag bits need to
568 *(volatile unsigned long *)(a+32) = p;
573 base_addr += way_incr;
574 } while (--way_count != 0);
578 * Break the 1, 2 and 4 way variants of this out into separate functions to
579 * avoid nearly all the overhead of having the conditional stuff in the function
580 * bodies (+ the 1 and 2 way cases avoid saving any registers too).
582 static void __flush_dcache_segment_1way(unsigned long start,
583 unsigned long extent_per_way)
585 unsigned long orig_sr, sr_with_bl;
586 unsigned long base_addr;
587 unsigned long way_incr, linesz, way_size;
588 struct cache_info *dcache;
589 register unsigned long a0, a0e;
591 asm volatile("stc sr, %0" : "=r" (orig_sr));
592 sr_with_bl = orig_sr | (1<<28);
593 base_addr = ((unsigned long)&empty_zero_page[0]);
596 * The previous code aligned base_addr to 16k, i.e. the way_size of all
597 * existing SH-4 D-caches. Whilst I don't see a need to have this
598 * aligned to any better than the cache line size (which it will be
599 * anyway by construction), let's align it to at least the way_size of
600 * any existing or conceivable SH-4 D-cache. -- RPC
602 base_addr = ((base_addr >> 16) << 16);
605 dcache = &cpu_data->dcache;
606 linesz = dcache->linesz;
607 way_incr = dcache->way_incr;
608 way_size = dcache->way_size;
611 a0e = base_addr + extent_per_way;
613 asm volatile("ldc %0, sr" : : "r" (sr_with_bl));
614 asm volatile("movca.l r0, @%0\n\t"
615 "ocbi @%0" : : "r" (a0));
617 asm volatile("movca.l r0, @%0\n\t"
618 "ocbi @%0" : : "r" (a0));
620 asm volatile("movca.l r0, @%0\n\t"
621 "ocbi @%0" : : "r" (a0));
623 asm volatile("movca.l r0, @%0\n\t"
624 "ocbi @%0" : : "r" (a0));
625 asm volatile("ldc %0, sr" : : "r" (orig_sr));
630 static void __flush_dcache_segment_2way(unsigned long start,
631 unsigned long extent_per_way)
633 unsigned long orig_sr, sr_with_bl;
634 unsigned long base_addr;
635 unsigned long way_incr, linesz, way_size;
636 struct cache_info *dcache;
637 register unsigned long a0, a1, a0e;
639 asm volatile("stc sr, %0" : "=r" (orig_sr));
640 sr_with_bl = orig_sr | (1<<28);
641 base_addr = ((unsigned long)&empty_zero_page[0]);
643 /* See comment under 1-way above */
644 base_addr = ((base_addr >> 16) << 16);
647 dcache = &cpu_data->dcache;
648 linesz = dcache->linesz;
649 way_incr = dcache->way_incr;
650 way_size = dcache->way_size;
654 a0e = base_addr + extent_per_way;
656 asm volatile("ldc %0, sr" : : "r" (sr_with_bl));
657 asm volatile("movca.l r0, @%0\n\t"
658 "movca.l r0, @%1\n\t"
664 asm volatile("movca.l r0, @%0\n\t"
665 "movca.l r0, @%1\n\t"
671 asm volatile("movca.l r0, @%0\n\t"
672 "movca.l r0, @%1\n\t"
678 asm volatile("movca.l r0, @%0\n\t"
679 "movca.l r0, @%1\n\t"
683 asm volatile("ldc %0, sr" : : "r" (orig_sr));
689 static void __flush_dcache_segment_4way(unsigned long start,
690 unsigned long extent_per_way)
692 unsigned long orig_sr, sr_with_bl;
693 unsigned long base_addr;
694 unsigned long way_incr, linesz, way_size;
695 struct cache_info *dcache;
696 register unsigned long a0, a1, a2, a3, a0e;
698 asm volatile("stc sr, %0" : "=r" (orig_sr));
699 sr_with_bl = orig_sr | (1<<28);
700 base_addr = ((unsigned long)&empty_zero_page[0]);
702 /* See comment under 1-way above */
703 base_addr = ((base_addr >> 16) << 16);
706 dcache = &cpu_data->dcache;
707 linesz = dcache->linesz;
708 way_incr = dcache->way_incr;
709 way_size = dcache->way_size;
715 a0e = base_addr + extent_per_way;
717 asm volatile("ldc %0, sr" : : "r" (sr_with_bl));
718 asm volatile("movca.l r0, @%0\n\t"
719 "movca.l r0, @%1\n\t"
720 "movca.l r0, @%2\n\t"
721 "movca.l r0, @%3\n\t"
726 "r" (a0), "r" (a1), "r" (a2), "r" (a3));
731 asm volatile("movca.l r0, @%0\n\t"
732 "movca.l r0, @%1\n\t"
733 "movca.l r0, @%2\n\t"
734 "movca.l r0, @%3\n\t"
739 "r" (a0), "r" (a1), "r" (a2), "r" (a3));
744 asm volatile("movca.l r0, @%0\n\t"
745 "movca.l r0, @%1\n\t"
746 "movca.l r0, @%2\n\t"
747 "movca.l r0, @%3\n\t"
752 "r" (a0), "r" (a1), "r" (a2), "r" (a3));
757 asm volatile("movca.l r0, @%0\n\t"
758 "movca.l r0, @%1\n\t"
759 "movca.l r0, @%2\n\t"
760 "movca.l r0, @%3\n\t"
765 "r" (a0), "r" (a1), "r" (a2), "r" (a3));
766 asm volatile("ldc %0, sr" : : "r" (orig_sr));