Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6] / arch / i386 / kernel / cpu / cpufreq / speedstep-centrino.c
1 /*
2  * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
3  * M (part of the Centrino chipset).
4  *
5  * Since the original Pentium M, most new Intel CPUs support Enhanced
6  * SpeedStep.
7  *
8  * Despite the "SpeedStep" in the name, this is almost entirely unlike
9  * traditional SpeedStep.
10  *
11  * Modelled on speedstep.c
12  *
13  * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
14  */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/cpufreq.h>
20 #include <linux/config.h>
21 #include <linux/sched.h>        /* current */
22 #include <linux/delay.h>
23 #include <linux/compiler.h>
24
25 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
26 #include <linux/acpi.h>
27 #include <acpi/processor.h>
28 #endif
29
30 #include <asm/msr.h>
31 #include <asm/processor.h>
32 #include <asm/cpufeature.h>
33
34 #define PFX             "speedstep-centrino: "
35 #define MAINTAINER      "cpufreq@lists.linux.org.uk"
36
37 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
38
39
40 struct cpu_id
41 {
42         __u8    x86;            /* CPU family */
43         __u8    x86_model;      /* model */
44         __u8    x86_mask;       /* stepping */
45 };
46
47 enum {
48         CPU_BANIAS,
49         CPU_DOTHAN_A1,
50         CPU_DOTHAN_A2,
51         CPU_DOTHAN_B0,
52         CPU_MP4HT_D0,
53         CPU_MP4HT_E0,
54 };
55
56 static const struct cpu_id cpu_ids[] = {
57         [CPU_BANIAS]    = { 6,  9, 5 },
58         [CPU_DOTHAN_A1] = { 6, 13, 1 },
59         [CPU_DOTHAN_A2] = { 6, 13, 2 },
60         [CPU_DOTHAN_B0] = { 6, 13, 6 },
61         [CPU_MP4HT_D0]  = {15,  3, 4 },
62         [CPU_MP4HT_E0]  = {15,  4, 1 },
63 };
64 #define N_IDS   ARRAY_SIZE(cpu_ids)
65
66 struct cpu_model
67 {
68         const struct cpu_id *cpu_id;
69         const char      *model_name;
70         unsigned        max_freq; /* max clock in kHz */
71
72         struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
73 };
74 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
75
76 /* Operating points for current CPU */
77 static struct cpu_model *centrino_model[NR_CPUS];
78 static const struct cpu_id *centrino_cpu[NR_CPUS];
79
80 static struct cpufreq_driver centrino_driver;
81
82 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
83
84 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
85    frequency/voltage operating point; frequency in MHz, volts in mV.
86    This is stored as "index" in the structure. */
87 #define OP(mhz, mv)                                                     \
88         {                                                               \
89                 .frequency = (mhz) * 1000,                              \
90                 .index = (((mhz)/100) << 8) | ((mv - 700) / 16)         \
91         }
92
93 /*
94  * These voltage tables were derived from the Intel Pentium M
95  * datasheet, document 25261202.pdf, Table 5.  I have verified they
96  * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
97  * M.
98  */
99
100 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
101 static struct cpufreq_frequency_table banias_900[] =
102 {
103         OP(600,  844),
104         OP(800,  988),
105         OP(900, 1004),
106         { .frequency = CPUFREQ_TABLE_END }
107 };
108
109 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
110 static struct cpufreq_frequency_table banias_1000[] =
111 {
112         OP(600,   844),
113         OP(800,   972),
114         OP(900,   988),
115         OP(1000, 1004),
116         { .frequency = CPUFREQ_TABLE_END }
117 };
118
119 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
120 static struct cpufreq_frequency_table banias_1100[] =
121 {
122         OP( 600,  956),
123         OP( 800, 1020),
124         OP( 900, 1100),
125         OP(1000, 1164),
126         OP(1100, 1180),
127         { .frequency = CPUFREQ_TABLE_END }
128 };
129
130
131 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
132 static struct cpufreq_frequency_table banias_1200[] =
133 {
134         OP( 600,  956),
135         OP( 800, 1004),
136         OP( 900, 1020),
137         OP(1000, 1100),
138         OP(1100, 1164),
139         OP(1200, 1180),
140         { .frequency = CPUFREQ_TABLE_END }
141 };
142
143 /* Intel Pentium M processor 1.30GHz (Banias) */
144 static struct cpufreq_frequency_table banias_1300[] =
145 {
146         OP( 600,  956),
147         OP( 800, 1260),
148         OP(1000, 1292),
149         OP(1200, 1356),
150         OP(1300, 1388),
151         { .frequency = CPUFREQ_TABLE_END }
152 };
153
154 /* Intel Pentium M processor 1.40GHz (Banias) */
155 static struct cpufreq_frequency_table banias_1400[] =
156 {
157         OP( 600,  956),
158         OP( 800, 1180),
159         OP(1000, 1308),
160         OP(1200, 1436),
161         OP(1400, 1484),
162         { .frequency = CPUFREQ_TABLE_END }
163 };
164
165 /* Intel Pentium M processor 1.50GHz (Banias) */
166 static struct cpufreq_frequency_table banias_1500[] =
167 {
168         OP( 600,  956),
169         OP( 800, 1116),
170         OP(1000, 1228),
171         OP(1200, 1356),
172         OP(1400, 1452),
173         OP(1500, 1484),
174         { .frequency = CPUFREQ_TABLE_END }
175 };
176
177 /* Intel Pentium M processor 1.60GHz (Banias) */
178 static struct cpufreq_frequency_table banias_1600[] =
179 {
180         OP( 600,  956),
181         OP( 800, 1036),
182         OP(1000, 1164),
183         OP(1200, 1276),
184         OP(1400, 1420),
185         OP(1600, 1484),
186         { .frequency = CPUFREQ_TABLE_END }
187 };
188
189 /* Intel Pentium M processor 1.70GHz (Banias) */
190 static struct cpufreq_frequency_table banias_1700[] =
191 {
192         OP( 600,  956),
193         OP( 800, 1004),
194         OP(1000, 1116),
195         OP(1200, 1228),
196         OP(1400, 1308),
197         OP(1700, 1484),
198         { .frequency = CPUFREQ_TABLE_END }
199 };
200 #undef OP
201
202 #define _BANIAS(cpuid, max, name)       \
203 {       .cpu_id         = cpuid,        \
204         .model_name     = "Intel(R) Pentium(R) M processor " name "MHz", \
205         .max_freq       = (max)*1000,   \
206         .op_points      = banias_##max, \
207 }
208 #define BANIAS(max)     _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
209
210 /* CPU models, their operating frequency range, and freq/voltage
211    operating points */
212 static struct cpu_model models[] =
213 {
214         _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
215         BANIAS(1000),
216         BANIAS(1100),
217         BANIAS(1200),
218         BANIAS(1300),
219         BANIAS(1400),
220         BANIAS(1500),
221         BANIAS(1600),
222         BANIAS(1700),
223
224         /* NULL model_name is a wildcard */
225         { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
226         { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
227         { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
228         { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
229         { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
230
231         { NULL, }
232 };
233 #undef _BANIAS
234 #undef BANIAS
235
236 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
237 {
238         struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
239         struct cpu_model *model;
240
241         for(model = models; model->cpu_id != NULL; model++)
242                 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
243                     (model->model_name == NULL ||
244                      strcmp(cpu->x86_model_id, model->model_name) == 0))
245                         break;
246
247         if (model->cpu_id == NULL) {
248                 /* No match at all */
249                 dprintk("no support for CPU model \"%s\": "
250                        "send /proc/cpuinfo to " MAINTAINER "\n",
251                        cpu->x86_model_id);
252                 return -ENOENT;
253         }
254
255         if (model->op_points == NULL) {
256                 /* Matched a non-match */
257                 dprintk("no table support for CPU model \"%s\"\n",
258                        cpu->x86_model_id);
259 #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
260                 dprintk("try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
261 #endif
262                 return -ENOENT;
263         }
264
265         centrino_model[policy->cpu] = model;
266
267         dprintk("found \"%s\": max frequency: %dkHz\n",
268                model->model_name, model->max_freq);
269
270         return 0;
271 }
272
273 #else
274 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
275 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
276
277 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
278 {
279         if ((c->x86 == x->x86) &&
280             (c->x86_model == x->x86_model) &&
281             (c->x86_mask == x->x86_mask))
282                 return 1;
283         return 0;
284 }
285
286 /* To be called only after centrino_model is initialized */
287 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
288 {
289         int i;
290
291         /*
292          * Extract clock in kHz from PERF_CTL value
293          * for centrino, as some DSDTs are buggy.
294          * Ideally, this can be done using the acpi_data structure.
295          */
296         if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
297             (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
298             (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
299                 msr = (msr >> 8) & 0xff;
300                 return msr * 100000;
301         }
302
303         if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
304                 return 0;
305
306         msr &= 0xffff;
307         for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
308                 if (msr == centrino_model[cpu]->op_points[i].index)
309                         return centrino_model[cpu]->op_points[i].frequency;
310         }
311         if (failsafe)
312                 return centrino_model[cpu]->op_points[i-1].frequency;
313         else
314                 return 0;
315 }
316
317 /* Return the current CPU frequency in kHz */
318 static unsigned int get_cur_freq(unsigned int cpu)
319 {
320         unsigned l, h;
321         unsigned clock_freq;
322         cpumask_t saved_mask;
323
324         saved_mask = current->cpus_allowed;
325         set_cpus_allowed(current, cpumask_of_cpu(cpu));
326         if (smp_processor_id() != cpu)
327                 return 0;
328
329         rdmsr(MSR_IA32_PERF_STATUS, l, h);
330         clock_freq = extract_clock(l, cpu, 0);
331
332         if (unlikely(clock_freq == 0)) {
333                 /*
334                  * On some CPUs, we can see transient MSR values (which are
335                  * not present in _PSS), while CPU is doing some automatic
336                  * P-state transition (like TM2). Get the last freq set 
337                  * in PERF_CTL.
338                  */
339                 rdmsr(MSR_IA32_PERF_CTL, l, h);
340                 clock_freq = extract_clock(l, cpu, 1);
341         }
342
343         set_cpus_allowed(current, saved_mask);
344         return clock_freq;
345 }
346
347
348 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
349
350 static struct acpi_processor_performance p;
351
352 /*
353  * centrino_cpu_init_acpi - register with ACPI P-States library
354  *
355  * Register with the ACPI P-States library (part of drivers/acpi/processor.c)
356  * in order to determine correct frequency and voltage pairings by reading
357  * the _PSS of the ACPI DSDT or SSDT tables.
358  */
359 static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
360 {
361         unsigned long                   cur_freq;
362         int                             result = 0, i;
363         unsigned int                    cpu = policy->cpu;
364
365         /* register with ACPI core */
366         if (acpi_processor_register_performance(&p, cpu)) {
367                 dprintk("obtaining ACPI data failed\n");
368                 return -EIO;
369         }
370
371         /* verify the acpi_data */
372         if (p.state_count <= 1) {
373                 dprintk("No P-States\n");
374                 result = -ENODEV;
375                 goto err_unreg;
376         }
377
378         if ((p.control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
379             (p.status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
380                 dprintk("Invalid control/status registers (%x - %x)\n",
381                         p.control_register.space_id, p.status_register.space_id);
382                 result = -EIO;
383                 goto err_unreg;
384         }
385
386         for (i=0; i<p.state_count; i++) {
387                 if (p.states[i].control != p.states[i].status) {
388                         dprintk("Different control (%llu) and status values (%llu)\n",
389                                 p.states[i].control, p.states[i].status);
390                         result = -EINVAL;
391                         goto err_unreg;
392                 }
393
394                 if (!p.states[i].core_frequency) {
395                         dprintk("Zero core frequency for state %u\n", i);
396                         result = -EINVAL;
397                         goto err_unreg;
398                 }
399
400                 if (p.states[i].core_frequency > p.states[0].core_frequency) {
401                         dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i,
402                                 p.states[i].core_frequency, p.states[0].core_frequency);
403                         p.states[i].core_frequency = 0;
404                         continue;
405                 }
406         }
407
408         centrino_model[cpu] = kzalloc(sizeof(struct cpu_model), GFP_KERNEL);
409         if (!centrino_model[cpu]) {
410                 result = -ENOMEM;
411                 goto err_unreg;
412         }
413
414         centrino_model[cpu]->model_name=NULL;
415         centrino_model[cpu]->max_freq = p.states[0].core_frequency * 1000;
416         centrino_model[cpu]->op_points =  kmalloc(sizeof(struct cpufreq_frequency_table) *
417                                              (p.state_count + 1), GFP_KERNEL);
418         if (!centrino_model[cpu]->op_points) {
419                 result = -ENOMEM;
420                 goto err_kfree;
421         }
422
423         for (i=0; i<p.state_count; i++) {
424                 centrino_model[cpu]->op_points[i].index = p.states[i].control;
425                 centrino_model[cpu]->op_points[i].frequency = p.states[i].core_frequency * 1000;
426                 dprintk("adding state %i with frequency %u and control value %04x\n", 
427                         i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index);
428         }
429         centrino_model[cpu]->op_points[p.state_count].frequency = CPUFREQ_TABLE_END;
430
431         cur_freq = get_cur_freq(cpu);
432
433         for (i=0; i<p.state_count; i++) {
434                 if (!p.states[i].core_frequency) {
435                         dprintk("skipping state %u\n", i);
436                         centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID;
437                         continue;
438                 }
439                 
440                 if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) !=
441                     (centrino_model[cpu]->op_points[i].frequency)) {
442                         dprintk("Invalid encoded frequency (%u vs. %u)\n",
443                                 extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0),
444                                 centrino_model[cpu]->op_points[i].frequency);
445                         result = -EINVAL;
446                         goto err_kfree_all;
447                 }
448
449                 if (cur_freq == centrino_model[cpu]->op_points[i].frequency)
450                         p.state = i;
451         }
452
453         /* notify BIOS that we exist */
454         acpi_processor_notify_smm(THIS_MODULE);
455
456         return 0;
457
458  err_kfree_all:
459         kfree(centrino_model[cpu]->op_points);
460  err_kfree:
461         kfree(centrino_model[cpu]);
462  err_unreg:
463         acpi_processor_unregister_performance(&p, cpu);
464         dprintk("invalid ACPI data\n");
465         return (result);
466 }
467 #else
468 static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
469 #endif
470
471 static int centrino_cpu_init(struct cpufreq_policy *policy)
472 {
473         struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
474         unsigned freq;
475         unsigned l, h;
476         int ret;
477         int i;
478
479         /* Only Intel makes Enhanced Speedstep-capable CPUs */
480         if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
481                 return -ENODEV;
482
483         if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
484                 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
485
486         if (centrino_cpu_init_acpi(policy)) {
487                 if (policy->cpu != 0)
488                         return -ENODEV;
489
490                 for (i = 0; i < N_IDS; i++)
491                         if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
492                                 break;
493
494                 if (i != N_IDS)
495                         centrino_cpu[policy->cpu] = &cpu_ids[i];
496
497                 if (!centrino_cpu[policy->cpu]) {
498                         dprintk("found unsupported CPU with "
499                         "Enhanced SpeedStep: send /proc/cpuinfo to "
500                         MAINTAINER "\n");
501                         return -ENODEV;
502                 }
503
504                 if (centrino_cpu_init_table(policy)) {
505                         return -ENODEV;
506                 }
507         }
508
509         /* Check to see if Enhanced SpeedStep is enabled, and try to
510            enable it if not. */
511         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
512
513         if (!(l & (1<<16))) {
514                 l |= (1<<16);
515                 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
516                 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
517
518                 /* check to see if it stuck */
519                 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
520                 if (!(l & (1<<16))) {
521                         printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
522                         return -ENODEV;
523                 }
524         }
525
526         freq = get_cur_freq(policy->cpu);
527
528         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
529         policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
530         policy->cur = freq;
531
532         dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
533
534         ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
535         if (ret)
536                 return (ret);
537
538         cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
539
540         return 0;
541 }
542
543 static int centrino_cpu_exit(struct cpufreq_policy *policy)
544 {
545         unsigned int cpu = policy->cpu;
546
547         if (!centrino_model[cpu])
548                 return -ENODEV;
549
550         cpufreq_frequency_table_put_attr(cpu);
551
552 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
553         if (!centrino_model[cpu]->model_name) {
554                 dprintk("unregistering and freeing ACPI data\n");
555                 acpi_processor_unregister_performance(&p, cpu);
556                 kfree(centrino_model[cpu]->op_points);
557                 kfree(centrino_model[cpu]);
558         }
559 #endif
560
561         centrino_model[cpu] = NULL;
562
563         return 0;
564 }
565
566 /**
567  * centrino_verify - verifies a new CPUFreq policy
568  * @policy: new policy
569  *
570  * Limit must be within this model's frequency range at least one
571  * border included.
572  */
573 static int centrino_verify (struct cpufreq_policy *policy)
574 {
575         return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
576 }
577
578 /**
579  * centrino_setpolicy - set a new CPUFreq policy
580  * @policy: new policy
581  * @target_freq: the target frequency
582  * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
583  *
584  * Sets a new CPUFreq policy.
585  */
586 static int centrino_target (struct cpufreq_policy *policy,
587                             unsigned int target_freq,
588                             unsigned int relation)
589 {
590         unsigned int    newstate = 0;
591         unsigned int    msr, oldmsr, h, cpu = policy->cpu;
592         struct cpufreq_freqs    freqs;
593         cpumask_t               saved_mask;
594         int                     retval;
595
596         if (centrino_model[cpu] == NULL)
597                 return -ENODEV;
598
599         /*
600          * Support for SMP systems.
601          * Make sure we are running on the CPU that wants to change frequency
602          */
603         saved_mask = current->cpus_allowed;
604         set_cpus_allowed(current, policy->cpus);
605         if (!cpu_isset(smp_processor_id(), policy->cpus)) {
606                 dprintk("couldn't limit to CPUs in this domain\n");
607                 return(-EAGAIN);
608         }
609
610         if (cpufreq_frequency_table_target(policy, centrino_model[cpu]->op_points, target_freq,
611                                            relation, &newstate)) {
612                 retval = -EINVAL;
613                 goto migrate_end;
614         }
615
616         msr = centrino_model[cpu]->op_points[newstate].index;
617         rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
618
619         if (msr == (oldmsr & 0xffff)) {
620                 retval = 0;
621                 dprintk("no change needed - msr was and needs to be %x\n", oldmsr);
622                 goto migrate_end;
623         }
624
625         freqs.cpu = cpu;
626         freqs.old = extract_clock(oldmsr, cpu, 0);
627         freqs.new = extract_clock(msr, cpu, 0);
628
629         dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
630                 target_freq, freqs.old, freqs.new, msr);
631
632         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
633
634         /* all but 16 LSB are "reserved", so treat them with
635            care */
636         oldmsr &= ~0xffff;
637         msr &= 0xffff;
638         oldmsr |= msr;
639
640         wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
641
642         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
643
644         retval = 0;
645 migrate_end:
646         set_cpus_allowed(current, saved_mask);
647         return (retval);
648 }
649
650 static struct freq_attr* centrino_attr[] = {
651         &cpufreq_freq_attr_scaling_available_freqs,
652         NULL,
653 };
654
655 static struct cpufreq_driver centrino_driver = {
656         .name           = "centrino", /* should be speedstep-centrino,
657                                          but there's a 16 char limit */
658         .init           = centrino_cpu_init,
659         .exit           = centrino_cpu_exit,
660         .verify         = centrino_verify,
661         .target         = centrino_target,
662         .get            = get_cur_freq,
663         .attr           = centrino_attr,
664         .owner          = THIS_MODULE,
665 };
666
667
668 /**
669  * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
670  *
671  * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
672  * unsupported devices, -ENOENT if there's no voltage table for this
673  * particular CPU model, -EINVAL on problems during initiatization,
674  * and zero on success.
675  *
676  * This is quite picky.  Not only does the CPU have to advertise the
677  * "est" flag in the cpuid capability flags, we look for a specific
678  * CPU model and stepping, and we need to have the exact model name in
679  * our voltage tables.  That is, be paranoid about not releasing
680  * someone's valuable magic smoke.
681  */
682 static int __init centrino_init(void)
683 {
684         struct cpuinfo_x86 *cpu = cpu_data;
685
686         if (!cpu_has(cpu, X86_FEATURE_EST))
687                 return -ENODEV;
688
689         return cpufreq_register_driver(&centrino_driver);
690 }
691
692 static void __exit centrino_exit(void)
693 {
694         cpufreq_unregister_driver(&centrino_driver);
695 }
696
697 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
698 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
699 MODULE_LICENSE ("GPL");
700
701 late_initcall(centrino_init);
702 module_exit(centrino_exit);