Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/cpufreq
[linux-2.6] / arch / powerpc / boot / dts / mpc8641_hpcn.dts
1 /*
2  * MPC8641 HPCN Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12
13 / {
14         model = "MPC8641HPCN";
15         compatible = "mpc86xx";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         cpus {
20                 #cpus = <2>;
21                 #address-cells = <1>;
22                 #size-cells = <0>;
23
24                 PowerPC,8641@0 {
25                         device_type = "cpu";
26                         reg = <0>;
27                         d-cache-line-size = <20>;       // 32 bytes
28                         i-cache-line-size = <20>;       // 32 bytes
29                         d-cache-size = <8000>;          // L1, 32K
30                         i-cache-size = <8000>;          // L1, 32K
31                         timebase-frequency = <0>;       // 33 MHz, from uboot
32                         bus-frequency = <0>;            // From uboot
33                         clock-frequency = <0>;          // From uboot
34                         32-bit;
35                 };
36                 PowerPC,8641@1 {
37                         device_type = "cpu";
38                         reg = <1>;
39                         d-cache-line-size = <20>;       // 32 bytes
40                         i-cache-line-size = <20>;       // 32 bytes
41                         d-cache-size = <8000>;          // L1, 32K
42                         i-cache-size = <8000>;          // L1, 32K
43                         timebase-frequency = <0>;       // 33 MHz, from uboot
44                         bus-frequency = <0>;            // From uboot
45                         clock-frequency = <0>;          // From uboot
46                         32-bit;
47                 };
48         };
49
50         memory {
51                 device_type = "memory";
52                 reg = <00000000 40000000>;      // 1G at 0x0
53         };
54
55         soc8641@f8000000 {
56                 #address-cells = <1>;
57                 #size-cells = <1>;
58                 #interrupt-cells = <2>;
59                 device_type = "soc";
60                 ranges = <0 f8000000 00100000>;
61                 reg = <f8000000 00100000>;      // CCSRBAR 1M
62                 bus-frequency = <0>;
63
64                 i2c@3000 {
65                         device_type = "i2c";
66                         compatible = "fsl-i2c";
67                         reg = <3000 100>;
68                         interrupts = <2b 2>;
69                         interrupt-parent = <&mpic>;
70                         dfsrr;
71                 };
72
73                 i2c@3100 {
74                         device_type = "i2c";
75                         compatible = "fsl-i2c";
76                         reg = <3100 100>;
77                         interrupts = <2b 2>;
78                         interrupt-parent = <&mpic>;
79                         dfsrr;
80                 };
81
82                 mdio@24520 {
83                         #address-cells = <1>;
84                         #size-cells = <0>;
85                         device_type = "mdio";
86                         compatible = "gianfar";
87                         reg = <24520 20>;
88                         phy0: ethernet-phy@0 {
89                                 interrupt-parent = <&mpic>;
90                                 interrupts = <4a 1>;
91                                 reg = <0>;
92                                 device_type = "ethernet-phy";
93                         };
94                         phy1: ethernet-phy@1 {
95                                 interrupt-parent = <&mpic>;
96                                 interrupts = <4a 1>;
97                                 reg = <1>;
98                                 device_type = "ethernet-phy";
99                         };
100                         phy2: ethernet-phy@2 {
101                                 interrupt-parent = <&mpic>;
102                                 interrupts = <4a 1>;
103                                 reg = <2>;
104                                 device_type = "ethernet-phy";
105                         };
106                         phy3: ethernet-phy@3 {
107                                 interrupt-parent = <&mpic>;
108                                 interrupts = <4a 1>;
109                                 reg = <3>;
110                                 device_type = "ethernet-phy";
111                         };
112                 };
113
114                 ethernet@24000 {
115                         #address-cells = <1>;
116                         #size-cells = <0>;
117                         device_type = "network";
118                         model = "TSEC";
119                         compatible = "gianfar";
120                         reg = <24000 1000>;
121                         mac-address = [ 00 E0 0C 00 73 00 ];
122                         interrupts = <1d 2 1e 2 22 2>;
123                         interrupt-parent = <&mpic>;
124                         phy-handle = <&phy0>;
125                 };
126
127                 ethernet@25000 {
128                         #address-cells = <1>;
129                         #size-cells = <0>;
130                         device_type = "network";
131                         model = "TSEC";
132                         compatible = "gianfar";
133                         reg = <25000 1000>;
134                         mac-address = [ 00 E0 0C 00 73 01 ];
135                         interrupts = <23 2 24 2 28 2>;
136                         interrupt-parent = <&mpic>;
137                         phy-handle = <&phy1>;
138                 };
139                 
140                 ethernet@26000 {
141                         #address-cells = <1>;
142                         #size-cells = <0>;
143                         device_type = "network";
144                         model = "TSEC";
145                         compatible = "gianfar";
146                         reg = <26000 1000>;
147                         mac-address = [ 00 E0 0C 00 02 FD ];
148                         interrupts = <1F 2 20 2 21 2>;
149                         interrupt-parent = <&mpic>;
150                         phy-handle = <&phy2>;
151                 };
152
153                 ethernet@27000 {
154                         #address-cells = <1>;
155                         #size-cells = <0>;
156                         device_type = "network";
157                         model = "TSEC";
158                         compatible = "gianfar";
159                         reg = <27000 1000>;
160                         mac-address = [ 00 E0 0C 00 03 FD ];
161                         interrupts = <25 2 26 2 27 2>;
162                         interrupt-parent = <&mpic>;
163                         phy-handle = <&phy3>;
164                 };
165                 serial@4500 {
166                         device_type = "serial";
167                         compatible = "ns16550";
168                         reg = <4500 100>;
169                         clock-frequency = <0>;
170                         interrupts = <2a 2>;
171                         interrupt-parent = <&mpic>;
172                 };
173
174                 serial@4600 {
175                         device_type = "serial";
176                         compatible = "ns16550";
177                         reg = <4600 100>;
178                         clock-frequency = <0>;
179                         interrupts = <1c 2>;
180                         interrupt-parent = <&mpic>;
181                 };
182
183                 pci@8000 {
184                         compatible = "86xx";
185                         device_type = "pci";
186                         #interrupt-cells = <1>;
187                         #size-cells = <2>;
188                         #address-cells = <3>;
189                         reg = <8000 1000>;
190                         bus-range = <0 fe>;
191                         ranges = <02000000 0 80000000 80000000 0 20000000
192                                   01000000 0 00000000 e2000000 0 00100000>;
193                         clock-frequency = <1fca055>;
194                         interrupt-parent = <&mpic>;
195                         interrupts = <18 2>;
196                         interrupt-map-mask = <f800 0 0 7>;
197                         interrupt-map = <
198                                 /* IDSEL 0x11 */
199                                 8800 0 0 1 &i8259 3 2
200                                 8800 0 0 2 &i8259 4 2
201                                 8800 0 0 3 &i8259 5 2
202                                 8800 0 0 4 &i8259 6 2
203
204                                 /* IDSEL 0x12 */
205                                 9000 0 0 1 &i8259 4 2
206                                 9000 0 0 2 &i8259 5 2
207                                 9000 0 0 3 &i8259 6 2
208                                 9000 0 0 4 &i8259 3 2
209
210                                 /* IDSEL 0x13 */
211                                 9800 0 0 1 &i8259 0 0
212                                 9800 0 0 2 &i8259 0 0
213                                 9800 0 0 3 &i8259 0 0
214                                 9800 0 0 4 &i8259 0 0
215
216                                 /* IDSEL 0x14 */
217                                 a000 0 0 1 &i8259 0 0
218                                 a000 0 0 2 &i8259 0 0
219                                 a000 0 0 3 &i8259 0 0
220                                 a000 0 0 4 &i8259 0 0
221
222                                 /* IDSEL 0x15 */
223                                 a800 0 0 1 &i8259 0 0
224                                 a800 0 0 2 &i8259 0 0
225                                 a800 0 0 3 &i8259 0 0
226                                 a800 0 0 4 &i8259 0 0
227
228                                 /* IDSEL 0x16 */
229                                 b000 0 0 1 &i8259 0 0
230                                 b000 0 0 2 &i8259 0 0
231                                 b000 0 0 3 &i8259 0 0
232                                 b000 0 0 4 &i8259 0 0
233
234                                 /* IDSEL 0x17 */
235                                 b800 0 0 1 &i8259 0 0
236                                 b800 0 0 2 &i8259 0 0
237                                 b800 0 0 3 &i8259 0 0
238                                 b800 0 0 4 &i8259 0 0
239
240                                 /* IDSEL 0x18 */
241                                 c000 0 0 1 &i8259 0 0
242                                 c000 0 0 2 &i8259 0 0
243                                 c000 0 0 3 &i8259 0 0
244                                 c000 0 0 4 &i8259 0 0
245
246                                 /* IDSEL 0x19 */
247                                 c800 0 0 1 &i8259 0 0
248                                 c800 0 0 2 &i8259 0 0
249                                 c800 0 0 3 &i8259 0 0
250                                 c800 0 0 4 &i8259 0 0
251
252                                 /* IDSEL 0x1a */
253                                 d000 0 0 1 &i8259 6 2
254                                 d000 0 0 2 &i8259 3 2
255                                 d000 0 0 3 &i8259 4 2
256                                 d000 0 0 4 &i8259 5 2
257
258
259                                 /* IDSEL 0x1b */
260                                 d800 0 0 1 &i8259 5 2
261                                 d800 0 0 2 &i8259 0 0
262                                 d800 0 0 3 &i8259 0 0
263                                 d800 0 0 4 &i8259 0 0
264
265                                 /* IDSEL 0x1c */
266                                 e000 0 0 1 &i8259 9 2
267                                 e000 0 0 2 &i8259 a 2
268                                 e000 0 0 3 &i8259 c 2
269                                 e000 0 0 4 &i8259 7 2
270
271                                 /* IDSEL 0x1d */
272                                 e800 0 0 1 &i8259 9 2
273                                 e800 0 0 2 &i8259 a 2
274                                 e800 0 0 3 &i8259 b 2
275                                 e800 0 0 4 &i8259 0 0
276
277                                 /* IDSEL 0x1e */
278                                 f000 0 0 1 &i8259 c 2
279                                 f000 0 0 2 &i8259 0 0
280                                 f000 0 0 3 &i8259 0 0
281                                 f000 0 0 4 &i8259 0 0
282
283                                 /* IDSEL 0x1f */
284                                 f800 0 0 1 &i8259 6 2
285                                 f800 0 0 2 &i8259 0 0
286                                 f800 0 0 3 &i8259 0 0
287                                 f800 0 0 4 &i8259 0 0
288                                 >;
289                         i8259: i8259@4d0 {
290                                 clock-frequency = <0>;
291                                 interrupt-controller;
292                                 device_type = "interrupt-controller";
293                                 #address-cells = <0>;
294                                 #interrupt-cells = <2>;
295                                 built-in;
296                                 compatible = "chrp,iic";
297                                 big-endian;
298                                 interrupts = <49 2>;
299                                 interrupt-parent = <&mpic>;
300                         };
301
302                 };
303                 mpic: pic@40000 {
304                         clock-frequency = <0>;
305                         interrupt-controller;
306                         #address-cells = <0>;
307                         #interrupt-cells = <2>;
308                         reg = <40000 40000>;
309                         built-in;
310                         compatible = "chrp,open-pic";
311                         device_type = "open-pic";
312                         big-endian;
313                 };
314         };
315 };