git.oblomov.eu Git - linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43
  44 #include <asm/system.h>
  45 #include <asm/io.h>
  46 #include <asm/byteorder.h>
  47 #include <asm/uaccess.h>
  48
  49 #ifdef CONFIG_SPARC64
  50 #include <asm/idprom.h>
  51 #include <asm/oplib.h>
  52 #include <asm/pbm.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #define TG3_TSO_SUPPORT 1
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define PFX DRV_MODULE_NAME     ": "
  67 #define DRV_MODULE_VERSION      "3.74"
  68 #define DRV_MODULE_RELDATE      "February 20, 2007"
  69
  70 #define TG3_DEF_MAC_MODE        0
  71 #define TG3_DEF_RX_MODE         0
  72 #define TG3_DEF_TX_MODE         0
  73 #define TG3_DEF_MSG_ENABLE        \
  74         (NETIF_MSG_DRV          | \
  75          NETIF_MSG_PROBE        | \
  76          NETIF_MSG_LINK         | \
  77          NETIF_MSG_TIMER        | \
  78          NETIF_MSG_IFDOWN       | \
  79          NETIF_MSG_IFUP         | \
  80          NETIF_MSG_RX_ERR       | \
  81          NETIF_MSG_TX_ERR)
  82
  83 /* length of time before we decide the hardware is borked,
  84  * and dev->tx_timeout() should be called to fix the problem
  85  */
  86 #define TG3_TX_TIMEOUT                  (5 * HZ)
  87
  88 /* hardware minimum and maximum for a single frame's data payload */
  89 #define TG3_MIN_MTU                     60
  90 #define TG3_MAX_MTU(tp) \
  91         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  92
  93 /* These numbers seem to be hard coded in the NIC firmware somehow.
  94  * You can't change the ring sizes, but you can change where you place
  95  * them in the NIC onboard memory.
  96  */
  97 #define TG3_RX_RING_SIZE                512
  98 #define TG3_DEF_RX_RING_PENDING         200
  99 #define TG3_RX_JUMBO_RING_SIZE          256
 100 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 101
 102 /* Do not place this n-ring entries value into the tp struct itself,
 103  * we really want to expose these constants to GCC so that modulo et
 104  * al.  operations are done with shifts and masks instead of with
 105  * hw multiply/modulo instructions.  Another solution would be to
 106  * replace things like '% foo' with '& (foo - 1)'.
 107  */
 108 #define TG3_RX_RCB_RING_SIZE(tp)        \
 109         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 110
 111 #define TG3_TX_RING_SIZE                512
 112 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 113
 114 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 115                                  TG3_RX_RING_SIZE)
 116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_JUMBO_RING_SIZE)
 118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 119                                    TG3_RX_RCB_RING_SIZE(tp))
 120 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 121                                  TG3_TX_RING_SIZE)
 122 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 123
 124 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 125 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 126
 127 /* minimum number of free TX descriptors required to wake up TX process */
 128 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 129
 130 /* number of ETHTOOL_GSTATS u64's */
 131 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 132
 133 #define TG3_NUM_TEST            6
 134
 135 static char version[] __devinitdata =
 136         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 137
 138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142
 143 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 144 module_param(tg3_debug, int, 0);
 145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 146
 147 static struct pci_device_id tg3_pci_tbl[] = {
 148         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 208         {}
 209 };
 210
 211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 212
 213 static const struct {
 214         const char string[ETH_GSTRING_LEN];
 215 } ethtool_stats_keys[TG3_NUM_STATS] = {
 216         { "rx_octets" },
 217         { "rx_fragments" },
 218         { "rx_ucast_packets" },
 219         { "rx_mcast_packets" },
 220         { "rx_bcast_packets" },
 221         { "rx_fcs_errors" },
 222         { "rx_align_errors" },
 223         { "rx_xon_pause_rcvd" },
 224         { "rx_xoff_pause_rcvd" },
 225         { "rx_mac_ctrl_rcvd" },
 226         { "rx_xoff_entered" },
 227         { "rx_frame_too_long_errors" },
 228         { "rx_jabbers" },
 229         { "rx_undersize_packets" },
 230         { "rx_in_length_errors" },
 231         { "rx_out_length_errors" },
 232         { "rx_64_or_less_octet_packets" },
 233         { "rx_65_to_127_octet_packets" },
 234         { "rx_128_to_255_octet_packets" },
 235         { "rx_256_to_511_octet_packets" },
 236         { "rx_512_to_1023_octet_packets" },
 237         { "rx_1024_to_1522_octet_packets" },
 238         { "rx_1523_to_2047_octet_packets" },
 239         { "rx_2048_to_4095_octet_packets" },
 240         { "rx_4096_to_8191_octet_packets" },
 241         { "rx_8192_to_9022_octet_packets" },
 242
 243         { "tx_octets" },
 244         { "tx_collisions" },
 245
 246         { "tx_xon_sent" },
 247         { "tx_xoff_sent" },
 248         { "tx_flow_control" },
 249         { "tx_mac_errors" },
 250         { "tx_single_collisions" },
 251         { "tx_mult_collisions" },
 252         { "tx_deferred" },
 253         { "tx_excessive_collisions" },
 254         { "tx_late_collisions" },
 255         { "tx_collide_2times" },
 256         { "tx_collide_3times" },
 257         { "tx_collide_4times" },
 258         { "tx_collide_5times" },
 259         { "tx_collide_6times" },
 260         { "tx_collide_7times" },
 261         { "tx_collide_8times" },
 262         { "tx_collide_9times" },
 263         { "tx_collide_10times" },
 264         { "tx_collide_11times" },
 265         { "tx_collide_12times" },
 266         { "tx_collide_13times" },
 267         { "tx_collide_14times" },
 268         { "tx_collide_15times" },
 269         { "tx_ucast_packets" },
 270         { "tx_mcast_packets" },
 271         { "tx_bcast_packets" },
 272         { "tx_carrier_sense_errors" },
 273         { "tx_discards" },
 274         { "tx_errors" },
 275
 276         { "dma_writeq_full" },
 277         { "dma_write_prioq_full" },
 278         { "rxbds_empty" },
 279         { "rx_discards" },
 280         { "rx_errors" },
 281         { "rx_threshold_hit" },
 282
 283         { "dma_readq_full" },
 284         { "dma_read_prioq_full" },
 285         { "tx_comp_queue_full" },
 286
 287         { "ring_set_send_prod_index" },
 288         { "ring_status_update" },
 289         { "nic_irqs" },
 290         { "nic_avoided_irqs" },
 291         { "nic_tx_threshold_hit" }
 292 };
 293
 294 static const struct {
 295         const char string[ETH_GSTRING_LEN];
 296 } ethtool_test_keys[TG3_NUM_TEST] = {
 297         { "nvram test     (online) " },
 298         { "link test      (online) " },
 299         { "register test  (offline)" },
 300         { "memory test    (offline)" },
 301         { "loopback test  (offline)" },
 302         { "interrupt test (offline)" },
 303 };
 304
 305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 306 {
 307         writel(val, tp->regs + off);
 308 }
 309
 310 static u32 tg3_read32(struct tg3 *tp, u32 off)
 311 {
 312         return (readl(tp->regs + off));
 313 }
 314
 315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 316 {
 317         unsigned long flags;
 318
 319         spin_lock_irqsave(&tp->indirect_lock, flags);
 320         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 321         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 322         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 323 }
 324
 325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 326 {
 327         writel(val, tp->regs + off);
 328         readl(tp->regs + off);
 329 }
 330
 331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 332 {
 333         unsigned long flags;
 334         u32 val;
 335
 336         spin_lock_irqsave(&tp->indirect_lock, flags);
 337         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 338         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 339         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 340         return val;
 341 }
 342
 343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 344 {
 345         unsigned long flags;
 346
 347         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 348                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 349                                        TG3_64BIT_REG_LOW, val);
 350                 return;
 351         }
 352         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 353                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 354                                        TG3_64BIT_REG_LOW, val);
 355                 return;
 356         }
 357
 358         spin_lock_irqsave(&tp->indirect_lock, flags);
 359         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 360         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 361         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 362
 363         /* In indirect mode when disabling interrupts, we also need
 364          * to clear the interrupt bit in the GRC local ctrl register.
 365          */
 366         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 367             (val == 0x1)) {
 368                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 369                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 370         }
 371 }
 372
 373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 374 {
 375         unsigned long flags;
 376         u32 val;
 377
 378         spin_lock_irqsave(&tp->indirect_lock, flags);
 379         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 380         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 381         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 382         return val;
 383 }
 384
 385 /* usec_wait specifies the wait time in usec when writing to certain registers
 386  * where it is unsafe to read back the register without some delay.
 387  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 388  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 389  */
 390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 391 {
 392         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 393             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 394                 /* Non-posted methods */
 395                 tp->write32(tp, off, val);
 396         else {
 397                 /* Posted method */
 398                 tg3_write32(tp, off, val);
 399                 if (usec_wait)
 400                         udelay(usec_wait);
 401                 tp->read32(tp, off);
 402         }
 403         /* Wait again after the read for the posted method to guarantee that
 404          * the wait time is met.
 405          */
 406         if (usec_wait)
 407                 udelay(usec_wait);
 408 }
 409
 410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 411 {
 412         tp->write32_mbox(tp, off, val);
 413         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 414             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 415                 tp->read32_mbox(tp, off);
 416 }
 417
 418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 419 {
 420         void __iomem *mbox = tp->regs + off;
 421         writel(val, mbox);
 422         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 423                 writel(val, mbox);
 424         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 425                 readl(mbox);
 426 }
 427
 428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 429 {
 430         return (readl(tp->regs + off + GRCMBOX_BASE));
 431 }
 432
 433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 434 {
 435         writel(val, tp->regs + off + GRCMBOX_BASE);
 436 }
 437
 438 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 439 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 440 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 441 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 442 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 443
 444 #define tw32(reg,val)           tp->write32(tp, reg, val)
 445 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 447 #define tr32(reg)               tp->read32(tp, reg)
 448
 449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 450 {
 451         unsigned long flags;
 452
 453         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 454             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 455                 return;
 456
 457         spin_lock_irqsave(&tp->indirect_lock, flags);
 458         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 459                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 460                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 461
 462                 /* Always leave this as zero. */
 463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 464         } else {
 465                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 466                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 467
 468                 /* Always leave this as zero. */
 469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 470         }
 471         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 472 }
 473
 474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 475 {
 476         unsigned long flags;
 477
 478         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 479             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 480                 *val = 0;
 481                 return;
 482         }
 483
 484         spin_lock_irqsave(&tp->indirect_lock, flags);
 485         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 486                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 487                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 488
 489                 /* Always leave this as zero. */
 490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 491         } else {
 492                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 493                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 494
 495                 /* Always leave this as zero. */
 496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 497         }
 498         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 499 }
 500
 501 static void tg3_disable_ints(struct tg3 *tp)
 502 {
 503         tw32(TG3PCI_MISC_HOST_CTRL,
 504              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 505         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 506 }
 507
 508 static inline void tg3_cond_int(struct tg3 *tp)
 509 {
 510         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 511             (tp->hw_status->status & SD_STATUS_UPDATED))
 512                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 513         else
 514                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 515                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 516 }
 517
 518 static void tg3_enable_ints(struct tg3 *tp)
 519 {
 520         tp->irq_sync = 0;
 521         wmb();
 522
 523         tw32(TG3PCI_MISC_HOST_CTRL,
 524              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 525         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 526                        (tp->last_tag << 24));
 527         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 528                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 529                                (tp->last_tag << 24));
 530         tg3_cond_int(tp);
 531 }
 532
 533 static inline unsigned int tg3_has_work(struct tg3 *tp)
 534 {
 535         struct tg3_hw_status *sblk = tp->hw_status;
 536         unsigned int work_exists = 0;
 537
 538         /* check for phy events */
 539         if (!(tp->tg3_flags &
 540               (TG3_FLAG_USE_LINKCHG_REG |
 541                TG3_FLAG_POLL_SERDES))) {
 542                 if (sblk->status & SD_STATUS_LINK_CHG)
 543                         work_exists = 1;
 544         }
 545         /* check for RX/TX work to do */
 546         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 547             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 548                 work_exists = 1;
 549
 550         return work_exists;
 551 }
 552
 553 /* tg3_restart_ints
 554  *  similar to tg3_enable_ints, but it accurately determines whether there
 555  *  is new work pending and can return without flushing the PIO write
 556  *  which reenables interrupts
 557  */
 558 static void tg3_restart_ints(struct tg3 *tp)
 559 {
 560         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 561                      tp->last_tag << 24);
 562         mmiowb();
 563
 564         /* When doing tagged status, this work check is unnecessary.
 565          * The last_tag we write above tells the chip which piece of
 566          * work we've completed.
 567          */
 568         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 569             tg3_has_work(tp))
 570                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 571                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 572 }
 573
 574 static inline void tg3_netif_stop(struct tg3 *tp)
 575 {
 576         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 577         netif_poll_disable(tp->dev);
 578         netif_tx_disable(tp->dev);
 579 }
 580
 581 static inline void tg3_netif_start(struct tg3 *tp)
 582 {
 583         netif_wake_queue(tp->dev);
 584         /* NOTE: unconditional netif_wake_queue is only appropriate
 585          * so long as all callers are assured to have free tx slots
 586          * (such as after tg3_init_hw)
 587          */
 588         netif_poll_enable(tp->dev);
 589         tp->hw_status->status |= SD_STATUS_UPDATED;
 590         tg3_enable_ints(tp);
 591 }
 592
 593 static void tg3_switch_clocks(struct tg3 *tp)
 594 {
 595         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 596         u32 orig_clock_ctrl;
 597
 598         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 599                 return;
 600
 601         orig_clock_ctrl = clock_ctrl;
 602         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 603                        CLOCK_CTRL_CLKRUN_OENABLE |
 604                        0x1f);
 605         tp->pci_clock_ctrl = clock_ctrl;
 606
 607         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 608                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 609                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 610                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 611                 }
 612         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 613                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 614                             clock_ctrl |
 615                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 616                             40);
 617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 618                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 619                             40);
 620         }
 621         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 622 }
 623
 624 #define PHY_BUSY_LOOPS  5000
 625
 626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 627 {
 628         u32 frame_val;
 629         unsigned int loops;
 630         int ret;
 631
 632         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 633                 tw32_f(MAC_MI_MODE,
 634                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 635                 udelay(80);
 636         }
 637
 638         *val = 0x0;
 639
 640         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 641                       MI_COM_PHY_ADDR_MASK);
 642         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 643                       MI_COM_REG_ADDR_MASK);
 644         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 645
 646         tw32_f(MAC_MI_COM, frame_val);
 647
 648         loops = PHY_BUSY_LOOPS;
 649         while (loops != 0) {
 650                 udelay(10);
 651                 frame_val = tr32(MAC_MI_COM);
 652
 653                 if ((frame_val & MI_COM_BUSY) == 0) {
 654                         udelay(5);
 655                         frame_val = tr32(MAC_MI_COM);
 656                         break;
 657                 }
 658                 loops -= 1;
 659         }
 660
 661         ret = -EBUSY;
 662         if (loops != 0) {
 663                 *val = frame_val & MI_COM_DATA_MASK;
 664                 ret = 0;
 665         }
 666
 667         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 668                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 669                 udelay(80);
 670         }
 671
 672         return ret;
 673 }
 674
 675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 676 {
 677         u32 frame_val;
 678         unsigned int loops;
 679         int ret;
 680
 681         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 682             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 683                 return 0;
 684
 685         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 686                 tw32_f(MAC_MI_MODE,
 687                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 688                 udelay(80);
 689         }
 690
 691         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 692                       MI_COM_PHY_ADDR_MASK);
 693         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 694                       MI_COM_REG_ADDR_MASK);
 695         frame_val |= (val & MI_COM_DATA_MASK);
 696         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 697
 698         tw32_f(MAC_MI_COM, frame_val);
 699
 700         loops = PHY_BUSY_LOOPS;
 701         while (loops != 0) {
 702                 udelay(10);
 703                 frame_val = tr32(MAC_MI_COM);
 704                 if ((frame_val & MI_COM_BUSY) == 0) {
 705                         udelay(5);
 706                         frame_val = tr32(MAC_MI_COM);
 707                         break;
 708                 }
 709                 loops -= 1;
 710         }
 711
 712         ret = -EBUSY;
 713         if (loops != 0)
 714                 ret = 0;
 715
 716         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 717                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 718                 udelay(80);
 719         }
 720
 721         return ret;
 722 }
 723
 724 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 725 {
 726         u32 val;
 727
 728         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 729                 return;
 730
 731         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 732             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 733                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 734                              (val | (1 << 15) | (1 << 4)));
 735 }
 736
 737 static int tg3_bmcr_reset(struct tg3 *tp)
 738 {
 739         u32 phy_control;
 740         int limit, err;
 741
 742         /* OK, reset it, and poll the BMCR_RESET bit until it
 743          * clears or we time out.
 744          */
 745         phy_control = BMCR_RESET;
 746         err = tg3_writephy(tp, MII_BMCR, phy_control);
 747         if (err != 0)
 748                 return -EBUSY;
 749
 750         limit = 5000;
 751         while (limit--) {
 752                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 753                 if (err != 0)
 754                         return -EBUSY;
 755
 756                 if ((phy_control & BMCR_RESET) == 0) {
 757                         udelay(40);
 758                         break;
 759                 }
 760                 udelay(10);
 761         }
 762         if (limit <= 0)
 763                 return -EBUSY;
 764
 765         return 0;
 766 }
 767
 768 static int tg3_wait_macro_done(struct tg3 *tp)
 769 {
 770         int limit = 100;
 771
 772         while (limit--) {
 773                 u32 tmp32;
 774
 775                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 776                         if ((tmp32 & 0x1000) == 0)
 777                                 break;
 778                 }
 779         }
 780         if (limit <= 0)
 781                 return -EBUSY;
 782
 783         return 0;
 784 }
 785
 786 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 787 {
 788         static const u32 test_pat[4][6] = {
 789         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 790         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 791         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 792         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 793         };
 794         int chan;
 795
 796         for (chan = 0; chan < 4; chan++) {
 797                 int i;
 798
 799                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 800                              (chan * 0x2000) | 0x0200);
 801                 tg3_writephy(tp, 0x16, 0x0002);
 802
 803                 for (i = 0; i < 6; i++)
 804                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 805                                      test_pat[chan][i]);
 806
 807                 tg3_writephy(tp, 0x16, 0x0202);
 808                 if (tg3_wait_macro_done(tp)) {
 809                         *resetp = 1;
 810                         return -EBUSY;
 811                 }
 812
 813                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 814                              (chan * 0x2000) | 0x0200);
 815                 tg3_writephy(tp, 0x16, 0x0082);
 816                 if (tg3_wait_macro_done(tp)) {
 817                         *resetp = 1;
 818                         return -EBUSY;
 819                 }
 820
 821                 tg3_writephy(tp, 0x16, 0x0802);
 822                 if (tg3_wait_macro_done(tp)) {
 823                         *resetp = 1;
 824                         return -EBUSY;
 825                 }
 826
 827                 for (i = 0; i < 6; i += 2) {
 828                         u32 low, high;
 829
 830                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 831                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 832                             tg3_wait_macro_done(tp)) {
 833                                 *resetp = 1;
 834                                 return -EBUSY;
 835                         }
 836                         low &= 0x7fff;
 837                         high &= 0x000f;
 838                         if (low != test_pat[chan][i] ||
 839                             high != test_pat[chan][i+1]) {
 840                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 841                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 842                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 843
 844                                 return -EBUSY;
 845                         }
 846                 }
 847         }
 848
 849         return 0;
 850 }
 851
 852 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 853 {
 854         int chan;
 855
 856         for (chan = 0; chan < 4; chan++) {
 857                 int i;
 858
 859                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 860                              (chan * 0x2000) | 0x0200);
 861                 tg3_writephy(tp, 0x16, 0x0002);
 862                 for (i = 0; i < 6; i++)
 863                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 864                 tg3_writephy(tp, 0x16, 0x0202);
 865                 if (tg3_wait_macro_done(tp))
 866                         return -EBUSY;
 867         }
 868
 869         return 0;
 870 }
 871
 872 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 873 {
 874         u32 reg32, phy9_orig;
 875         int retries, do_phy_reset, err;
 876
 877         retries = 10;
 878         do_phy_reset = 1;
 879         do {
 880                 if (do_phy_reset) {
 881                         err = tg3_bmcr_reset(tp);
 882                         if (err)
 883                                 return err;
 884                         do_phy_reset = 0;
 885                 }
 886
 887                 /* Disable transmitter and interrupt.  */
 888                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 889                         continue;
 890
 891                 reg32 |= 0x3000;
 892                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 893
 894                 /* Set full-duplex, 1000 mbps.  */
 895                 tg3_writephy(tp, MII_BMCR,
 896                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 897
 898                 /* Set to master mode.  */
 899                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 900                         continue;
 901
 902                 tg3_writephy(tp, MII_TG3_CTRL,
 903                              (MII_TG3_CTRL_AS_MASTER |
 904                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 905
 906                 /* Enable SM_DSP_CLOCK and 6dB.  */
 907                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 908
 909                 /* Block the PHY control access.  */
 910                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 911                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 912
 913                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 914                 if (!err)
 915                         break;
 916         } while (--retries);
 917
 918         err = tg3_phy_reset_chanpat(tp);
 919         if (err)
 920                 return err;
 921
 922         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 923         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 924
 925         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 926         tg3_writephy(tp, 0x16, 0x0000);
 927
 928         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 929             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 930                 /* Set Extended packet length bit for jumbo frames */
 931                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 932         }
 933         else {
 934                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 935         }
 936
 937         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 938
 939         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 940                 reg32 &= ~0x3000;
 941                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 942         } else if (!err)
 943                 err = -EBUSY;
 944
 945         return err;
 946 }
 947
 948 static void tg3_link_report(struct tg3 *);
 949
 950 /* This will reset the tigon3 PHY if there is no valid
 951  * link unless the FORCE argument is non-zero.
 952  */
 953 static int tg3_phy_reset(struct tg3 *tp)
 954 {
 955         u32 phy_status;
 956         int err;
 957
 958         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 959                 u32 val;
 960
 961                 val = tr32(GRC_MISC_CFG);
 962                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
 963                 udelay(40);
 964         }
 965         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 966         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 967         if (err != 0)
 968                 return -EBUSY;
 969
 970         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 971                 netif_carrier_off(tp->dev);
 972                 tg3_link_report(tp);
 973         }
 974
 975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 978                 err = tg3_phy_reset_5703_4_5(tp);
 979                 if (err)
 980                         return err;
 981                 goto out;
 982         }
 983
 984         err = tg3_bmcr_reset(tp);
 985         if (err)
 986                 return err;
 987
 988 out:
 989         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 990                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 991                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 992                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 993                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 994                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 996         }
 997         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 998                 tg3_writephy(tp, 0x1c, 0x8d68);
 999                 tg3_writephy(tp, 0x1c, 0x8d68);
1000         }
1001         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010         }
1011         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1014                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016                         tg3_writephy(tp, MII_TG3_TEST1,
1017                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1018                 } else
1019                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021         }
1022         /* Set Extended packet length bit (bit 14) on all chips that */
1023         /* support jumbo frames */
1024         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025                 /* Cannot do read-modify-write on 5401 */
1026                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1027         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1028                 u32 phy_reg;
1029
1030                 /* Set bit 14 with read-modify-write to preserve other bits */
1031                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034         }
1035
1036         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037          * jumbo frames transmission.
1038          */
1039         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1040                 u32 phy_reg;
1041
1042                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045         }
1046
1047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048                 u32 phy_reg;
1049
1050                 /* adjust output voltage */
1051                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054                         u32 phy_reg2;
1055
1056                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058                         /* Enable auto-MDIX */
1059                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062                 }
1063         }
1064
1065         tg3_phy_set_wirespeed(tp);
1066         return 0;
1067 }
1068
1069 static void tg3_frob_aux_power(struct tg3 *tp)
1070 {
1071         struct tg3 *tp_peer = tp;
1072
1073         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1074                 return;
1075
1076         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078                 struct net_device *dev_peer;
1079
1080                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1081                 /* remove_one() may have been run on the peer. */
1082                 if (!dev_peer)
1083                         tp_peer = tp;
1084                 else
1085                         tp_peer = netdev_priv(dev_peer);
1086         }
1087
1088         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1089             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1092                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095                                     (GRC_LCLCTRL_GPIO_OE0 |
1096                                      GRC_LCLCTRL_GPIO_OE1 |
1097                                      GRC_LCLCTRL_GPIO_OE2 |
1098                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1099                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1100                                     100);
1101                 } else {
1102                         u32 no_gpio2;
1103                         u32 grc_local_ctrl = 0;
1104
1105                         if (tp_peer != tp &&
1106                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107                                 return;
1108
1109                         /* Workaround to prevent overdrawing Amps. */
1110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111                             ASIC_REV_5714) {
1112                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1113                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114                                             grc_local_ctrl, 100);
1115                         }
1116
1117                         /* On 5753 and variants, GPIO2 cannot be used. */
1118                         no_gpio2 = tp->nic_sram_data_cfg &
1119                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
1121                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1122                                          GRC_LCLCTRL_GPIO_OE1 |
1123                                          GRC_LCLCTRL_GPIO_OE2 |
1124                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1125                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1126                         if (no_gpio2) {
1127                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1129                         }
1130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131                                                     grc_local_ctrl, 100);
1132
1133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
1135                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136                                                     grc_local_ctrl, 100);
1137
1138                         if (!no_gpio2) {
1139                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1140                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141                                             grc_local_ctrl, 100);
1142                         }
1143                 }
1144         } else {
1145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147                         if (tp_peer != tp &&
1148                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149                                 return;
1150
1151                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152                                     (GRC_LCLCTRL_GPIO_OE1 |
1153                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1154
1155                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156                                     GRC_LCLCTRL_GPIO_OE1, 100);
1157
1158                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159                                     (GRC_LCLCTRL_GPIO_OE1 |
1160                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1161                 }
1162         }
1163 }
1164
1165 static int tg3_setup_phy(struct tg3 *, int);
1166
1167 #define RESET_KIND_SHUTDOWN     0
1168 #define RESET_KIND_INIT         1
1169 #define RESET_KIND_SUSPEND      2
1170
1171 static void tg3_write_sig_post_reset(struct tg3 *, int);
1172 static int tg3_halt_cpu(struct tg3 *, u32);
1173 static int tg3_nvram_lock(struct tg3 *);
1174 static void tg3_nvram_unlock(struct tg3 *);
1175
1176 static void tg3_power_down_phy(struct tg3 *tp)
1177 {
1178         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1179                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1180                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1181                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1182
1183                         sg_dig_ctrl |=
1184                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1185                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1186                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1187                 }
1188                 return;
1189         }
1190
1191         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1192                 u32 val;
1193
1194                 tg3_bmcr_reset(tp);
1195                 val = tr32(GRC_MISC_CFG);
1196                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1197                 udelay(40);
1198                 return;
1199         } else {
1200                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1201                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1202                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1203         }
1204
1205         /* The PHY should not be powered down on some chips because
1206          * of bugs.
1207          */
1208         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1209             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1210             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1211              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1212                 return;
1213         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1214 }
1215
1216 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1217 {
1218         u32 misc_host_ctrl;
1219         u16 power_control, power_caps;
1220         int pm = tp->pm_cap;
1221
1222         /* Make sure register accesses (indirect or otherwise)
1223          * will function correctly.
1224          */
1225         pci_write_config_dword(tp->pdev,
1226                                TG3PCI_MISC_HOST_CTRL,
1227                                tp->misc_host_ctrl);
1228
1229         pci_read_config_word(tp->pdev,
1230                              pm + PCI_PM_CTRL,
1231                              &power_control);
1232         power_control |= PCI_PM_CTRL_PME_STATUS;
1233         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1234         switch (state) {
1235         case PCI_D0:
1236                 power_control |= 0;
1237                 pci_write_config_word(tp->pdev,
1238                                       pm + PCI_PM_CTRL,
1239                                       power_control);
1240                 udelay(100);    /* Delay after power state change */
1241
1242                 /* Switch out of Vaux if it is a NIC */
1243                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1244                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1245
1246                 return 0;
1247
1248         case PCI_D1:
1249                 power_control |= 1;
1250                 break;
1251
1252         case PCI_D2:
1253                 power_control |= 2;
1254                 break;
1255
1256         case PCI_D3hot:
1257                 power_control |= 3;
1258                 break;
1259
1260         default:
1261                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1262                        "requested.\n",
1263                        tp->dev->name, state);
1264                 return -EINVAL;
1265         };
1266
1267         power_control |= PCI_PM_CTRL_PME_ENABLE;
1268
1269         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1270         tw32(TG3PCI_MISC_HOST_CTRL,
1271              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1272
1273         if (tp->link_config.phy_is_low_power == 0) {
1274                 tp->link_config.phy_is_low_power = 1;
1275                 tp->link_config.orig_speed = tp->link_config.speed;
1276                 tp->link_config.orig_duplex = tp->link_config.duplex;
1277                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1278         }
1279
1280         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1281                 tp->link_config.speed = SPEED_10;
1282                 tp->link_config.duplex = DUPLEX_HALF;
1283                 tp->link_config.autoneg = AUTONEG_ENABLE;
1284                 tg3_setup_phy(tp, 0);
1285         }
1286
1287         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1288                 u32 val;
1289
1290                 val = tr32(GRC_VCPU_EXT_CTRL);
1291                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1292         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1293                 int i;
1294                 u32 val;
1295
1296                 for (i = 0; i < 200; i++) {
1297                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1298                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1299                                 break;
1300                         msleep(1);
1301                 }
1302         }
1303         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1304                                              WOL_DRV_STATE_SHUTDOWN |
1305                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1306
1307         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1308
1309         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1310                 u32 mac_mode;
1311
1312                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1313                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1314                         udelay(40);
1315
1316                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1317                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1318                         else
1319                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1320
1321                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1322                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1323                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1324                 } else {
1325                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1326                 }
1327
1328                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1329                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1330
1331                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1332                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1333                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1334
1335                 tw32_f(MAC_MODE, mac_mode);
1336                 udelay(100);
1337
1338                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1339                 udelay(10);
1340         }
1341
1342         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1343             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1344              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1345                 u32 base_val;
1346
1347                 base_val = tp->pci_clock_ctrl;
1348                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1349                              CLOCK_CTRL_TXCLK_DISABLE);
1350
1351                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1352                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1353         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1354                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1355                 /* do nothing */
1356         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1357                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1358                 u32 newbits1, newbits2;
1359
1360                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1361                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1362                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1363                                     CLOCK_CTRL_TXCLK_DISABLE |
1364                                     CLOCK_CTRL_ALTCLK);
1365                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1366                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1367                         newbits1 = CLOCK_CTRL_625_CORE;
1368                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1369                 } else {
1370                         newbits1 = CLOCK_CTRL_ALTCLK;
1371                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1372                 }
1373
1374                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1375                             40);
1376
1377                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1378                             40);
1379
1380                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1381                         u32 newbits3;
1382
1383                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1384                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1385                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1386                                             CLOCK_CTRL_TXCLK_DISABLE |
1387                                             CLOCK_CTRL_44MHZ_CORE);
1388                         } else {
1389                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1390                         }
1391
1392                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1393                                     tp->pci_clock_ctrl | newbits3, 40);
1394                 }
1395         }
1396
1397         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1398             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1399                 tg3_power_down_phy(tp);
1400
1401         tg3_frob_aux_power(tp);
1402
1403         /* Workaround for unstable PLL clock */
1404         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1405             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1406                 u32 val = tr32(0x7d00);
1407
1408                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1409                 tw32(0x7d00, val);
1410                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1411                         int err;
1412
1413                         err = tg3_nvram_lock(tp);
1414                         tg3_halt_cpu(tp, RX_CPU_BASE);
1415                         if (!err)
1416                                 tg3_nvram_unlock(tp);
1417                 }
1418         }
1419
1420         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1421
1422         /* Finally, set the new power state. */
1423         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1424         udelay(100);    /* Delay after power state change */
1425
1426         return 0;
1427 }
1428
1429 static void tg3_link_report(struct tg3 *tp)
1430 {
1431         if (!netif_carrier_ok(tp->dev)) {
1432                 if (netif_msg_link(tp))
1433                         printk(KERN_INFO PFX "%s: Link is down.\n",
1434                                tp->dev->name);
1435         } else if (netif_msg_link(tp)) {
1436                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1437                        tp->dev->name,
1438                        (tp->link_config.active_speed == SPEED_1000 ?
1439                         1000 :
1440                         (tp->link_config.active_speed == SPEED_100 ?
1441                          100 : 10)),
1442                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1443                         "full" : "half"));
1444
1445                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1446                        "%s for RX.\n",
1447                        tp->dev->name,
1448                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1449                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1450         }
1451 }
1452
1453 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1454 {
1455         u32 new_tg3_flags = 0;
1456         u32 old_rx_mode = tp->rx_mode;
1457         u32 old_tx_mode = tp->tx_mode;
1458
1459         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1460
1461                 /* Convert 1000BaseX flow control bits to 1000BaseT
1462                  * bits before resolving flow control.
1463                  */
1464                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1465                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1466                                        ADVERTISE_PAUSE_ASYM);
1467                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1468
1469                         if (local_adv & ADVERTISE_1000XPAUSE)
1470                                 local_adv |= ADVERTISE_PAUSE_CAP;
1471                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1472                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1473                         if (remote_adv & LPA_1000XPAUSE)
1474                                 remote_adv |= LPA_PAUSE_CAP;
1475                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1476                                 remote_adv |= LPA_PAUSE_ASYM;
1477                 }
1478
1479                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1480                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1481                                 if (remote_adv & LPA_PAUSE_CAP)
1482                                         new_tg3_flags |=
1483                                                 (TG3_FLAG_RX_PAUSE |
1484                                                 TG3_FLAG_TX_PAUSE);
1485                                 else if (remote_adv & LPA_PAUSE_ASYM)
1486                                         new_tg3_flags |=
1487                                                 (TG3_FLAG_RX_PAUSE);
1488                         } else {
1489                                 if (remote_adv & LPA_PAUSE_CAP)
1490                                         new_tg3_flags |=
1491                                                 (TG3_FLAG_RX_PAUSE |
1492                                                 TG3_FLAG_TX_PAUSE);
1493                         }
1494                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1495                         if ((remote_adv & LPA_PAUSE_CAP) &&
1496                         (remote_adv & LPA_PAUSE_ASYM))
1497                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1498                 }
1499
1500                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1501                 tp->tg3_flags |= new_tg3_flags;
1502         } else {
1503                 new_tg3_flags = tp->tg3_flags;
1504         }
1505
1506         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1507                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1508         else
1509                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1510
1511         if (old_rx_mode != tp->rx_mode) {
1512                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1513         }
1514
1515         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1516                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1517         else
1518                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1519
1520         if (old_tx_mode != tp->tx_mode) {
1521                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1522         }
1523 }
1524
1525 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1526 {
1527         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1528         case MII_TG3_AUX_STAT_10HALF:
1529                 *speed = SPEED_10;
1530                 *duplex = DUPLEX_HALF;
1531                 break;
1532
1533         case MII_TG3_AUX_STAT_10FULL:
1534                 *speed = SPEED_10;
1535                 *duplex = DUPLEX_FULL;
1536                 break;
1537
1538         case MII_TG3_AUX_STAT_100HALF:
1539                 *speed = SPEED_100;
1540                 *duplex = DUPLEX_HALF;
1541                 break;
1542
1543         case MII_TG3_AUX_STAT_100FULL:
1544                 *speed = SPEED_100;
1545                 *duplex = DUPLEX_FULL;
1546                 break;
1547
1548         case MII_TG3_AUX_STAT_1000HALF:
1549                 *speed = SPEED_1000;
1550                 *duplex = DUPLEX_HALF;
1551                 break;
1552
1553         case MII_TG3_AUX_STAT_1000FULL:
1554                 *speed = SPEED_1000;
1555                 *duplex = DUPLEX_FULL;
1556                 break;
1557
1558         default:
1559                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1560                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1561                                  SPEED_10;
1562                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1563                                   DUPLEX_HALF;
1564                         break;
1565                 }
1566                 *speed = SPEED_INVALID;
1567                 *duplex = DUPLEX_INVALID;
1568                 break;
1569         };
1570 }
1571
1572 static void tg3_phy_copper_begin(struct tg3 *tp)
1573 {
1574         u32 new_adv;
1575         int i;
1576
1577         if (tp->link_config.phy_is_low_power) {
1578                 /* Entering low power mode.  Disable gigabit and
1579                  * 100baseT advertisements.
1580                  */
1581                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1582
1583                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1584                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1585                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1586                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1587
1588                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1589         } else if (tp->link_config.speed == SPEED_INVALID) {
1590                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1591                         tp->link_config.advertising &=
1592                                 ~(ADVERTISED_1000baseT_Half |
1593                                   ADVERTISED_1000baseT_Full);
1594
1595                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1596                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1597                         new_adv |= ADVERTISE_10HALF;
1598                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1599                         new_adv |= ADVERTISE_10FULL;
1600                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1601                         new_adv |= ADVERTISE_100HALF;
1602                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1603                         new_adv |= ADVERTISE_100FULL;
1604                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1605
1606                 if (tp->link_config.advertising &
1607                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1608                         new_adv = 0;
1609                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1610                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1611                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1612                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1613                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1614                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1615                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1616                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1617                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1618                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1619                 } else {
1620                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1621                 }
1622         } else {
1623                 /* Asking for a specific link mode. */
1624                 if (tp->link_config.speed == SPEED_1000) {
1625                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1626                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1627
1628                         if (tp->link_config.duplex == DUPLEX_FULL)
1629                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1630                         else
1631                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1632                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1633                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1634                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1635                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1636                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1637                 } else {
1638                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1639
1640                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1641                         if (tp->link_config.speed == SPEED_100) {
1642                                 if (tp->link_config.duplex == DUPLEX_FULL)
1643                                         new_adv |= ADVERTISE_100FULL;
1644                                 else
1645                                         new_adv |= ADVERTISE_100HALF;
1646                         } else {
1647                                 if (tp->link_config.duplex == DUPLEX_FULL)
1648                                         new_adv |= ADVERTISE_10FULL;
1649                                 else
1650                                         new_adv |= ADVERTISE_10HALF;
1651                         }
1652                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1653                 }
1654         }
1655
1656         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1657             tp->link_config.speed != SPEED_INVALID) {
1658                 u32 bmcr, orig_bmcr;
1659
1660                 tp->link_config.active_speed = tp->link_config.speed;
1661                 tp->link_config.active_duplex = tp->link_config.duplex;
1662
1663                 bmcr = 0;
1664                 switch (tp->link_config.speed) {
1665                 default:
1666                 case SPEED_10:
1667                         break;
1668
1669                 case SPEED_100:
1670                         bmcr |= BMCR_SPEED100;
1671                         break;
1672
1673                 case SPEED_1000:
1674                         bmcr |= TG3_BMCR_SPEED1000;
1675                         break;
1676                 };
1677
1678                 if (tp->link_config.duplex == DUPLEX_FULL)
1679                         bmcr |= BMCR_FULLDPLX;
1680
1681                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1682                     (bmcr != orig_bmcr)) {
1683                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1684                         for (i = 0; i < 1500; i++) {
1685                                 u32 tmp;
1686
1687                                 udelay(10);
1688                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1689                                     tg3_readphy(tp, MII_BMSR, &tmp))
1690                                         continue;
1691                                 if (!(tmp & BMSR_LSTATUS)) {
1692                                         udelay(40);
1693                                         break;
1694                                 }
1695                         }
1696                         tg3_writephy(tp, MII_BMCR, bmcr);
1697                         udelay(40);
1698                 }
1699         } else {
1700                 tg3_writephy(tp, MII_BMCR,
1701                              BMCR_ANENABLE | BMCR_ANRESTART);
1702         }
1703 }
1704
1705 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1706 {
1707         int err;
1708
1709         /* Turn off tap power management. */
1710         /* Set Extended packet length bit */
1711         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1712
1713         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1714         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1715
1716         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1717         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1718
1719         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1720         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1721
1722         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1723         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1724
1725         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1726         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1727
1728         udelay(40);
1729
1730         return err;
1731 }
1732
1733 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1734 {
1735         u32 adv_reg, all_mask = 0;
1736
1737         if (mask & ADVERTISED_10baseT_Half)
1738                 all_mask |= ADVERTISE_10HALF;
1739         if (mask & ADVERTISED_10baseT_Full)
1740                 all_mask |= ADVERTISE_10FULL;
1741         if (mask & ADVERTISED_100baseT_Half)
1742                 all_mask |= ADVERTISE_100HALF;
1743         if (mask & ADVERTISED_100baseT_Full)
1744                 all_mask |= ADVERTISE_100FULL;
1745
1746         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1747                 return 0;
1748
1749         if ((adv_reg & all_mask) != all_mask)
1750                 return 0;
1751         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1752                 u32 tg3_ctrl;
1753
1754                 all_mask = 0;
1755                 if (mask & ADVERTISED_1000baseT_Half)
1756                         all_mask |= ADVERTISE_1000HALF;
1757                 if (mask & ADVERTISED_1000baseT_Full)
1758                         all_mask |= ADVERTISE_1000FULL;
1759
1760                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1761                         return 0;
1762
1763                 if ((tg3_ctrl & all_mask) != all_mask)
1764                         return 0;
1765         }
1766         return 1;
1767 }
1768
1769 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1770 {
1771         int current_link_up;
1772         u32 bmsr, dummy;
1773         u16 current_speed;
1774         u8 current_duplex;
1775         int i, err;
1776
1777         tw32(MAC_EVENT, 0);
1778
1779         tw32_f(MAC_STATUS,
1780              (MAC_STATUS_SYNC_CHANGED |
1781               MAC_STATUS_CFG_CHANGED |
1782               MAC_STATUS_MI_COMPLETION |
1783               MAC_STATUS_LNKSTATE_CHANGED));
1784         udelay(40);
1785
1786         tp->mi_mode = MAC_MI_MODE_BASE;
1787         tw32_f(MAC_MI_MODE, tp->mi_mode);
1788         udelay(80);
1789
1790         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1791
1792         /* Some third-party PHYs need to be reset on link going
1793          * down.
1794          */
1795         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1796              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1797              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1798             netif_carrier_ok(tp->dev)) {
1799                 tg3_readphy(tp, MII_BMSR, &bmsr);
1800                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1801                     !(bmsr & BMSR_LSTATUS))
1802                         force_reset = 1;
1803         }
1804         if (force_reset)
1805                 tg3_phy_reset(tp);
1806
1807         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1808                 tg3_readphy(tp, MII_BMSR, &bmsr);
1809                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1810                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1811                         bmsr = 0;
1812
1813                 if (!(bmsr & BMSR_LSTATUS)) {
1814                         err = tg3_init_5401phy_dsp(tp);
1815                         if (err)
1816                                 return err;
1817
1818                         tg3_readphy(tp, MII_BMSR, &bmsr);
1819                         for (i = 0; i < 1000; i++) {
1820                                 udelay(10);
1821                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1822                                     (bmsr & BMSR_LSTATUS)) {
1823                                         udelay(40);
1824                                         break;
1825                                 }
1826                         }
1827
1828                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1829                             !(bmsr & BMSR_LSTATUS) &&
1830                             tp->link_config.active_speed == SPEED_1000) {
1831                                 err = tg3_phy_reset(tp);
1832                                 if (!err)
1833                                         err = tg3_init_5401phy_dsp(tp);
1834                                 if (err)
1835                                         return err;
1836                         }
1837                 }
1838         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1839                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1840                 /* 5701 {A0,B0} CRC bug workaround */
1841                 tg3_writephy(tp, 0x15, 0x0a75);
1842                 tg3_writephy(tp, 0x1c, 0x8c68);
1843                 tg3_writephy(tp, 0x1c, 0x8d68);
1844                 tg3_writephy(tp, 0x1c, 0x8c68);
1845         }
1846
1847         /* Clear pending interrupts... */
1848         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1849         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1850
1851         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1852                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1853         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1854                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1855
1856         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1857             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1858                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1859                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1860                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1861                 else
1862                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1863         }
1864
1865         current_link_up = 0;
1866         current_speed = SPEED_INVALID;
1867         current_duplex = DUPLEX_INVALID;
1868
1869         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1870                 u32 val;
1871
1872                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1873                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1874                 if (!(val & (1 << 10))) {
1875                         val |= (1 << 10);
1876                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1877                         goto relink;
1878                 }
1879         }
1880
1881         bmsr = 0;
1882         for (i = 0; i < 100; i++) {
1883                 tg3_readphy(tp, MII_BMSR, &bmsr);
1884                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1885                     (bmsr & BMSR_LSTATUS))
1886                         break;
1887                 udelay(40);
1888         }
1889
1890         if (bmsr & BMSR_LSTATUS) {
1891                 u32 aux_stat, bmcr;
1892
1893                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1894                 for (i = 0; i < 2000; i++) {
1895                         udelay(10);
1896                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1897                             aux_stat)
1898                                 break;
1899                 }
1900
1901                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1902                                              &current_speed,
1903                                              &current_duplex);
1904
1905                 bmcr = 0;
1906                 for (i = 0; i < 200; i++) {
1907                         tg3_readphy(tp, MII_BMCR, &bmcr);
1908                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1909                                 continue;
1910                         if (bmcr && bmcr != 0x7fff)
1911                                 break;
1912                         udelay(10);
1913                 }
1914
1915                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1916                         if (bmcr & BMCR_ANENABLE) {
1917                                 current_link_up = 1;
1918
1919                                 /* Force autoneg restart if we are exiting
1920                                  * low power mode.
1921                                  */
1922                                 if (!tg3_copper_is_advertising_all(tp,
1923                                                 tp->link_config.advertising))
1924                                         current_link_up = 0;
1925                         } else {
1926                                 current_link_up = 0;
1927                         }
1928                 } else {
1929                         if (!(bmcr & BMCR_ANENABLE) &&
1930                             tp->link_config.speed == current_speed &&
1931                             tp->link_config.duplex == current_duplex) {
1932                                 current_link_up = 1;
1933                         } else {
1934                                 current_link_up = 0;
1935                         }
1936                 }
1937
1938                 tp->link_config.active_speed = current_speed;
1939                 tp->link_config.active_duplex = current_duplex;
1940         }
1941
1942         if (current_link_up == 1 &&
1943             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1944             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1945                 u32 local_adv, remote_adv;
1946
1947                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1948                         local_adv = 0;
1949                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1950
1951                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1952                         remote_adv = 0;
1953
1954                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1955
1956                 /* If we are not advertising full pause capability,
1957                  * something is wrong.  Bring the link down and reconfigure.
1958                  */
1959                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1960                         current_link_up = 0;
1961                 } else {
1962                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1963                 }
1964         }
1965 relink:
1966         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1967                 u32 tmp;
1968
1969                 tg3_phy_copper_begin(tp);
1970
1971                 tg3_readphy(tp, MII_BMSR, &tmp);
1972                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1973                     (tmp & BMSR_LSTATUS))
1974                         current_link_up = 1;
1975         }
1976
1977         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1978         if (current_link_up == 1) {
1979                 if (tp->link_config.active_speed == SPEED_100 ||
1980                     tp->link_config.active_speed == SPEED_10)
1981                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1982                 else
1983                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1984         } else
1985                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1986
1987         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1988         if (tp->link_config.active_duplex == DUPLEX_HALF)
1989                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1990
1991         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1993                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1994                     (current_link_up == 1 &&
1995                      tp->link_config.active_speed == SPEED_10))
1996                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1997         } else {
1998                 if (current_link_up == 1)
1999                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2000         }
2001
2002         /* ??? Without this setting Netgear GA302T PHY does not
2003          * ??? send/receive packets...
2004          */
2005         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2006             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2007                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2008                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2009                 udelay(80);
2010         }
2011
2012         tw32_f(MAC_MODE, tp->mac_mode);
2013         udelay(40);
2014
2015         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2016                 /* Polled via timer. */
2017                 tw32_f(MAC_EVENT, 0);
2018         } else {
2019                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2020         }
2021         udelay(40);
2022
2023         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2024             current_link_up == 1 &&
2025             tp->link_config.active_speed == SPEED_1000 &&
2026             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2027              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2028                 udelay(120);
2029                 tw32_f(MAC_STATUS,
2030                      (MAC_STATUS_SYNC_CHANGED |
2031                       MAC_STATUS_CFG_CHANGED));
2032                 udelay(40);
2033                 tg3_write_mem(tp,
2034                               NIC_SRAM_FIRMWARE_MBOX,
2035                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2036         }
2037
2038         if (current_link_up != netif_carrier_ok(tp->dev)) {
2039                 if (current_link_up)
2040                         netif_carrier_on(tp->dev);
2041                 else
2042                         netif_carrier_off(tp->dev);
2043                 tg3_link_report(tp);
2044         }
2045
2046         return 0;
2047 }
2048
2049 struct tg3_fiber_aneginfo {
2050         int state;
2051 #define ANEG_STATE_UNKNOWN              0
2052 #define ANEG_STATE_AN_ENABLE            1
2053 #define ANEG_STATE_RESTART_INIT         2
2054 #define ANEG_STATE_RESTART              3
2055 #define ANEG_STATE_DISABLE_LINK_OK      4
2056 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2057 #define ANEG_STATE_ABILITY_DETECT       6
2058 #define ANEG_STATE_ACK_DETECT_INIT      7
2059 #define ANEG_STATE_ACK_DETECT           8
2060 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2061 #define ANEG_STATE_COMPLETE_ACK         10
2062 #define ANEG_STATE_IDLE_DETECT_INIT     11
2063 #define ANEG_STATE_IDLE_DETECT          12
2064 #define ANEG_STATE_LINK_OK              13
2065 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2066 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2067
2068         u32 flags;
2069 #define MR_AN_ENABLE            0x00000001
2070 #define MR_RESTART_AN           0x00000002
2071 #define MR_AN_COMPLETE          0x00000004
2072 #define MR_PAGE_RX              0x00000008
2073 #define MR_NP_LOADED            0x00000010
2074 #define MR_TOGGLE_TX            0x00000020
2075 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2076 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2077 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2078 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2079 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2080 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2081 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2082 #define MR_TOGGLE_RX            0x00002000
2083 #define MR_NP_RX                0x00004000
2084
2085 #define MR_LINK_OK              0x80000000
2086
2087         unsigned long link_time, cur_time;
2088
2089         u32 ability_match_cfg;
2090         int ability_match_count;
2091
2092         char ability_match, idle_match, ack_match;
2093
2094         u32 txconfig, rxconfig;
2095 #define ANEG_CFG_NP             0x00000080
2096 #define ANEG_CFG_ACK            0x00000040
2097 #define ANEG_CFG_RF2            0x00000020
2098 #define ANEG_CFG_RF1            0x00000010
2099 #define ANEG_CFG_PS2            0x00000001
2100 #define ANEG_CFG_PS1            0x00008000
2101 #define ANEG_CFG_HD             0x00004000
2102 #define ANEG_CFG_FD             0x00002000
2103 #define ANEG_CFG_INVAL          0x00001f06
2104
2105 };
2106 #define ANEG_OK         0
2107 #define ANEG_DONE       1
2108 #define ANEG_TIMER_ENAB 2
2109 #define ANEG_FAILED     -1
2110
2111 #define ANEG_STATE_SETTLE_TIME  10000
2112
2113 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2114                                    struct tg3_fiber_aneginfo *ap)
2115 {
2116         unsigned long delta;
2117         u32 rx_cfg_reg;
2118         int ret;
2119
2120         if (ap->state == ANEG_STATE_UNKNOWN) {
2121                 ap->rxconfig = 0;
2122                 ap->link_time = 0;
2123                 ap->cur_time = 0;
2124                 ap->ability_match_cfg = 0;
2125                 ap->ability_match_count = 0;
2126                 ap->ability_match = 0;
2127                 ap->idle_match = 0;
2128                 ap->ack_match = 0;
2129         }
2130         ap->cur_time++;
2131
2132         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2133                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2134
2135                 if (rx_cfg_reg != ap->ability_match_cfg) {
2136                         ap->ability_match_cfg = rx_cfg_reg;
2137                         ap->ability_match = 0;
2138                         ap->ability_match_count = 0;
2139                 } else {
2140                         if (++ap->ability_match_count > 1) {
2141                                 ap->ability_match = 1;
2142                                 ap->ability_match_cfg = rx_cfg_reg;
2143                         }
2144                 }
2145                 if (rx_cfg_reg & ANEG_CFG_ACK)
2146                         ap->ack_match = 1;
2147                 else
2148                         ap->ack_match = 0;
2149
2150                 ap->idle_match = 0;
2151         } else {
2152                 ap->idle_match = 1;
2153                 ap->ability_match_cfg = 0;
2154                 ap->ability_match_count = 0;
2155                 ap->ability_match = 0;
2156                 ap->ack_match = 0;
2157
2158                 rx_cfg_reg = 0;
2159         }
2160
2161         ap->rxconfig = rx_cfg_reg;
2162         ret = ANEG_OK;
2163
2164         switch(ap->state) {
2165         case ANEG_STATE_UNKNOWN:
2166                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2167                         ap->state = ANEG_STATE_AN_ENABLE;
2168
2169                 /* fallthru */
2170         case ANEG_STATE_AN_ENABLE:
2171                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2172                 if (ap->flags & MR_AN_ENABLE) {
2173                         ap->link_time = 0;
2174                         ap->cur_time = 0;
2175                         ap->ability_match_cfg = 0;
2176                         ap->ability_match_count = 0;
2177                         ap->ability_match = 0;
2178                         ap->idle_match = 0;
2179                         ap->ack_match = 0;
2180
2181                         ap->state = ANEG_STATE_RESTART_INIT;
2182                 } else {
2183                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2184                 }
2185                 break;
2186
2187         case ANEG_STATE_RESTART_INIT:
2188                 ap->link_time = ap->cur_time;
2189                 ap->flags &= ~(MR_NP_LOADED);
2190                 ap->txconfig = 0;
2191                 tw32(MAC_TX_AUTO_NEG, 0);
2192                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2193                 tw32_f(MAC_MODE, tp->mac_mode);
2194                 udelay(40);
2195
2196                 ret = ANEG_TIMER_ENAB;
2197                 ap->state = ANEG_STATE_RESTART;
2198
2199                 /* fallthru */
2200         case ANEG_STATE_RESTART:
2201                 delta = ap->cur_time - ap->link_time;
2202                 if (delta > ANEG_STATE_SETTLE_TIME) {
2203                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2204                 } else {
2205                         ret = ANEG_TIMER_ENAB;
2206                 }
2207                 break;
2208
2209         case ANEG_STATE_DISABLE_LINK_OK:
2210                 ret = ANEG_DONE;
2211                 break;
2212
2213         case ANEG_STATE_ABILITY_DETECT_INIT:
2214                 ap->flags &= ~(MR_TOGGLE_TX);
2215                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2216                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2217                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2218                 tw32_f(MAC_MODE, tp->mac_mode);
2219                 udelay(40);
2220
2221                 ap->state = ANEG_STATE_ABILITY_DETECT;
2222                 break;
2223
2224         case ANEG_STATE_ABILITY_DETECT:
2225                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2226                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2227                 }
2228                 break;
2229
2230         case ANEG_STATE_ACK_DETECT_INIT:
2231                 ap->txconfig |= ANEG_CFG_ACK;
2232                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2233                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2234                 tw32_f(MAC_MODE, tp->mac_mode);
2235                 udelay(40);
2236
2237                 ap->state = ANEG_STATE_ACK_DETECT;
2238
2239                 /* fallthru */
2240         case ANEG_STATE_ACK_DETECT:
2241                 if (ap->ack_match != 0) {
2242                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2243                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2244                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2245                         } else {
2246                                 ap->state = ANEG_STATE_AN_ENABLE;
2247                         }
2248                 } else if (ap->ability_match != 0 &&
2249                            ap->rxconfig == 0) {
2250                         ap->state = ANEG_STATE_AN_ENABLE;
2251                 }
2252                 break;
2253
2254         case ANEG_STATE_COMPLETE_ACK_INIT:
2255                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2256                         ret = ANEG_FAILED;
2257                         break;
2258                 }
2259                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2260                                MR_LP_ADV_HALF_DUPLEX |
2261                                MR_LP_ADV_SYM_PAUSE |
2262                                MR_LP_ADV_ASYM_PAUSE |
2263                                MR_LP_ADV_REMOTE_FAULT1 |
2264                                MR_LP_ADV_REMOTE_FAULT2 |
2265                                MR_LP_ADV_NEXT_PAGE |
2266                                MR_TOGGLE_RX |
2267                                MR_NP_RX);
2268                 if (ap->rxconfig & ANEG_CFG_FD)
2269                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2270                 if (ap->rxconfig & ANEG_CFG_HD)
2271                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2272                 if (ap->rxconfig & ANEG_CFG_PS1)
2273                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2274                 if (ap->rxconfig & ANEG_CFG_PS2)
2275                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2276                 if (ap->rxconfig & ANEG_CFG_RF1)
2277                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2278                 if (ap->rxconfig & ANEG_CFG_RF2)
2279                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2280                 if (ap->rxconfig & ANEG_CFG_NP)
2281                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2282
2283                 ap->link_time = ap->cur_time;
2284
2285                 ap->flags ^= (MR_TOGGLE_TX);
2286                 if (ap->rxconfig & 0x0008)
2287                         ap->flags |= MR_TOGGLE_RX;
2288                 if (ap->rxconfig & ANEG_CFG_NP)
2289                         ap->flags |= MR_NP_RX;
2290                 ap->flags |= MR_PAGE_RX;
2291
2292                 ap->state = ANEG_STATE_COMPLETE_ACK;
2293                 ret = ANEG_TIMER_ENAB;
2294                 break;
2295
2296         case ANEG_STATE_COMPLETE_ACK:
2297                 if (ap->ability_match != 0 &&
2298                     ap->rxconfig == 0) {
2299                         ap->state = ANEG_STATE_AN_ENABLE;
2300                         break;
2301                 }
2302                 delta = ap->cur_time - ap->link_time;
2303                 if (delta > ANEG_STATE_SETTLE_TIME) {
2304                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2305                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2306                         } else {
2307                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2308                                     !(ap->flags & MR_NP_RX)) {
2309                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2310                                 } else {
2311                                         ret = ANEG_FAILED;
2312                                 }
2313                         }
2314                 }
2315                 break;
2316
2317         case ANEG_STATE_IDLE_DETECT_INIT:
2318                 ap->link_time = ap->cur_time;
2319                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2320                 tw32_f(MAC_MODE, tp->mac_mode);
2321                 udelay(40);
2322
2323                 ap->state = ANEG_STATE_IDLE_DETECT;
2324                 ret = ANEG_TIMER_ENAB;
2325                 break;
2326
2327         case ANEG_STATE_IDLE_DETECT:
2328                 if (ap->ability_match != 0 &&
2329                     ap->rxconfig == 0) {
2330                         ap->state = ANEG_STATE_AN_ENABLE;
2331                         break;
2332                 }
2333                 delta = ap->cur_time - ap->link_time;
2334                 if (delta > ANEG_STATE_SETTLE_TIME) {
2335                         /* XXX another gem from the Broadcom driver :( */
2336                         ap->state = ANEG_STATE_LINK_OK;
2337                 }
2338                 break;
2339
2340         case ANEG_STATE_LINK_OK:
2341                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2342                 ret = ANEG_DONE;
2343                 break;
2344
2345         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2346                 /* ??? unimplemented */
2347                 break;
2348
2349         case ANEG_STATE_NEXT_PAGE_WAIT:
2350                 /* ??? unimplemented */
2351                 break;
2352
2353         default:
2354                 ret = ANEG_FAILED;
2355                 break;
2356         };
2357
2358         return ret;
2359 }
2360
2361 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2362 {
2363         int res = 0;
2364         struct tg3_fiber_aneginfo aninfo;
2365         int status = ANEG_FAILED;
2366         unsigned int tick;
2367         u32 tmp;
2368
2369         tw32_f(MAC_TX_AUTO_NEG, 0);
2370
2371         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2372         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2373         udelay(40);
2374
2375         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2376         udelay(40);
2377
2378         memset(&aninfo, 0, sizeof(aninfo));
2379         aninfo.flags |= MR_AN_ENABLE;
2380         aninfo.state = ANEG_STATE_UNKNOWN;
2381         aninfo.cur_time = 0;
2382         tick = 0;
2383         while (++tick < 195000) {
2384                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2385                 if (status == ANEG_DONE || status == ANEG_FAILED)
2386                         break;
2387
2388                 udelay(1);
2389         }
2390
2391         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2392         tw32_f(MAC_MODE, tp->mac_mode);
2393         udelay(40);
2394
2395         *flags = aninfo.flags;
2396
2397         if (status == ANEG_DONE &&
2398             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2399                              MR_LP_ADV_FULL_DUPLEX)))
2400                 res = 1;
2401
2402         return res;
2403 }
2404
2405 static void tg3_init_bcm8002(struct tg3 *tp)
2406 {
2407         u32 mac_status = tr32(MAC_STATUS);
2408         int i;
2409
2410         /* Reset when initting first time or we have a link. */
2411         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2412             !(mac_status & MAC_STATUS_PCS_SYNCED))
2413                 return;
2414
2415         /* Set PLL lock range. */
2416         tg3_writephy(tp, 0x16, 0x8007);
2417
2418         /* SW reset */
2419         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2420
2421         /* Wait for reset to complete. */
2422         /* XXX schedule_timeout() ... */
2423         for (i = 0; i < 500; i++)
2424                 udelay(10);
2425
2426         /* Config mode; select PMA/Ch 1 regs. */
2427         tg3_writephy(tp, 0x10, 0x8411);
2428
2429         /* Enable auto-lock and comdet, select txclk for tx. */
2430         tg3_writephy(tp, 0x11, 0x0a10);
2431
2432         tg3_writephy(tp, 0x18, 0x00a0);
2433         tg3_writephy(tp, 0x16, 0x41ff);
2434
2435         /* Assert and deassert POR. */
2436         tg3_writephy(tp, 0x13, 0x0400);
2437         udelay(40);
2438         tg3_writephy(tp, 0x13, 0x0000);
2439
2440         tg3_writephy(tp, 0x11, 0x0a50);
2441         udelay(40);
2442         tg3_writephy(tp, 0x11, 0x0a10);
2443
2444         /* Wait for signal to stabilize */
2445         /* XXX schedule_timeout() ... */
2446         for (i = 0; i < 15000; i++)
2447                 udelay(10);
2448
2449         /* Deselect the channel register so we can read the PHYID
2450          * later.
2451          */
2452         tg3_writephy(tp, 0x10, 0x8011);
2453 }
2454
2455 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2456 {
2457         u32 sg_dig_ctrl, sg_dig_status;
2458         u32 serdes_cfg, expected_sg_dig_ctrl;
2459         int workaround, port_a;
2460         int current_link_up;
2461
2462         serdes_cfg = 0;
2463         expected_sg_dig_ctrl = 0;
2464         workaround = 0;
2465         port_a = 1;
2466         current_link_up = 0;
2467
2468         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2469             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2470                 workaround = 1;
2471                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2472                         port_a = 0;
2473
2474                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2475                 /* preserve bits 20-23 for voltage regulator */
2476                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2477         }
2478
2479         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2480
2481         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2482                 if (sg_dig_ctrl & (1 << 31)) {
2483                         if (workaround) {
2484                                 u32 val = serdes_cfg;
2485
2486                                 if (port_a)
2487                                         val |= 0xc010000;
2488                                 else
2489                                         val |= 0x4010000;
2490                                 tw32_f(MAC_SERDES_CFG, val);
2491                         }
2492                         tw32_f(SG_DIG_CTRL, 0x01388400);
2493                 }
2494                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2495                         tg3_setup_flow_control(tp, 0, 0);
2496                         current_link_up = 1;
2497                 }
2498                 goto out;
2499         }
2500
2501         /* Want auto-negotiation.  */
2502         expected_sg_dig_ctrl = 0x81388400;
2503
2504         /* Pause capability */
2505         expected_sg_dig_ctrl |= (1 << 11);
2506
2507         /* Asymettric pause */
2508         expected_sg_dig_ctrl |= (1 << 12);
2509
2510         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2511                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2512                     tp->serdes_counter &&
2513                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2514                                     MAC_STATUS_RCVD_CFG)) ==
2515                      MAC_STATUS_PCS_SYNCED)) {
2516                         tp->serdes_counter--;
2517                         current_link_up = 1;
2518                         goto out;
2519                 }
2520 restart_autoneg:
2521                 if (workaround)
2522                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2523                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2524                 udelay(5);
2525                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2526
2527                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2528                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2529         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2530                                  MAC_STATUS_SIGNAL_DET)) {
2531                 sg_dig_status = tr32(SG_DIG_STATUS);
2532                 mac_status = tr32(MAC_STATUS);
2533
2534                 if ((sg_dig_status & (1 << 1)) &&
2535                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2536                         u32 local_adv, remote_adv;
2537
2538                         local_adv = ADVERTISE_PAUSE_CAP;
2539                         remote_adv = 0;
2540                         if (sg_dig_status & (1 << 19))
2541                                 remote_adv |= LPA_PAUSE_CAP;
2542                         if (sg_dig_status & (1 << 20))
2543                                 remote_adv |= LPA_PAUSE_ASYM;
2544
2545                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2546                         current_link_up = 1;
2547                         tp->serdes_counter = 0;
2548                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2549                 } else if (!(sg_dig_status & (1 << 1))) {
2550                         if (tp->serdes_counter)
2551                                 tp->serdes_counter--;
2552                         else {
2553                                 if (workaround) {
2554                                         u32 val = serdes_cfg;
2555
2556                                         if (port_a)
2557                                                 val |= 0xc010000;
2558                                         else
2559                                                 val |= 0x4010000;
2560
2561                                         tw32_f(MAC_SERDES_CFG, val);
2562                                 }
2563
2564                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2565                                 udelay(40);
2566
2567                                 /* Link parallel detection - link is up */
2568                                 /* only if we have PCS_SYNC and not */
2569                                 /* receiving config code words */
2570                                 mac_status = tr32(MAC_STATUS);
2571                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2572                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2573                                         tg3_setup_flow_control(tp, 0, 0);
2574                                         current_link_up = 1;
2575                                         tp->tg3_flags2 |=
2576                                                 TG3_FLG2_PARALLEL_DETECT;
2577                                         tp->serdes_counter =
2578                                                 SERDES_PARALLEL_DET_TIMEOUT;
2579                                 } else
2580                                         goto restart_autoneg;
2581                         }
2582                 }
2583         } else {
2584                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2585                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2586         }
2587
2588 out:
2589         return current_link_up;
2590 }
2591
2592 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2593 {
2594         int current_link_up = 0;
2595
2596         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2597                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2598                 goto out;
2599         }
2600
2601         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2602                 u32 flags;
2603                 int i;
2604
2605                 if (fiber_autoneg(tp, &flags)) {
2606                         u32 local_adv, remote_adv;
2607
2608                         local_adv = ADVERTISE_PAUSE_CAP;
2609                         remote_adv = 0;
2610                         if (flags & MR_LP_ADV_SYM_PAUSE)
2611                                 remote_adv |= LPA_PAUSE_CAP;
2612                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2613                                 remote_adv |= LPA_PAUSE_ASYM;
2614
2615                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2616
2617                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2618                         current_link_up = 1;
2619                 }
2620                 for (i = 0; i < 30; i++) {
2621                         udelay(20);
2622                         tw32_f(MAC_STATUS,
2623                                (MAC_STATUS_SYNC_CHANGED |
2624                                 MAC_STATUS_CFG_CHANGED));
2625                         udelay(40);
2626                         if ((tr32(MAC_STATUS) &
2627                              (MAC_STATUS_SYNC_CHANGED |
2628                               MAC_STATUS_CFG_CHANGED)) == 0)
2629                                 break;
2630                 }
2631
2632                 mac_status = tr32(MAC_STATUS);
2633                 if (current_link_up == 0 &&
2634                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2635                     !(mac_status & MAC_STATUS_RCVD_CFG))
2636                         current_link_up = 1;
2637         } else {
2638                 /* Forcing 1000FD link up. */
2639                 current_link_up = 1;
2640                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2641
2642                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2643                 udelay(40);
2644         }
2645
2646 out:
2647         return current_link_up;
2648 }
2649
2650 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2651 {
2652         u32 orig_pause_cfg;
2653         u16 orig_active_speed;
2654         u8 orig_active_duplex;
2655         u32 mac_status;
2656         int current_link_up;
2657         int i;
2658
2659         orig_pause_cfg =
2660                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2661                                   TG3_FLAG_TX_PAUSE));
2662         orig_active_speed = tp->link_config.active_speed;
2663         orig_active_duplex = tp->link_config.active_duplex;
2664
2665         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2666             netif_carrier_ok(tp->dev) &&
2667             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2668                 mac_status = tr32(MAC_STATUS);
2669                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2670                                MAC_STATUS_SIGNAL_DET |
2671                                MAC_STATUS_CFG_CHANGED |
2672                                MAC_STATUS_RCVD_CFG);
2673                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2674                                    MAC_STATUS_SIGNAL_DET)) {
2675                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2676                                             MAC_STATUS_CFG_CHANGED));
2677                         return 0;
2678                 }
2679         }
2680
2681         tw32_f(MAC_TX_AUTO_NEG, 0);
2682
2683         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2684         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2685         tw32_f(MAC_MODE, tp->mac_mode);
2686         udelay(40);
2687
2688         if (tp->phy_id == PHY_ID_BCM8002)
2689                 tg3_init_bcm8002(tp);
2690
2691         /* Enable link change event even when serdes polling.  */
2692         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2693         udelay(40);
2694
2695         current_link_up = 0;
2696         mac_status = tr32(MAC_STATUS);
2697
2698         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2699                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2700         else
2701                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2702
2703         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2704         tw32_f(MAC_MODE, tp->mac_mode);
2705         udelay(40);
2706
2707         tp->hw_status->status =
2708                 (SD_STATUS_UPDATED |
2709                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2710
2711         for (i = 0; i < 100; i++) {
2712                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2713                                     MAC_STATUS_CFG_CHANGED));
2714                 udelay(5);
2715                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2716                                          MAC_STATUS_CFG_CHANGED |
2717                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2718                         break;
2719         }
2720
2721         mac_status = tr32(MAC_STATUS);
2722         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2723                 current_link_up = 0;
2724                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2725                     tp->serdes_counter == 0) {
2726                         tw32_f(MAC_MODE, (tp->mac_mode |
2727                                           MAC_MODE_SEND_CONFIGS));
2728                         udelay(1);
2729                         tw32_f(MAC_MODE, tp->mac_mode);
2730                 }
2731         }
2732
2733         if (current_link_up == 1) {
2734                 tp->link_config.active_speed = SPEED_1000;
2735                 tp->link_config.active_duplex = DUPLEX_FULL;
2736                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2737                                     LED_CTRL_LNKLED_OVERRIDE |
2738                                     LED_CTRL_1000MBPS_ON));
2739         } else {
2740                 tp->link_config.active_speed = SPEED_INVALID;
2741                 tp->link_config.active_duplex = DUPLEX_INVALID;
2742                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2743                                     LED_CTRL_LNKLED_OVERRIDE |
2744                                     LED_CTRL_TRAFFIC_OVERRIDE));
2745         }
2746
2747         if (current_link_up != netif_carrier_ok(tp->dev)) {
2748                 if (current_link_up)
2749                         netif_carrier_on(tp->dev);
2750                 else
2751                         netif_carrier_off(tp->dev);
2752                 tg3_link_report(tp);
2753         } else {
2754                 u32 now_pause_cfg =
2755                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2756                                          TG3_FLAG_TX_PAUSE);
2757                 if (orig_pause_cfg != now_pause_cfg ||
2758                     orig_active_speed != tp->link_config.active_speed ||
2759                     orig_active_duplex != tp->link_config.active_duplex)
2760                         tg3_link_report(tp);
2761         }
2762
2763         return 0;
2764 }
2765
2766 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2767 {
2768         int current_link_up, err = 0;
2769         u32 bmsr, bmcr;
2770         u16 current_speed;
2771         u8 current_duplex;
2772
2773         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2774         tw32_f(MAC_MODE, tp->mac_mode);
2775         udelay(40);
2776
2777         tw32(MAC_EVENT, 0);
2778
2779         tw32_f(MAC_STATUS,
2780              (MAC_STATUS_SYNC_CHANGED |
2781               MAC_STATUS_CFG_CHANGED |
2782               MAC_STATUS_MI_COMPLETION |
2783               MAC_STATUS_LNKSTATE_CHANGED));
2784         udelay(40);
2785
2786         if (force_reset)
2787                 tg3_phy_reset(tp);
2788
2789         current_link_up = 0;
2790         current_speed = SPEED_INVALID;
2791         current_duplex = DUPLEX_INVALID;
2792
2793         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2794         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2795         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2796                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2797                         bmsr |= BMSR_LSTATUS;
2798                 else
2799                         bmsr &= ~BMSR_LSTATUS;
2800         }
2801
2802         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2803
2804         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2805             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2806                 /* do nothing, just check for link up at the end */
2807         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2808                 u32 adv, new_adv;
2809
2810                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2811                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2812                                   ADVERTISE_1000XPAUSE |
2813                                   ADVERTISE_1000XPSE_ASYM |
2814                                   ADVERTISE_SLCT);
2815
2816                 /* Always advertise symmetric PAUSE just like copper */
2817                 new_adv |= ADVERTISE_1000XPAUSE;
2818
2819                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2820                         new_adv |= ADVERTISE_1000XHALF;
2821                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2822                         new_adv |= ADVERTISE_1000XFULL;
2823
2824                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2825                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2826                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2827                         tg3_writephy(tp, MII_BMCR, bmcr);
2828
2829                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2830                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2831                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2832
2833                         return err;
2834                 }
2835         } else {
2836                 u32 new_bmcr;
2837
2838                 bmcr &= ~BMCR_SPEED1000;
2839                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2840
2841                 if (tp->link_config.duplex == DUPLEX_FULL)
2842                         new_bmcr |= BMCR_FULLDPLX;
2843
2844                 if (new_bmcr != bmcr) {
2845                         /* BMCR_SPEED1000 is a reserved bit that needs
2846                          * to be set on write.
2847                          */
2848                         new_bmcr |= BMCR_SPEED1000;
2849
2850                         /* Force a linkdown */
2851                         if (netif_carrier_ok(tp->dev)) {
2852                                 u32 adv;
2853
2854                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2855                                 adv &= ~(ADVERTISE_1000XFULL |
2856                                          ADVERTISE_1000XHALF |
2857                                          ADVERTISE_SLCT);
2858                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2859                                 tg3_writephy(tp, MII_BMCR, bmcr |
2860                                                            BMCR_ANRESTART |
2861                                                            BMCR_ANENABLE);
2862                                 udelay(10);
2863                                 netif_carrier_off(tp->dev);
2864                         }
2865                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2866                         bmcr = new_bmcr;
2867                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2868                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2869                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2870                             ASIC_REV_5714) {
2871                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2872                                         bmsr |= BMSR_LSTATUS;
2873                                 else
2874                                         bmsr &= ~BMSR_LSTATUS;
2875                         }
2876                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2877                 }
2878         }
2879
2880         if (bmsr & BMSR_LSTATUS) {
2881                 current_speed = SPEED_1000;
2882                 current_link_up = 1;
2883                 if (bmcr & BMCR_FULLDPLX)
2884                         current_duplex = DUPLEX_FULL;
2885                 else
2886                         current_duplex = DUPLEX_HALF;
2887
2888                 if (bmcr & BMCR_ANENABLE) {
2889                         u32 local_adv, remote_adv, common;
2890
2891                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2892                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2893                         common = local_adv & remote_adv;
2894                         if (common & (ADVERTISE_1000XHALF |
2895                                       ADVERTISE_1000XFULL)) {
2896                                 if (common & ADVERTISE_1000XFULL)
2897                                         current_duplex = DUPLEX_FULL;
2898                                 else
2899                                         current_duplex = DUPLEX_HALF;
2900
2901                                 tg3_setup_flow_control(tp, local_adv,
2902                                                        remote_adv);
2903                         }
2904                         else
2905                                 current_link_up = 0;
2906                 }
2907         }
2908
2909         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2910         if (tp->link_config.active_duplex == DUPLEX_HALF)
2911                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2912
2913         tw32_f(MAC_MODE, tp->mac_mode);
2914         udelay(40);
2915
2916         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2917
2918         tp->link_config.active_speed = current_speed;
2919         tp->link_config.active_duplex = current_duplex;
2920
2921         if (current_link_up != netif_carrier_ok(tp->dev)) {
2922                 if (current_link_up)
2923                         netif_carrier_on(tp->dev);
2924                 else {
2925                         netif_carrier_off(tp->dev);
2926                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2927                 }
2928                 tg3_link_report(tp);
2929         }
2930         return err;
2931 }
2932
2933 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2934 {
2935         if (tp->serdes_counter) {
2936                 /* Give autoneg time to complete. */
2937                 tp->serdes_counter--;
2938                 return;
2939         }
2940         if (!netif_carrier_ok(tp->dev) &&
2941             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2942                 u32 bmcr;
2943
2944                 tg3_readphy(tp, MII_BMCR, &bmcr);
2945                 if (bmcr & BMCR_ANENABLE) {
2946                         u32 phy1, phy2;
2947
2948                         /* Select shadow register 0x1f */
2949                         tg3_writephy(tp, 0x1c, 0x7c00);
2950                         tg3_readphy(tp, 0x1c, &phy1);
2951
2952                         /* Select expansion interrupt status register */
2953                         tg3_writephy(tp, 0x17, 0x0f01);
2954                         tg3_readphy(tp, 0x15, &phy2);
2955                         tg3_readphy(tp, 0x15, &phy2);
2956
2957                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2958                                 /* We have signal detect and not receiving
2959                                  * config code words, link is up by parallel
2960                                  * detection.
2961                                  */
2962
2963                                 bmcr &= ~BMCR_ANENABLE;
2964                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2965                                 tg3_writephy(tp, MII_BMCR, bmcr);
2966                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2967                         }
2968                 }
2969         }
2970         else if (netif_carrier_ok(tp->dev) &&
2971                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2972                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2973                 u32 phy2;
2974
2975                 /* Select expansion interrupt status register */
2976                 tg3_writephy(tp, 0x17, 0x0f01);
2977                 tg3_readphy(tp, 0x15, &phy2);
2978                 if (phy2 & 0x20) {
2979                         u32 bmcr;
2980
2981                         /* Config code words received, turn on autoneg. */
2982                         tg3_readphy(tp, MII_BMCR, &bmcr);
2983                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2984
2985                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2986
2987                 }
2988         }
2989 }
2990
2991 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2992 {
2993         int err;
2994
2995         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2996                 err = tg3_setup_fiber_phy(tp, force_reset);
2997         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2998                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2999         } else {
3000                 err = tg3_setup_copper_phy(tp, force_reset);
3001         }
3002
3003         if (tp->link_config.active_speed == SPEED_1000 &&
3004             tp->link_config.active_duplex == DUPLEX_HALF)
3005                 tw32(MAC_TX_LENGTHS,
3006                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3007                       (6 << TX_LENGTHS_IPG_SHIFT) |
3008                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3009         else
3010                 tw32(MAC_TX_LENGTHS,
3011                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3012                       (6 << TX_LENGTHS_IPG_SHIFT) |
3013                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3014
3015         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3016                 if (netif_carrier_ok(tp->dev)) {
3017                         tw32(HOSTCC_STAT_COAL_TICKS,
3018                              tp->coal.stats_block_coalesce_usecs);
3019                 } else {
3020                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3021                 }
3022         }
3023
3024         return err;
3025 }
3026
3027 /* This is called whenever we suspect that the system chipset is re-
3028  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3029  * is bogus tx completions. We try to recover by setting the
3030  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3031  * in the workqueue.
3032  */
3033 static void tg3_tx_recover(struct tg3 *tp)
3034 {
3035         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3036                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3037
3038         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3039                "mapped I/O cycles to the network device, attempting to "
3040                "recover. Please report the problem to the driver maintainer "
3041                "and include system chipset information.\n", tp->dev->name);
3042
3043         spin_lock(&tp->lock);
3044         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3045         spin_unlock(&tp->lock);
3046 }
3047
3048 static inline u32 tg3_tx_avail(struct tg3 *tp)
3049 {
3050         smp_mb();
3051         return (tp->tx_pending -
3052                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3053 }
3054
3055 /* Tigon3 never reports partial packet sends.  So we do not
3056  * need special logic to handle SKBs that have not had all
3057  * of their frags sent yet, like SunGEM does.
3058  */
3059 static void tg3_tx(struct tg3 *tp)
3060 {
3061         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3062         u32 sw_idx = tp->tx_cons;
3063
3064         while (sw_idx != hw_idx) {
3065                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3066                 struct sk_buff *skb = ri->skb;
3067                 int i, tx_bug = 0;
3068
3069                 if (unlikely(skb == NULL)) {
3070                         tg3_tx_recover(tp);
3071                         return;
3072                 }
3073
3074                 pci_unmap_single(tp->pdev,
3075                                  pci_unmap_addr(ri, mapping),
3076                                  skb_headlen(skb),
3077                                  PCI_DMA_TODEVICE);
3078
3079                 ri->skb = NULL;
3080
3081                 sw_idx = NEXT_TX(sw_idx);
3082
3083                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3084                         ri = &tp->tx_buffers[sw_idx];
3085                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3086                                 tx_bug = 1;
3087
3088                         pci_unmap_page(tp->pdev,
3089                                        pci_unmap_addr(ri, mapping),
3090                                        skb_shinfo(skb)->frags[i].size,
3091                                        PCI_DMA_TODEVICE);
3092
3093                         sw_idx = NEXT_TX(sw_idx);
3094                 }
3095
3096                 dev_kfree_skb(skb);
3097
3098                 if (unlikely(tx_bug)) {
3099                         tg3_tx_recover(tp);
3100                         return;
3101                 }
3102         }
3103
3104         tp->tx_cons = sw_idx;
3105
3106         /* Need to make the tx_cons update visible to tg3_start_xmit()
3107          * before checking for netif_queue_stopped().  Without the
3108          * memory barrier, there is a small possibility that tg3_start_xmit()
3109          * will miss it and cause the queue to be stopped forever.
3110          */
3111         smp_mb();
3112
3113         if (unlikely(netif_queue_stopped(tp->dev) &&
3114                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3115                 netif_tx_lock(tp->dev);
3116                 if (netif_queue_stopped(tp->dev) &&
3117                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3118                         netif_wake_queue(tp->dev);
3119                 netif_tx_unlock(tp->dev);
3120         }
3121 }
3122
3123 /* Returns size of skb allocated or < 0 on error.
3124  *
3125  * We only need to fill in the address because the other members
3126  * of the RX descriptor are invariant, see tg3_init_rings.
3127  *
3128  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3129  * posting buffers we only dirty the first cache line of the RX
3130  * descriptor (containing the address).  Whereas for the RX status
3131  * buffers the cpu only reads the last cacheline of the RX descriptor
3132  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3133  */
3134 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3135                             int src_idx, u32 dest_idx_unmasked)
3136 {
3137         struct tg3_rx_buffer_desc *desc;
3138         struct ring_info *map, *src_map;
3139         struct sk_buff *skb;
3140         dma_addr_t mapping;
3141         int skb_size, dest_idx;
3142
3143         src_map = NULL;
3144         switch (opaque_key) {
3145         case RXD_OPAQUE_RING_STD:
3146                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3147                 desc = &tp->rx_std[dest_idx];
3148                 map = &tp->rx_std_buffers[dest_idx];
3149                 if (src_idx >= 0)
3150                         src_map = &tp->rx_std_buffers[src_idx];
3151                 skb_size = tp->rx_pkt_buf_sz;
3152                 break;
3153
3154         case RXD_OPAQUE_RING_JUMBO:
3155                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3156                 desc = &tp->rx_jumbo[dest_idx];
3157                 map = &tp->rx_jumbo_buffers[dest_idx];
3158                 if (src_idx >= 0)
3159                         src_map = &tp->rx_jumbo_buffers[src_idx];
3160                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3161                 break;
3162
3163         default:
3164                 return -EINVAL;
3165         };
3166
3167         /* Do not overwrite any of the map or rp information
3168          * until we are sure we can commit to a new buffer.
3169          *
3170          * Callers depend upon this behavior and assume that
3171          * we leave everything unchanged if we fail.
3172          */
3173         skb = netdev_alloc_skb(tp->dev, skb_size);
3174         if (skb == NULL)
3175                 return -ENOMEM;
3176
3177         skb_reserve(skb, tp->rx_offset);
3178
3179         mapping = pci_map_single(tp->pdev, skb->data,
3180                                  skb_size - tp->rx_offset,
3181                                  PCI_DMA_FROMDEVICE);
3182
3183         map->skb = skb;
3184         pci_unmap_addr_set(map, mapping, mapping);
3185
3186         if (src_map != NULL)
3187                 src_map->skb = NULL;
3188
3189         desc->addr_hi = ((u64)mapping >> 32);
3190         desc->addr_lo = ((u64)mapping & 0xffffffff);
3191
3192         return skb_size;
3193 }
3194
3195 /* We only need to move over in the address because the other
3196  * members of the RX descriptor are invariant.  See notes above
3197  * tg3_alloc_rx_skb for full details.
3198  */
3199 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3200                            int src_idx, u32 dest_idx_unmasked)
3201 {
3202         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3203         struct ring_info *src_map, *dest_map;
3204         int dest_idx;
3205
3206         switch (opaque_key) {
3207         case RXD_OPAQUE_RING_STD:
3208                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3209                 dest_desc = &tp->rx_std[dest_idx];
3210                 dest_map = &tp->rx_std_buffers[dest_idx];
3211                 src_desc = &tp->rx_std[src_idx];
3212                 src_map = &tp->rx_std_buffers[src_idx];
3213                 break;
3214
3215         case RXD_OPAQUE_RING_JUMBO:
3216                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3217                 dest_desc = &tp->rx_jumbo[dest_idx];
3218                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3219                 src_desc = &tp->rx_jumbo[src_idx];
3220                 src_map = &tp->rx_jumbo_buffers[src_idx];
3221                 break;
3222
3223         default:
3224                 return;
3225         };
3226
3227         dest_map->skb = src_map->skb;
3228         pci_unmap_addr_set(dest_map, mapping,
3229                            pci_unmap_addr(src_map, mapping));
3230         dest_desc->addr_hi = src_desc->addr_hi;
3231         dest_desc->addr_lo = src_desc->addr_lo;
3232
3233         src_map->skb = NULL;
3234 }
3235
3236 #if TG3_VLAN_TAG_USED
3237 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3238 {
3239         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3240 }
3241 #endif
3242
3243 /* The RX ring scheme is composed of multiple rings which post fresh
3244  * buffers to the chip, and one special ring the chip uses to report
3245  * status back to the host.
3246  *
3247  * The special ring reports the status of received packets to the
3248  * host.  The chip does not write into the original descriptor the
3249  * RX buffer was obtained from.  The chip simply takes the original
3250  * descriptor as provided by the host, updates the status and length
3251  * field, then writes this into the next status ring entry.
3252  *
3253  * Each ring the host uses to post buffers to the chip is described
3254  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3255  * it is first placed into the on-chip ram.  When the packet's length
3256  * is known, it walks down the TG3_BDINFO entries to select the ring.
3257  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3258  * which is within the range of the new packet's length is chosen.
3259  *
3260  * The "separate ring for rx status" scheme may sound queer, but it makes
3261  * sense from a cache coherency perspective.  If only the host writes
3262  * to the buffer post rings, and only the chip writes to the rx status
3263  * rings, then cache lines never move beyond shared-modified state.
3264  * If both the host and chip were to write into the same ring, cache line
3265  * eviction could occur since both entities want it in an exclusive state.
3266  */
3267 static int tg3_rx(struct tg3 *tp, int budget)
3268 {
3269         u32 work_mask, rx_std_posted = 0;
3270         u32 sw_idx = tp->rx_rcb_ptr;
3271         u16 hw_idx;
3272         int received;
3273
3274         hw_idx = tp->hw_status->idx[0].rx_producer;
3275         /*
3276          * We need to order the read of hw_idx and the read of
3277          * the opaque cookie.
3278          */
3279         rmb();
3280         work_mask = 0;
3281         received = 0;
3282         while (sw_idx != hw_idx && budget > 0) {
3283                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3284                 unsigned int len;
3285                 struct sk_buff *skb;
3286                 dma_addr_t dma_addr;
3287                 u32 opaque_key, desc_idx, *post_ptr;
3288
3289                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3290                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3291                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3292                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3293                                                   mapping);
3294                         skb = tp->rx_std_buffers[desc_idx].skb;
3295                         post_ptr = &tp->rx_std_ptr;
3296                         rx_std_posted++;
3297                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3298                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3299                                                   mapping);
3300                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3301                         post_ptr = &tp->rx_jumbo_ptr;
3302                 }
3303                 else {
3304                         goto next_pkt_nopost;
3305                 }
3306
3307                 work_mask |= opaque_key;
3308
3309                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3310                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3311                 drop_it:
3312                         tg3_recycle_rx(tp, opaque_key,
3313                                        desc_idx, *post_ptr);
3314                 drop_it_no_recycle:
3315                         /* Other statistics kept track of by card. */
3316                         tp->net_stats.rx_dropped++;
3317                         goto next_pkt;
3318                 }
3319
3320                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3321
3322                 if (len > RX_COPY_THRESHOLD
3323                         && tp->rx_offset == 2
3324                         /* rx_offset != 2 iff this is a 5701 card running
3325                          * in PCI-X mode [see tg3_get_invariants()] */
3326                 ) {
3327                         int skb_size;
3328
3329                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3330                                                     desc_idx, *post_ptr);
3331                         if (skb_size < 0)
3332                                 goto drop_it;
3333
3334                         pci_unmap_single(tp->pdev, dma_addr,
3335                                          skb_size - tp->rx_offset,
3336                                          PCI_DMA_FROMDEVICE);
3337
3338                         skb_put(skb, len);
3339                 } else {
3340                         struct sk_buff *copy_skb;
3341
3342                         tg3_recycle_rx(tp, opaque_key,
3343                                        desc_idx, *post_ptr);
3344
3345                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3346                         if (copy_skb == NULL)
3347                                 goto drop_it_no_recycle;
3348
3349                         skb_reserve(copy_skb, 2);
3350                         skb_put(copy_skb, len);
3351                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3352                         memcpy(copy_skb->data, skb->data, len);
3353                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3354
3355                         /* We'll reuse the original ring buffer. */
3356                         skb = copy_skb;
3357                 }
3358
3359                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3360                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3361                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3362                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3363                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3364                 else
3365                         skb->ip_summed = CHECKSUM_NONE;
3366
3367                 skb->protocol = eth_type_trans(skb, tp->dev);
3368 #if TG3_VLAN_TAG_USED
3369                 if (tp->vlgrp != NULL &&
3370                     desc->type_flags & RXD_FLAG_VLAN) {
3371                         tg3_vlan_rx(tp, skb,
3372                                     desc->err_vlan & RXD_VLAN_MASK);
3373                 } else
3374 #endif
3375                         netif_receive_skb(skb);
3376
3377                 tp->dev->last_rx = jiffies;
3378                 received++;
3379                 budget--;
3380
3381 next_pkt:
3382                 (*post_ptr)++;
3383
3384                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3385                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3386
3387                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3388                                      TG3_64BIT_REG_LOW, idx);
3389                         work_mask &= ~RXD_OPAQUE_RING_STD;
3390                         rx_std_posted = 0;
3391                 }
3392 next_pkt_nopost:
3393                 sw_idx++;
3394                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3395
3396                 /* Refresh hw_idx to see if there is new work */
3397                 if (sw_idx == hw_idx) {
3398                         hw_idx = tp->hw_status->idx[0].rx_producer;
3399                         rmb();
3400                 }
3401         }
3402
3403         /* ACK the status ring. */
3404         tp->rx_rcb_ptr = sw_idx;
3405         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3406
3407         /* Refill RX ring(s). */
3408         if (work_mask & RXD_OPAQUE_RING_STD) {
3409                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3410                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3411                              sw_idx);
3412         }
3413         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3414                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3415                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3416                              sw_idx);
3417         }
3418         mmiowb();
3419
3420         return received;
3421 }
3422
3423 static int tg3_poll(struct net_device *netdev, int *budget)
3424 {
3425         struct tg3 *tp = netdev_priv(netdev);
3426         struct tg3_hw_status *sblk = tp->hw_status;
3427         int done;
3428
3429         /* handle link change and other phy events */
3430         if (!(tp->tg3_flags &
3431               (TG3_FLAG_USE_LINKCHG_REG |
3432                TG3_FLAG_POLL_SERDES))) {
3433                 if (sblk->status & SD_STATUS_LINK_CHG) {
3434                         sblk->status = SD_STATUS_UPDATED |
3435                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3436                         spin_lock(&tp->lock);
3437                         tg3_setup_phy(tp, 0);
3438                         spin_unlock(&tp->lock);
3439                 }
3440         }
3441
3442         /* run TX completion thread */
3443         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3444                 tg3_tx(tp);
3445                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3446                         netif_rx_complete(netdev);
3447                         schedule_work(&tp->reset_task);
3448                         return 0;
3449                 }
3450         }
3451
3452         /* run RX thread, within the bounds set by NAPI.
3453          * All RX "locking" is done by ensuring outside
3454          * code synchronizes with dev->poll()
3455          */
3456         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3457                 int orig_budget = *budget;
3458                 int work_done;
3459
3460                 if (orig_budget > netdev->quota)
3461                         orig_budget = netdev->quota;
3462
3463                 work_done = tg3_rx(tp, orig_budget);
3464
3465                 *budget -= work_done;
3466                 netdev->quota -= work_done;
3467         }
3468
3469         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3470                 tp->last_tag = sblk->status_tag;
3471                 rmb();
3472         } else
3473                 sblk->status &= ~SD_STATUS_UPDATED;
3474
3475         /* if no more work, tell net stack and NIC we're done */
3476         done = !tg3_has_work(tp);
3477         if (done) {
3478                 netif_rx_complete(netdev);
3479                 tg3_restart_ints(tp);
3480         }
3481
3482         return (done ? 0 : 1);
3483 }
3484
3485 static void tg3_irq_quiesce(struct tg3 *tp)
3486 {
3487         BUG_ON(tp->irq_sync);
3488
3489         tp->irq_sync = 1;
3490         smp_mb();
3491
3492         synchronize_irq(tp->pdev->irq);
3493 }
3494
3495 static inline int tg3_irq_sync(struct tg3 *tp)
3496 {
3497         return tp->irq_sync;
3498 }
3499
3500 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3501  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3502  * with as well.  Most of the time, this is not necessary except when
3503  * shutting down the device.
3504  */
3505 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3506 {
3507         if (irq_sync)
3508                 tg3_irq_quiesce(tp);
3509         spin_lock_bh(&tp->lock);
3510 }
3511
3512 static inline void tg3_full_unlock(struct tg3 *tp)
3513 {
3514         spin_unlock_bh(&tp->lock);
3515 }
3516
3517 /* One-shot MSI handler - Chip automatically disables interrupt
3518  * after sending MSI so driver doesn't have to do it.
3519  */
3520 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3521 {
3522         struct net_device *dev = dev_id;
3523         struct tg3 *tp = netdev_priv(dev);
3524
3525         prefetch(tp->hw_status);
3526         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3527
3528         if (likely(!tg3_irq_sync(tp)))
3529                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3530
3531         return IRQ_HANDLED;
3532 }
3533
3534 /* MSI ISR - No need to check for interrupt sharing and no need to
3535  * flush status block and interrupt mailbox. PCI ordering rules
3536  * guarantee that MSI will arrive after the status block.
3537  */
3538 static irqreturn_t tg3_msi(int irq, void *dev_id)
3539 {
3540         struct net_device *dev = dev_id;
3541         struct tg3 *tp = netdev_priv(dev);
3542
3543         prefetch(tp->hw_status);
3544         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3545         /*
3546          * Writing any value to intr-mbox-0 clears PCI INTA# and
3547          * chip-internal interrupt pending events.
3548          * Writing non-zero to intr-mbox-0 additional tells the
3549          * NIC to stop sending us irqs, engaging "in-intr-handler"
3550          * event coalescing.
3551          */
3552         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3553         if (likely(!tg3_irq_sync(tp)))
3554                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3555
3556         return IRQ_RETVAL(1);
3557 }
3558
3559 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3560 {
3561         struct net_device *dev = dev_id;
3562         struct tg3 *tp = netdev_priv(dev);
3563         struct tg3_hw_status *sblk = tp->hw_status;
3564         unsigned int handled = 1;
3565
3566         /* In INTx mode, it is possible for the interrupt to arrive at
3567          * the CPU before the status block posted prior to the interrupt.
3568          * Reading the PCI State register will confirm whether the
3569          * interrupt is ours and will flush the status block.
3570          */
3571         if ((sblk->status & SD_STATUS_UPDATED) ||
3572             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3573                 /*
3574                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3575                  * chip-internal interrupt pending events.
3576                  * Writing non-zero to intr-mbox-0 additional tells the
3577                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3578                  * event coalescing.
3579                  */
3580                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3581                              0x00000001);
3582                 if (tg3_irq_sync(tp))
3583                         goto out;
3584                 sblk->status &= ~SD_STATUS_UPDATED;
3585                 if (likely(tg3_has_work(tp))) {
3586                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3587                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3588                 } else {
3589                         /* No work, shared interrupt perhaps?  re-enable
3590                          * interrupts, and flush that PCI write
3591                          */
3592                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3593                                 0x00000000);
3594                 }
3595         } else {        /* shared interrupt */
3596                 handled = 0;
3597         }
3598 out:
3599         return IRQ_RETVAL(handled);
3600 }
3601
3602 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3603 {
3604         struct net_device *dev = dev_id;
3605         struct tg3 *tp = netdev_priv(dev);
3606         struct tg3_hw_status *sblk = tp->hw_status;
3607         unsigned int handled = 1;
3608
3609         /* In INTx mode, it is possible for the interrupt to arrive at
3610          * the CPU before the status block posted prior to the interrupt.
3611          * Reading the PCI State register will confirm whether the
3612          * interrupt is ours and will flush the status block.
3613          */
3614         if ((sblk->status_tag != tp->last_tag) ||
3615             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3616                 /*
3617                  * writing any value to intr-mbox-0 clears PCI INTA# and
3618                  * chip-internal interrupt pending events.
3619                  * writing non-zero to intr-mbox-0 additional tells the
3620                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3621                  * event coalescing.
3622                  */
3623                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3624                              0x00000001);
3625                 if (tg3_irq_sync(tp))
3626                         goto out;
3627                 if (netif_rx_schedule_prep(dev)) {
3628                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3629                         /* Update last_tag to mark that this status has been
3630                          * seen. Because interrupt may be shared, we may be
3631                          * racing with tg3_poll(), so only update last_tag
3632                          * if tg3_poll() is not scheduled.
3633                          */
3634                         tp->last_tag = sblk->status_tag;
3635                         __netif_rx_schedule(dev);
3636                 }
3637         } else {        /* shared interrupt */
3638                 handled = 0;
3639         }
3640 out:
3641         return IRQ_RETVAL(handled);
3642 }
3643
3644 /* ISR for interrupt test */
3645 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3646 {
3647         struct net_device *dev = dev_id;
3648         struct tg3 *tp = netdev_priv(dev);
3649         struct tg3_hw_status *sblk = tp->hw_status;
3650
3651         if ((sblk->status & SD_STATUS_UPDATED) ||
3652             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3653                 tg3_disable_ints(tp);
3654                 return IRQ_RETVAL(1);
3655         }
3656         return IRQ_RETVAL(0);
3657 }
3658
3659 static int tg3_init_hw(struct tg3 *, int);
3660 static int tg3_halt(struct tg3 *, int, int);
3661
3662 /* Restart hardware after configuration changes, self-test, etc.
3663  * Invoked with tp->lock held.
3664  */
3665 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3666 {
3667         int err;
3668
3669         err = tg3_init_hw(tp, reset_phy);
3670         if (err) {
3671                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3672                        "aborting.\n", tp->dev->name);
3673                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3674                 tg3_full_unlock(tp);
3675                 del_timer_sync(&tp->timer);
3676                 tp->irq_sync = 0;
3677                 netif_poll_enable(tp->dev);
3678                 dev_close(tp->dev);
3679                 tg3_full_lock(tp, 0);
3680         }
3681         return err;
3682 }
3683
3684 #ifdef CONFIG_NET_POLL_CONTROLLER
3685 static void tg3_poll_controller(struct net_device *dev)
3686 {
3687         struct tg3 *tp = netdev_priv(dev);
3688
3689         tg3_interrupt(tp->pdev->irq, dev);
3690 }
3691 #endif
3692
3693 static void tg3_reset_task(struct work_struct *work)
3694 {
3695         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3696         unsigned int restart_timer;
3697
3698         tg3_full_lock(tp, 0);
3699         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3700
3701         if (!netif_running(tp->dev)) {
3702                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3703                 tg3_full_unlock(tp);
3704                 return;
3705         }
3706
3707         tg3_full_unlock(tp);
3708
3709         tg3_netif_stop(tp);
3710
3711         tg3_full_lock(tp, 1);
3712
3713         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3714         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3715
3716         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3717                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3718                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3719                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3720                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3721         }
3722
3723         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3724         if (tg3_init_hw(tp, 1))
3725                 goto out;
3726
3727         tg3_netif_start(tp);
3728
3729         if (restart_timer)
3730                 mod_timer(&tp->timer, jiffies + 1);
3731
3732 out:
3733         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3734
3735         tg3_full_unlock(tp);
3736 }
3737
3738 static void tg3_dump_short_state(struct tg3 *tp)
3739 {
3740         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3741                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3742         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3743                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3744 }
3745
3746 static void tg3_tx_timeout(struct net_device *dev)
3747 {
3748         struct tg3 *tp = netdev_priv(dev);
3749
3750         if (netif_msg_tx_err(tp)) {
3751                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3752                        dev->name);
3753                 tg3_dump_short_state(tp);
3754         }
3755
3756         schedule_work(&tp->reset_task);
3757 }
3758
3759 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3760 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3761 {
3762         u32 base = (u32) mapping & 0xffffffff;
3763
3764         return ((base > 0xffffdcc0) &&
3765                 (base + len + 8 < base));
3766 }
3767
3768 /* Test for DMA addresses > 40-bit */
3769 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3770                                           int len)
3771 {
3772 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3773         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3774                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3775         return 0;
3776 #else
3777         return 0;
3778 #endif
3779 }
3780
3781 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3782
3783 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3784 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3785                                        u32 last_plus_one, u32 *start,
3786                                        u32 base_flags, u32 mss)
3787 {
3788         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3789         dma_addr_t new_addr = 0;
3790         u32 entry = *start;
3791         int i, ret = 0;
3792
3793         if (!new_skb) {
3794                 ret = -1;
3795         } else {
3796                 /* New SKB is guaranteed to be linear. */
3797                 entry = *start;
3798                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3799                                           PCI_DMA_TODEVICE);
3800                 /* Make sure new skb does not cross any 4G boundaries.
3801                  * Drop the packet if it does.
3802                  */
3803                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3804                         ret = -1;
3805                         dev_kfree_skb(new_skb);
3806                         new_skb = NULL;
3807                 } else {
3808                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3809                                     base_flags, 1 | (mss << 1));
3810                         *start = NEXT_TX(entry);
3811                 }
3812         }
3813
3814         /* Now clean up the sw ring entries. */
3815         i = 0;
3816         while (entry != last_plus_one) {
3817                 int len;
3818
3819                 if (i == 0)
3820                         len = skb_headlen(skb);
3821                 else
3822                         len = skb_shinfo(skb)->frags[i-1].size;
3823                 pci_unmap_single(tp->pdev,
3824                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3825                                  len, PCI_DMA_TODEVICE);
3826                 if (i == 0) {
3827                         tp->tx_buffers[entry].skb = new_skb;
3828                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3829                 } else {
3830                         tp->tx_buffers[entry].skb = NULL;
3831                 }
3832                 entry = NEXT_TX(entry);
3833                 i++;
3834         }
3835
3836         dev_kfree_skb(skb);
3837
3838         return ret;
3839 }
3840
3841 static void tg3_set_txd(struct tg3 *tp, int entry,
3842                         dma_addr_t mapping, int len, u32 flags,
3843                         u32 mss_and_is_end)
3844 {
3845         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3846         int is_end = (mss_and_is_end & 0x1);
3847         u32 mss = (mss_and_is_end >> 1);
3848         u32 vlan_tag = 0;
3849
3850         if (is_end)
3851                 flags |= TXD_FLAG_END;
3852         if (flags & TXD_FLAG_VLAN) {
3853                 vlan_tag = flags >> 16;
3854                 flags &= 0xffff;
3855         }
3856         vlan_tag |= (mss << TXD_MSS_SHIFT);
3857
3858         txd->addr_hi = ((u64) mapping >> 32);
3859         txd->addr_lo = ((u64) mapping & 0xffffffff);
3860         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3861         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3862 }
3863
3864 /* hard_start_xmit for devices that don't have any bugs and
3865  * support TG3_FLG2_HW_TSO_2 only.
3866  */
3867 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3868 {
3869         struct tg3 *tp = netdev_priv(dev);
3870         dma_addr_t mapping;
3871         u32 len, entry, base_flags, mss;
3872
3873         len = skb_headlen(skb);
3874
3875         /* We are running in BH disabled context with netif_tx_lock
3876          * and TX reclaim runs via tp->poll inside of a software
3877          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3878          * no IRQ context deadlocks to worry about either.  Rejoice!
3879          */
3880         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3881                 if (!netif_queue_stopped(dev)) {
3882                         netif_stop_queue(dev);
3883
3884                         /* This is a hard error, log it. */
3885                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3886                                "queue awake!\n", dev->name);
3887                 }
3888                 return NETDEV_TX_BUSY;
3889         }
3890
3891         entry = tp->tx_prod;
3892         base_flags = 0;
3893         mss = 0;
3894         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3895             (mss = skb_shinfo(skb)->gso_size) != 0) {
3896                 int tcp_opt_len, ip_tcp_len;
3897
3898                 if (skb_header_cloned(skb) &&
3899                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3900                         dev_kfree_skb(skb);
3901                         goto out_unlock;
3902                 }
3903
3904                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3905                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3906                 else {
3907                         tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3908                         ip_tcp_len = (skb->nh.iph->ihl * 4) +
3909                                      sizeof(struct tcphdr);
3910
3911                         skb->nh.iph->check = 0;
3912                         skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3913                                                      tcp_opt_len);
3914                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3915                 }
3916
3917                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3918                                TXD_FLAG_CPU_POST_DMA);
3919
3920                 skb->h.th->check = 0;
3921
3922         }
3923         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3924                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3925 #if TG3_VLAN_TAG_USED
3926         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3927                 base_flags |= (TXD_FLAG_VLAN |
3928                                (vlan_tx_tag_get(skb) << 16));
3929 #endif
3930
3931         /* Queue skb data, a.k.a. the main skb fragment. */
3932         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3933
3934         tp->tx_buffers[entry].skb = skb;
3935         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3936
3937         tg3_set_txd(tp, entry, mapping, len, base_flags,
3938                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3939
3940         entry = NEXT_TX(entry);
3941
3942         /* Now loop through additional data fragments, and queue them. */
3943         if (skb_shinfo(skb)->nr_frags > 0) {
3944                 unsigned int i, last;
3945
3946                 last = skb_shinfo(skb)->nr_frags - 1;
3947                 for (i = 0; i <= last; i++) {
3948                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3949
3950                         len = frag->size;
3951                         mapping = pci_map_page(tp->pdev,
3952                                                frag->page,
3953                                                frag->page_offset,
3954                                                len, PCI_DMA_TODEVICE);
3955
3956                         tp->tx_buffers[entry].skb = NULL;
3957                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3958
3959                         tg3_set_txd(tp, entry, mapping, len,
3960                                     base_flags, (i == last) | (mss << 1));
3961
3962                         entry = NEXT_TX(entry);
3963                 }
3964         }
3965
3966         /* Packets are ready, update Tx producer idx local and on card. */
3967         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3968
3969         tp->tx_prod = entry;
3970         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3971                 netif_stop_queue(dev);
3972                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3973                         netif_wake_queue(tp->dev);
3974         }
3975
3976 out_unlock:
3977         mmiowb();
3978
3979         dev->trans_start = jiffies;
3980
3981         return NETDEV_TX_OK;
3982 }
3983
3984 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3985
3986 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3987  * TSO header is greater than 80 bytes.
3988  */
3989 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3990 {
3991         struct sk_buff *segs, *nskb;
3992
3993         /* Estimate the number of fragments in the worst case */
3994         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3995                 netif_stop_queue(tp->dev);
3996                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
3997                         return NETDEV_TX_BUSY;
3998
3999                 netif_wake_queue(tp->dev);
4000         }
4001
4002         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4003         if (unlikely(IS_ERR(segs)))
4004                 goto tg3_tso_bug_end;
4005
4006         do {
4007                 nskb = segs;
4008                 segs = segs->next;
4009                 nskb->next = NULL;
4010                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4011         } while (segs);
4012
4013 tg3_tso_bug_end:
4014         dev_kfree_skb(skb);
4015
4016         return NETDEV_TX_OK;
4017 }
4018
4019 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4020  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4021  */
4022 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4023 {
4024         struct tg3 *tp = netdev_priv(dev);
4025         dma_addr_t mapping;
4026         u32 len, entry, base_flags, mss;
4027         int would_hit_hwbug;
4028
4029         len = skb_headlen(skb);
4030
4031         /* We are running in BH disabled context with netif_tx_lock
4032          * and TX reclaim runs via tp->poll inside of a software
4033          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4034          * no IRQ context deadlocks to worry about either.  Rejoice!
4035          */
4036         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4037                 if (!netif_queue_stopped(dev)) {
4038                         netif_stop_queue(dev);
4039
4040                         /* This is a hard error, log it. */
4041                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4042                                "queue awake!\n", dev->name);
4043                 }
4044                 return NETDEV_TX_BUSY;
4045         }
4046
4047         entry = tp->tx_prod;
4048         base_flags = 0;
4049         if (skb->ip_summed == CHECKSUM_PARTIAL)
4050                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4051         mss = 0;
4052         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4053             (mss = skb_shinfo(skb)->gso_size) != 0) {
4054                 int tcp_opt_len, ip_tcp_len, hdr_len;
4055
4056                 if (skb_header_cloned(skb) &&
4057                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4058                         dev_kfree_skb(skb);
4059                         goto out_unlock;
4060                 }
4061
4062                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4063                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4064
4065                 hdr_len = ip_tcp_len + tcp_opt_len;
4066                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4067                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4068                         return (tg3_tso_bug(tp, skb));
4069
4070                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4071                                TXD_FLAG_CPU_POST_DMA);
4072
4073                 skb->nh.iph->check = 0;
4074                 skb->nh.iph->tot_len = htons(mss + hdr_len);
4075                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4076                         skb->h.th->check = 0;
4077                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4078                 }
4079                 else {
4080                         skb->h.th->check =
4081                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4082                                                    skb->nh.iph->daddr,
4083                                                    0, IPPROTO_TCP, 0);
4084                 }
4085
4086                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4087                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4088                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4089                                 int tsflags;
4090
4091                                 tsflags = ((skb->nh.iph->ihl - 5) +
4092                                            (tcp_opt_len >> 2));
4093                                 mss |= (tsflags << 11);
4094                         }
4095                 } else {
4096                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4097                                 int tsflags;
4098
4099                                 tsflags = ((skb->nh.iph->ihl - 5) +
4100                                            (tcp_opt_len >> 2));
4101                                 base_flags |= tsflags << 12;
4102                         }
4103                 }
4104         }
4105 #if TG3_VLAN_TAG_USED
4106         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4107                 base_flags |= (TXD_FLAG_VLAN |
4108                                (vlan_tx_tag_get(skb) << 16));
4109 #endif
4110
4111         /* Queue skb data, a.k.a. the main skb fragment. */
4112         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4113
4114         tp->tx_buffers[entry].skb = skb;
4115         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4116
4117         would_hit_hwbug = 0;
4118
4119         if (tg3_4g_overflow_test(mapping, len))
4120                 would_hit_hwbug = 1;
4121
4122         tg3_set_txd(tp, entry, mapping, len, base_flags,
4123                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4124
4125         entry = NEXT_TX(entry);
4126
4127         /* Now loop through additional data fragments, and queue them. */
4128         if (skb_shinfo(skb)->nr_frags > 0) {
4129                 unsigned int i, last;
4130
4131                 last = skb_shinfo(skb)->nr_frags - 1;
4132                 for (i = 0; i <= last; i++) {
4133                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4134
4135                         len = frag->size;
4136                         mapping = pci_map_page(tp->pdev,
4137                                                frag->page,
4138                                                frag->page_offset,
4139                                                len, PCI_DMA_TODEVICE);
4140
4141                         tp->tx_buffers[entry].skb = NULL;
4142                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4143
4144                         if (tg3_4g_overflow_test(mapping, len))
4145                                 would_hit_hwbug = 1;
4146
4147                         if (tg3_40bit_overflow_test(tp, mapping, len))
4148                                 would_hit_hwbug = 1;
4149
4150                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4151                                 tg3_set_txd(tp, entry, mapping, len,
4152                                             base_flags, (i == last)|(mss << 1));
4153                         else
4154                                 tg3_set_txd(tp, entry, mapping, len,
4155                                             base_flags, (i == last));
4156
4157                         entry = NEXT_TX(entry);
4158                 }
4159         }
4160
4161         if (would_hit_hwbug) {
4162                 u32 last_plus_one = entry;
4163                 u32 start;
4164
4165                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4166                 start &= (TG3_TX_RING_SIZE - 1);
4167
4168                 /* If the workaround fails due to memory/mapping
4169                  * failure, silently drop this packet.
4170                  */
4171                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4172                                                 &start, base_flags, mss))
4173                         goto out_unlock;
4174
4175                 entry = start;
4176         }
4177
4178         /* Packets are ready, update Tx producer idx local and on card. */
4179         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4180
4181         tp->tx_prod = entry;
4182         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4183                 netif_stop_queue(dev);
4184                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4185                         netif_wake_queue(tp->dev);
4186         }
4187
4188 out_unlock:
4189         mmiowb();
4190
4191         dev->trans_start = jiffies;
4192
4193         return NETDEV_TX_OK;
4194 }
4195
4196 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4197                                int new_mtu)
4198 {
4199         dev->mtu = new_mtu;
4200
4201         if (new_mtu > ETH_DATA_LEN) {
4202                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4203                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4204                         ethtool_op_set_tso(dev, 0);
4205                 }
4206                 else
4207                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4208         } else {
4209                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4210                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4211                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4212         }
4213 }
4214
4215 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4216 {
4217         struct tg3 *tp = netdev_priv(dev);
4218         int err;
4219
4220         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4221                 return -EINVAL;
4222
4223         if (!netif_running(dev)) {
4224                 /* We'll just catch it later when the
4225                  * device is up'd.
4226                  */
4227                 tg3_set_mtu(dev, tp, new_mtu);
4228                 return 0;
4229         }
4230
4231         tg3_netif_stop(tp);
4232
4233         tg3_full_lock(tp, 1);
4234
4235         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4236
4237         tg3_set_mtu(dev, tp, new_mtu);
4238
4239         err = tg3_restart_hw(tp, 0);
4240
4241         if (!err)
4242                 tg3_netif_start(tp);
4243
4244         tg3_full_unlock(tp);
4245
4246         return err;
4247 }
4248
4249 /* Free up pending packets in all rx/tx rings.
4250  *
4251  * The chip has been shut down and the driver detached from
4252  * the networking, so no interrupts or new tx packets will
4253  * end up in the driver.  tp->{tx,}lock is not held and we are not
4254  * in an interrupt context and thus may sleep.
4255  */
4256 static void tg3_free_rings(struct tg3 *tp)
4257 {
4258         struct ring_info *rxp;
4259         int i;
4260
4261         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4262                 rxp = &tp->rx_std_buffers[i];
4263
4264                 if (rxp->skb == NULL)
4265                         continue;
4266                 pci_unmap_single(tp->pdev,
4267                                  pci_unmap_addr(rxp, mapping),
4268                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4269                                  PCI_DMA_FROMDEVICE);
4270                 dev_kfree_skb_any(rxp->skb);
4271                 rxp->skb = NULL;
4272         }
4273
4274         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4275                 rxp = &tp->rx_jumbo_buffers[i];
4276
4277                 if (rxp->skb == NULL)
4278                         continue;
4279                 pci_unmap_single(tp->pdev,
4280                                  pci_unmap_addr(rxp, mapping),
4281                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4282                                  PCI_DMA_FROMDEVICE);
4283                 dev_kfree_skb_any(rxp->skb);
4284                 rxp->skb = NULL;
4285         }
4286
4287         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4288                 struct tx_ring_info *txp;
4289                 struct sk_buff *skb;
4290                 int j;
4291
4292                 txp = &tp->tx_buffers[i];
4293                 skb = txp->skb;
4294
4295                 if (skb == NULL) {
4296                         i++;
4297                         continue;
4298                 }
4299
4300                 pci_unmap_single(tp->pdev,
4301                                  pci_unmap_addr(txp, mapping),
4302                                  skb_headlen(skb),
4303                                  PCI_DMA_TODEVICE);
4304                 txp->skb = NULL;
4305
4306                 i++;
4307
4308                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4309                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4310                         pci_unmap_page(tp->pdev,
4311                                        pci_unmap_addr(txp, mapping),
4312                                        skb_shinfo(skb)->frags[j].size,
4313                                        PCI_DMA_TODEVICE);
4314                         i++;
4315                 }
4316
4317                 dev_kfree_skb_any(skb);
4318         }
4319 }
4320
4321 /* Initialize tx/rx rings for packet processing.
4322  *
4323  * The chip has been shut down and the driver detached from
4324  * the networking, so no interrupts or new tx packets will
4325  * end up in the driver.  tp->{tx,}lock are held and thus
4326  * we may not sleep.
4327  */
4328 static int tg3_init_rings(struct tg3 *tp)
4329 {
4330         u32 i;
4331
4332         /* Free up all the SKBs. */
4333         tg3_free_rings(tp);
4334
4335         /* Zero out all descriptors. */
4336         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4337         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4338         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4339         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4340
4341         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4342         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4343             (tp->dev->mtu > ETH_DATA_LEN))
4344                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4345
4346         /* Initialize invariants of the rings, we only set this
4347          * stuff once.  This works because the card does not
4348          * write into the rx buffer posting rings.
4349          */
4350         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4351                 struct tg3_rx_buffer_desc *rxd;
4352
4353                 rxd = &tp->rx_std[i];
4354                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4355                         << RXD_LEN_SHIFT;
4356                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4357                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4358                                (i << RXD_OPAQUE_INDEX_SHIFT));
4359         }
4360
4361         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4362                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4363                         struct tg3_rx_buffer_desc *rxd;
4364
4365                         rxd = &tp->rx_jumbo[i];
4366                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4367                                 << RXD_LEN_SHIFT;
4368                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4369                                 RXD_FLAG_JUMBO;
4370                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4371                                (i << RXD_OPAQUE_INDEX_SHIFT));
4372                 }
4373         }
4374
4375         /* Now allocate fresh SKBs for each rx ring. */
4376         for (i = 0; i < tp->rx_pending; i++) {
4377                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4378                         printk(KERN_WARNING PFX
4379                                "%s: Using a smaller RX standard ring, "
4380                                "only %d out of %d buffers were allocated "
4381                                "successfully.\n",
4382                                tp->dev->name, i, tp->rx_pending);
4383                         if (i == 0)
4384                                 return -ENOMEM;
4385                         tp->rx_pending = i;
4386                         break;
4387                 }
4388         }
4389
4390         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4391                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4392                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4393                                              -1, i) < 0) {
4394                                 printk(KERN_WARNING PFX
4395                                        "%s: Using a smaller RX jumbo ring, "
4396                                        "only %d out of %d buffers were "
4397                                        "allocated successfully.\n",
4398                                        tp->dev->name, i, tp->rx_jumbo_pending);
4399                                 if (i == 0) {
4400                                         tg3_free_rings(tp);
4401                                         return -ENOMEM;
4402                                 }
4403                                 tp->rx_jumbo_pending = i;
4404                                 break;
4405                         }
4406                 }
4407         }
4408         return 0;
4409 }
4410
4411 /*
4412  * Must not be invoked with interrupt sources disabled and
4413  * the hardware shutdown down.
4414  */
4415 static void tg3_free_consistent(struct tg3 *tp)
4416 {
4417         kfree(tp->rx_std_buffers);
4418         tp->rx_std_buffers = NULL;
4419         if (tp->rx_std) {
4420                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4421                                     tp->rx_std, tp->rx_std_mapping);
4422                 tp->rx_std = NULL;
4423         }
4424         if (tp->rx_jumbo) {
4425                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4426                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4427                 tp->rx_jumbo = NULL;
4428         }
4429         if (tp->rx_rcb) {
4430                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4431                                     tp->rx_rcb, tp->rx_rcb_mapping);
4432                 tp->rx_rcb = NULL;
4433         }
4434         if (tp->tx_ring) {
4435                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4436                         tp->tx_ring, tp->tx_desc_mapping);
4437                 tp->tx_ring = NULL;
4438         }
4439         if (tp->hw_status) {
4440                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4441                                     tp->hw_status, tp->status_mapping);
4442                 tp->hw_status = NULL;
4443         }
4444         if (tp->hw_stats) {
4445                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4446                                     tp->hw_stats, tp->stats_mapping);
4447                 tp->hw_stats = NULL;
4448         }
4449 }
4450
4451 /*
4452  * Must not be invoked with interrupt sources disabled and
4453  * the hardware shutdown down.  Can sleep.
4454  */
4455 static int tg3_alloc_consistent(struct tg3 *tp)
4456 {
4457         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4458                                       (TG3_RX_RING_SIZE +
4459                                        TG3_RX_JUMBO_RING_SIZE)) +
4460                                      (sizeof(struct tx_ring_info) *
4461                                       TG3_TX_RING_SIZE),
4462                                      GFP_KERNEL);
4463         if (!tp->rx_std_buffers)
4464                 return -ENOMEM;
4465
4466         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4467         tp->tx_buffers = (struct tx_ring_info *)
4468                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4469
4470         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4471                                           &tp->rx_std_mapping);
4472         if (!tp->rx_std)
4473                 goto err_out;
4474
4475         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4476                                             &tp->rx_jumbo_mapping);
4477
4478         if (!tp->rx_jumbo)
4479                 goto err_out;
4480
4481         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4482                                           &tp->rx_rcb_mapping);
4483         if (!tp->rx_rcb)
4484                 goto err_out;
4485
4486         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4487                                            &tp->tx_desc_mapping);
4488         if (!tp->tx_ring)
4489                 goto err_out;
4490
4491         tp->hw_status = pci_alloc_consistent(tp->pdev,
4492                                              TG3_HW_STATUS_SIZE,
4493                                              &tp->status_mapping);
4494         if (!tp->hw_status)
4495                 goto err_out;
4496
4497         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4498                                             sizeof(struct tg3_hw_stats),
4499                                             &tp->stats_mapping);
4500         if (!tp->hw_stats)
4501                 goto err_out;
4502
4503         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4504         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4505
4506         return 0;
4507
4508 err_out:
4509         tg3_free_consistent(tp);
4510         return -ENOMEM;
4511 }
4512
4513 #define MAX_WAIT_CNT 1000
4514
4515 /* To stop a block, clear the enable bit and poll till it
4516  * clears.  tp->lock is held.
4517  */
4518 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4519 {
4520         unsigned int i;
4521         u32 val;
4522
4523         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4524                 switch (ofs) {
4525                 case RCVLSC_MODE:
4526                 case DMAC_MODE:
4527                 case MBFREE_MODE:
4528                 case BUFMGR_MODE:
4529                 case MEMARB_MODE:
4530                         /* We can't enable/disable these bits of the
4531                          * 5705/5750, just say success.
4532                          */
4533                         return 0;
4534
4535                 default:
4536                         break;
4537                 };
4538         }
4539
4540         val = tr32(ofs);
4541         val &= ~enable_bit;
4542         tw32_f(ofs, val);
4543
4544         for (i = 0; i < MAX_WAIT_CNT; i++) {
4545                 udelay(100);
4546                 val = tr32(ofs);
4547                 if ((val & enable_bit) == 0)
4548                         break;
4549         }
4550
4551         if (i == MAX_WAIT_CNT && !silent) {
4552                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4553                        "ofs=%lx enable_bit=%x\n",
4554                        ofs, enable_bit);
4555                 return -ENODEV;
4556         }
4557
4558         return 0;
4559 }
4560
4561 /* tp->lock is held. */
4562 static int tg3_abort_hw(struct tg3 *tp, int silent)
4563 {
4564         int i, err;
4565
4566         tg3_disable_ints(tp);
4567
4568         tp->rx_mode &= ~RX_MODE_ENABLE;
4569         tw32_f(MAC_RX_MODE, tp->rx_mode);
4570         udelay(10);
4571
4572         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4573         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4574         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4575         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4576         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4577         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4578
4579         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4580         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4581         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4582         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4583         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4584         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4585         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4586
4587         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4588         tw32_f(MAC_MODE, tp->mac_mode);
4589         udelay(40);
4590
4591         tp->tx_mode &= ~TX_MODE_ENABLE;
4592         tw32_f(MAC_TX_MODE, tp->tx_mode);
4593
4594         for (i = 0; i < MAX_WAIT_CNT; i++) {
4595                 udelay(100);
4596                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4597                         break;
4598         }
4599         if (i >= MAX_WAIT_CNT) {
4600                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4601                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4602                        tp->dev->name, tr32(MAC_TX_MODE));
4603                 err |= -ENODEV;
4604         }
4605
4606         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4607         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4608         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4609
4610         tw32(FTQ_RESET, 0xffffffff);
4611         tw32(FTQ_RESET, 0x00000000);
4612
4613         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4614         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4615
4616         if (tp->hw_status)
4617                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4618         if (tp->hw_stats)
4619                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4620
4621         return err;
4622 }
4623
4624 /* tp->lock is held. */
4625 static int tg3_nvram_lock(struct tg3 *tp)
4626 {
4627         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4628                 int i;
4629
4630                 if (tp->nvram_lock_cnt == 0) {
4631                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4632                         for (i = 0; i < 8000; i++) {
4633                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4634                                         break;
4635                                 udelay(20);
4636                         }
4637                         if (i == 8000) {
4638                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4639                                 return -ENODEV;
4640                         }
4641                 }
4642                 tp->nvram_lock_cnt++;
4643         }
4644         return 0;
4645 }
4646
4647 /* tp->lock is held. */
4648 static void tg3_nvram_unlock(struct tg3 *tp)
4649 {
4650         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4651                 if (tp->nvram_lock_cnt > 0)
4652                         tp->nvram_lock_cnt--;
4653                 if (tp->nvram_lock_cnt == 0)
4654                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4655         }
4656 }
4657
4658 /* tp->lock is held. */
4659 static void tg3_enable_nvram_access(struct tg3 *tp)
4660 {
4661         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4662             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4663                 u32 nvaccess = tr32(NVRAM_ACCESS);
4664
4665                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4666         }
4667 }
4668
4669 /* tp->lock is held. */
4670 static void tg3_disable_nvram_access(struct tg3 *tp)
4671 {
4672         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4673             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4674                 u32 nvaccess = tr32(NVRAM_ACCESS);
4675
4676                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4677         }
4678 }
4679
4680 /* tp->lock is held. */
4681 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4682 {
4683         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4684                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4685
4686         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4687                 switch (kind) {
4688                 case RESET_KIND_INIT:
4689                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4690                                       DRV_STATE_START);
4691                         break;
4692
4693                 case RESET_KIND_SHUTDOWN:
4694                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4695                                       DRV_STATE_UNLOAD);
4696                         break;
4697
4698                 case RESET_KIND_SUSPEND:
4699                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4700                                       DRV_STATE_SUSPEND);
4701                         break;
4702
4703                 default:
4704                         break;
4705                 };
4706         }
4707 }
4708
4709 /* tp->lock is held. */
4710 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4711 {
4712         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4713                 switch (kind) {
4714                 case RESET_KIND_INIT:
4715                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4716                                       DRV_STATE_START_DONE);
4717                         break;
4718
4719                 case RESET_KIND_SHUTDOWN:
4720                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4721                                       DRV_STATE_UNLOAD_DONE);
4722                         break;
4723
4724                 default:
4725                         break;
4726                 };
4727         }
4728 }
4729
4730 /* tp->lock is held. */
4731 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4732 {
4733         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4734                 switch (kind) {
4735                 case RESET_KIND_INIT:
4736                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4737                                       DRV_STATE_START);
4738                         break;
4739
4740                 case RESET_KIND_SHUTDOWN:
4741                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4742                                       DRV_STATE_UNLOAD);
4743                         break;
4744
4745                 case RESET_KIND_SUSPEND:
4746                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4747                                       DRV_STATE_SUSPEND);
4748                         break;
4749
4750                 default:
4751                         break;
4752                 };
4753         }
4754 }
4755
4756 static int tg3_poll_fw(struct tg3 *tp)
4757 {
4758         int i;
4759         u32 val;
4760
4761         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4762                 /* Wait up to 20ms for init done. */
4763                 for (i = 0; i < 200; i++) {
4764                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4765                                 return 0;
4766                         udelay(100);
4767                 }
4768                 return -ENODEV;
4769         }
4770
4771         /* Wait for firmware initialization to complete. */
4772         for (i = 0; i < 100000; i++) {
4773                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4774                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4775                         break;
4776                 udelay(10);
4777         }
4778
4779         /* Chip might not be fitted with firmware.  Some Sun onboard
4780          * parts are configured like that.  So don't signal the timeout
4781          * of the above loop as an error, but do report the lack of
4782          * running firmware once.
4783          */
4784         if (i >= 100000 &&
4785             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4786                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4787
4788                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4789                        tp->dev->name);
4790         }
4791
4792         return 0;
4793 }
4794
4795 static void tg3_stop_fw(struct tg3 *);
4796
4797 /* tp->lock is held. */
4798 static int tg3_chip_reset(struct tg3 *tp)
4799 {
4800         u32 val;
4801         void (*write_op)(struct tg3 *, u32, u32);
4802         int err;
4803
4804         tg3_nvram_lock(tp);
4805
4806         /* No matching tg3_nvram_unlock() after this because
4807          * chip reset below will undo the nvram lock.
4808          */
4809         tp->nvram_lock_cnt = 0;
4810
4811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4812             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4813             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4814                 tw32(GRC_FASTBOOT_PC, 0);
4815
4816         /*
4817          * We must avoid the readl() that normally takes place.
4818          * It locks machines, causes machine checks, and other
4819          * fun things.  So, temporarily disable the 5701
4820          * hardware workaround, while we do the reset.
4821          */
4822         write_op = tp->write32;
4823         if (write_op == tg3_write_flush_reg32)
4824                 tp->write32 = tg3_write32;
4825
4826         /* do the reset */
4827         val = GRC_MISC_CFG_CORECLK_RESET;
4828
4829         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4830                 if (tr32(0x7e2c) == 0x60) {
4831                         tw32(0x7e2c, 0x20);
4832                 }
4833                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4834                         tw32(GRC_MISC_CFG, (1 << 29));
4835                         val |= (1 << 29);
4836                 }
4837         }
4838
4839         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4840                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4841                 tw32(GRC_VCPU_EXT_CTRL,
4842                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4843         }
4844
4845         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4846                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4847         tw32(GRC_MISC_CFG, val);
4848
4849         /* restore 5701 hardware bug workaround write method */
4850         tp->write32 = write_op;
4851
4852         /* Unfortunately, we have to delay before the PCI read back.
4853          * Some 575X chips even will not respond to a PCI cfg access
4854          * when the reset command is given to the chip.
4855          *
4856          * How do these hardware designers expect things to work
4857          * properly if the PCI write is posted for a long period
4858          * of time?  It is always necessary to have some method by
4859          * which a register read back can occur to push the write
4860          * out which does the reset.
4861          *
4862          * For most tg3 variants the trick below was working.
4863          * Ho hum...
4864          */
4865         udelay(120);
4866
4867         /* Flush PCI posted writes.  The normal MMIO registers
4868          * are inaccessible at this time so this is the only
4869          * way to make this reliably (actually, this is no longer
4870          * the case, see above).  I tried to use indirect
4871          * register read/write but this upset some 5701 variants.
4872          */
4873         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4874
4875         udelay(120);
4876
4877         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4878                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4879                         int i;
4880                         u32 cfg_val;
4881
4882                         /* Wait for link training to complete.  */
4883                         for (i = 0; i < 5000; i++)
4884                                 udelay(100);
4885
4886                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4887                         pci_write_config_dword(tp->pdev, 0xc4,
4888                                                cfg_val | (1 << 15));
4889                 }
4890                 /* Set PCIE max payload size and clear error status.  */
4891                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4892         }
4893
4894         /* Re-enable indirect register accesses. */
4895         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4896                                tp->misc_host_ctrl);
4897
4898         /* Set MAX PCI retry to zero. */
4899         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4900         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4901             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4902                 val |= PCISTATE_RETRY_SAME_DMA;
4903         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4904
4905         pci_restore_state(tp->pdev);
4906
4907         /* Make sure PCI-X relaxed ordering bit is clear. */
4908         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4909         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4910         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4911
4912         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4913                 u32 val;
4914
4915                 /* Chip reset on 5780 will reset MSI enable bit,
4916                  * so need to restore it.
4917                  */
4918                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4919                         u16 ctrl;
4920
4921                         pci_read_config_word(tp->pdev,
4922                                              tp->msi_cap + PCI_MSI_FLAGS,
4923                                              &ctrl);
4924                         pci_write_config_word(tp->pdev,
4925                                               tp->msi_cap + PCI_MSI_FLAGS,
4926                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4927                         val = tr32(MSGINT_MODE);
4928                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4929                 }
4930
4931                 val = tr32(MEMARB_MODE);
4932                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4933
4934         } else
4935                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4936
4937         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4938                 tg3_stop_fw(tp);
4939                 tw32(0x5000, 0x400);
4940         }
4941
4942         tw32(GRC_MODE, tp->grc_mode);
4943
4944         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4945                 u32 val = tr32(0xc4);
4946
4947                 tw32(0xc4, val | (1 << 15));
4948         }
4949
4950         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4951             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4952                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4953                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4954                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4955                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4956         }
4957
4958         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4959                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4960                 tw32_f(MAC_MODE, tp->mac_mode);
4961         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4962                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4963                 tw32_f(MAC_MODE, tp->mac_mode);
4964         } else
4965                 tw32_f(MAC_MODE, 0);
4966         udelay(40);
4967
4968         err = tg3_poll_fw(tp);
4969         if (err)
4970                 return err;
4971
4972         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4973             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4974                 u32 val = tr32(0x7c00);
4975
4976                 tw32(0x7c00, val | (1 << 25));
4977         }
4978
4979         /* Reprobe ASF enable state.  */
4980         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4981         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4982         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4983         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4984                 u32 nic_cfg;
4985
4986                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4987                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4988                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4989                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4990                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4991                 }
4992         }
4993
4994         return 0;
4995 }
4996
4997 /* tp->lock is held. */
4998 static void tg3_stop_fw(struct tg3 *tp)
4999 {
5000         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5001                 u32 val;
5002                 int i;
5003
5004                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5005                 val = tr32(GRC_RX_CPU_EVENT);
5006                 val |= (1 << 14);
5007                 tw32(GRC_RX_CPU_EVENT, val);
5008
5009                 /* Wait for RX cpu to ACK the event.  */
5010                 for (i = 0; i < 100; i++) {
5011                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5012                                 break;
5013                         udelay(1);
5014                 }
5015         }
5016 }
5017
5018 /* tp->lock is held. */
5019 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5020 {
5021         int err;
5022
5023         tg3_stop_fw(tp);
5024
5025         tg3_write_sig_pre_reset(tp, kind);
5026
5027         tg3_abort_hw(tp, silent);
5028         err = tg3_chip_reset(tp);
5029
5030         tg3_write_sig_legacy(tp, kind);
5031         tg3_write_sig_post_reset(tp, kind);
5032
5033         if (err)
5034                 return err;
5035
5036         return 0;
5037 }
5038
5039 #define TG3_FW_RELEASE_MAJOR    0x0
5040 #define TG3_FW_RELASE_MINOR     0x0
5041 #define TG3_FW_RELEASE_FIX      0x0
5042 #define TG3_FW_START_ADDR       0x08000000
5043 #define TG3_FW_TEXT_ADDR        0x08000000
5044 #define TG3_FW_TEXT_LEN         0x9c0
5045 #define TG3_FW_RODATA_ADDR      0x080009c0
5046 #define TG3_FW_RODATA_LEN       0x60
5047 #define TG3_FW_DATA_ADDR        0x08000a40
5048 #define TG3_FW_DATA_LEN         0x20
5049 #define TG3_FW_SBSS_ADDR        0x08000a60
5050 #define TG3_FW_SBSS_LEN         0xc
5051 #define TG3_FW_BSS_ADDR         0x08000a70
5052 #define TG3_FW_BSS_LEN          0x10
5053
5054 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5055         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5056         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5057         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5058         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5059         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5060         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5061         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5062         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5063         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5064         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5065         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5066         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5067         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5068         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5069         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5070         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5071         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5072         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5073         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5074         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5075         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5076         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5077         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5078         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5079         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5080         0, 0, 0, 0, 0, 0,
5081         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5082         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5083         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5084         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5085         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5086         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5087         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5088         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5089         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5090         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5091         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5092         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5093         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5094         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5095         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5096         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5097         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5098         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5099         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5100         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5101         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5102         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5103         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5104         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5105         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5106         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5107         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5108         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5109         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5110         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5111         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5112         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5113         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5114         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5115         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5116         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5117         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5118         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5119         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5120         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5121         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5122         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5123         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5124         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5125         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5126         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5127         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5128         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5129         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5130         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5131         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5132         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5133         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5134         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5135         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5136         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5137         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5138         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5139         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5140         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5141         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5142         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5143         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5144         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5145         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5146 };
5147
5148 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5149         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5150         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5151         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5152         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5153         0x00000000
5154 };
5155
5156 #if 0 /* All zeros, don't eat up space with it. */
5157 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5158         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5159         0x00000000, 0x00000000, 0x00000000, 0x00000000
5160 };
5161 #endif
5162
5163 #define RX_CPU_SCRATCH_BASE     0x30000
5164 #define RX_CPU_SCRATCH_SIZE     0x04000
5165 #define TX_CPU_SCRATCH_BASE     0x34000
5166 #define TX_CPU_SCRATCH_SIZE     0x04000
5167
5168 /* tp->lock is held. */
5169 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5170 {
5171         int i;
5172
5173         BUG_ON(offset == TX_CPU_BASE &&
5174             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5175
5176         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5177                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5178
5179                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5180                 return 0;
5181         }
5182         if (offset == RX_CPU_BASE) {
5183                 for (i = 0; i < 10000; i++) {
5184                         tw32(offset + CPU_STATE, 0xffffffff);
5185                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5186                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5187                                 break;
5188                 }
5189
5190                 tw32(offset + CPU_STATE, 0xffffffff);
5191                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5192                 udelay(10);
5193         } else {
5194                 for (i = 0; i < 10000; i++) {
5195                         tw32(offset + CPU_STATE, 0xffffffff);
5196                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5197                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5198                                 break;
5199                 }
5200         }
5201
5202         if (i >= 10000) {
5203                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5204                        "and %s CPU\n",
5205                        tp->dev->name,
5206                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5207                 return -ENODEV;
5208         }
5209
5210         /* Clear firmware's nvram arbitration. */
5211         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5212                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5213         return 0;
5214 }
5215
5216 struct fw_info {
5217         unsigned int text_base;
5218         unsigned int text_len;
5219         const u32 *text_data;
5220         unsigned int rodata_base;
5221         unsigned int rodata_len;
5222         const u32 *rodata_data;
5223         unsigned int data_base;
5224         unsigned int data_len;
5225         const u32 *data_data;
5226 };
5227
5228 /* tp->lock is held. */
5229 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5230                                  int cpu_scratch_size, struct fw_info *info)
5231 {
5232         int err, lock_err, i;
5233         void (*write_op)(struct tg3 *, u32, u32);
5234
5235         if (cpu_base == TX_CPU_BASE &&
5236             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5237                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5238                        "TX cpu firmware on %s which is 5705.\n",
5239                        tp->dev->name);
5240                 return -EINVAL;
5241         }
5242
5243         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5244                 write_op = tg3_write_mem;
5245         else
5246                 write_op = tg3_write_indirect_reg32;
5247
5248         /* It is possible that bootcode is still loading at this point.
5249          * Get the nvram lock first before halting the cpu.
5250          */
5251         lock_err = tg3_nvram_lock(tp);
5252         err = tg3_halt_cpu(tp, cpu_base);
5253         if (!lock_err)
5254                 tg3_nvram_unlock(tp);
5255         if (err)
5256                 goto out;
5257
5258         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5259                 write_op(tp, cpu_scratch_base + i, 0);
5260         tw32(cpu_base + CPU_STATE, 0xffffffff);
5261         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5262         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5263                 write_op(tp, (cpu_scratch_base +
5264                               (info->text_base & 0xffff) +
5265                               (i * sizeof(u32))),
5266                          (info->text_data ?
5267                           info->text_data[i] : 0));
5268         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5269                 write_op(tp, (cpu_scratch_base +
5270                               (info->rodata_base & 0xffff) +
5271                               (i * sizeof(u32))),
5272                          (info->rodata_data ?
5273                           info->rodata_data[i] : 0));
5274         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5275                 write_op(tp, (cpu_scratch_base +
5276                               (info->data_base & 0xffff) +
5277                               (i * sizeof(u32))),
5278                          (info->data_data ?
5279                           info->data_data[i] : 0));
5280
5281         err = 0;
5282
5283 out:
5284         return err;
5285 }
5286
5287 /* tp->lock is held. */
5288 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5289 {
5290         struct fw_info info;
5291         int err, i;
5292
5293         info.text_base = TG3_FW_TEXT_ADDR;
5294         info.text_len = TG3_FW_TEXT_LEN;
5295         info.text_data = &tg3FwText[0];
5296         info.rodata_base = TG3_FW_RODATA_ADDR;
5297         info.rodata_len = TG3_FW_RODATA_LEN;
5298         info.rodata_data = &tg3FwRodata[0];
5299         info.data_base = TG3_FW_DATA_ADDR;
5300         info.data_len = TG3_FW_DATA_LEN;
5301         info.data_data = NULL;
5302
5303         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5304                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5305                                     &info);
5306         if (err)
5307                 return err;
5308
5309         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5310                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5311                                     &info);
5312         if (err)
5313                 return err;
5314
5315         /* Now startup only the RX cpu. */
5316         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5317         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5318
5319         for (i = 0; i < 5; i++) {
5320                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5321                         break;
5322                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5323                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5324                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5325                 udelay(1000);
5326         }
5327         if (i >= 5) {
5328                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5329                        "to set RX CPU PC, is %08x should be %08x\n",
5330                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5331                        TG3_FW_TEXT_ADDR);
5332                 return -ENODEV;
5333         }
5334         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5335         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5336
5337         return 0;
5338 }
5339
5340
5341 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5342 #define TG3_TSO_FW_RELASE_MINOR         0x6
5343 #define TG3_TSO_FW_RELEASE_FIX          0x0
5344 #define TG3_TSO_FW_START_ADDR           0x08000000
5345 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5346 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5347 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5348 #define TG3_TSO_FW_RODATA_LEN           0x60
5349 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5350 #define TG3_TSO_FW_DATA_LEN             0x30
5351 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5352 #define TG3_TSO_FW_SBSS_LEN             0x2c
5353 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5354 #define TG3_TSO_FW_BSS_LEN              0x894
5355
5356 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5357         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5358         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5359         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5360         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5361         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5362         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5363         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5364         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5365         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5366         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5367         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5368         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5369         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5370         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5371         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5372         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5373         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5374         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5375         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5376         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5377         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5378         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5379         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5380         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5381         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5382         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5383         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5384         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5385         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5386         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5387         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5388         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5389         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5390         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5391         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5392         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5393         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5394         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5395         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5396         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5397         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5398         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5399         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5400         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5401         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5402         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5403         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5404         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5405         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5406         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5407         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5408         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5409         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5410         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5411         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5412         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5413         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5414         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5415         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5416         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5417         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5418         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5419         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5420         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5421         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5422         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5423         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5424         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5425         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5426         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5427         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5428         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5429         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5430         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5431         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5432         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5433         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5434         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5435         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5436         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5437         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5438         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5439         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5440         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5441         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5442         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5443         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5444         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5445         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5446         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5447         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5448         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5449         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5450         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5451         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5452         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5453         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5454         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5455         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5456         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5457         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5458         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5459         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5460         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5461         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5462         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5463         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5464         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5465         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5466         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5467         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5468         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5469         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5470         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5471         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5472         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5473         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5474         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5475         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5476         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5477         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5478         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5479         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5480         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5481         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5482         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5483         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5484         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5485         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5486         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5487         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5488         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5489         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5490         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5491         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5492         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5493         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5494         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5495         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5496         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5497         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5498         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5499         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5500         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5501         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5502         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5503         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5504         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5505         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5506         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5507         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5508         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5509         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5510         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5511         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5512         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5513         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5514         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5515         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5516         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5517         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5518         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5519         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5520         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5521         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5522         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5523         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5524         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5525         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5526         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5527         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5528         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5529         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5530         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5531         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5532         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5533         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5534         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5535         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5536         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5537         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5538         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5539         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5540         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5541         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5542         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5543         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5544         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5545         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5546         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5547         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5548         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5549         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5550         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5551         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5552         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5553         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5554         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5555         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5556         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5557         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5558         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5559         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5560         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5561         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5562         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5563         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5564         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5565         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5566         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5567         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5568         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5569         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5570         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5571         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5572         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5573         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5574         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5575         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5576         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5577         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5578         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5579         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5580         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5581         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5582         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5583         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5584         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5585         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5586         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5587         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5588         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5589         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5590         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5591         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5592         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5593         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5594         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5595         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5596         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5597         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5598         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5599         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5600         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5601         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5602         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5603         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5604         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5605         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5606         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5607         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5608         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5609         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5610         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5611         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5612         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5613         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5614         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5615         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5616         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5617         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5618         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5619         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5620         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5621         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5622         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5623         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5624         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5625         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5626         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5627         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5628         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5629         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5630         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5631         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5632         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5633         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5634         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5635         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5636         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5637         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5638         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5639         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5640         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5641 };
5642
5643 static const u32 tg3TsoFwRodata[] = {
5644         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5645         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5646         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5647         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5648         0x00000000,
5649 };
5650
5651 static const u32 tg3TsoFwData[] = {
5652         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5653         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5654         0x00000000,
5655 };
5656
5657 /* 5705 needs a special version of the TSO firmware.  */
5658 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5659 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5660 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5661 #define TG3_TSO5_FW_START_ADDR          0x00010000
5662 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5663 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5664 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5665 #define TG3_TSO5_FW_RODATA_LEN          0x50
5666 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5667 #define TG3_TSO5_FW_DATA_LEN            0x20
5668 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5669 #define TG3_TSO5_FW_SBSS_LEN            0x28
5670 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5671 #define TG3_TSO5_FW_BSS_LEN             0x88
5672
5673 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5674         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5675         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5676         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5677         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5678         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5679         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5680         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5681         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5682         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5683         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5684         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5685         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5686         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5687         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5688         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5689         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5690         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5691         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5692         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5693         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5694         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5695         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5696         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5697         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5698         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5699         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5700         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5701         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5702         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5703         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5704         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5705         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5706         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5707         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5708         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5709         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5710         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5711         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5712         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5713         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5714         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5715         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5716         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5717         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5718         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5719         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5720         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5721         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5722         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5723         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5724         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5725         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5726         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5727         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5728         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5729         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5730         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5731         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5732         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5733         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5734         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5735         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5736         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5737         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5738         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5739         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5740         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5741         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5742         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5743         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5744         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5745         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5746         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5747         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5748         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5749         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5750         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5751         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5752         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5753         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5754         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5755         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5756         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5757         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5758         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5759         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5760         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5761         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5762         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5763         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5764         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5765         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5766         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5767         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5768         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5769         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5770         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5771         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5772         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5773         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5774         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5775         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5776         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5777         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5778         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5779         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5780         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5781         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5782         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5783         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5784         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5785         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5786         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5787         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5788         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5789         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5790         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5791         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5792         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5793         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5794         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5795         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5796         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5797         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5798         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5799         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5800         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5801         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5802         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5803         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5804         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5805         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5806         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5807         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5808         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5809         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5810         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5811         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5812         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5813         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5814         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5815         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5816         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5817         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5818         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5819         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5820         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5821         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5822         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5823         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5824         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5825         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5826         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5827         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5828         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5829         0x00000000, 0x00000000, 0x00000000,
5830 };
5831
5832 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5833         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5834         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5835         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5836         0x00000000, 0x00000000, 0x00000000,
5837 };
5838
5839 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5840         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5841         0x00000000, 0x00000000, 0x00000000,
5842 };
5843
5844 /* tp->lock is held. */
5845 static int tg3_load_tso_firmware(struct tg3 *tp)
5846 {
5847         struct fw_info info;
5848         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5849         int err, i;
5850
5851         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5852                 return 0;
5853
5854         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5855                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5856                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5857                 info.text_data = &tg3Tso5FwText[0];
5858                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5859                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5860                 info.rodata_data = &tg3Tso5FwRodata[0];
5861                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5862                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5863                 info.data_data = &tg3Tso5FwData[0];
5864                 cpu_base = RX_CPU_BASE;
5865                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5866                 cpu_scratch_size = (info.text_len +
5867                                     info.rodata_len +
5868                                     info.data_len +
5869                                     TG3_TSO5_FW_SBSS_LEN +
5870                                     TG3_TSO5_FW_BSS_LEN);
5871         } else {
5872                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5873                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5874                 info.text_data = &tg3TsoFwText[0];
5875                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5876                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5877                 info.rodata_data = &tg3TsoFwRodata[0];
5878                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5879                 info.data_len = TG3_TSO_FW_DATA_LEN;
5880                 info.data_data = &tg3TsoFwData[0];
5881                 cpu_base = TX_CPU_BASE;
5882                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5883                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5884         }
5885
5886         err = tg3_load_firmware_cpu(tp, cpu_base,
5887                                     cpu_scratch_base, cpu_scratch_size,
5888                                     &info);
5889         if (err)
5890                 return err;
5891
5892         /* Now startup the cpu. */
5893         tw32(cpu_base + CPU_STATE, 0xffffffff);
5894         tw32_f(cpu_base + CPU_PC,    info.text_base);
5895
5896         for (i = 0; i < 5; i++) {
5897                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5898                         break;
5899                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5900                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5901                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5902                 udelay(1000);
5903         }
5904         if (i >= 5) {
5905                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5906                        "to set CPU PC, is %08x should be %08x\n",
5907                        tp->dev->name, tr32(cpu_base + CPU_PC),
5908                        info.text_base);
5909                 return -ENODEV;
5910         }
5911         tw32(cpu_base + CPU_STATE, 0xffffffff);
5912         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5913         return 0;
5914 }
5915
5916
5917 /* tp->lock is held. */
5918 static void __tg3_set_mac_addr(struct tg3 *tp)
5919 {
5920         u32 addr_high, addr_low;
5921         int i;
5922
5923         addr_high = ((tp->dev->dev_addr[0] << 8) |
5924                      tp->dev->dev_addr[1]);
5925         addr_low = ((tp->dev->dev_addr[2] << 24) |
5926                     (tp->dev->dev_addr[3] << 16) |
5927                     (tp->dev->dev_addr[4] <<  8) |
5928                     (tp->dev->dev_addr[5] <<  0));
5929         for (i = 0; i < 4; i++) {
5930                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5931                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5932         }
5933
5934         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5935             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5936                 for (i = 0; i < 12; i++) {
5937                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5938                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5939                 }
5940         }
5941
5942         addr_high = (tp->dev->dev_addr[0] +
5943                      tp->dev->dev_addr[1] +
5944                      tp->dev->dev_addr[2] +
5945                      tp->dev->dev_addr[3] +
5946                      tp->dev->dev_addr[4] +
5947                      tp->dev->dev_addr[5]) &
5948                 TX_BACKOFF_SEED_MASK;
5949         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5950 }
5951
5952 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5953 {
5954         struct tg3 *tp = netdev_priv(dev);
5955         struct sockaddr *addr = p;
5956         int err = 0;
5957
5958         if (!is_valid_ether_addr(addr->sa_data))
5959                 return -EINVAL;
5960
5961         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5962
5963         if (!netif_running(dev))
5964                 return 0;
5965
5966         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5967                 /* Reset chip so that ASF can re-init any MAC addresses it
5968                  * needs.
5969                  */
5970                 tg3_netif_stop(tp);
5971                 tg3_full_lock(tp, 1);
5972
5973                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5974                 err = tg3_restart_hw(tp, 0);
5975                 if (!err)
5976                         tg3_netif_start(tp);
5977                 tg3_full_unlock(tp);
5978         } else {
5979                 spin_lock_bh(&tp->lock);
5980                 __tg3_set_mac_addr(tp);
5981                 spin_unlock_bh(&tp->lock);
5982         }
5983
5984         return err;
5985 }
5986
5987 /* tp->lock is held. */
5988 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5989                            dma_addr_t mapping, u32 maxlen_flags,
5990                            u32 nic_addr)
5991 {
5992         tg3_write_mem(tp,
5993                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5994                       ((u64) mapping >> 32));
5995         tg3_write_mem(tp,
5996                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5997                       ((u64) mapping & 0xffffffff));
5998         tg3_write_mem(tp,
5999                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6000                        maxlen_flags);
6001
6002         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6003                 tg3_write_mem(tp,
6004                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6005                               nic_addr);
6006 }
6007
6008 static void __tg3_set_rx_mode(struct net_device *);
6009 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6010 {
6011         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6012         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6013         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6014         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6015         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6016                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6017                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6018         }
6019         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6020         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6021         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6022                 u32 val = ec->stats_block_coalesce_usecs;
6023
6024                 if (!netif_carrier_ok(tp->dev))
6025                         val = 0;
6026
6027                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6028         }
6029 }
6030
6031 /* tp->lock is held. */
6032 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6033 {
6034         u32 val, rdmac_mode;
6035         int i, err, limit;
6036
6037         tg3_disable_ints(tp);
6038
6039         tg3_stop_fw(tp);
6040
6041         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6042
6043         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6044                 tg3_abort_hw(tp, 1);
6045         }
6046
6047         if (reset_phy)
6048                 tg3_phy_reset(tp);
6049
6050         err = tg3_chip_reset(tp);
6051         if (err)
6052                 return err;
6053
6054         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6055
6056         /* This works around an issue with Athlon chipsets on
6057          * B3 tigon3 silicon.  This bit has no effect on any
6058          * other revision.  But do not set this on PCI Express
6059          * chips.
6060          */
6061         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6062                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6063         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6064
6065         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6066             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6067                 val = tr32(TG3PCI_PCISTATE);
6068                 val |= PCISTATE_RETRY_SAME_DMA;
6069                 tw32(TG3PCI_PCISTATE, val);
6070         }
6071
6072         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6073                 /* Enable some hw fixes.  */
6074                 val = tr32(TG3PCI_MSI_DATA);
6075                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6076                 tw32(TG3PCI_MSI_DATA, val);
6077         }
6078
6079         /* Descriptor ring init may make accesses to the
6080          * NIC SRAM area to setup the TX descriptors, so we
6081          * can only do this after the hardware has been
6082          * successfully reset.
6083          */
6084         err = tg3_init_rings(tp);
6085         if (err)
6086                 return err;
6087
6088         /* This value is determined during the probe time DMA
6089          * engine test, tg3_test_dma.
6090          */
6091         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6092
6093         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6094                           GRC_MODE_4X_NIC_SEND_RINGS |
6095                           GRC_MODE_NO_TX_PHDR_CSUM |
6096                           GRC_MODE_NO_RX_PHDR_CSUM);
6097         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6098
6099         /* Pseudo-header checksum is done by hardware logic and not
6100          * the offload processers, so make the chip do the pseudo-
6101          * header checksums on receive.  For transmit it is more
6102          * convenient to do the pseudo-header checksum in software
6103          * as Linux does that on transmit for us in all cases.
6104          */
6105         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6106
6107         tw32(GRC_MODE,
6108              tp->grc_mode |
6109              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6110
6111         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6112         val = tr32(GRC_MISC_CFG);
6113         val &= ~0xff;
6114         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6115         tw32(GRC_MISC_CFG, val);
6116
6117         /* Initialize MBUF/DESC pool. */
6118         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6119                 /* Do nothing.  */
6120         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6121                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6122                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6123                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6124                 else
6125                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6126                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6127                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6128         }
6129         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6130                 int fw_len;
6131
6132                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6133                           TG3_TSO5_FW_RODATA_LEN +
6134                           TG3_TSO5_FW_DATA_LEN +
6135                           TG3_TSO5_FW_SBSS_LEN +
6136                           TG3_TSO5_FW_BSS_LEN);
6137                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6138                 tw32(BUFMGR_MB_POOL_ADDR,
6139                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6140                 tw32(BUFMGR_MB_POOL_SIZE,
6141                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6142         }
6143
6144         if (tp->dev->mtu <= ETH_DATA_LEN) {
6145                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6146                      tp->bufmgr_config.mbuf_read_dma_low_water);
6147                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6148                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6149                 tw32(BUFMGR_MB_HIGH_WATER,
6150                      tp->bufmgr_config.mbuf_high_water);
6151         } else {
6152                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6153                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6154                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6155                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6156                 tw32(BUFMGR_MB_HIGH_WATER,
6157                      tp->bufmgr_config.mbuf_high_water_jumbo);
6158         }
6159         tw32(BUFMGR_DMA_LOW_WATER,
6160              tp->bufmgr_config.dma_low_water);
6161         tw32(BUFMGR_DMA_HIGH_WATER,
6162              tp->bufmgr_config.dma_high_water);
6163
6164         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6165         for (i = 0; i < 2000; i++) {
6166                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6167                         break;
6168                 udelay(10);
6169         }
6170         if (i >= 2000) {
6171                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6172                        tp->dev->name);
6173                 return -ENODEV;
6174         }
6175
6176         /* Setup replenish threshold. */
6177         val = tp->rx_pending / 8;
6178         if (val == 0)
6179                 val = 1;
6180         else if (val > tp->rx_std_max_post)
6181                 val = tp->rx_std_max_post;
6182         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6183                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6184                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6185
6186                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6187                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6188         }
6189
6190         tw32(RCVBDI_STD_THRESH, val);
6191
6192         /* Initialize TG3_BDINFO's at:
6193          *  RCVDBDI_STD_BD:     standard eth size rx ring
6194          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6195          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6196          *
6197          * like so:
6198          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6199          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6200          *                              ring attribute flags
6201          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6202          *
6203          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6204          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6205          *
6206          * The size of each ring is fixed in the firmware, but the location is
6207          * configurable.
6208          */
6209         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6210              ((u64) tp->rx_std_mapping >> 32));
6211         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6212              ((u64) tp->rx_std_mapping & 0xffffffff));
6213         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6214              NIC_SRAM_RX_BUFFER_DESC);
6215
6216         /* Don't even try to program the JUMBO/MINI buffer descriptor
6217          * configs on 5705.
6218          */
6219         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6220                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6221                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6222         } else {
6223                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6224                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6225
6226                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6227                      BDINFO_FLAGS_DISABLED);
6228
6229                 /* Setup replenish threshold. */
6230                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6231
6232                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6233                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6234                              ((u64) tp->rx_jumbo_mapping >> 32));
6235                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6236                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6237                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6238                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6239                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6240                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6241                 } else {
6242                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6243                              BDINFO_FLAGS_DISABLED);
6244                 }
6245
6246         }
6247
6248         /* There is only one send ring on 5705/5750, no need to explicitly
6249          * disable the others.
6250          */
6251         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6252                 /* Clear out send RCB ring in SRAM. */
6253                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6254                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6255                                       BDINFO_FLAGS_DISABLED);
6256         }
6257
6258         tp->tx_prod = 0;
6259         tp->tx_cons = 0;
6260         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6261         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6262
6263         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6264                        tp->tx_desc_mapping,
6265                        (TG3_TX_RING_SIZE <<
6266                         BDINFO_FLAGS_MAXLEN_SHIFT),
6267                        NIC_SRAM_TX_BUFFER_DESC);
6268
6269         /* There is only one receive return ring on 5705/5750, no need
6270          * to explicitly disable the others.
6271          */
6272         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6273                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6274                      i += TG3_BDINFO_SIZE) {
6275                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6276                                       BDINFO_FLAGS_DISABLED);
6277                 }
6278         }
6279
6280         tp->rx_rcb_ptr = 0;
6281         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6282
6283         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6284                        tp->rx_rcb_mapping,
6285                        (TG3_RX_RCB_RING_SIZE(tp) <<
6286                         BDINFO_FLAGS_MAXLEN_SHIFT),
6287                        0);
6288
6289         tp->rx_std_ptr = tp->rx_pending;
6290         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6291                      tp->rx_std_ptr);
6292
6293         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6294                                                 tp->rx_jumbo_pending : 0;
6295         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6296                      tp->rx_jumbo_ptr);
6297
6298         /* Initialize MAC address and backoff seed. */
6299         __tg3_set_mac_addr(tp);
6300
6301         /* MTU + ethernet header + FCS + optional VLAN tag */
6302         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6303
6304         /* The slot time is changed by tg3_setup_phy if we
6305          * run at gigabit with half duplex.
6306          */
6307         tw32(MAC_TX_LENGTHS,
6308              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6309              (6 << TX_LENGTHS_IPG_SHIFT) |
6310              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6311
6312         /* Receive rules. */
6313         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6314         tw32(RCVLPC_CONFIG, 0x0181);
6315
6316         /* Calculate RDMAC_MODE setting early, we need it to determine
6317          * the RCVLPC_STATE_ENABLE mask.
6318          */
6319         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6320                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6321                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6322                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6323                       RDMAC_MODE_LNGREAD_ENAB);
6324         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6325                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6326
6327         /* If statement applies to 5705 and 5750 PCI devices only */
6328         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6329              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6330             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6331                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6332                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6333                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6334                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6335                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6336                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6337                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6338                 }
6339         }
6340
6341         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6342                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6343
6344         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6345                 rdmac_mode |= (1 << 27);
6346
6347         /* Receive/send statistics. */
6348         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6349                 val = tr32(RCVLPC_STATS_ENABLE);
6350                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6351                 tw32(RCVLPC_STATS_ENABLE, val);
6352         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6353                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6354                 val = tr32(RCVLPC_STATS_ENABLE);
6355                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6356                 tw32(RCVLPC_STATS_ENABLE, val);
6357         } else {
6358                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6359         }
6360         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6361         tw32(SNDDATAI_STATSENAB, 0xffffff);
6362         tw32(SNDDATAI_STATSCTRL,
6363              (SNDDATAI_SCTRL_ENABLE |
6364               SNDDATAI_SCTRL_FASTUPD));
6365
6366         /* Setup host coalescing engine. */
6367         tw32(HOSTCC_MODE, 0);
6368         for (i = 0; i < 2000; i++) {
6369                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6370                         break;
6371                 udelay(10);
6372         }
6373
6374         __tg3_set_coalesce(tp, &tp->coal);
6375
6376         /* set status block DMA address */
6377         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6378              ((u64) tp->status_mapping >> 32));
6379         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6380              ((u64) tp->status_mapping & 0xffffffff));
6381
6382         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6383                 /* Status/statistics block address.  See tg3_timer,
6384                  * the tg3_periodic_fetch_stats call there, and
6385                  * tg3_get_stats to see how this works for 5705/5750 chips.
6386                  */
6387                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6388                      ((u64) tp->stats_mapping >> 32));
6389                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6390                      ((u64) tp->stats_mapping & 0xffffffff));
6391                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6392                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6393         }
6394
6395         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6396
6397         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6398         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6399         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6400                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6401
6402         /* Clear statistics/status block in chip, and status block in ram. */
6403         for (i = NIC_SRAM_STATS_BLK;
6404              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6405              i += sizeof(u32)) {
6406                 tg3_write_mem(tp, i, 0);
6407                 udelay(40);
6408         }
6409         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6410
6411         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6412                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6413                 /* reset to prevent losing 1st rx packet intermittently */
6414                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6415                 udelay(10);
6416         }
6417
6418         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6419                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6420         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6421         udelay(40);
6422
6423         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6424          * If TG3_FLG2_IS_NIC is zero, we should read the
6425          * register to preserve the GPIO settings for LOMs. The GPIOs,
6426          * whether used as inputs or outputs, are set by boot code after
6427          * reset.
6428          */
6429         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6430                 u32 gpio_mask;
6431
6432                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6433                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6434                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6435
6436                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6437                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6438                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6439
6440                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6441                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6442
6443                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6444
6445                 /* GPIO1 must be driven high for eeprom write protect */
6446                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6447                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6448                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6449         }
6450         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6451         udelay(100);
6452
6453         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6454         tp->last_tag = 0;
6455
6456         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6457                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6458                 udelay(40);
6459         }
6460
6461         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6462                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6463                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6464                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6465                WDMAC_MODE_LNGREAD_ENAB);
6466
6467         /* If statement applies to 5705 and 5750 PCI devices only */
6468         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6469              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6470             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6471                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6472                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6473                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6474                         /* nothing */
6475                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6476                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6477                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6478                         val |= WDMAC_MODE_RX_ACCEL;
6479                 }
6480         }
6481
6482         /* Enable host coalescing bug fix */
6483         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6484             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6485                 val |= (1 << 29);
6486
6487         tw32_f(WDMAC_MODE, val);
6488         udelay(40);
6489
6490         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6491                 val = tr32(TG3PCI_X_CAPS);
6492                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6493                         val &= ~PCIX_CAPS_BURST_MASK;
6494                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6495                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6496                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6497                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6498                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6499                                 val |= (tp->split_mode_max_reqs <<
6500                                         PCIX_CAPS_SPLIT_SHIFT);
6501                 }
6502                 tw32(TG3PCI_X_CAPS, val);
6503         }
6504
6505         tw32_f(RDMAC_MODE, rdmac_mode);
6506         udelay(40);
6507
6508         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6509         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6510                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6511         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6512         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6513         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6514         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6515         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6516         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6517                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6518         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6519         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6520
6521         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6522                 err = tg3_load_5701_a0_firmware_fix(tp);
6523                 if (err)
6524                         return err;
6525         }
6526
6527         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6528                 err = tg3_load_tso_firmware(tp);
6529                 if (err)
6530                         return err;
6531         }
6532
6533         tp->tx_mode = TX_MODE_ENABLE;
6534         tw32_f(MAC_TX_MODE, tp->tx_mode);
6535         udelay(100);
6536
6537         tp->rx_mode = RX_MODE_ENABLE;
6538         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6539                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6540
6541         tw32_f(MAC_RX_MODE, tp->rx_mode);
6542         udelay(10);
6543
6544         if (tp->link_config.phy_is_low_power) {
6545                 tp->link_config.phy_is_low_power = 0;
6546                 tp->link_config.speed = tp->link_config.orig_speed;
6547                 tp->link_config.duplex = tp->link_config.orig_duplex;
6548                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6549         }
6550
6551         tp->mi_mode = MAC_MI_MODE_BASE;
6552         tw32_f(MAC_MI_MODE, tp->mi_mode);
6553         udelay(80);
6554
6555         tw32(MAC_LED_CTRL, tp->led_ctrl);
6556
6557         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6558         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6559                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6560                 udelay(10);
6561         }
6562         tw32_f(MAC_RX_MODE, tp->rx_mode);
6563         udelay(10);
6564
6565         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6566                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6567                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6568                         /* Set drive transmission level to 1.2V  */
6569                         /* only if the signal pre-emphasis bit is not set  */
6570                         val = tr32(MAC_SERDES_CFG);
6571                         val &= 0xfffff000;
6572                         val |= 0x880;
6573                         tw32(MAC_SERDES_CFG, val);
6574                 }
6575                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6576                         tw32(MAC_SERDES_CFG, 0x616000);
6577         }
6578
6579         /* Prevent chip from dropping frames when flow control
6580          * is enabled.
6581          */
6582         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6583
6584         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6585             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6586                 /* Use hardware link auto-negotiation */
6587                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6588         }
6589
6590         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6591             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6592                 u32 tmp;
6593
6594                 tmp = tr32(SERDES_RX_CTRL);
6595                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6596                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6597                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6598                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6599         }
6600
6601         err = tg3_setup_phy(tp, 0);
6602         if (err)
6603                 return err;
6604
6605         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6606             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6607                 u32 tmp;
6608
6609                 /* Clear CRC stats. */
6610                 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6611                         tg3_writephy(tp, MII_TG3_TEST1,
6612                                      tmp | MII_TG3_TEST1_CRC_EN);
6613                         tg3_readphy(tp, 0x14, &tmp);
6614                 }
6615         }
6616
6617         __tg3_set_rx_mode(tp->dev);
6618
6619         /* Initialize receive rules. */
6620         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6621         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6622         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6623         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6624
6625         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6626             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6627                 limit = 8;
6628         else
6629                 limit = 16;
6630         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6631                 limit -= 4;
6632         switch (limit) {
6633         case 16:
6634                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6635         case 15:
6636                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6637         case 14:
6638                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6639         case 13:
6640                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6641         case 12:
6642                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6643         case 11:
6644                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6645         case 10:
6646                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6647         case 9:
6648                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6649         case 8:
6650                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6651         case 7:
6652                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6653         case 6:
6654                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6655         case 5:
6656                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6657         case 4:
6658                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6659         case 3:
6660                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6661         case 2:
6662         case 1:
6663
6664         default:
6665                 break;
6666         };
6667
6668         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6669
6670         return 0;
6671 }
6672
6673 /* Called at device open time to get the chip ready for
6674  * packet processing.  Invoked with tp->lock held.
6675  */
6676 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6677 {
6678         int err;
6679
6680         /* Force the chip into D0. */
6681         err = tg3_set_power_state(tp, PCI_D0);
6682         if (err)
6683                 goto out;
6684
6685         tg3_switch_clocks(tp);
6686
6687         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6688
6689         err = tg3_reset_hw(tp, reset_phy);
6690
6691 out:
6692         return err;
6693 }
6694
6695 #define TG3_STAT_ADD32(PSTAT, REG) \
6696 do {    u32 __val = tr32(REG); \
6697         (PSTAT)->low += __val; \
6698         if ((PSTAT)->low < __val) \
6699                 (PSTAT)->high += 1; \
6700 } while (0)
6701
6702 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6703 {
6704         struct tg3_hw_stats *sp = tp->hw_stats;
6705
6706         if (!netif_carrier_ok(tp->dev))
6707                 return;
6708
6709         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6710         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6711         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6712         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6713         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6714         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6715         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6716         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6717         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6718         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6719         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6720         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6721         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6722
6723         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6724         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6725         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6726         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6727         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6728         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6729         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6730         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6731         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6732         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6733         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6734         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6735         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6736         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6737
6738         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6739         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6740         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6741 }
6742
6743 static void tg3_timer(unsigned long __opaque)
6744 {
6745         struct tg3 *tp = (struct tg3 *) __opaque;
6746
6747         if (tp->irq_sync)
6748                 goto restart_timer;
6749
6750         spin_lock(&tp->lock);
6751
6752         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6753                 /* All of this garbage is because when using non-tagged
6754                  * IRQ status the mailbox/status_block protocol the chip
6755                  * uses with the cpu is race prone.
6756                  */
6757                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6758                         tw32(GRC_LOCAL_CTRL,
6759                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6760                 } else {
6761                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6762                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6763                 }
6764
6765                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6766                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6767                         spin_unlock(&tp->lock);
6768                         schedule_work(&tp->reset_task);
6769                         return;
6770                 }
6771         }
6772
6773         /* This part only runs once per second. */
6774         if (!--tp->timer_counter) {
6775                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6776                         tg3_periodic_fetch_stats(tp);
6777
6778                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6779                         u32 mac_stat;
6780                         int phy_event;
6781
6782                         mac_stat = tr32(MAC_STATUS);
6783
6784                         phy_event = 0;
6785                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6786                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6787                                         phy_event = 1;
6788                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6789                                 phy_event = 1;
6790
6791                         if (phy_event)
6792                                 tg3_setup_phy(tp, 0);
6793                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6794                         u32 mac_stat = tr32(MAC_STATUS);
6795                         int need_setup = 0;
6796
6797                         if (netif_carrier_ok(tp->dev) &&
6798                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6799                                 need_setup = 1;
6800                         }
6801                         if (! netif_carrier_ok(tp->dev) &&
6802                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6803                                          MAC_STATUS_SIGNAL_DET))) {
6804                                 need_setup = 1;
6805                         }
6806                         if (need_setup) {
6807                                 if (!tp->serdes_counter) {
6808                                         tw32_f(MAC_MODE,
6809                                              (tp->mac_mode &
6810                                               ~MAC_MODE_PORT_MODE_MASK));
6811                                         udelay(40);
6812                                         tw32_f(MAC_MODE, tp->mac_mode);
6813                                         udelay(40);
6814                                 }
6815                                 tg3_setup_phy(tp, 0);
6816                         }
6817                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6818                         tg3_serdes_parallel_detect(tp);
6819
6820                 tp->timer_counter = tp->timer_multiplier;
6821         }
6822
6823         /* Heartbeat is only sent once every 2 seconds.
6824          *
6825          * The heartbeat is to tell the ASF firmware that the host
6826          * driver is still alive.  In the event that the OS crashes,
6827          * ASF needs to reset the hardware to free up the FIFO space
6828          * that may be filled with rx packets destined for the host.
6829          * If the FIFO is full, ASF will no longer function properly.
6830          *
6831          * Unintended resets have been reported on real time kernels
6832          * where the timer doesn't run on time.  Netpoll will also have
6833          * same problem.
6834          *
6835          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6836          * to check the ring condition when the heartbeat is expiring
6837          * before doing the reset.  This will prevent most unintended
6838          * resets.
6839          */
6840         if (!--tp->asf_counter) {
6841                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6842                         u32 val;
6843
6844                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6845                                       FWCMD_NICDRV_ALIVE3);
6846                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6847                         /* 5 seconds timeout */
6848                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6849                         val = tr32(GRC_RX_CPU_EVENT);
6850                         val |= (1 << 14);
6851                         tw32(GRC_RX_CPU_EVENT, val);
6852                 }
6853                 tp->asf_counter = tp->asf_multiplier;
6854         }
6855
6856         spin_unlock(&tp->lock);
6857
6858 restart_timer:
6859         tp->timer.expires = jiffies + tp->timer_offset;
6860         add_timer(&tp->timer);
6861 }
6862
6863 static int tg3_request_irq(struct tg3 *tp)
6864 {
6865         irq_handler_t fn;
6866         unsigned long flags;
6867         struct net_device *dev = tp->dev;
6868
6869         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6870                 fn = tg3_msi;
6871                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6872                         fn = tg3_msi_1shot;
6873                 flags = IRQF_SAMPLE_RANDOM;
6874         } else {
6875                 fn = tg3_interrupt;
6876                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6877                         fn = tg3_interrupt_tagged;
6878                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6879         }
6880         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6881 }
6882
6883 static int tg3_test_interrupt(struct tg3 *tp)
6884 {
6885         struct net_device *dev = tp->dev;
6886         int err, i, intr_ok = 0;
6887
6888         if (!netif_running(dev))
6889                 return -ENODEV;
6890
6891         tg3_disable_ints(tp);
6892
6893         free_irq(tp->pdev->irq, dev);
6894
6895         err = request_irq(tp->pdev->irq, tg3_test_isr,
6896                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6897         if (err)
6898                 return err;
6899
6900         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6901         tg3_enable_ints(tp);
6902
6903         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6904                HOSTCC_MODE_NOW);
6905
6906         for (i = 0; i < 5; i++) {
6907                 u32 int_mbox, misc_host_ctrl;
6908
6909                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6910                                         TG3_64BIT_REG_LOW);
6911                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6912
6913                 if ((int_mbox != 0) ||
6914                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6915                         intr_ok = 1;
6916                         break;
6917                 }
6918
6919                 msleep(10);
6920         }
6921
6922         tg3_disable_ints(tp);
6923
6924         free_irq(tp->pdev->irq, dev);
6925
6926         err = tg3_request_irq(tp);
6927
6928         if (err)
6929                 return err;
6930
6931         if (intr_ok)
6932                 return 0;
6933
6934         return -EIO;
6935 }
6936
6937 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6938  * successfully restored
6939  */
6940 static int tg3_test_msi(struct tg3 *tp)
6941 {
6942         struct net_device *dev = tp->dev;
6943         int err;
6944         u16 pci_cmd;
6945
6946         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6947                 return 0;
6948
6949         /* Turn off SERR reporting in case MSI terminates with Master
6950          * Abort.
6951          */
6952         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6953         pci_write_config_word(tp->pdev, PCI_COMMAND,
6954                               pci_cmd & ~PCI_COMMAND_SERR);
6955
6956         err = tg3_test_interrupt(tp);
6957
6958         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6959
6960         if (!err)
6961                 return 0;
6962
6963         /* other failures */
6964         if (err != -EIO)
6965                 return err;
6966
6967         /* MSI test failed, go back to INTx mode */
6968         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6969                "switching to INTx mode. Please report this failure to "
6970                "the PCI maintainer and include system chipset information.\n",
6971                        tp->dev->name);
6972
6973         free_irq(tp->pdev->irq, dev);
6974         pci_disable_msi(tp->pdev);
6975
6976         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6977
6978         err = tg3_request_irq(tp);
6979         if (err)
6980                 return err;
6981
6982         /* Need to reset the chip because the MSI cycle may have terminated
6983          * with Master Abort.
6984          */
6985         tg3_full_lock(tp, 1);
6986
6987         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6988         err = tg3_init_hw(tp, 1);
6989
6990         tg3_full_unlock(tp);
6991
6992         if (err)
6993                 free_irq(tp->pdev->irq, dev);
6994
6995         return err;
6996 }
6997
6998 static int tg3_open(struct net_device *dev)
6999 {
7000         struct tg3 *tp = netdev_priv(dev);
7001         int err;
7002
7003         netif_carrier_off(tp->dev);
7004
7005         tg3_full_lock(tp, 0);
7006
7007         err = tg3_set_power_state(tp, PCI_D0);
7008         if (err) {
7009                 tg3_full_unlock(tp);
7010                 return err;
7011         }
7012
7013         tg3_disable_ints(tp);
7014         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7015
7016         tg3_full_unlock(tp);
7017
7018         /* The placement of this call is tied
7019          * to the setup and use of Host TX descriptors.
7020          */
7021         err = tg3_alloc_consistent(tp);
7022         if (err)
7023                 return err;
7024
7025         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7026             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
7027             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7028             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7029               (tp->pdev_peer == tp->pdev))) {
7030                 /* All MSI supporting chips should support tagged
7031                  * status.  Assert that this is the case.
7032                  */
7033                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7034                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7035                                "Not using MSI.\n", tp->dev->name);
7036                 } else if (pci_enable_msi(tp->pdev) == 0) {
7037                         u32 msi_mode;
7038
7039                         msi_mode = tr32(MSGINT_MODE);
7040                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7041                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7042                 }
7043         }
7044         err = tg3_request_irq(tp);
7045
7046         if (err) {
7047                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7048                         pci_disable_msi(tp->pdev);
7049                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7050                 }
7051                 tg3_free_consistent(tp);
7052                 return err;
7053         }
7054
7055         tg3_full_lock(tp, 0);
7056
7057         err = tg3_init_hw(tp, 1);
7058         if (err) {
7059                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7060                 tg3_free_rings(tp);
7061         } else {
7062                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7063                         tp->timer_offset = HZ;
7064                 else
7065                         tp->timer_offset = HZ / 10;
7066
7067                 BUG_ON(tp->timer_offset > HZ);
7068                 tp->timer_counter = tp->timer_multiplier =
7069                         (HZ / tp->timer_offset);
7070                 tp->asf_counter = tp->asf_multiplier =
7071                         ((HZ / tp->timer_offset) * 2);
7072
7073                 init_timer(&tp->timer);
7074                 tp->timer.expires = jiffies + tp->timer_offset;
7075                 tp->timer.data = (unsigned long) tp;
7076                 tp->timer.function = tg3_timer;
7077         }
7078
7079         tg3_full_unlock(tp);
7080
7081         if (err) {
7082                 free_irq(tp->pdev->irq, dev);
7083                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7084                         pci_disable_msi(tp->pdev);
7085                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7086                 }
7087                 tg3_free_consistent(tp);
7088                 return err;
7089         }
7090
7091         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7092                 err = tg3_test_msi(tp);
7093
7094                 if (err) {
7095                         tg3_full_lock(tp, 0);
7096
7097                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7098                                 pci_disable_msi(tp->pdev);
7099                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7100                         }
7101                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7102                         tg3_free_rings(tp);
7103                         tg3_free_consistent(tp);
7104
7105                         tg3_full_unlock(tp);
7106
7107                         return err;
7108                 }
7109
7110                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7111                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7112                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7113
7114                                 tw32(PCIE_TRANSACTION_CFG,
7115                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7116                         }
7117                 }
7118         }
7119
7120         tg3_full_lock(tp, 0);
7121
7122         add_timer(&tp->timer);
7123         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7124         tg3_enable_ints(tp);
7125
7126         tg3_full_unlock(tp);
7127
7128         netif_start_queue(dev);
7129
7130         return 0;
7131 }
7132
7133 #if 0
7134 /*static*/ void tg3_dump_state(struct tg3 *tp)
7135 {
7136         u32 val32, val32_2, val32_3, val32_4, val32_5;
7137         u16 val16;
7138         int i;
7139
7140         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7141         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7142         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7143                val16, val32);
7144
7145         /* MAC block */
7146         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7147                tr32(MAC_MODE), tr32(MAC_STATUS));
7148         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7149                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7150         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7151                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7152         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7153                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7154
7155         /* Send data initiator control block */
7156         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7157                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7158         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7159                tr32(SNDDATAI_STATSCTRL));
7160
7161         /* Send data completion control block */
7162         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7163
7164         /* Send BD ring selector block */
7165         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7166                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7167
7168         /* Send BD initiator control block */
7169         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7170                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7171
7172         /* Send BD completion control block */
7173         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7174
7175         /* Receive list placement control block */
7176         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7177                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7178         printk("       RCVLPC_STATSCTRL[%08x]\n",
7179                tr32(RCVLPC_STATSCTRL));
7180
7181         /* Receive data and receive BD initiator control block */
7182         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7183                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7184
7185         /* Receive data completion control block */
7186         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7187                tr32(RCVDCC_MODE));
7188
7189         /* Receive BD initiator control block */
7190         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7191                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7192
7193         /* Receive BD completion control block */
7194         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7195                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7196
7197         /* Receive list selector control block */
7198         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7199                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7200
7201         /* Mbuf cluster free block */
7202         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7203                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7204
7205         /* Host coalescing control block */
7206         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7207                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7208         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7209                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7210                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7211         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7212                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7213                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7214         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7215                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7216         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7217                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7218
7219         /* Memory arbiter control block */
7220         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7221                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7222
7223         /* Buffer manager control block */
7224         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7225                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7226         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7227                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7228         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7229                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7230                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7231                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7232
7233         /* Read DMA control block */
7234         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7235                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7236
7237         /* Write DMA control block */
7238         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7239                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7240
7241         /* DMA completion block */
7242         printk("DEBUG: DMAC_MODE[%08x]\n",
7243                tr32(DMAC_MODE));
7244
7245         /* GRC block */
7246         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7247                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7248         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7249                tr32(GRC_LOCAL_CTRL));
7250
7251         /* TG3_BDINFOs */
7252         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7253                tr32(RCVDBDI_JUMBO_BD + 0x0),
7254                tr32(RCVDBDI_JUMBO_BD + 0x4),
7255                tr32(RCVDBDI_JUMBO_BD + 0x8),
7256                tr32(RCVDBDI_JUMBO_BD + 0xc));
7257         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7258                tr32(RCVDBDI_STD_BD + 0x0),
7259                tr32(RCVDBDI_STD_BD + 0x4),
7260                tr32(RCVDBDI_STD_BD + 0x8),
7261                tr32(RCVDBDI_STD_BD + 0xc));
7262         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7263                tr32(RCVDBDI_MINI_BD + 0x0),
7264                tr32(RCVDBDI_MINI_BD + 0x4),
7265                tr32(RCVDBDI_MINI_BD + 0x8),
7266                tr32(RCVDBDI_MINI_BD + 0xc));
7267
7268         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7269         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7270         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7271         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7272         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7273                val32, val32_2, val32_3, val32_4);
7274
7275         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7276         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7277         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7278         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7279         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7280                val32, val32_2, val32_3, val32_4);
7281
7282         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7283         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7284         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7285         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7286         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7287         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7288                val32, val32_2, val32_3, val32_4, val32_5);
7289
7290         /* SW status block */
7291         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7292                tp->hw_status->status,
7293                tp->hw_status->status_tag,
7294                tp->hw_status->rx_jumbo_consumer,
7295                tp->hw_status->rx_consumer,
7296                tp->hw_status->rx_mini_consumer,
7297                tp->hw_status->idx[0].rx_producer,
7298                tp->hw_status->idx[0].tx_consumer);
7299
7300         /* SW statistics block */
7301         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7302                ((u32 *)tp->hw_stats)[0],
7303                ((u32 *)tp->hw_stats)[1],
7304                ((u32 *)tp->hw_stats)[2],
7305                ((u32 *)tp->hw_stats)[3]);
7306
7307         /* Mailboxes */
7308         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7309                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7310                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7311                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7312                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7313
7314         /* NIC side send descriptors. */
7315         for (i = 0; i < 6; i++) {
7316                 unsigned long txd;
7317
7318                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7319                         + (i * sizeof(struct tg3_tx_buffer_desc));
7320                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7321                        i,
7322                        readl(txd + 0x0), readl(txd + 0x4),
7323                        readl(txd + 0x8), readl(txd + 0xc));
7324         }
7325
7326         /* NIC side RX descriptors. */
7327         for (i = 0; i < 6; i++) {
7328                 unsigned long rxd;
7329
7330                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7331                         + (i * sizeof(struct tg3_rx_buffer_desc));
7332                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7333                        i,
7334                        readl(rxd + 0x0), readl(rxd + 0x4),
7335                        readl(rxd + 0x8), readl(rxd + 0xc));
7336                 rxd += (4 * sizeof(u32));
7337                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7338                        i,
7339                        readl(rxd + 0x0), readl(rxd + 0x4),
7340                        readl(rxd + 0x8), readl(rxd + 0xc));
7341         }
7342
7343         for (i = 0; i < 6; i++) {
7344                 unsigned long rxd;
7345
7346                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7347                         + (i * sizeof(struct tg3_rx_buffer_desc));
7348                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7349                        i,
7350                        readl(rxd + 0x0), readl(rxd + 0x4),
7351                        readl(rxd + 0x8), readl(rxd + 0xc));
7352                 rxd += (4 * sizeof(u32));
7353                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7354                        i,
7355                        readl(rxd + 0x0), readl(rxd + 0x4),
7356                        readl(rxd + 0x8), readl(rxd + 0xc));
7357         }
7358 }
7359 #endif
7360
7361 static struct net_device_stats *tg3_get_stats(struct net_device *);
7362 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7363
7364 static int tg3_close(struct net_device *dev)
7365 {
7366         struct tg3 *tp = netdev_priv(dev);
7367
7368         /* Calling flush_scheduled_work() may deadlock because
7369          * linkwatch_event() may be on the workqueue and it will try to get
7370          * the rtnl_lock which we are holding.
7371          */
7372         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7373                 msleep(1);
7374
7375         netif_stop_queue(dev);
7376
7377         del_timer_sync(&tp->timer);
7378
7379         tg3_full_lock(tp, 1);
7380 #if 0
7381         tg3_dump_state(tp);
7382 #endif
7383
7384         tg3_disable_ints(tp);
7385
7386         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7387         tg3_free_rings(tp);
7388         tp->tg3_flags &=
7389                 ~(TG3_FLAG_INIT_COMPLETE |
7390                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7391
7392         tg3_full_unlock(tp);
7393
7394         free_irq(tp->pdev->irq, dev);
7395         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7396                 pci_disable_msi(tp->pdev);
7397                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7398         }
7399
7400         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7401                sizeof(tp->net_stats_prev));
7402         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7403                sizeof(tp->estats_prev));
7404
7405         tg3_free_consistent(tp);
7406
7407         tg3_set_power_state(tp, PCI_D3hot);
7408
7409         netif_carrier_off(tp->dev);
7410
7411         return 0;
7412 }
7413
7414 static inline unsigned long get_stat64(tg3_stat64_t *val)
7415 {
7416         unsigned long ret;
7417
7418 #if (BITS_PER_LONG == 32)
7419         ret = val->low;
7420 #else
7421         ret = ((u64)val->high << 32) | ((u64)val->low);
7422 #endif
7423         return ret;
7424 }
7425
7426 static unsigned long calc_crc_errors(struct tg3 *tp)
7427 {
7428         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7429
7430         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7431             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7432              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7433                 u32 val;
7434
7435                 spin_lock_bh(&tp->lock);
7436                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7437                         tg3_writephy(tp, MII_TG3_TEST1,
7438                                      val | MII_TG3_TEST1_CRC_EN);
7439                         tg3_readphy(tp, 0x14, &val);
7440                 } else
7441                         val = 0;
7442                 spin_unlock_bh(&tp->lock);
7443
7444                 tp->phy_crc_errors += val;
7445
7446                 return tp->phy_crc_errors;
7447         }
7448
7449         return get_stat64(&hw_stats->rx_fcs_errors);
7450 }
7451
7452 #define ESTAT_ADD(member) \
7453         estats->member =        old_estats->member + \
7454                                 get_stat64(&hw_stats->member)
7455
7456 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7457 {
7458         struct tg3_ethtool_stats *estats = &tp->estats;
7459         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7460         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7461
7462         if (!hw_stats)
7463                 return old_estats;
7464
7465         ESTAT_ADD(rx_octets);
7466         ESTAT_ADD(rx_fragments);
7467         ESTAT_ADD(rx_ucast_packets);
7468         ESTAT_ADD(rx_mcast_packets);
7469         ESTAT_ADD(rx_bcast_packets);
7470         ESTAT_ADD(rx_fcs_errors);
7471         ESTAT_ADD(rx_align_errors);
7472         ESTAT_ADD(rx_xon_pause_rcvd);
7473         ESTAT_ADD(rx_xoff_pause_rcvd);
7474         ESTAT_ADD(rx_mac_ctrl_rcvd);
7475         ESTAT_ADD(rx_xoff_entered);
7476         ESTAT_ADD(rx_frame_too_long_errors);
7477         ESTAT_ADD(rx_jabbers);
7478         ESTAT_ADD(rx_undersize_packets);
7479         ESTAT_ADD(rx_in_length_errors);
7480         ESTAT_ADD(rx_out_length_errors);
7481         ESTAT_ADD(rx_64_or_less_octet_packets);
7482         ESTAT_ADD(rx_65_to_127_octet_packets);
7483         ESTAT_ADD(rx_128_to_255_octet_packets);
7484         ESTAT_ADD(rx_256_to_511_octet_packets);
7485         ESTAT_ADD(rx_512_to_1023_octet_packets);
7486         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7487         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7488         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7489         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7490         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7491
7492         ESTAT_ADD(tx_octets);
7493         ESTAT_ADD(tx_collisions);
7494         ESTAT_ADD(tx_xon_sent);
7495         ESTAT_ADD(tx_xoff_sent);
7496         ESTAT_ADD(tx_flow_control);
7497         ESTAT_ADD(tx_mac_errors);
7498         ESTAT_ADD(tx_single_collisions);
7499         ESTAT_ADD(tx_mult_collisions);
7500         ESTAT_ADD(tx_deferred);
7501         ESTAT_ADD(tx_excessive_collisions);
7502         ESTAT_ADD(tx_late_collisions);
7503         ESTAT_ADD(tx_collide_2times);
7504         ESTAT_ADD(tx_collide_3times);
7505         ESTAT_ADD(tx_collide_4times);
7506         ESTAT_ADD(tx_collide_5times);
7507         ESTAT_ADD(tx_collide_6times);
7508         ESTAT_ADD(tx_collide_7times);
7509         ESTAT_ADD(tx_collide_8times);
7510         ESTAT_ADD(tx_collide_9times);
7511         ESTAT_ADD(tx_collide_10times);
7512         ESTAT_ADD(tx_collide_11times);
7513         ESTAT_ADD(tx_collide_12times);
7514         ESTAT_ADD(tx_collide_13times);
7515         ESTAT_ADD(tx_collide_14times);
7516         ESTAT_ADD(tx_collide_15times);
7517         ESTAT_ADD(tx_ucast_packets);
7518         ESTAT_ADD(tx_mcast_packets);
7519         ESTAT_ADD(tx_bcast_packets);
7520         ESTAT_ADD(tx_carrier_sense_errors);
7521         ESTAT_ADD(tx_discards);
7522         ESTAT_ADD(tx_errors);
7523
7524         ESTAT_ADD(dma_writeq_full);
7525         ESTAT_ADD(dma_write_prioq_full);
7526         ESTAT_ADD(rxbds_empty);
7527         ESTAT_ADD(rx_discards);
7528         ESTAT_ADD(rx_errors);
7529         ESTAT_ADD(rx_threshold_hit);
7530
7531         ESTAT_ADD(dma_readq_full);
7532         ESTAT_ADD(dma_read_prioq_full);
7533         ESTAT_ADD(tx_comp_queue_full);
7534
7535         ESTAT_ADD(ring_set_send_prod_index);
7536         ESTAT_ADD(ring_status_update);
7537         ESTAT_ADD(nic_irqs);
7538         ESTAT_ADD(nic_avoided_irqs);
7539         ESTAT_ADD(nic_tx_threshold_hit);
7540
7541         return estats;
7542 }
7543
7544 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7545 {
7546         struct tg3 *tp = netdev_priv(dev);
7547         struct net_device_stats *stats = &tp->net_stats;
7548         struct net_device_stats *old_stats = &tp->net_stats_prev;
7549         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7550
7551         if (!hw_stats)
7552                 return old_stats;
7553
7554         stats->rx_packets = old_stats->rx_packets +
7555                 get_stat64(&hw_stats->rx_ucast_packets) +
7556                 get_stat64(&hw_stats->rx_mcast_packets) +
7557                 get_stat64(&hw_stats->rx_bcast_packets);
7558
7559         stats->tx_packets = old_stats->tx_packets +
7560                 get_stat64(&hw_stats->tx_ucast_packets) +
7561                 get_stat64(&hw_stats->tx_mcast_packets) +
7562                 get_stat64(&hw_stats->tx_bcast_packets);
7563
7564         stats->rx_bytes = old_stats->rx_bytes +
7565                 get_stat64(&hw_stats->rx_octets);
7566         stats->tx_bytes = old_stats->tx_bytes +
7567                 get_stat64(&hw_stats->tx_octets);
7568
7569         stats->rx_errors = old_stats->rx_errors +
7570                 get_stat64(&hw_stats->rx_errors);
7571         stats->tx_errors = old_stats->tx_errors +
7572                 get_stat64(&hw_stats->tx_errors) +
7573                 get_stat64(&hw_stats->tx_mac_errors) +
7574                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7575                 get_stat64(&hw_stats->tx_discards);
7576
7577         stats->multicast = old_stats->multicast +
7578                 get_stat64(&hw_stats->rx_mcast_packets);
7579         stats->collisions = old_stats->collisions +
7580                 get_stat64(&hw_stats->tx_collisions);
7581
7582         stats->rx_length_errors = old_stats->rx_length_errors +
7583                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7584                 get_stat64(&hw_stats->rx_undersize_packets);
7585
7586         stats->rx_over_errors = old_stats->rx_over_errors +
7587                 get_stat64(&hw_stats->rxbds_empty);
7588         stats->rx_frame_errors = old_stats->rx_frame_errors +
7589                 get_stat64(&hw_stats->rx_align_errors);
7590         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7591                 get_stat64(&hw_stats->tx_discards);
7592         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7593                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7594
7595         stats->rx_crc_errors = old_stats->rx_crc_errors +
7596                 calc_crc_errors(tp);
7597
7598         stats->rx_missed_errors = old_stats->rx_missed_errors +
7599                 get_stat64(&hw_stats->rx_discards);
7600
7601         return stats;
7602 }
7603
7604 static inline u32 calc_crc(unsigned char *buf, int len)
7605 {
7606         u32 reg;
7607         u32 tmp;
7608         int j, k;
7609
7610         reg = 0xffffffff;
7611
7612         for (j = 0; j < len; j++) {
7613                 reg ^= buf[j];
7614
7615                 for (k = 0; k < 8; k++) {
7616                         tmp = reg & 0x01;
7617
7618                         reg >>= 1;
7619
7620                         if (tmp) {
7621                                 reg ^= 0xedb88320;
7622                         }
7623                 }
7624         }
7625
7626         return ~reg;
7627 }
7628
7629 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7630 {
7631         /* accept or reject all multicast frames */
7632         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7633         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7634         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7635         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7636 }
7637
7638 static void __tg3_set_rx_mode(struct net_device *dev)
7639 {
7640         struct tg3 *tp = netdev_priv(dev);
7641         u32 rx_mode;
7642
7643         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7644                                   RX_MODE_KEEP_VLAN_TAG);
7645
7646         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7647          * flag clear.
7648          */
7649 #if TG3_VLAN_TAG_USED
7650         if (!tp->vlgrp &&
7651             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7652                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7653 #else
7654         /* By definition, VLAN is disabled always in this
7655          * case.
7656          */
7657         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7658                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7659 #endif
7660
7661         if (dev->flags & IFF_PROMISC) {
7662                 /* Promiscuous mode. */
7663                 rx_mode |= RX_MODE_PROMISC;
7664         } else if (dev->flags & IFF_ALLMULTI) {
7665                 /* Accept all multicast. */
7666                 tg3_set_multi (tp, 1);
7667         } else if (dev->mc_count < 1) {
7668                 /* Reject all multicast. */
7669                 tg3_set_multi (tp, 0);
7670         } else {
7671                 /* Accept one or more multicast(s). */
7672                 struct dev_mc_list *mclist;
7673                 unsigned int i;
7674                 u32 mc_filter[4] = { 0, };
7675                 u32 regidx;
7676                 u32 bit;
7677                 u32 crc;
7678
7679                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7680                      i++, mclist = mclist->next) {
7681
7682                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7683                         bit = ~crc & 0x7f;
7684                         regidx = (bit & 0x60) >> 5;
7685                         bit &= 0x1f;
7686                         mc_filter[regidx] |= (1 << bit);
7687                 }
7688
7689                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7690                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7691                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7692                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7693         }
7694
7695         if (rx_mode != tp->rx_mode) {
7696                 tp->rx_mode = rx_mode;
7697                 tw32_f(MAC_RX_MODE, rx_mode);
7698                 udelay(10);
7699         }
7700 }
7701
7702 static void tg3_set_rx_mode(struct net_device *dev)
7703 {
7704         struct tg3 *tp = netdev_priv(dev);
7705
7706         if (!netif_running(dev))
7707                 return;
7708
7709         tg3_full_lock(tp, 0);
7710         __tg3_set_rx_mode(dev);
7711         tg3_full_unlock(tp);
7712 }
7713
7714 #define TG3_REGDUMP_LEN         (32 * 1024)
7715
7716 static int tg3_get_regs_len(struct net_device *dev)
7717 {
7718         return TG3_REGDUMP_LEN;
7719 }
7720
7721 static void tg3_get_regs(struct net_device *dev,
7722                 struct ethtool_regs *regs, void *_p)
7723 {
7724         u32 *p = _p;
7725         struct tg3 *tp = netdev_priv(dev);
7726         u8 *orig_p = _p;
7727         int i;
7728
7729         regs->version = 0;
7730
7731         memset(p, 0, TG3_REGDUMP_LEN);
7732
7733         if (tp->link_config.phy_is_low_power)
7734                 return;
7735
7736         tg3_full_lock(tp, 0);
7737
7738 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7739 #define GET_REG32_LOOP(base,len)                \
7740 do {    p = (u32 *)(orig_p + (base));           \
7741         for (i = 0; i < len; i += 4)            \
7742                 __GET_REG32((base) + i);        \
7743 } while (0)
7744 #define GET_REG32_1(reg)                        \
7745 do {    p = (u32 *)(orig_p + (reg));            \
7746         __GET_REG32((reg));                     \
7747 } while (0)
7748
7749         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7750         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7751         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7752         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7753         GET_REG32_1(SNDDATAC_MODE);
7754         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7755         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7756         GET_REG32_1(SNDBDC_MODE);
7757         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7758         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7759         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7760         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7761         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7762         GET_REG32_1(RCVDCC_MODE);
7763         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7764         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7765         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7766         GET_REG32_1(MBFREE_MODE);
7767         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7768         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7769         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7770         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7771         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7772         GET_REG32_1(RX_CPU_MODE);
7773         GET_REG32_1(RX_CPU_STATE);
7774         GET_REG32_1(RX_CPU_PGMCTR);
7775         GET_REG32_1(RX_CPU_HWBKPT);
7776         GET_REG32_1(TX_CPU_MODE);
7777         GET_REG32_1(TX_CPU_STATE);
7778         GET_REG32_1(TX_CPU_PGMCTR);
7779         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7780         GET_REG32_LOOP(FTQ_RESET, 0x120);
7781         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7782         GET_REG32_1(DMAC_MODE);
7783         GET_REG32_LOOP(GRC_MODE, 0x4c);
7784         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7785                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7786
7787 #undef __GET_REG32
7788 #undef GET_REG32_LOOP
7789 #undef GET_REG32_1
7790
7791         tg3_full_unlock(tp);
7792 }
7793
7794 static int tg3_get_eeprom_len(struct net_device *dev)
7795 {
7796         struct tg3 *tp = netdev_priv(dev);
7797
7798         return tp->nvram_size;
7799 }
7800
7801 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7802 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7803
7804 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7805 {
7806         struct tg3 *tp = netdev_priv(dev);
7807         int ret;
7808         u8  *pd;
7809         u32 i, offset, len, val, b_offset, b_count;
7810
7811         if (tp->link_config.phy_is_low_power)
7812                 return -EAGAIN;
7813
7814         offset = eeprom->offset;
7815         len = eeprom->len;
7816         eeprom->len = 0;
7817
7818         eeprom->magic = TG3_EEPROM_MAGIC;
7819
7820         if (offset & 3) {
7821                 /* adjustments to start on required 4 byte boundary */
7822                 b_offset = offset & 3;
7823                 b_count = 4 - b_offset;
7824                 if (b_count > len) {
7825                         /* i.e. offset=1 len=2 */
7826                         b_count = len;
7827                 }
7828                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7829                 if (ret)
7830                         return ret;
7831                 val = cpu_to_le32(val);
7832                 memcpy(data, ((char*)&val) + b_offset, b_count);
7833                 len -= b_count;
7834                 offset += b_count;
7835                 eeprom->len += b_count;
7836         }
7837
7838         /* read bytes upto the last 4 byte boundary */
7839         pd = &data[eeprom->len];
7840         for (i = 0; i < (len - (len & 3)); i += 4) {
7841                 ret = tg3_nvram_read(tp, offset + i, &val);
7842                 if (ret) {
7843                         eeprom->len += i;
7844                         return ret;
7845                 }
7846                 val = cpu_to_le32(val);
7847                 memcpy(pd + i, &val, 4);
7848         }
7849         eeprom->len += i;
7850
7851         if (len & 3) {
7852                 /* read last bytes not ending on 4 byte boundary */
7853                 pd = &data[eeprom->len];
7854                 b_count = len & 3;
7855                 b_offset = offset + len - b_count;
7856                 ret = tg3_nvram_read(tp, b_offset, &val);
7857                 if (ret)
7858                         return ret;
7859                 val = cpu_to_le32(val);
7860                 memcpy(pd, ((char*)&val), b_count);
7861                 eeprom->len += b_count;
7862         }
7863         return 0;
7864 }
7865
7866 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7867
7868 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7869 {
7870         struct tg3 *tp = netdev_priv(dev);
7871         int ret;
7872         u32 offset, len, b_offset, odd_len, start, end;
7873         u8 *buf;
7874
7875         if (tp->link_config.phy_is_low_power)
7876                 return -EAGAIN;
7877
7878         if (eeprom->magic != TG3_EEPROM_MAGIC)
7879                 return -EINVAL;
7880
7881         offset = eeprom->offset;
7882         len = eeprom->len;
7883
7884         if ((b_offset = (offset & 3))) {
7885                 /* adjustments to start on required 4 byte boundary */
7886                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7887                 if (ret)
7888                         return ret;
7889                 start = cpu_to_le32(start);
7890                 len += b_offset;
7891                 offset &= ~3;
7892                 if (len < 4)
7893                         len = 4;
7894         }
7895
7896         odd_len = 0;
7897         if (len & 3) {
7898                 /* adjustments to end on required 4 byte boundary */
7899                 odd_len = 1;
7900                 len = (len + 3) & ~3;
7901                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7902                 if (ret)
7903                         return ret;
7904                 end = cpu_to_le32(end);
7905         }
7906
7907         buf = data;
7908         if (b_offset || odd_len) {
7909                 buf = kmalloc(len, GFP_KERNEL);
7910                 if (buf == 0)
7911                         return -ENOMEM;
7912                 if (b_offset)
7913                         memcpy(buf, &start, 4);
7914                 if (odd_len)
7915                         memcpy(buf+len-4, &end, 4);
7916                 memcpy(buf + b_offset, data, eeprom->len);
7917         }
7918
7919         ret = tg3_nvram_write_block(tp, offset, len, buf);
7920
7921         if (buf != data)
7922                 kfree(buf);
7923
7924         return ret;
7925 }
7926
7927 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7928 {
7929         struct tg3 *tp = netdev_priv(dev);
7930
7931         cmd->supported = (SUPPORTED_Autoneg);
7932
7933         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7934                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7935                                    SUPPORTED_1000baseT_Full);
7936
7937         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7938                 cmd->supported |= (SUPPORTED_100baseT_Half |
7939                                   SUPPORTED_100baseT_Full |
7940                                   SUPPORTED_10baseT_Half |
7941                                   SUPPORTED_10baseT_Full |
7942                                   SUPPORTED_MII);
7943                 cmd->port = PORT_TP;
7944         } else {
7945                 cmd->supported |= SUPPORTED_FIBRE;
7946                 cmd->port = PORT_FIBRE;
7947         }
7948
7949         cmd->advertising = tp->link_config.advertising;
7950         if (netif_running(dev)) {
7951                 cmd->speed = tp->link_config.active_speed;
7952                 cmd->duplex = tp->link_config.active_duplex;
7953         }
7954         cmd->phy_address = PHY_ADDR;
7955         cmd->transceiver = 0;
7956         cmd->autoneg = tp->link_config.autoneg;
7957         cmd->maxtxpkt = 0;
7958         cmd->maxrxpkt = 0;
7959         return 0;
7960 }
7961
7962 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7963 {
7964         struct tg3 *tp = netdev_priv(dev);
7965
7966         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7967                 /* These are the only valid advertisement bits allowed.  */
7968                 if (cmd->autoneg == AUTONEG_ENABLE &&
7969                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7970                                           ADVERTISED_1000baseT_Full |
7971                                           ADVERTISED_Autoneg |
7972                                           ADVERTISED_FIBRE)))
7973                         return -EINVAL;
7974                 /* Fiber can only do SPEED_1000.  */
7975                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7976                          (cmd->speed != SPEED_1000))
7977                         return -EINVAL;
7978         /* Copper cannot force SPEED_1000.  */
7979         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7980                    (cmd->speed == SPEED_1000))
7981                 return -EINVAL;
7982         else if ((cmd->speed == SPEED_1000) &&
7983                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7984                 return -EINVAL;
7985
7986         tg3_full_lock(tp, 0);
7987
7988         tp->link_config.autoneg = cmd->autoneg;
7989         if (cmd->autoneg == AUTONEG_ENABLE) {
7990                 tp->link_config.advertising = cmd->advertising;
7991                 tp->link_config.speed = SPEED_INVALID;
7992                 tp->link_config.duplex = DUPLEX_INVALID;
7993         } else {
7994                 tp->link_config.advertising = 0;
7995                 tp->link_config.speed = cmd->speed;
7996                 tp->link_config.duplex = cmd->duplex;
7997         }
7998
7999         tp->link_config.orig_speed = tp->link_config.speed;
8000         tp->link_config.orig_duplex = tp->link_config.duplex;
8001         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8002
8003         if (netif_running(dev))
8004                 tg3_setup_phy(tp, 1);
8005
8006         tg3_full_unlock(tp);
8007
8008         return 0;
8009 }
8010
8011 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8012 {
8013         struct tg3 *tp = netdev_priv(dev);
8014
8015         strcpy(info->driver, DRV_MODULE_NAME);
8016         strcpy(info->version, DRV_MODULE_VERSION);
8017         strcpy(info->fw_version, tp->fw_ver);
8018         strcpy(info->bus_info, pci_name(tp->pdev));
8019 }
8020
8021 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8022 {
8023         struct tg3 *tp = netdev_priv(dev);
8024
8025         wol->supported = WAKE_MAGIC;
8026         wol->wolopts = 0;
8027         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8028                 wol->wolopts = WAKE_MAGIC;
8029         memset(&wol->sopass, 0, sizeof(wol->sopass));
8030 }
8031
8032 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8033 {
8034         struct tg3 *tp = netdev_priv(dev);
8035
8036         if (wol->wolopts & ~WAKE_MAGIC)
8037                 return -EINVAL;
8038         if ((wol->wolopts & WAKE_MAGIC) &&
8039             tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
8040             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8041                 return -EINVAL;
8042
8043         spin_lock_bh(&tp->lock);
8044         if (wol->wolopts & WAKE_MAGIC)
8045                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8046         else
8047                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8048         spin_unlock_bh(&tp->lock);
8049
8050         return 0;
8051 }
8052
8053 static u32 tg3_get_msglevel(struct net_device *dev)
8054 {
8055         struct tg3 *tp = netdev_priv(dev);
8056         return tp->msg_enable;
8057 }
8058
8059 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8060 {
8061         struct tg3 *tp = netdev_priv(dev);
8062         tp->msg_enable = value;
8063 }
8064
8065 static int tg3_set_tso(struct net_device *dev, u32 value)
8066 {
8067         struct tg3 *tp = netdev_priv(dev);
8068
8069         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8070                 if (value)
8071                         return -EINVAL;
8072                 return 0;
8073         }
8074         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8075             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8076                 if (value)
8077                         dev->features |= NETIF_F_TSO6;
8078                 else
8079                         dev->features &= ~NETIF_F_TSO6;
8080         }
8081         return ethtool_op_set_tso(dev, value);
8082 }
8083
8084 static int tg3_nway_reset(struct net_device *dev)
8085 {
8086         struct tg3 *tp = netdev_priv(dev);
8087         u32 bmcr;
8088         int r;
8089
8090         if (!netif_running(dev))
8091                 return -EAGAIN;
8092
8093         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8094                 return -EINVAL;
8095
8096         spin_lock_bh(&tp->lock);
8097         r = -EINVAL;
8098         tg3_readphy(tp, MII_BMCR, &bmcr);
8099         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8100             ((bmcr & BMCR_ANENABLE) ||
8101              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8102                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8103                                            BMCR_ANENABLE);
8104                 r = 0;
8105         }
8106         spin_unlock_bh(&tp->lock);
8107
8108         return r;
8109 }
8110
8111 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8112 {
8113         struct tg3 *tp = netdev_priv(dev);
8114
8115         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8116         ering->rx_mini_max_pending = 0;
8117         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8118                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8119         else
8120                 ering->rx_jumbo_max_pending = 0;
8121
8122         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8123
8124         ering->rx_pending = tp->rx_pending;
8125         ering->rx_mini_pending = 0;
8126         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8127                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8128         else
8129                 ering->rx_jumbo_pending = 0;
8130
8131         ering->tx_pending = tp->tx_pending;
8132 }
8133
8134 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8135 {
8136         struct tg3 *tp = netdev_priv(dev);
8137         int irq_sync = 0, err = 0;
8138
8139         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8140             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8141             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8142             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8143             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8144              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8145                 return -EINVAL;
8146
8147         if (netif_running(dev)) {
8148                 tg3_netif_stop(tp);
8149                 irq_sync = 1;
8150         }
8151
8152         tg3_full_lock(tp, irq_sync);
8153
8154         tp->rx_pending = ering->rx_pending;
8155
8156         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8157             tp->rx_pending > 63)
8158                 tp->rx_pending = 63;
8159         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8160         tp->tx_pending = ering->tx_pending;
8161
8162         if (netif_running(dev)) {
8163                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8164                 err = tg3_restart_hw(tp, 1);
8165                 if (!err)
8166                         tg3_netif_start(tp);
8167         }
8168
8169         tg3_full_unlock(tp);
8170
8171         return err;
8172 }
8173
8174 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8175 {
8176         struct tg3 *tp = netdev_priv(dev);
8177
8178         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8179         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8180         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8181 }
8182
8183 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8184 {
8185         struct tg3 *tp = netdev_priv(dev);
8186         int irq_sync = 0, err = 0;
8187
8188         if (netif_running(dev)) {
8189                 tg3_netif_stop(tp);
8190                 irq_sync = 1;
8191         }
8192
8193         tg3_full_lock(tp, irq_sync);
8194
8195         if (epause->autoneg)
8196                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8197         else
8198                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8199         if (epause->rx_pause)
8200                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8201         else
8202                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8203         if (epause->tx_pause)
8204                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8205         else
8206                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8207
8208         if (netif_running(dev)) {
8209                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8210                 err = tg3_restart_hw(tp, 1);
8211                 if (!err)
8212                         tg3_netif_start(tp);
8213         }
8214
8215         tg3_full_unlock(tp);
8216
8217         return err;
8218 }
8219
8220 static u32 tg3_get_rx_csum(struct net_device *dev)
8221 {
8222         struct tg3 *tp = netdev_priv(dev);
8223         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8224 }
8225
8226 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8227 {
8228         struct tg3 *tp = netdev_priv(dev);
8229
8230         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8231                 if (data != 0)
8232                         return -EINVAL;
8233                 return 0;
8234         }
8235
8236         spin_lock_bh(&tp->lock);
8237         if (data)
8238                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8239         else
8240                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8241         spin_unlock_bh(&tp->lock);
8242
8243         return 0;
8244 }
8245
8246 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8247 {
8248         struct tg3 *tp = netdev_priv(dev);
8249
8250         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8251                 if (data != 0)
8252                         return -EINVAL;
8253                 return 0;
8254         }
8255
8256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8257             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8258                 ethtool_op_set_tx_hw_csum(dev, data);
8259         else
8260                 ethtool_op_set_tx_csum(dev, data);
8261
8262         return 0;
8263 }
8264
8265 static int tg3_get_stats_count (struct net_device *dev)
8266 {
8267         return TG3_NUM_STATS;
8268 }
8269
8270 static int tg3_get_test_count (struct net_device *dev)
8271 {
8272         return TG3_NUM_TEST;
8273 }
8274
8275 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8276 {
8277         switch (stringset) {
8278         case ETH_SS_STATS:
8279                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8280                 break;
8281         case ETH_SS_TEST:
8282                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8283                 break;
8284         default:
8285                 WARN_ON(1);     /* we need a WARN() */
8286                 break;
8287         }
8288 }
8289
8290 static int tg3_phys_id(struct net_device *dev, u32 data)
8291 {
8292         struct tg3 *tp = netdev_priv(dev);
8293         int i;
8294
8295         if (!netif_running(tp->dev))
8296                 return -EAGAIN;
8297
8298         if (data == 0)
8299                 data = 2;
8300
8301         for (i = 0; i < (data * 2); i++) {
8302                 if ((i % 2) == 0)
8303                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8304                                            LED_CTRL_1000MBPS_ON |
8305                                            LED_CTRL_100MBPS_ON |
8306                                            LED_CTRL_10MBPS_ON |
8307                                            LED_CTRL_TRAFFIC_OVERRIDE |
8308                                            LED_CTRL_TRAFFIC_BLINK |
8309                                            LED_CTRL_TRAFFIC_LED);
8310
8311                 else
8312                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8313                                            LED_CTRL_TRAFFIC_OVERRIDE);
8314
8315                 if (msleep_interruptible(500))
8316                         break;
8317         }
8318         tw32(MAC_LED_CTRL, tp->led_ctrl);
8319         return 0;
8320 }
8321
8322 static void tg3_get_ethtool_stats (struct net_device *dev,
8323                                    struct ethtool_stats *estats, u64 *tmp_stats)
8324 {
8325         struct tg3 *tp = netdev_priv(dev);
8326         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8327 }
8328
8329 #define NVRAM_TEST_SIZE 0x100
8330 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8331 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8332 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8333
8334 static int tg3_test_nvram(struct tg3 *tp)
8335 {
8336         u32 *buf, csum, magic;
8337         int i, j, err = 0, size;
8338
8339         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8340                 return -EIO;
8341
8342         if (magic == TG3_EEPROM_MAGIC)
8343                 size = NVRAM_TEST_SIZE;
8344         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8345                 if ((magic & 0xe00000) == 0x200000)
8346                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8347                 else
8348                         return 0;
8349         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8350                 size = NVRAM_SELFBOOT_HW_SIZE;
8351         else
8352                 return -EIO;
8353
8354         buf = kmalloc(size, GFP_KERNEL);
8355         if (buf == NULL)
8356                 return -ENOMEM;
8357
8358         err = -EIO;
8359         for (i = 0, j = 0; i < size; i += 4, j++) {
8360                 u32 val;
8361
8362                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8363                         break;
8364                 buf[j] = cpu_to_le32(val);
8365         }
8366         if (i < size)
8367                 goto out;
8368
8369         /* Selfboot format */
8370         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8371             TG3_EEPROM_MAGIC_FW) {
8372                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8373
8374                 for (i = 0; i < size; i++)
8375                         csum8 += buf8[i];
8376
8377                 if (csum8 == 0) {
8378                         err = 0;
8379                         goto out;
8380                 }
8381
8382                 err = -EIO;
8383                 goto out;
8384         }
8385
8386         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8387             TG3_EEPROM_MAGIC_HW) {
8388                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8389                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8390                 u8 *buf8 = (u8 *) buf;
8391                 int j, k;
8392
8393                 /* Separate the parity bits and the data bytes.  */
8394                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8395                         if ((i == 0) || (i == 8)) {
8396                                 int l;
8397                                 u8 msk;
8398
8399                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8400                                         parity[k++] = buf8[i] & msk;
8401                                 i++;
8402                         }
8403                         else if (i == 16) {
8404                                 int l;
8405                                 u8 msk;
8406
8407                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8408                                         parity[k++] = buf8[i] & msk;
8409                                 i++;
8410
8411                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8412                                         parity[k++] = buf8[i] & msk;
8413                                 i++;
8414                         }
8415                         data[j++] = buf8[i];
8416                 }
8417
8418                 err = -EIO;
8419                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8420                         u8 hw8 = hweight8(data[i]);
8421
8422                         if ((hw8 & 0x1) && parity[i])
8423                                 goto out;
8424                         else if (!(hw8 & 0x1) && !parity[i])
8425                                 goto out;
8426                 }
8427                 err = 0;
8428                 goto out;
8429         }
8430
8431         /* Bootstrap checksum at offset 0x10 */
8432         csum = calc_crc((unsigned char *) buf, 0x10);
8433         if(csum != cpu_to_le32(buf[0x10/4]))
8434                 goto out;
8435
8436         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8437         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8438         if (csum != cpu_to_le32(buf[0xfc/4]))
8439                  goto out;
8440
8441         err = 0;
8442
8443 out:
8444         kfree(buf);
8445         return err;
8446 }
8447
8448 #define TG3_SERDES_TIMEOUT_SEC  2
8449 #define TG3_COPPER_TIMEOUT_SEC  6
8450
8451 static int tg3_test_link(struct tg3 *tp)
8452 {
8453         int i, max;
8454
8455         if (!netif_running(tp->dev))
8456                 return -ENODEV;
8457
8458         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8459                 max = TG3_SERDES_TIMEOUT_SEC;
8460         else
8461                 max = TG3_COPPER_TIMEOUT_SEC;
8462
8463         for (i = 0; i < max; i++) {
8464                 if (netif_carrier_ok(tp->dev))
8465                         return 0;
8466
8467                 if (msleep_interruptible(1000))
8468                         break;
8469         }
8470
8471         return -EIO;
8472 }
8473
8474 /* Only test the commonly used registers */
8475 static int tg3_test_registers(struct tg3 *tp)
8476 {
8477         int i, is_5705, is_5750;
8478         u32 offset, read_mask, write_mask, val, save_val, read_val;
8479         static struct {
8480                 u16 offset;
8481                 u16 flags;
8482 #define TG3_FL_5705     0x1
8483 #define TG3_FL_NOT_5705 0x2
8484 #define TG3_FL_NOT_5788 0x4
8485 #define TG3_FL_NOT_5750 0x8
8486                 u32 read_mask;
8487                 u32 write_mask;
8488         } reg_tbl[] = {
8489                 /* MAC Control Registers */
8490                 { MAC_MODE, TG3_FL_NOT_5705,
8491                         0x00000000, 0x00ef6f8c },
8492                 { MAC_MODE, TG3_FL_5705,
8493                         0x00000000, 0x01ef6b8c },
8494                 { MAC_STATUS, TG3_FL_NOT_5705,
8495                         0x03800107, 0x00000000 },
8496                 { MAC_STATUS, TG3_FL_5705,
8497                         0x03800100, 0x00000000 },
8498                 { MAC_ADDR_0_HIGH, 0x0000,
8499                         0x00000000, 0x0000ffff },
8500                 { MAC_ADDR_0_LOW, 0x0000,
8501                         0x00000000, 0xffffffff },
8502                 { MAC_RX_MTU_SIZE, 0x0000,
8503                         0x00000000, 0x0000ffff },
8504                 { MAC_TX_MODE, 0x0000,
8505                         0x00000000, 0x00000070 },
8506                 { MAC_TX_LENGTHS, 0x0000,
8507                         0x00000000, 0x00003fff },
8508                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8509                         0x00000000, 0x000007fc },
8510                 { MAC_RX_MODE, TG3_FL_5705,
8511                         0x00000000, 0x000007dc },
8512                 { MAC_HASH_REG_0, 0x0000,
8513                         0x00000000, 0xffffffff },
8514                 { MAC_HASH_REG_1, 0x0000,
8515                         0x00000000, 0xffffffff },
8516                 { MAC_HASH_REG_2, 0x0000,
8517                         0x00000000, 0xffffffff },
8518                 { MAC_HASH_REG_3, 0x0000,
8519                         0x00000000, 0xffffffff },
8520
8521                 /* Receive Data and Receive BD Initiator Control Registers. */
8522                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8523                         0x00000000, 0xffffffff },
8524                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8525                         0x00000000, 0xffffffff },
8526                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8527                         0x00000000, 0x00000003 },
8528                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8529                         0x00000000, 0xffffffff },
8530                 { RCVDBDI_STD_BD+0, 0x0000,
8531                         0x00000000, 0xffffffff },
8532                 { RCVDBDI_STD_BD+4, 0x0000,
8533                         0x00000000, 0xffffffff },
8534                 { RCVDBDI_STD_BD+8, 0x0000,
8535                         0x00000000, 0xffff0002 },
8536                 { RCVDBDI_STD_BD+0xc, 0x0000,
8537                         0x00000000, 0xffffffff },
8538
8539                 /* Receive BD Initiator Control Registers. */
8540                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8541                         0x00000000, 0xffffffff },
8542                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8543                         0x00000000, 0x000003ff },
8544                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8545                         0x00000000, 0xffffffff },
8546
8547                 /* Host Coalescing Control Registers. */
8548                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8549                         0x00000000, 0x00000004 },
8550                 { HOSTCC_MODE, TG3_FL_5705,
8551                         0x00000000, 0x000000f6 },
8552                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8553                         0x00000000, 0xffffffff },
8554                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8555                         0x00000000, 0x000003ff },
8556                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8557                         0x00000000, 0xffffffff },
8558                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8559                         0x00000000, 0x000003ff },
8560                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8561                         0x00000000, 0xffffffff },
8562                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8563                         0x00000000, 0x000000ff },
8564                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8565                         0x00000000, 0xffffffff },
8566                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8567                         0x00000000, 0x000000ff },
8568                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8569                         0x00000000, 0xffffffff },
8570                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8571                         0x00000000, 0xffffffff },
8572                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8573                         0x00000000, 0xffffffff },
8574                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8575                         0x00000000, 0x000000ff },
8576                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8577                         0x00000000, 0xffffffff },
8578                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8579                         0x00000000, 0x000000ff },
8580                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8581                         0x00000000, 0xffffffff },
8582                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8583                         0x00000000, 0xffffffff },
8584                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8585                         0x00000000, 0xffffffff },
8586                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8587                         0x00000000, 0xffffffff },
8588                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8589                         0x00000000, 0xffffffff },
8590                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8591                         0xffffffff, 0x00000000 },
8592                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8593                         0xffffffff, 0x00000000 },
8594
8595                 /* Buffer Manager Control Registers. */
8596                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8597                         0x00000000, 0x007fff80 },
8598                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8599                         0x00000000, 0x007fffff },
8600                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8601                         0x00000000, 0x0000003f },
8602                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8603                         0x00000000, 0x000001ff },
8604                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8605                         0x00000000, 0x000001ff },
8606                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8607                         0xffffffff, 0x00000000 },
8608                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8609                         0xffffffff, 0x00000000 },
8610
8611                 /* Mailbox Registers */
8612                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8613                         0x00000000, 0x000001ff },
8614                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8615                         0x00000000, 0x000001ff },
8616                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8617                         0x00000000, 0x000007ff },
8618                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8619                         0x00000000, 0x000001ff },
8620
8621                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8622         };
8623
8624         is_5705 = is_5750 = 0;
8625         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8626                 is_5705 = 1;
8627                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8628                         is_5750 = 1;
8629         }
8630
8631         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8632                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8633                         continue;
8634
8635                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8636                         continue;
8637
8638                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8639                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8640                         continue;
8641
8642                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8643                         continue;
8644
8645                 offset = (u32) reg_tbl[i].offset;
8646                 read_mask = reg_tbl[i].read_mask;
8647                 write_mask = reg_tbl[i].write_mask;
8648
8649                 /* Save the original register content */
8650                 save_val = tr32(offset);
8651
8652                 /* Determine the read-only value. */
8653                 read_val = save_val & read_mask;
8654
8655                 /* Write zero to the register, then make sure the read-only bits
8656                  * are not changed and the read/write bits are all zeros.
8657                  */
8658                 tw32(offset, 0);
8659
8660                 val = tr32(offset);
8661
8662                 /* Test the read-only and read/write bits. */
8663                 if (((val & read_mask) != read_val) || (val & write_mask))
8664                         goto out;
8665
8666                 /* Write ones to all the bits defined by RdMask and WrMask, then
8667                  * make sure the read-only bits are not changed and the
8668                  * read/write bits are all ones.
8669                  */
8670                 tw32(offset, read_mask | write_mask);
8671
8672                 val = tr32(offset);
8673
8674                 /* Test the read-only bits. */
8675                 if ((val & read_mask) != read_val)
8676                         goto out;
8677
8678                 /* Test the read/write bits. */
8679                 if ((val & write_mask) != write_mask)
8680                         goto out;
8681
8682                 tw32(offset, save_val);
8683         }
8684
8685         return 0;
8686
8687 out:
8688         if (netif_msg_hw(tp))
8689                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8690                        offset);
8691         tw32(offset, save_val);
8692         return -EIO;
8693 }
8694
8695 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8696 {
8697         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8698         int i;
8699         u32 j;
8700
8701         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8702                 for (j = 0; j < len; j += 4) {
8703                         u32 val;
8704
8705                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8706                         tg3_read_mem(tp, offset + j, &val);
8707                         if (val != test_pattern[i])
8708                                 return -EIO;
8709                 }
8710         }
8711         return 0;
8712 }
8713
8714 static int tg3_test_memory(struct tg3 *tp)
8715 {
8716         static struct mem_entry {
8717                 u32 offset;
8718                 u32 len;
8719         } mem_tbl_570x[] = {
8720                 { 0x00000000, 0x00b50},
8721                 { 0x00002000, 0x1c000},
8722                 { 0xffffffff, 0x00000}
8723         }, mem_tbl_5705[] = {
8724                 { 0x00000100, 0x0000c},
8725                 { 0x00000200, 0x00008},
8726                 { 0x00004000, 0x00800},
8727                 { 0x00006000, 0x01000},
8728                 { 0x00008000, 0x02000},
8729                 { 0x00010000, 0x0e000},
8730                 { 0xffffffff, 0x00000}
8731         }, mem_tbl_5755[] = {
8732                 { 0x00000200, 0x00008},
8733                 { 0x00004000, 0x00800},
8734                 { 0x00006000, 0x00800},
8735                 { 0x00008000, 0x02000},
8736                 { 0x00010000, 0x0c000},
8737                 { 0xffffffff, 0x00000}
8738         }, mem_tbl_5906[] = {
8739                 { 0x00000200, 0x00008},
8740                 { 0x00004000, 0x00400},
8741                 { 0x00006000, 0x00400},
8742                 { 0x00008000, 0x01000},
8743                 { 0x00010000, 0x01000},
8744                 { 0xffffffff, 0x00000}
8745         };
8746         struct mem_entry *mem_tbl;
8747         int err = 0;
8748         int i;
8749
8750         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8751                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8752                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8753                         mem_tbl = mem_tbl_5755;
8754                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8755                         mem_tbl = mem_tbl_5906;
8756                 else
8757                         mem_tbl = mem_tbl_5705;
8758         } else
8759                 mem_tbl = mem_tbl_570x;
8760
8761         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8762                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8763                     mem_tbl[i].len)) != 0)
8764                         break;
8765         }
8766
8767         return err;
8768 }
8769
8770 #define TG3_MAC_LOOPBACK        0
8771 #define TG3_PHY_LOOPBACK        1
8772
8773 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8774 {
8775         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8776         u32 desc_idx;
8777         struct sk_buff *skb, *rx_skb;
8778         u8 *tx_data;
8779         dma_addr_t map;
8780         int num_pkts, tx_len, rx_len, i, err;
8781         struct tg3_rx_buffer_desc *desc;
8782
8783         if (loopback_mode == TG3_MAC_LOOPBACK) {
8784                 /* HW errata - mac loopback fails in some cases on 5780.
8785                  * Normal traffic and PHY loopback are not affected by
8786                  * errata.
8787                  */
8788                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8789                         return 0;
8790
8791                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8792                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8793                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8794                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8795                 else
8796                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8797                 tw32(MAC_MODE, mac_mode);
8798         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8799                 u32 val;
8800
8801                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8802                         u32 phytest;
8803
8804                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8805                                 u32 phy;
8806
8807                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8808                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8809                                 if (!tg3_readphy(tp, 0x1b, &phy))
8810                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8811                                 if (!tg3_readphy(tp, 0x10, &phy))
8812                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
8813                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8814                         }
8815                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8816                 } else
8817                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8818
8819                 tg3_writephy(tp, MII_BMCR, val);
8820                 udelay(40);
8821
8822                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8823                            MAC_MODE_LINK_POLARITY;
8824                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8825                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8826                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8827                 } else
8828                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8829
8830                 /* reset to prevent losing 1st rx packet intermittently */
8831                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8832                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8833                         udelay(10);
8834                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8835                 }
8836                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8837                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8838                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8839                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8840                 }
8841                 tw32(MAC_MODE, mac_mode);
8842         }
8843         else
8844                 return -EINVAL;
8845
8846         err = -EIO;
8847
8848         tx_len = 1514;
8849         skb = netdev_alloc_skb(tp->dev, tx_len);
8850         if (!skb)
8851                 return -ENOMEM;
8852
8853         tx_data = skb_put(skb, tx_len);
8854         memcpy(tx_data, tp->dev->dev_addr, 6);
8855         memset(tx_data + 6, 0x0, 8);
8856
8857         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8858
8859         for (i = 14; i < tx_len; i++)
8860                 tx_data[i] = (u8) (i & 0xff);
8861
8862         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8863
8864         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8865              HOSTCC_MODE_NOW);
8866
8867         udelay(10);
8868
8869         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8870
8871         num_pkts = 0;
8872
8873         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8874
8875         tp->tx_prod++;
8876         num_pkts++;
8877
8878         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8879                      tp->tx_prod);
8880         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8881
8882         udelay(10);
8883
8884         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8885         for (i = 0; i < 25; i++) {
8886                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8887                        HOSTCC_MODE_NOW);
8888
8889                 udelay(10);
8890
8891                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8892                 rx_idx = tp->hw_status->idx[0].rx_producer;
8893                 if ((tx_idx == tp->tx_prod) &&
8894                     (rx_idx == (rx_start_idx + num_pkts)))
8895                         break;
8896         }
8897
8898         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8899         dev_kfree_skb(skb);
8900
8901         if (tx_idx != tp->tx_prod)
8902                 goto out;
8903
8904         if (rx_idx != rx_start_idx + num_pkts)
8905                 goto out;
8906
8907         desc = &tp->rx_rcb[rx_start_idx];
8908         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8909         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8910         if (opaque_key != RXD_OPAQUE_RING_STD)
8911                 goto out;
8912
8913         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8914             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8915                 goto out;
8916
8917         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8918         if (rx_len != tx_len)
8919                 goto out;
8920
8921         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8922
8923         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8924         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8925
8926         for (i = 14; i < tx_len; i++) {
8927                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8928                         goto out;
8929         }
8930         err = 0;
8931
8932         /* tg3_free_rings will unmap and free the rx_skb */
8933 out:
8934         return err;
8935 }
8936
8937 #define TG3_MAC_LOOPBACK_FAILED         1
8938 #define TG3_PHY_LOOPBACK_FAILED         2
8939 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8940                                          TG3_PHY_LOOPBACK_FAILED)
8941
8942 static int tg3_test_loopback(struct tg3 *tp)
8943 {
8944         int err = 0;
8945
8946         if (!netif_running(tp->dev))
8947                 return TG3_LOOPBACK_FAILED;
8948
8949         err = tg3_reset_hw(tp, 1);
8950         if (err)
8951                 return TG3_LOOPBACK_FAILED;
8952
8953         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8954                 err |= TG3_MAC_LOOPBACK_FAILED;
8955         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8956                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8957                         err |= TG3_PHY_LOOPBACK_FAILED;
8958         }
8959
8960         return err;
8961 }
8962
8963 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8964                           u64 *data)
8965 {
8966         struct tg3 *tp = netdev_priv(dev);
8967
8968         if (tp->link_config.phy_is_low_power)
8969                 tg3_set_power_state(tp, PCI_D0);
8970
8971         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8972
8973         if (tg3_test_nvram(tp) != 0) {
8974                 etest->flags |= ETH_TEST_FL_FAILED;
8975                 data[0] = 1;
8976         }
8977         if (tg3_test_link(tp) != 0) {
8978                 etest->flags |= ETH_TEST_FL_FAILED;
8979                 data[1] = 1;
8980         }
8981         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8982                 int err, irq_sync = 0;
8983
8984                 if (netif_running(dev)) {
8985                         tg3_netif_stop(tp);
8986                         irq_sync = 1;
8987                 }
8988
8989                 tg3_full_lock(tp, irq_sync);
8990
8991                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8992                 err = tg3_nvram_lock(tp);
8993                 tg3_halt_cpu(tp, RX_CPU_BASE);
8994                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8995                         tg3_halt_cpu(tp, TX_CPU_BASE);
8996                 if (!err)
8997                         tg3_nvram_unlock(tp);
8998
8999                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9000                         tg3_phy_reset(tp);
9001
9002                 if (tg3_test_registers(tp) != 0) {
9003                         etest->flags |= ETH_TEST_FL_FAILED;
9004                         data[2] = 1;
9005                 }
9006                 if (tg3_test_memory(tp) != 0) {
9007                         etest->flags |= ETH_TEST_FL_FAILED;
9008                         data[3] = 1;
9009                 }
9010                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9011                         etest->flags |= ETH_TEST_FL_FAILED;
9012
9013                 tg3_full_unlock(tp);
9014
9015                 if (tg3_test_interrupt(tp) != 0) {
9016                         etest->flags |= ETH_TEST_FL_FAILED;
9017                         data[5] = 1;
9018                 }
9019
9020                 tg3_full_lock(tp, 0);
9021
9022                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9023                 if (netif_running(dev)) {
9024                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9025                         if (!tg3_restart_hw(tp, 1))
9026                                 tg3_netif_start(tp);
9027                 }
9028
9029                 tg3_full_unlock(tp);
9030         }
9031         if (tp->link_config.phy_is_low_power)
9032                 tg3_set_power_state(tp, PCI_D3hot);
9033
9034 }
9035
9036 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9037 {
9038         struct mii_ioctl_data *data = if_mii(ifr);
9039         struct tg3 *tp = netdev_priv(dev);
9040         int err;
9041
9042         switch(cmd) {
9043         case SIOCGMIIPHY:
9044                 data->phy_id = PHY_ADDR;
9045
9046                 /* fallthru */
9047         case SIOCGMIIREG: {
9048                 u32 mii_regval;
9049
9050                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9051                         break;                  /* We have no PHY */
9052
9053                 if (tp->link_config.phy_is_low_power)
9054                         return -EAGAIN;
9055
9056                 spin_lock_bh(&tp->lock);
9057                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9058                 spin_unlock_bh(&tp->lock);
9059
9060                 data->val_out = mii_regval;
9061
9062                 return err;
9063         }
9064
9065         case SIOCSMIIREG:
9066                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9067                         break;                  /* We have no PHY */
9068
9069                 if (!capable(CAP_NET_ADMIN))
9070                         return -EPERM;
9071
9072                 if (tp->link_config.phy_is_low_power)
9073                         return -EAGAIN;
9074
9075                 spin_lock_bh(&tp->lock);
9076                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9077                 spin_unlock_bh(&tp->lock);
9078
9079                 return err;
9080
9081         default:
9082                 /* do nothing */
9083                 break;
9084         }
9085         return -EOPNOTSUPP;
9086 }
9087
9088 #if TG3_VLAN_TAG_USED
9089 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9090 {
9091         struct tg3 *tp = netdev_priv(dev);
9092
9093         if (netif_running(dev))
9094                 tg3_netif_stop(tp);
9095
9096         tg3_full_lock(tp, 0);
9097
9098         tp->vlgrp = grp;
9099
9100         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9101         __tg3_set_rx_mode(dev);
9102
9103         tg3_full_unlock(tp);
9104
9105         if (netif_running(dev))
9106                 tg3_netif_start(tp);
9107 }
9108
9109 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9110 {
9111         struct tg3 *tp = netdev_priv(dev);
9112
9113         if (netif_running(dev))
9114                 tg3_netif_stop(tp);
9115
9116         tg3_full_lock(tp, 0);
9117         if (tp->vlgrp)
9118                 tp->vlgrp->vlan_devices[vid] = NULL;
9119         tg3_full_unlock(tp);
9120
9121         if (netif_running(dev))
9122                 tg3_netif_start(tp);
9123 }
9124 #endif
9125
9126 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9127 {
9128         struct tg3 *tp = netdev_priv(dev);
9129
9130         memcpy(ec, &tp->coal, sizeof(*ec));
9131         return 0;
9132 }
9133
9134 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9135 {
9136         struct tg3 *tp = netdev_priv(dev);
9137         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9138         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9139
9140         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9141                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9142                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9143                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9144                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9145         }
9146
9147         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9148             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9149             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9150             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9151             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9152             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9153             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9154             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9155             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9156             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9157                 return -EINVAL;
9158
9159         /* No rx interrupts will be generated if both are zero */
9160         if ((ec->rx_coalesce_usecs == 0) &&
9161             (ec->rx_max_coalesced_frames == 0))
9162                 return -EINVAL;
9163
9164         /* No tx interrupts will be generated if both are zero */
9165         if ((ec->tx_coalesce_usecs == 0) &&
9166             (ec->tx_max_coalesced_frames == 0))
9167                 return -EINVAL;
9168
9169         /* Only copy relevant parameters, ignore all others. */
9170         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9171         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9172         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9173         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9174         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9175         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9176         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9177         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9178         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9179
9180         if (netif_running(dev)) {
9181                 tg3_full_lock(tp, 0);
9182                 __tg3_set_coalesce(tp, &tp->coal);
9183                 tg3_full_unlock(tp);
9184         }
9185         return 0;
9186 }
9187
9188 static const struct ethtool_ops tg3_ethtool_ops = {
9189         .get_settings           = tg3_get_settings,
9190         .set_settings           = tg3_set_settings,
9191         .get_drvinfo            = tg3_get_drvinfo,
9192         .get_regs_len           = tg3_get_regs_len,
9193         .get_regs               = tg3_get_regs,
9194         .get_wol                = tg3_get_wol,
9195         .set_wol                = tg3_set_wol,
9196         .get_msglevel           = tg3_get_msglevel,
9197         .set_msglevel           = tg3_set_msglevel,
9198         .nway_reset             = tg3_nway_reset,
9199         .get_link               = ethtool_op_get_link,
9200         .get_eeprom_len         = tg3_get_eeprom_len,
9201         .get_eeprom             = tg3_get_eeprom,
9202         .set_eeprom             = tg3_set_eeprom,
9203         .get_ringparam          = tg3_get_ringparam,
9204         .set_ringparam          = tg3_set_ringparam,
9205         .get_pauseparam         = tg3_get_pauseparam,
9206         .set_pauseparam         = tg3_set_pauseparam,
9207         .get_rx_csum            = tg3_get_rx_csum,
9208         .set_rx_csum            = tg3_set_rx_csum,
9209         .get_tx_csum            = ethtool_op_get_tx_csum,
9210         .set_tx_csum            = tg3_set_tx_csum,
9211         .get_sg                 = ethtool_op_get_sg,
9212         .set_sg                 = ethtool_op_set_sg,
9213         .get_tso                = ethtool_op_get_tso,
9214         .set_tso                = tg3_set_tso,
9215         .self_test_count        = tg3_get_test_count,
9216         .self_test              = tg3_self_test,
9217         .get_strings            = tg3_get_strings,
9218         .phys_id                = tg3_phys_id,
9219         .get_stats_count        = tg3_get_stats_count,
9220         .get_ethtool_stats      = tg3_get_ethtool_stats,
9221         .get_coalesce           = tg3_get_coalesce,
9222         .set_coalesce           = tg3_set_coalesce,
9223         .get_perm_addr          = ethtool_op_get_perm_addr,
9224 };
9225
9226 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9227 {
9228         u32 cursize, val, magic;
9229
9230         tp->nvram_size = EEPROM_CHIP_SIZE;
9231
9232         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9233                 return;
9234
9235         if ((magic != TG3_EEPROM_MAGIC) &&
9236             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9237             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9238                 return;
9239
9240         /*
9241          * Size the chip by reading offsets at increasing powers of two.
9242          * When we encounter our validation signature, we know the addressing
9243          * has wrapped around, and thus have our chip size.
9244          */
9245         cursize = 0x10;
9246
9247         while (cursize < tp->nvram_size) {
9248                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9249                         return;
9250
9251                 if (val == magic)
9252                         break;
9253
9254                 cursize <<= 1;
9255         }
9256
9257         tp->nvram_size = cursize;
9258 }
9259
9260 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9261 {
9262         u32 val;
9263
9264         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9265                 return;
9266
9267         /* Selfboot format */
9268         if (val != TG3_EEPROM_MAGIC) {
9269                 tg3_get_eeprom_size(tp);
9270                 return;
9271         }
9272
9273         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9274                 if (val != 0) {
9275                         tp->nvram_size = (val >> 16) * 1024;
9276                         return;
9277                 }
9278         }
9279         tp->nvram_size = 0x20000;
9280 }
9281
9282 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9283 {
9284         u32 nvcfg1;
9285
9286         nvcfg1 = tr32(NVRAM_CFG1);
9287         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9288                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9289         }
9290         else {
9291                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9292                 tw32(NVRAM_CFG1, nvcfg1);
9293         }
9294
9295         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9296             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9297                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9298                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9299                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9300                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9301                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9302                                 break;
9303                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9304                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9305                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9306                                 break;
9307                         case FLASH_VENDOR_ATMEL_EEPROM:
9308                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9309                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9310                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9311                                 break;
9312                         case FLASH_VENDOR_ST:
9313                                 tp->nvram_jedecnum = JEDEC_ST;
9314                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9315                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9316                                 break;
9317                         case FLASH_VENDOR_SAIFUN:
9318                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9319                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9320                                 break;
9321                         case FLASH_VENDOR_SST_SMALL:
9322                         case FLASH_VENDOR_SST_LARGE:
9323                                 tp->nvram_jedecnum = JEDEC_SST;
9324                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9325                                 break;
9326                 }
9327         }
9328         else {
9329                 tp->nvram_jedecnum = JEDEC_ATMEL;
9330                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9331                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9332         }
9333 }
9334
9335 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9336 {
9337         u32 nvcfg1;
9338
9339         nvcfg1 = tr32(NVRAM_CFG1);
9340
9341         /* NVRAM protection for TPM */
9342         if (nvcfg1 & (1 << 27))
9343                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9344
9345         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9346                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9347                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9348                         tp->nvram_jedecnum = JEDEC_ATMEL;
9349                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9350                         break;
9351                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9352                         tp->nvram_jedecnum = JEDEC_ATMEL;
9353                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9354                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9355                         break;
9356                 case FLASH_5752VENDOR_ST_M45PE10:
9357                 case FLASH_5752VENDOR_ST_M45PE20:
9358                 case FLASH_5752VENDOR_ST_M45PE40:
9359                         tp->nvram_jedecnum = JEDEC_ST;
9360                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9361                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9362                         break;
9363         }
9364
9365         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9366                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9367                         case FLASH_5752PAGE_SIZE_256:
9368                                 tp->nvram_pagesize = 256;
9369                                 break;
9370                         case FLASH_5752PAGE_SIZE_512:
9371                                 tp->nvram_pagesize = 512;
9372                                 break;
9373                         case FLASH_5752PAGE_SIZE_1K:
9374                                 tp->nvram_pagesize = 1024;
9375                                 break;
9376                         case FLASH_5752PAGE_SIZE_2K:
9377                                 tp->nvram_pagesize = 2048;
9378                                 break;
9379                         case FLASH_5752PAGE_SIZE_4K:
9380                                 tp->nvram_pagesize = 4096;
9381                                 break;
9382                         case FLASH_5752PAGE_SIZE_264:
9383                                 tp->nvram_pagesize = 264;
9384                                 break;
9385                 }
9386         }
9387         else {
9388                 /* For eeprom, set pagesize to maximum eeprom size */
9389                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9390
9391                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9392                 tw32(NVRAM_CFG1, nvcfg1);
9393         }
9394 }
9395
9396 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9397 {
9398         u32 nvcfg1;
9399
9400         nvcfg1 = tr32(NVRAM_CFG1);
9401
9402         /* NVRAM protection for TPM */
9403         if (nvcfg1 & (1 << 27))
9404                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9405
9406         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9407                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9408                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9409                         tp->nvram_jedecnum = JEDEC_ATMEL;
9410                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9411                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9412
9413                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9414                         tw32(NVRAM_CFG1, nvcfg1);
9415                         break;
9416                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9417                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9418                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9419                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9420                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9421                         tp->nvram_jedecnum = JEDEC_ATMEL;
9422                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9423                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9424                         tp->nvram_pagesize = 264;
9425                         break;
9426                 case FLASH_5752VENDOR_ST_M45PE10:
9427                 case FLASH_5752VENDOR_ST_M45PE20:
9428                 case FLASH_5752VENDOR_ST_M45PE40:
9429                         tp->nvram_jedecnum = JEDEC_ST;
9430                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9431                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9432                         tp->nvram_pagesize = 256;
9433                         break;
9434         }
9435 }
9436
9437 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9438 {
9439         u32 nvcfg1;
9440
9441         nvcfg1 = tr32(NVRAM_CFG1);
9442
9443         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9444                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9445                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9446                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9447                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9448                         tp->nvram_jedecnum = JEDEC_ATMEL;
9449                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9450                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9451
9452                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9453                         tw32(NVRAM_CFG1, nvcfg1);
9454                         break;
9455                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9456                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9457                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9458                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9459                         tp->nvram_jedecnum = JEDEC_ATMEL;
9460                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9461                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9462                         tp->nvram_pagesize = 264;
9463                         break;
9464                 case FLASH_5752VENDOR_ST_M45PE10:
9465                 case FLASH_5752VENDOR_ST_M45PE20:
9466                 case FLASH_5752VENDOR_ST_M45PE40:
9467                         tp->nvram_jedecnum = JEDEC_ST;
9468                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9469                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9470                         tp->nvram_pagesize = 256;
9471                         break;
9472         }
9473 }
9474
9475 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9476 {
9477         tp->nvram_jedecnum = JEDEC_ATMEL;
9478         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9479         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9480 }
9481
9482 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9483 static void __devinit tg3_nvram_init(struct tg3 *tp)
9484 {
9485         tw32_f(GRC_EEPROM_ADDR,
9486              (EEPROM_ADDR_FSM_RESET |
9487               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9488                EEPROM_ADDR_CLKPERD_SHIFT)));
9489
9490         msleep(1);
9491
9492         /* Enable seeprom accesses. */
9493         tw32_f(GRC_LOCAL_CTRL,
9494              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9495         udelay(100);
9496
9497         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9498             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9499                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9500
9501                 if (tg3_nvram_lock(tp)) {
9502                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9503                                "tg3_nvram_init failed.\n", tp->dev->name);
9504                         return;
9505                 }
9506                 tg3_enable_nvram_access(tp);
9507
9508                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9509                         tg3_get_5752_nvram_info(tp);
9510                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9511                         tg3_get_5755_nvram_info(tp);
9512                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9513                         tg3_get_5787_nvram_info(tp);
9514                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9515                         tg3_get_5906_nvram_info(tp);
9516                 else
9517                         tg3_get_nvram_info(tp);
9518
9519                 tg3_get_nvram_size(tp);
9520
9521                 tg3_disable_nvram_access(tp);
9522                 tg3_nvram_unlock(tp);
9523
9524         } else {
9525                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9526
9527                 tg3_get_eeprom_size(tp);
9528         }
9529 }
9530
9531 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9532                                         u32 offset, u32 *val)
9533 {
9534         u32 tmp;
9535         int i;
9536
9537         if (offset > EEPROM_ADDR_ADDR_MASK ||
9538             (offset % 4) != 0)
9539                 return -EINVAL;
9540
9541         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9542                                         EEPROM_ADDR_DEVID_MASK |
9543                                         EEPROM_ADDR_READ);
9544         tw32(GRC_EEPROM_ADDR,
9545              tmp |
9546              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9547              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9548               EEPROM_ADDR_ADDR_MASK) |
9549              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9550
9551         for (i = 0; i < 1000; i++) {
9552                 tmp = tr32(GRC_EEPROM_ADDR);
9553
9554                 if (tmp & EEPROM_ADDR_COMPLETE)
9555                         break;
9556                 msleep(1);
9557         }
9558         if (!(tmp & EEPROM_ADDR_COMPLETE))
9559                 return -EBUSY;
9560
9561         *val = tr32(GRC_EEPROM_DATA);
9562         return 0;
9563 }
9564
9565 #define NVRAM_CMD_TIMEOUT 10000
9566
9567 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9568 {
9569         int i;
9570
9571         tw32(NVRAM_CMD, nvram_cmd);
9572         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9573                 udelay(10);
9574                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9575                         udelay(10);
9576                         break;
9577                 }
9578         }
9579         if (i == NVRAM_CMD_TIMEOUT) {
9580                 return -EBUSY;
9581         }
9582         return 0;
9583 }
9584
9585 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9586 {
9587         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9588             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9589             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9590             (tp->nvram_jedecnum == JEDEC_ATMEL))
9591
9592                 addr = ((addr / tp->nvram_pagesize) <<
9593                         ATMEL_AT45DB0X1B_PAGE_POS) +
9594                        (addr % tp->nvram_pagesize);
9595
9596         return addr;
9597 }
9598
9599 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9600 {
9601         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9602             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9603             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9604             (tp->nvram_jedecnum == JEDEC_ATMEL))
9605
9606                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9607                         tp->nvram_pagesize) +
9608                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9609
9610         return addr;
9611 }
9612
9613 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9614 {
9615         int ret;
9616
9617         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9618                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9619
9620         offset = tg3_nvram_phys_addr(tp, offset);
9621
9622         if (offset > NVRAM_ADDR_MSK)
9623                 return -EINVAL;
9624
9625         ret = tg3_nvram_lock(tp);
9626         if (ret)
9627                 return ret;
9628
9629         tg3_enable_nvram_access(tp);
9630
9631         tw32(NVRAM_ADDR, offset);
9632         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9633                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9634
9635         if (ret == 0)
9636                 *val = swab32(tr32(NVRAM_RDDATA));
9637
9638         tg3_disable_nvram_access(tp);
9639
9640         tg3_nvram_unlock(tp);
9641
9642         return ret;
9643 }
9644
9645 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9646 {
9647         int err;
9648         u32 tmp;
9649
9650         err = tg3_nvram_read(tp, offset, &tmp);
9651         *val = swab32(tmp);
9652         return err;
9653 }
9654
9655 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9656                                     u32 offset, u32 len, u8 *buf)
9657 {
9658         int i, j, rc = 0;
9659         u32 val;
9660
9661         for (i = 0; i < len; i += 4) {
9662                 u32 addr, data;
9663
9664                 addr = offset + i;
9665
9666                 memcpy(&data, buf + i, 4);
9667
9668                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9669
9670                 val = tr32(GRC_EEPROM_ADDR);
9671                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9672
9673                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9674                         EEPROM_ADDR_READ);
9675                 tw32(GRC_EEPROM_ADDR, val |
9676                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9677                         (addr & EEPROM_ADDR_ADDR_MASK) |
9678                         EEPROM_ADDR_START |
9679                         EEPROM_ADDR_WRITE);
9680
9681                 for (j = 0; j < 1000; j++) {
9682                         val = tr32(GRC_EEPROM_ADDR);
9683
9684                         if (val & EEPROM_ADDR_COMPLETE)
9685                                 break;
9686                         msleep(1);
9687                 }
9688                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9689                         rc = -EBUSY;
9690                         break;
9691                 }
9692         }
9693
9694         return rc;
9695 }
9696
9697 /* offset and length are dword aligned */
9698 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9699                 u8 *buf)
9700 {
9701         int ret = 0;
9702         u32 pagesize = tp->nvram_pagesize;
9703         u32 pagemask = pagesize - 1;
9704         u32 nvram_cmd;
9705         u8 *tmp;
9706
9707         tmp = kmalloc(pagesize, GFP_KERNEL);
9708         if (tmp == NULL)
9709                 return -ENOMEM;
9710
9711         while (len) {
9712                 int j;
9713                 u32 phy_addr, page_off, size;
9714
9715                 phy_addr = offset & ~pagemask;
9716
9717                 for (j = 0; j < pagesize; j += 4) {
9718                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9719                                                 (u32 *) (tmp + j))))
9720                                 break;
9721                 }
9722                 if (ret)
9723                         break;
9724
9725                 page_off = offset & pagemask;
9726                 size = pagesize;
9727                 if (len < size)
9728                         size = len;
9729
9730                 len -= size;
9731
9732                 memcpy(tmp + page_off, buf, size);
9733
9734                 offset = offset + (pagesize - page_off);
9735
9736                 tg3_enable_nvram_access(tp);
9737
9738                 /*
9739                  * Before we can erase the flash page, we need
9740                  * to issue a special "write enable" command.
9741                  */
9742                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9743
9744                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9745                         break;
9746
9747                 /* Erase the target page */
9748                 tw32(NVRAM_ADDR, phy_addr);
9749
9750                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9751                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9752
9753                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9754                         break;
9755
9756                 /* Issue another write enable to start the write. */
9757                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9758
9759                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9760                         break;
9761
9762                 for (j = 0; j < pagesize; j += 4) {
9763                         u32 data;
9764
9765                         data = *((u32 *) (tmp + j));
9766                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9767
9768                         tw32(NVRAM_ADDR, phy_addr + j);
9769
9770                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9771                                 NVRAM_CMD_WR;
9772
9773                         if (j == 0)
9774                                 nvram_cmd |= NVRAM_CMD_FIRST;
9775                         else if (j == (pagesize - 4))
9776                                 nvram_cmd |= NVRAM_CMD_LAST;
9777
9778                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9779                                 break;
9780                 }
9781                 if (ret)
9782                         break;
9783         }
9784
9785         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9786         tg3_nvram_exec_cmd(tp, nvram_cmd);
9787
9788         kfree(tmp);
9789
9790         return ret;
9791 }
9792
9793 /* offset and length are dword aligned */
9794 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9795                 u8 *buf)
9796 {
9797         int i, ret = 0;
9798
9799         for (i = 0; i < len; i += 4, offset += 4) {
9800                 u32 data, page_off, phy_addr, nvram_cmd;
9801
9802                 memcpy(&data, buf + i, 4);
9803                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9804
9805                 page_off = offset % tp->nvram_pagesize;
9806
9807                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9808
9809                 tw32(NVRAM_ADDR, phy_addr);
9810
9811                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9812
9813                 if ((page_off == 0) || (i == 0))
9814                         nvram_cmd |= NVRAM_CMD_FIRST;
9815                 if (page_off == (tp->nvram_pagesize - 4))
9816                         nvram_cmd |= NVRAM_CMD_LAST;
9817
9818                 if (i == (len - 4))
9819                         nvram_cmd |= NVRAM_CMD_LAST;
9820
9821                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9822                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9823                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9824                     (tp->nvram_jedecnum == JEDEC_ST) &&
9825                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9826
9827                         if ((ret = tg3_nvram_exec_cmd(tp,
9828                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9829                                 NVRAM_CMD_DONE)))
9830
9831                                 break;
9832                 }
9833                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9834                         /* We always do complete word writes to eeprom. */
9835                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9836                 }
9837
9838                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9839                         break;
9840         }
9841         return ret;
9842 }
9843
9844 /* offset and length are dword aligned */
9845 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9846 {
9847         int ret;
9848
9849         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9850                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9851                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9852                 udelay(40);
9853         }
9854
9855         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9856                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9857         }
9858         else {
9859                 u32 grc_mode;
9860
9861                 ret = tg3_nvram_lock(tp);
9862                 if (ret)
9863                         return ret;
9864
9865                 tg3_enable_nvram_access(tp);
9866                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9867                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9868                         tw32(NVRAM_WRITE1, 0x406);
9869
9870                 grc_mode = tr32(GRC_MODE);
9871                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9872
9873                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9874                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9875
9876                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9877                                 buf);
9878                 }
9879                 else {
9880                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9881                                 buf);
9882                 }
9883
9884                 grc_mode = tr32(GRC_MODE);
9885                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9886
9887                 tg3_disable_nvram_access(tp);
9888                 tg3_nvram_unlock(tp);
9889         }
9890
9891         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9892                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9893                 udelay(40);
9894         }
9895
9896         return ret;
9897 }
9898
9899 struct subsys_tbl_ent {
9900         u16 subsys_vendor, subsys_devid;
9901         u32 phy_id;
9902 };
9903
9904 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9905         /* Broadcom boards. */
9906         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9907         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9908         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9909         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9910         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9911         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9912         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9913         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9914         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9915         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9916         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9917
9918         /* 3com boards. */
9919         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9920         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9921         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9922         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9923         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9924
9925         /* DELL boards. */
9926         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9927         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9928         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9929         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9930
9931         /* Compaq boards. */
9932         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9933         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9934         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9935         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9936         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9937
9938         /* IBM boards. */
9939         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9940 };
9941
9942 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9943 {
9944         int i;
9945
9946         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9947                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9948                      tp->pdev->subsystem_vendor) &&
9949                     (subsys_id_to_phy_id[i].subsys_devid ==
9950                      tp->pdev->subsystem_device))
9951                         return &subsys_id_to_phy_id[i];
9952         }
9953         return NULL;
9954 }
9955
9956 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9957 {
9958         u32 val;
9959         u16 pmcsr;
9960
9961         /* On some early chips the SRAM cannot be accessed in D3hot state,
9962          * so need make sure we're in D0.
9963          */
9964         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9965         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9966         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9967         msleep(1);
9968
9969         /* Make sure register accesses (indirect or otherwise)
9970          * will function correctly.
9971          */
9972         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9973                                tp->misc_host_ctrl);
9974
9975         /* The memory arbiter has to be enabled in order for SRAM accesses
9976          * to succeed.  Normally on powerup the tg3 chip firmware will make
9977          * sure it is enabled, but other entities such as system netboot
9978          * code might disable it.
9979          */
9980         val = tr32(MEMARB_MODE);
9981         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9982
9983         tp->phy_id = PHY_ID_INVALID;
9984         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9985
9986         /* Assume an onboard device by default.  */
9987         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9988
9989         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9990                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
9991                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9992                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
9993                 }
9994                 return;
9995         }
9996
9997         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9998         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9999                 u32 nic_cfg, led_cfg;
10000                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10001                 int eeprom_phy_serdes = 0;
10002
10003                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10004                 tp->nic_sram_data_cfg = nic_cfg;
10005
10006                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10007                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10008                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10009                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10010                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10011                     (ver > 0) && (ver < 0x100))
10012                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10013
10014                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10015                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10016                         eeprom_phy_serdes = 1;
10017
10018                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10019                 if (nic_phy_id != 0) {
10020                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10021                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10022
10023                         eeprom_phy_id  = (id1 >> 16) << 10;
10024                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10025                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10026                 } else
10027                         eeprom_phy_id = 0;
10028
10029                 tp->phy_id = eeprom_phy_id;
10030                 if (eeprom_phy_serdes) {
10031                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10032                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10033                         else
10034                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10035                 }
10036
10037                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10038                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10039                                     SHASTA_EXT_LED_MODE_MASK);
10040                 else
10041                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10042
10043                 switch (led_cfg) {
10044                 default:
10045                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10046                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10047                         break;
10048
10049                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10050                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10051                         break;
10052
10053                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10054                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10055
10056                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10057                          * read on some older 5700/5701 bootcode.
10058                          */
10059                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10060                             ASIC_REV_5700 ||
10061                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10062                             ASIC_REV_5701)
10063                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10064
10065                         break;
10066
10067                 case SHASTA_EXT_LED_SHARED:
10068                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10069                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10070                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10071                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10072                                                  LED_CTRL_MODE_PHY_2);
10073                         break;
10074
10075                 case SHASTA_EXT_LED_MAC:
10076                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10077                         break;
10078
10079                 case SHASTA_EXT_LED_COMBO:
10080                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10081                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10082                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10083                                                  LED_CTRL_MODE_PHY_2);
10084                         break;
10085
10086                 };
10087
10088                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10089                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10090                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10091                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10092
10093                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10094                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10095                         if ((tp->pdev->subsystem_vendor ==
10096                              PCI_VENDOR_ID_ARIMA) &&
10097                             (tp->pdev->subsystem_device == 0x205a ||
10098                              tp->pdev->subsystem_device == 0x2063))
10099                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10100                 } else {
10101                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10102                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10103                 }
10104
10105                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10106                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10107                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10108                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10109                 }
10110                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10111                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10112
10113                 if (cfg2 & (1 << 17))
10114                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10115
10116                 /* serdes signal pre-emphasis in register 0x590 set by */
10117                 /* bootcode if bit 18 is set */
10118                 if (cfg2 & (1 << 18))
10119                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10120         }
10121 }
10122
10123 static int __devinit tg3_phy_probe(struct tg3 *tp)
10124 {
10125         u32 hw_phy_id_1, hw_phy_id_2;
10126         u32 hw_phy_id, hw_phy_id_masked;
10127         int err;
10128
10129         /* Reading the PHY ID register can conflict with ASF
10130          * firwmare access to the PHY hardware.
10131          */
10132         err = 0;
10133         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10134                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10135         } else {
10136                 /* Now read the physical PHY_ID from the chip and verify
10137                  * that it is sane.  If it doesn't look good, we fall back
10138                  * to either the hard-coded table based PHY_ID and failing
10139                  * that the value found in the eeprom area.
10140                  */
10141                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10142                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10143
10144                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10145                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10146                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10147
10148                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10149         }
10150
10151         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10152                 tp->phy_id = hw_phy_id;
10153                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10154                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10155                 else
10156                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10157         } else {
10158                 if (tp->phy_id != PHY_ID_INVALID) {
10159                         /* Do nothing, phy ID already set up in
10160                          * tg3_get_eeprom_hw_cfg().
10161                          */
10162                 } else {
10163                         struct subsys_tbl_ent *p;
10164
10165                         /* No eeprom signature?  Try the hardcoded
10166                          * subsys device table.
10167                          */
10168                         p = lookup_by_subsys(tp);
10169                         if (!p)
10170                                 return -ENODEV;
10171
10172                         tp->phy_id = p->phy_id;
10173                         if (!tp->phy_id ||
10174                             tp->phy_id == PHY_ID_BCM8002)
10175                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10176                 }
10177         }
10178
10179         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10180             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10181                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10182
10183                 tg3_readphy(tp, MII_BMSR, &bmsr);
10184                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10185                     (bmsr & BMSR_LSTATUS))
10186                         goto skip_phy_reset;
10187
10188                 err = tg3_phy_reset(tp);
10189                 if (err)
10190                         return err;
10191
10192                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10193                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10194                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10195                 tg3_ctrl = 0;
10196                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10197                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10198                                     MII_TG3_CTRL_ADV_1000_FULL);
10199                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10200                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10201                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10202                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10203                 }
10204
10205                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10206                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10207                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10208                 if (!tg3_copper_is_advertising_all(tp, mask)) {
10209                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10210
10211                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10212                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10213
10214                         tg3_writephy(tp, MII_BMCR,
10215                                      BMCR_ANENABLE | BMCR_ANRESTART);
10216                 }
10217                 tg3_phy_set_wirespeed(tp);
10218
10219                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10220                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10221                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10222         }
10223
10224 skip_phy_reset:
10225         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10226                 err = tg3_init_5401phy_dsp(tp);
10227                 if (err)
10228                         return err;
10229         }
10230
10231         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10232                 err = tg3_init_5401phy_dsp(tp);
10233         }
10234
10235         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10236                 tp->link_config.advertising =
10237                         (ADVERTISED_1000baseT_Half |
10238                          ADVERTISED_1000baseT_Full |
10239                          ADVERTISED_Autoneg |
10240                          ADVERTISED_FIBRE);
10241         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10242                 tp->link_config.advertising &=
10243                         ~(ADVERTISED_1000baseT_Half |
10244                           ADVERTISED_1000baseT_Full);
10245
10246         return err;
10247 }
10248
10249 static void __devinit tg3_read_partno(struct tg3 *tp)
10250 {
10251         unsigned char vpd_data[256];
10252         unsigned int i;
10253         u32 magic;
10254
10255         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10256                 goto out_not_found;
10257
10258         if (magic == TG3_EEPROM_MAGIC) {
10259                 for (i = 0; i < 256; i += 4) {
10260                         u32 tmp;
10261
10262                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10263                                 goto out_not_found;
10264
10265                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10266                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10267                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10268                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10269                 }
10270         } else {
10271                 int vpd_cap;
10272
10273                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10274                 for (i = 0; i < 256; i += 4) {
10275                         u32 tmp, j = 0;
10276                         u16 tmp16;
10277
10278                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10279                                               i);
10280                         while (j++ < 100) {
10281                                 pci_read_config_word(tp->pdev, vpd_cap +
10282                                                      PCI_VPD_ADDR, &tmp16);
10283                                 if (tmp16 & 0x8000)
10284                                         break;
10285                                 msleep(1);
10286                         }
10287                         if (!(tmp16 & 0x8000))
10288                                 goto out_not_found;
10289
10290                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10291                                               &tmp);
10292                         tmp = cpu_to_le32(tmp);
10293                         memcpy(&vpd_data[i], &tmp, 4);
10294                 }
10295         }
10296
10297         /* Now parse and find the part number. */
10298         for (i = 0; i < 254; ) {
10299                 unsigned char val = vpd_data[i];
10300                 unsigned int block_end;
10301
10302                 if (val == 0x82 || val == 0x91) {
10303                         i = (i + 3 +
10304                              (vpd_data[i + 1] +
10305                               (vpd_data[i + 2] << 8)));
10306                         continue;
10307                 }
10308
10309                 if (val != 0x90)
10310                         goto out_not_found;
10311
10312                 block_end = (i + 3 +
10313                              (vpd_data[i + 1] +
10314                               (vpd_data[i + 2] << 8)));
10315                 i += 3;
10316
10317                 if (block_end > 256)
10318                         goto out_not_found;
10319
10320                 while (i < (block_end - 2)) {
10321                         if (vpd_data[i + 0] == 'P' &&
10322                             vpd_data[i + 1] == 'N') {
10323                                 int partno_len = vpd_data[i + 2];
10324
10325                                 i += 3;
10326                                 if (partno_len > 24 || (partno_len + i) > 256)
10327                                         goto out_not_found;
10328
10329                                 memcpy(tp->board_part_number,
10330                                        &vpd_data[i], partno_len);
10331
10332                                 /* Success. */
10333                                 return;
10334                         }
10335                         i += 3 + vpd_data[i + 2];
10336                 }
10337
10338                 /* Part number not found. */
10339                 goto out_not_found;
10340         }
10341
10342 out_not_found:
10343         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10344                 strcpy(tp->board_part_number, "BCM95906");
10345         else
10346                 strcpy(tp->board_part_number, "none");
10347 }
10348
10349 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10350 {
10351         u32 val, offset, start;
10352
10353         if (tg3_nvram_read_swab(tp, 0, &val))
10354                 return;
10355
10356         if (val != TG3_EEPROM_MAGIC)
10357                 return;
10358
10359         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10360             tg3_nvram_read_swab(tp, 0x4, &start))
10361                 return;
10362
10363         offset = tg3_nvram_logical_addr(tp, offset);
10364         if (tg3_nvram_read_swab(tp, offset, &val))
10365                 return;
10366
10367         if ((val & 0xfc000000) == 0x0c000000) {
10368                 u32 ver_offset, addr;
10369                 int i;
10370
10371                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10372                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10373                         return;
10374
10375                 if (val != 0)
10376                         return;
10377
10378                 addr = offset + ver_offset - start;
10379                 for (i = 0; i < 16; i += 4) {
10380                         if (tg3_nvram_read(tp, addr + i, &val))
10381                                 return;
10382
10383                         val = cpu_to_le32(val);
10384                         memcpy(tp->fw_ver + i, &val, 4);
10385                 }
10386         }
10387 }
10388
10389 static int __devinit tg3_get_invariants(struct tg3 *tp)
10390 {
10391         static struct pci_device_id write_reorder_chipsets[] = {
10392                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10393                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10394                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10395                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10396                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10397                              PCI_DEVICE_ID_VIA_8385_0) },
10398                 { },
10399         };
10400         u32 misc_ctrl_reg;
10401         u32 cacheline_sz_reg;
10402         u32 pci_state_reg, grc_misc_cfg;
10403         u32 val;
10404         u16 pci_cmd;
10405         int err, pcie_cap;
10406
10407         /* Force memory write invalidate off.  If we leave it on,
10408          * then on 5700_BX chips we have to enable a workaround.
10409          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10410          * to match the cacheline size.  The Broadcom driver have this
10411          * workaround but turns MWI off all the times so never uses
10412          * it.  This seems to suggest that the workaround is insufficient.
10413          */
10414         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10415         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10416         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10417
10418         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10419          * has the register indirect write enable bit set before
10420          * we try to access any of the MMIO registers.  It is also
10421          * critical that the PCI-X hw workaround situation is decided
10422          * before that as well.
10423          */
10424         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10425                               &misc_ctrl_reg);
10426
10427         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10428                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10429
10430         /* Wrong chip ID in 5752 A0. This code can be removed later
10431          * as A0 is not in production.
10432          */
10433         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10434                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10435
10436         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10437          * we need to disable memory and use config. cycles
10438          * only to access all registers. The 5702/03 chips
10439          * can mistakenly decode the special cycles from the
10440          * ICH chipsets as memory write cycles, causing corruption
10441          * of register and memory space. Only certain ICH bridges
10442          * will drive special cycles with non-zero data during the
10443          * address phase which can fall within the 5703's address
10444          * range. This is not an ICH bug as the PCI spec allows
10445          * non-zero address during special cycles. However, only
10446          * these ICH bridges are known to drive non-zero addresses
10447          * during special cycles.
10448          *
10449          * Since special cycles do not cross PCI bridges, we only
10450          * enable this workaround if the 5703 is on the secondary
10451          * bus of these ICH bridges.
10452          */
10453         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10454             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10455                 static struct tg3_dev_id {
10456                         u32     vendor;
10457                         u32     device;
10458                         u32     rev;
10459                 } ich_chipsets[] = {
10460                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10461                           PCI_ANY_ID },
10462                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10463                           PCI_ANY_ID },
10464                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10465                           0xa },
10466                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10467                           PCI_ANY_ID },
10468                         { },
10469                 };
10470                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10471                 struct pci_dev *bridge = NULL;
10472
10473                 while (pci_id->vendor != 0) {
10474                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10475                                                 bridge);
10476                         if (!bridge) {
10477                                 pci_id++;
10478                                 continue;
10479                         }
10480                         if (pci_id->rev != PCI_ANY_ID) {
10481                                 u8 rev;
10482
10483                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10484                                                      &rev);
10485                                 if (rev > pci_id->rev)
10486                                         continue;
10487                         }
10488                         if (bridge->subordinate &&
10489                             (bridge->subordinate->number ==
10490                              tp->pdev->bus->number)) {
10491
10492                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10493                                 pci_dev_put(bridge);
10494                                 break;
10495                         }
10496                 }
10497         }
10498
10499         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10500          * DMA addresses > 40-bit. This bridge may have other additional
10501          * 57xx devices behind it in some 4-port NIC designs for example.
10502          * Any tg3 device found behind the bridge will also need the 40-bit
10503          * DMA workaround.
10504          */
10505         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10506             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10507                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10508                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10509                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10510         }
10511         else {
10512                 struct pci_dev *bridge = NULL;
10513
10514                 do {
10515                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10516                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10517                                                 bridge);
10518                         if (bridge && bridge->subordinate &&
10519                             (bridge->subordinate->number <=
10520                              tp->pdev->bus->number) &&
10521                             (bridge->subordinate->subordinate >=
10522                              tp->pdev->bus->number)) {
10523                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10524                                 pci_dev_put(bridge);
10525                                 break;
10526                         }
10527                 } while (bridge);
10528         }
10529
10530         /* Initialize misc host control in PCI block. */
10531         tp->misc_host_ctrl |= (misc_ctrl_reg &
10532                                MISC_HOST_CTRL_CHIPREV);
10533         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10534                                tp->misc_host_ctrl);
10535
10536         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10537                               &cacheline_sz_reg);
10538
10539         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10540         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10541         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10542         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10543
10544         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10545             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10546             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10547             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10548             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10549             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10550                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10551
10552         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10553             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10554                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10555
10556         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10557                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10558                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10559                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10560                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10561                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10562                 } else {
10563                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10564                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10565                                 ASIC_REV_5750 &&
10566                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10567                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10568                 }
10569         }
10570
10571         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10572             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10573             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10574             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10575             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10576             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10577                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10578
10579         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10580         if (pcie_cap != 0) {
10581                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10582                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10583                         u16 lnkctl;
10584
10585                         pci_read_config_word(tp->pdev,
10586                                              pcie_cap + PCI_EXP_LNKCTL,
10587                                              &lnkctl);
10588                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10589                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10590                 }
10591         }
10592
10593         /* If we have an AMD 762 or VIA K8T800 chipset, write
10594          * reordering to the mailbox registers done by the host
10595          * controller can cause major troubles.  We read back from
10596          * every mailbox register write to force the writes to be
10597          * posted to the chip in order.
10598          */
10599         if (pci_dev_present(write_reorder_chipsets) &&
10600             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10601                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10602
10603         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10604             tp->pci_lat_timer < 64) {
10605                 tp->pci_lat_timer = 64;
10606
10607                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10608                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10609                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10610                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10611
10612                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10613                                        cacheline_sz_reg);
10614         }
10615
10616         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10617                               &pci_state_reg);
10618
10619         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10620                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10621
10622                 /* If this is a 5700 BX chipset, and we are in PCI-X
10623                  * mode, enable register write workaround.
10624                  *
10625                  * The workaround is to use indirect register accesses
10626                  * for all chip writes not to mailbox registers.
10627                  */
10628                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10629                         u32 pm_reg;
10630                         u16 pci_cmd;
10631
10632                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10633
10634                         /* The chip can have it's power management PCI config
10635                          * space registers clobbered due to this bug.
10636                          * So explicitly force the chip into D0 here.
10637                          */
10638                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10639                                               &pm_reg);
10640                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10641                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10642                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10643                                                pm_reg);
10644
10645                         /* Also, force SERR#/PERR# in PCI command. */
10646                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10647                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10648                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10649                 }
10650         }
10651
10652         /* 5700 BX chips need to have their TX producer index mailboxes
10653          * written twice to workaround a bug.
10654          */
10655         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10656                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10657
10658         /* Back to back register writes can cause problems on this chip,
10659          * the workaround is to read back all reg writes except those to
10660          * mailbox regs.  See tg3_write_indirect_reg32().
10661          *
10662          * PCI Express 5750_A0 rev chips need this workaround too.
10663          */
10664         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10665             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10666              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10667                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10668
10669         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10670                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10671         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10672                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10673
10674         /* Chip-specific fixup from Broadcom driver */
10675         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10676             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10677                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10678                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10679         }
10680
10681         /* Default fast path register access methods */
10682         tp->read32 = tg3_read32;
10683         tp->write32 = tg3_write32;
10684         tp->read32_mbox = tg3_read32;
10685         tp->write32_mbox = tg3_write32;
10686         tp->write32_tx_mbox = tg3_write32;
10687         tp->write32_rx_mbox = tg3_write32;
10688
10689         /* Various workaround register access methods */
10690         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10691                 tp->write32 = tg3_write_indirect_reg32;
10692         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10693                 tp->write32 = tg3_write_flush_reg32;
10694
10695         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10696             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10697                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10698                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10699                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10700         }
10701
10702         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10703                 tp->read32 = tg3_read_indirect_reg32;
10704                 tp->write32 = tg3_write_indirect_reg32;
10705                 tp->read32_mbox = tg3_read_indirect_mbox;
10706                 tp->write32_mbox = tg3_write_indirect_mbox;
10707                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10708                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10709
10710                 iounmap(tp->regs);
10711                 tp->regs = NULL;
10712
10713                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10714                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10715                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10716         }
10717         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10718                 tp->read32_mbox = tg3_read32_mbox_5906;
10719                 tp->write32_mbox = tg3_write32_mbox_5906;
10720                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10721                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10722         }
10723
10724         if (tp->write32 == tg3_write_indirect_reg32 ||
10725             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10726              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10727               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10728                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10729
10730         /* Get eeprom hw config before calling tg3_set_power_state().
10731          * In particular, the TG3_FLG2_IS_NIC flag must be
10732          * determined before calling tg3_set_power_state() so that
10733          * we know whether or not to switch out of Vaux power.
10734          * When the flag is set, it means that GPIO1 is used for eeprom
10735          * write protect and also implies that it is a LOM where GPIOs
10736          * are not used to switch power.
10737          */
10738         tg3_get_eeprom_hw_cfg(tp);
10739
10740         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10741          * GPIO1 driven high will bring 5700's external PHY out of reset.
10742          * It is also used as eeprom write protect on LOMs.
10743          */
10744         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10745         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10746             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10747                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10748                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10749         /* Unused GPIO3 must be driven as output on 5752 because there
10750          * are no pull-up resistors on unused GPIO pins.
10751          */
10752         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10753                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10754
10755         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10756                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10757
10758         /* Force the chip into D0. */
10759         err = tg3_set_power_state(tp, PCI_D0);
10760         if (err) {
10761                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10762                        pci_name(tp->pdev));
10763                 return err;
10764         }
10765
10766         /* 5700 B0 chips do not support checksumming correctly due
10767          * to hardware bugs.
10768          */
10769         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10770                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10771
10772         /* Derive initial jumbo mode from MTU assigned in
10773          * ether_setup() via the alloc_etherdev() call
10774          */
10775         if (tp->dev->mtu > ETH_DATA_LEN &&
10776             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10777                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10778
10779         /* Determine WakeOnLan speed to use. */
10780         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10781             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10782             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10783             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10784                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10785         } else {
10786                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10787         }
10788
10789         /* A few boards don't want Ethernet@WireSpeed phy feature */
10790         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10791             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10792              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10793              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10794             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10795             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10796                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10797
10798         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10799             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10800                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10801         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10802                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10803
10804         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10805                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10806                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10807                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10808                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10809                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10810                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10811                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10812                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10813                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10814         }
10815
10816         tp->coalesce_mode = 0;
10817         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10818             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10819                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10820
10821         /* Initialize MAC MI mode, polling disabled. */
10822         tw32_f(MAC_MI_MODE, tp->mi_mode);
10823         udelay(80);
10824
10825         /* Initialize data/descriptor byte/word swapping. */
10826         val = tr32(GRC_MODE);
10827         val &= GRC_MODE_HOST_STACKUP;
10828         tw32(GRC_MODE, val | tp->grc_mode);
10829
10830         tg3_switch_clocks(tp);
10831
10832         /* Clear this out for sanity. */
10833         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10834
10835         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10836                               &pci_state_reg);
10837         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10838             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10839                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10840
10841                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10842                     chiprevid == CHIPREV_ID_5701_B0 ||
10843                     chiprevid == CHIPREV_ID_5701_B2 ||
10844                     chiprevid == CHIPREV_ID_5701_B5) {
10845                         void __iomem *sram_base;
10846
10847                         /* Write some dummy words into the SRAM status block
10848                          * area, see if it reads back correctly.  If the return
10849                          * value is bad, force enable the PCIX workaround.
10850                          */
10851                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10852
10853                         writel(0x00000000, sram_base);
10854                         writel(0x00000000, sram_base + 4);
10855                         writel(0xffffffff, sram_base + 4);
10856                         if (readl(sram_base) != 0x00000000)
10857                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10858                 }
10859         }
10860
10861         udelay(50);
10862         tg3_nvram_init(tp);
10863
10864         grc_misc_cfg = tr32(GRC_MISC_CFG);
10865         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10866
10867         /* Broadcom's driver says that CIOBE multisplit has a bug */
10868 #if 0
10869         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10870             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10871                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10872                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10873         }
10874 #endif
10875         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10876             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10877              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10878                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10879
10880         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10881             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10882                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10883         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10884                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10885                                       HOSTCC_MODE_CLRTICK_TXBD);
10886
10887                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10888                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10889                                        tp->misc_host_ctrl);
10890         }
10891
10892         /* these are limited to 10/100 only */
10893         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10894              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10895             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10896              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10897              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10898               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10899               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10900             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10901              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10902               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10903               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10904             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10905                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10906
10907         err = tg3_phy_probe(tp);
10908         if (err) {
10909                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10910                        pci_name(tp->pdev), err);
10911                 /* ... but do not return immediately ... */
10912         }
10913
10914         tg3_read_partno(tp);
10915         tg3_read_fw_ver(tp);
10916
10917         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10918                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10919         } else {
10920                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10921                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10922                 else
10923                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10924         }
10925
10926         /* 5700 {AX,BX} chips have a broken status block link
10927          * change bit implementation, so we must use the
10928          * status register in those cases.
10929          */
10930         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10931                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10932         else
10933                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10934
10935         /* The led_ctrl is set during tg3_phy_probe, here we might
10936          * have to force the link status polling mechanism based
10937          * upon subsystem IDs.
10938          */
10939         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10940             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10941                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10942                                   TG3_FLAG_USE_LINKCHG_REG);
10943         }
10944
10945         /* For all SERDES we poll the MAC status register. */
10946         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10947                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10948         else
10949                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10950
10951         /* All chips before 5787 can get confused if TX buffers
10952          * straddle the 4GB address boundary in some cases.
10953          */
10954         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10955             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10956             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10957                 tp->dev->hard_start_xmit = tg3_start_xmit;
10958         else
10959                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10960
10961         tp->rx_offset = 2;
10962         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10963             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10964                 tp->rx_offset = 0;
10965
10966         tp->rx_std_max_post = TG3_RX_RING_SIZE;
10967
10968         /* Increment the rx prod index on the rx std ring by at most
10969          * 8 for these chips to workaround hw errata.
10970          */
10971         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10972             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10973             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10974                 tp->rx_std_max_post = 8;
10975
10976         /* By default, disable wake-on-lan.  User can change this
10977          * using ETHTOOL_SWOL.
10978          */
10979         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10980
10981         return err;
10982 }
10983
10984 #ifdef CONFIG_SPARC64
10985 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10986 {
10987         struct net_device *dev = tp->dev;
10988         struct pci_dev *pdev = tp->pdev;
10989         struct pcidev_cookie *pcp = pdev->sysdata;
10990
10991         if (pcp != NULL) {
10992                 unsigned char *addr;
10993                 int len;
10994
10995                 addr = of_get_property(pcp->prom_node, "local-mac-address",
10996                                         &len);
10997                 if (addr && len == 6) {
10998                         memcpy(dev->dev_addr, addr, 6);
10999                         memcpy(dev->perm_addr, dev->dev_addr, 6);
11000                         return 0;
11001                 }
11002         }
11003         return -ENODEV;
11004 }
11005
11006 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11007 {
11008         struct net_device *dev = tp->dev;
11009
11010         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11011         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11012         return 0;
11013 }
11014 #endif
11015
11016 static int __devinit tg3_get_device_address(struct tg3 *tp)
11017 {
11018         struct net_device *dev = tp->dev;
11019         u32 hi, lo, mac_offset;
11020         int addr_ok = 0;
11021
11022 #ifdef CONFIG_SPARC64
11023         if (!tg3_get_macaddr_sparc(tp))
11024                 return 0;
11025 #endif
11026
11027         mac_offset = 0x7c;
11028         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11029             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11030                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11031                         mac_offset = 0xcc;
11032                 if (tg3_nvram_lock(tp))
11033                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11034                 else
11035                         tg3_nvram_unlock(tp);
11036         }
11037         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11038                 mac_offset = 0x10;
11039
11040         /* First try to get it from MAC address mailbox. */
11041         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11042         if ((hi >> 16) == 0x484b) {
11043                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11044                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11045
11046                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11047                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11048                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11049                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11050                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11051
11052                 /* Some old bootcode may report a 0 MAC address in SRAM */
11053                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11054         }
11055         if (!addr_ok) {
11056                 /* Next, try NVRAM. */
11057                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11058                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11059                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11060                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11061                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11062                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11063                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11064                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11065                 }
11066                 /* Finally just fetch it out of the MAC control regs. */
11067                 else {
11068                         hi = tr32(MAC_ADDR_0_HIGH);
11069                         lo = tr32(MAC_ADDR_0_LOW);
11070
11071                         dev->dev_addr[5] = lo & 0xff;
11072                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11073                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11074                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11075                         dev->dev_addr[1] = hi & 0xff;
11076                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11077                 }
11078         }
11079
11080         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11081 #ifdef CONFIG_SPARC64
11082                 if (!tg3_get_default_macaddr_sparc(tp))
11083                         return 0;
11084 #endif
11085                 return -EINVAL;
11086         }
11087         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11088         return 0;
11089 }
11090
11091 #define BOUNDARY_SINGLE_CACHELINE       1
11092 #define BOUNDARY_MULTI_CACHELINE        2
11093
11094 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11095 {
11096         int cacheline_size;
11097         u8 byte;
11098         int goal;
11099
11100         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11101         if (byte == 0)
11102                 cacheline_size = 1024;
11103         else
11104                 cacheline_size = (int) byte * 4;
11105
11106         /* On 5703 and later chips, the boundary bits have no
11107          * effect.
11108          */
11109         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11110             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11111             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11112                 goto out;
11113
11114 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11115         goal = BOUNDARY_MULTI_CACHELINE;
11116 #else
11117 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11118         goal = BOUNDARY_SINGLE_CACHELINE;
11119 #else
11120         goal = 0;
11121 #endif
11122 #endif
11123
11124         if (!goal)
11125                 goto out;
11126
11127         /* PCI controllers on most RISC systems tend to disconnect
11128          * when a device tries to burst across a cache-line boundary.
11129          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11130          *
11131          * Unfortunately, for PCI-E there are only limited
11132          * write-side controls for this, and thus for reads
11133          * we will still get the disconnects.  We'll also waste
11134          * these PCI cycles for both read and write for chips
11135          * other than 5700 and 5701 which do not implement the
11136          * boundary bits.
11137          */
11138         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11139             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11140                 switch (cacheline_size) {
11141                 case 16:
11142                 case 32:
11143                 case 64:
11144                 case 128:
11145                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11146                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11147                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11148                         } else {
11149                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11150                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11151                         }
11152                         break;
11153
11154                 case 256:
11155                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11156                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11157                         break;
11158
11159                 default:
11160                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11161                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11162                         break;
11163                 };
11164         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11165                 switch (cacheline_size) {
11166                 case 16:
11167                 case 32:
11168                 case 64:
11169                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11170                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11171                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11172                                 break;
11173                         }
11174                         /* fallthrough */
11175                 case 128:
11176                 default:
11177                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11178                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11179                         break;
11180                 };
11181         } else {
11182                 switch (cacheline_size) {
11183                 case 16:
11184                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11185                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11186                                         DMA_RWCTRL_WRITE_BNDRY_16);
11187                                 break;
11188                         }
11189                         /* fallthrough */
11190                 case 32:
11191                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11192                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11193                                         DMA_RWCTRL_WRITE_BNDRY_32);
11194                                 break;
11195                         }
11196                         /* fallthrough */
11197                 case 64:
11198                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11199                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11200                                         DMA_RWCTRL_WRITE_BNDRY_64);
11201                                 break;
11202                         }
11203                         /* fallthrough */
11204                 case 128:
11205                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11206                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11207                                         DMA_RWCTRL_WRITE_BNDRY_128);
11208                                 break;
11209                         }
11210                         /* fallthrough */
11211                 case 256:
11212                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11213                                 DMA_RWCTRL_WRITE_BNDRY_256);
11214                         break;
11215                 case 512:
11216                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11217                                 DMA_RWCTRL_WRITE_BNDRY_512);
11218                         break;
11219                 case 1024:
11220                 default:
11221                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11222                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11223                         break;
11224                 };
11225         }
11226
11227 out:
11228         return val;
11229 }
11230
11231 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11232 {
11233         struct tg3_internal_buffer_desc test_desc;
11234         u32 sram_dma_descs;
11235         int i, ret;
11236
11237         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11238
11239         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11240         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11241         tw32(RDMAC_STATUS, 0);
11242         tw32(WDMAC_STATUS, 0);
11243
11244         tw32(BUFMGR_MODE, 0);
11245         tw32(FTQ_RESET, 0);
11246
11247         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11248         test_desc.addr_lo = buf_dma & 0xffffffff;
11249         test_desc.nic_mbuf = 0x00002100;
11250         test_desc.len = size;
11251
11252         /*
11253          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11254          * the *second* time the tg3 driver was getting loaded after an
11255          * initial scan.
11256          *
11257          * Broadcom tells me:
11258          *   ...the DMA engine is connected to the GRC block and a DMA
11259          *   reset may affect the GRC block in some unpredictable way...
11260          *   The behavior of resets to individual blocks has not been tested.
11261          *
11262          * Broadcom noted the GRC reset will also reset all sub-components.
11263          */
11264         if (to_device) {
11265                 test_desc.cqid_sqid = (13 << 8) | 2;
11266
11267                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11268                 udelay(40);
11269         } else {
11270                 test_desc.cqid_sqid = (16 << 8) | 7;
11271
11272                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11273                 udelay(40);
11274         }
11275         test_desc.flags = 0x00000005;
11276
11277         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11278                 u32 val;
11279
11280                 val = *(((u32 *)&test_desc) + i);
11281                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11282                                        sram_dma_descs + (i * sizeof(u32)));
11283                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11284         }
11285         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11286
11287         if (to_device) {
11288                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11289         } else {
11290                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11291         }
11292
11293         ret = -ENODEV;
11294         for (i = 0; i < 40; i++) {
11295                 u32 val;
11296
11297                 if (to_device)
11298                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11299                 else
11300                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11301                 if ((val & 0xffff) == sram_dma_descs) {
11302                         ret = 0;
11303                         break;
11304                 }
11305
11306                 udelay(100);
11307         }
11308
11309         return ret;
11310 }
11311
11312 #define TEST_BUFFER_SIZE        0x2000
11313
11314 static int __devinit tg3_test_dma(struct tg3 *tp)
11315 {
11316         dma_addr_t buf_dma;
11317         u32 *buf, saved_dma_rwctrl;
11318         int ret;
11319
11320         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11321         if (!buf) {
11322                 ret = -ENOMEM;
11323                 goto out_nofree;
11324         }
11325
11326         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11327                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11328
11329         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11330
11331         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11332                 /* DMA read watermark not used on PCIE */
11333                 tp->dma_rwctrl |= 0x00180000;
11334         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11335                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11336                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11337                         tp->dma_rwctrl |= 0x003f0000;
11338                 else
11339                         tp->dma_rwctrl |= 0x003f000f;
11340         } else {
11341                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11342                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11343                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11344                         u32 read_water = 0x7;
11345
11346                         /* If the 5704 is behind the EPB bridge, we can
11347                          * do the less restrictive ONE_DMA workaround for
11348                          * better performance.
11349                          */
11350                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11351                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11352                                 tp->dma_rwctrl |= 0x8000;
11353                         else if (ccval == 0x6 || ccval == 0x7)
11354                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11355
11356                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11357                                 read_water = 4;
11358                         /* Set bit 23 to enable PCIX hw bug fix */
11359                         tp->dma_rwctrl |=
11360                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11361                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11362                                 (1 << 23);
11363                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11364                         /* 5780 always in PCIX mode */
11365                         tp->dma_rwctrl |= 0x00144000;
11366                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11367                         /* 5714 always in PCIX mode */
11368                         tp->dma_rwctrl |= 0x00148000;
11369                 } else {
11370                         tp->dma_rwctrl |= 0x001b000f;
11371                 }
11372         }
11373
11374         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11375             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11376                 tp->dma_rwctrl &= 0xfffffff0;
11377
11378         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11379             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11380                 /* Remove this if it causes problems for some boards. */
11381                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11382
11383                 /* On 5700/5701 chips, we need to set this bit.
11384                  * Otherwise the chip will issue cacheline transactions
11385                  * to streamable DMA memory with not all the byte
11386                  * enables turned on.  This is an error on several
11387                  * RISC PCI controllers, in particular sparc64.
11388                  *
11389                  * On 5703/5704 chips, this bit has been reassigned
11390                  * a different meaning.  In particular, it is used
11391                  * on those chips to enable a PCI-X workaround.
11392                  */
11393                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11394         }
11395
11396         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11397
11398 #if 0
11399         /* Unneeded, already done by tg3_get_invariants.  */
11400         tg3_switch_clocks(tp);
11401 #endif
11402
11403         ret = 0;
11404         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11405             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11406                 goto out;
11407
11408         /* It is best to perform DMA test with maximum write burst size
11409          * to expose the 5700/5701 write DMA bug.
11410          */
11411         saved_dma_rwctrl = tp->dma_rwctrl;
11412         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11413         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11414
11415         while (1) {
11416                 u32 *p = buf, i;
11417
11418                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11419                         p[i] = i;
11420
11421                 /* Send the buffer to the chip. */
11422                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11423                 if (ret) {
11424                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11425                         break;
11426                 }
11427
11428 #if 0
11429                 /* validate data reached card RAM correctly. */
11430                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11431                         u32 val;
11432                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11433                         if (le32_to_cpu(val) != p[i]) {
11434                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11435                                 /* ret = -ENODEV here? */
11436                         }
11437                         p[i] = 0;
11438                 }
11439 #endif
11440                 /* Now read it back. */
11441                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11442                 if (ret) {
11443                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11444
11445                         break;
11446                 }
11447
11448                 /* Verify it. */
11449                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11450                         if (p[i] == i)
11451                                 continue;
11452
11453                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11454                             DMA_RWCTRL_WRITE_BNDRY_16) {
11455                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11456                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11457                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11458                                 break;
11459                         } else {
11460                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11461                                 ret = -ENODEV;
11462                                 goto out;
11463                         }
11464                 }
11465
11466                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11467                         /* Success. */
11468                         ret = 0;
11469                         break;
11470                 }
11471         }
11472         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11473             DMA_RWCTRL_WRITE_BNDRY_16) {
11474                 static struct pci_device_id dma_wait_state_chipsets[] = {
11475                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11476                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11477                         { },
11478                 };
11479
11480                 /* DMA test passed without adjusting DMA boundary,
11481                  * now look for chipsets that are known to expose the
11482                  * DMA bug without failing the test.
11483                  */
11484                 if (pci_dev_present(dma_wait_state_chipsets)) {
11485                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11486                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11487                 }
11488                 else
11489                         /* Safe to use the calculated DMA boundary. */
11490                         tp->dma_rwctrl = saved_dma_rwctrl;
11491
11492                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11493         }
11494
11495 out:
11496         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11497 out_nofree:
11498         return ret;
11499 }
11500
11501 static void __devinit tg3_init_link_config(struct tg3 *tp)
11502 {
11503         tp->link_config.advertising =
11504                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11505                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11506                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11507                  ADVERTISED_Autoneg | ADVERTISED_MII);
11508         tp->link_config.speed = SPEED_INVALID;
11509         tp->link_config.duplex = DUPLEX_INVALID;
11510         tp->link_config.autoneg = AUTONEG_ENABLE;
11511         tp->link_config.active_speed = SPEED_INVALID;
11512         tp->link_config.active_duplex = DUPLEX_INVALID;
11513         tp->link_config.phy_is_low_power = 0;
11514         tp->link_config.orig_speed = SPEED_INVALID;
11515         tp->link_config.orig_duplex = DUPLEX_INVALID;
11516         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11517 }
11518
11519 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11520 {
11521         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11522                 tp->bufmgr_config.mbuf_read_dma_low_water =
11523                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11524                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11525                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11526                 tp->bufmgr_config.mbuf_high_water =
11527                         DEFAULT_MB_HIGH_WATER_5705;
11528                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11529                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11530                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11531                         tp->bufmgr_config.mbuf_high_water =
11532                                 DEFAULT_MB_HIGH_WATER_5906;
11533                 }
11534
11535                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11536                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11537                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11538                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11539                 tp->bufmgr_config.mbuf_high_water_jumbo =
11540                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11541         } else {
11542                 tp->bufmgr_config.mbuf_read_dma_low_water =
11543                         DEFAULT_MB_RDMA_LOW_WATER;
11544                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11545                         DEFAULT_MB_MACRX_LOW_WATER;
11546                 tp->bufmgr_config.mbuf_high_water =
11547                         DEFAULT_MB_HIGH_WATER;
11548
11549                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11550                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11551                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11552                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11553                 tp->bufmgr_config.mbuf_high_water_jumbo =
11554                         DEFAULT_MB_HIGH_WATER_JUMBO;
11555         }
11556
11557         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11558         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11559 }
11560
11561 static char * __devinit tg3_phy_string(struct tg3 *tp)
11562 {
11563         switch (tp->phy_id & PHY_ID_MASK) {
11564         case PHY_ID_BCM5400:    return "5400";
11565         case PHY_ID_BCM5401:    return "5401";
11566         case PHY_ID_BCM5411:    return "5411";
11567         case PHY_ID_BCM5701:    return "5701";
11568         case PHY_ID_BCM5703:    return "5703";
11569         case PHY_ID_BCM5704:    return "5704";
11570         case PHY_ID_BCM5705:    return "5705";
11571         case PHY_ID_BCM5750:    return "5750";
11572         case PHY_ID_BCM5752:    return "5752";
11573         case PHY_ID_BCM5714:    return "5714";
11574         case PHY_ID_BCM5780:    return "5780";
11575         case PHY_ID_BCM5755:    return "5755";
11576         case PHY_ID_BCM5787:    return "5787";
11577         case PHY_ID_BCM5756:    return "5722/5756";
11578         case PHY_ID_BCM5906:    return "5906";
11579         case PHY_ID_BCM8002:    return "8002/serdes";
11580         case 0:                 return "serdes";
11581         default:                return "unknown";
11582         };
11583 }
11584
11585 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11586 {
11587         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11588                 strcpy(str, "PCI Express");
11589                 return str;
11590         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11591                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11592
11593                 strcpy(str, "PCIX:");
11594
11595                 if ((clock_ctrl == 7) ||
11596                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11597                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11598                         strcat(str, "133MHz");
11599                 else if (clock_ctrl == 0)
11600                         strcat(str, "33MHz");
11601                 else if (clock_ctrl == 2)
11602                         strcat(str, "50MHz");
11603                 else if (clock_ctrl == 4)
11604                         strcat(str, "66MHz");
11605                 else if (clock_ctrl == 6)
11606                         strcat(str, "100MHz");
11607         } else {
11608                 strcpy(str, "PCI:");
11609                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11610                         strcat(str, "66MHz");
11611                 else
11612                         strcat(str, "33MHz");
11613         }
11614         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11615                 strcat(str, ":32-bit");
11616         else
11617                 strcat(str, ":64-bit");
11618         return str;
11619 }
11620
11621 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11622 {
11623         struct pci_dev *peer;
11624         unsigned int func, devnr = tp->pdev->devfn & ~7;
11625
11626         for (func = 0; func < 8; func++) {
11627                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11628                 if (peer && peer != tp->pdev)
11629                         break;
11630                 pci_dev_put(peer);
11631         }
11632         /* 5704 can be configured in single-port mode, set peer to
11633          * tp->pdev in that case.
11634          */
11635         if (!peer) {
11636                 peer = tp->pdev;
11637                 return peer;
11638         }
11639
11640         /*
11641          * We don't need to keep the refcount elevated; there's no way
11642          * to remove one half of this device without removing the other
11643          */
11644         pci_dev_put(peer);
11645
11646         return peer;
11647 }
11648
11649 static void __devinit tg3_init_coal(struct tg3 *tp)
11650 {
11651         struct ethtool_coalesce *ec = &tp->coal;
11652
11653         memset(ec, 0, sizeof(*ec));
11654         ec->cmd = ETHTOOL_GCOALESCE;
11655         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11656         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11657         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11658         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11659         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11660         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11661         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11662         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11663         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11664
11665         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11666                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11667                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11668                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11669                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11670                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11671         }
11672
11673         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11674                 ec->rx_coalesce_usecs_irq = 0;
11675                 ec->tx_coalesce_usecs_irq = 0;
11676                 ec->stats_block_coalesce_usecs = 0;
11677         }
11678 }
11679
11680 static int __devinit tg3_init_one(struct pci_dev *pdev,
11681                                   const struct pci_device_id *ent)
11682 {
11683         static int tg3_version_printed = 0;
11684         unsigned long tg3reg_base, tg3reg_len;
11685         struct net_device *dev;
11686         struct tg3 *tp;
11687         int i, err, pm_cap;
11688         char str[40];
11689         u64 dma_mask, persist_dma_mask;
11690
11691         if (tg3_version_printed++ == 0)
11692                 printk(KERN_INFO "%s", version);
11693
11694         err = pci_enable_device(pdev);
11695         if (err) {
11696                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11697                        "aborting.\n");
11698                 return err;
11699         }
11700
11701         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11702                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11703                        "base address, aborting.\n");
11704                 err = -ENODEV;
11705                 goto err_out_disable_pdev;
11706         }
11707
11708         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11709         if (err) {
11710                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11711                        "aborting.\n");
11712                 goto err_out_disable_pdev;
11713         }
11714
11715         pci_set_master(pdev);
11716
11717         /* Find power-management capability. */
11718         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11719         if (pm_cap == 0) {
11720                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11721                        "aborting.\n");
11722                 err = -EIO;
11723                 goto err_out_free_res;
11724         }
11725
11726         tg3reg_base = pci_resource_start(pdev, 0);
11727         tg3reg_len = pci_resource_len(pdev, 0);
11728
11729         dev = alloc_etherdev(sizeof(*tp));
11730         if (!dev) {
11731                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11732                 err = -ENOMEM;
11733                 goto err_out_free_res;
11734         }
11735
11736         SET_MODULE_OWNER(dev);
11737         SET_NETDEV_DEV(dev, &pdev->dev);
11738
11739 #if TG3_VLAN_TAG_USED
11740         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11741         dev->vlan_rx_register = tg3_vlan_rx_register;
11742         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11743 #endif
11744
11745         tp = netdev_priv(dev);
11746         tp->pdev = pdev;
11747         tp->dev = dev;
11748         tp->pm_cap = pm_cap;
11749         tp->mac_mode = TG3_DEF_MAC_MODE;
11750         tp->rx_mode = TG3_DEF_RX_MODE;
11751         tp->tx_mode = TG3_DEF_TX_MODE;
11752         tp->mi_mode = MAC_MI_MODE_BASE;
11753         if (tg3_debug > 0)
11754                 tp->msg_enable = tg3_debug;
11755         else
11756                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11757
11758         /* The word/byte swap controls here control register access byte
11759          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11760          * setting below.
11761          */
11762         tp->misc_host_ctrl =
11763                 MISC_HOST_CTRL_MASK_PCI_INT |
11764                 MISC_HOST_CTRL_WORD_SWAP |
11765                 MISC_HOST_CTRL_INDIR_ACCESS |
11766                 MISC_HOST_CTRL_PCISTATE_RW;
11767
11768         /* The NONFRM (non-frame) byte/word swap controls take effect
11769          * on descriptor entries, anything which isn't packet data.
11770          *
11771          * The StrongARM chips on the board (one for tx, one for rx)
11772          * are running in big-endian mode.
11773          */
11774         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11775                         GRC_MODE_WSWAP_NONFRM_DATA);
11776 #ifdef __BIG_ENDIAN
11777         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11778 #endif
11779         spin_lock_init(&tp->lock);
11780         spin_lock_init(&tp->indirect_lock);
11781         INIT_WORK(&tp->reset_task, tg3_reset_task);
11782
11783         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11784         if (tp->regs == 0UL) {
11785                 printk(KERN_ERR PFX "Cannot map device registers, "
11786                        "aborting.\n");
11787                 err = -ENOMEM;
11788                 goto err_out_free_dev;
11789         }
11790
11791         tg3_init_link_config(tp);
11792
11793         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11794         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11795         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11796
11797         dev->open = tg3_open;
11798         dev->stop = tg3_close;
11799         dev->get_stats = tg3_get_stats;
11800         dev->set_multicast_list = tg3_set_rx_mode;
11801         dev->set_mac_address = tg3_set_mac_addr;
11802         dev->do_ioctl = tg3_ioctl;
11803         dev->tx_timeout = tg3_tx_timeout;
11804         dev->poll = tg3_poll;
11805         dev->ethtool_ops = &tg3_ethtool_ops;
11806         dev->weight = 64;
11807         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11808         dev->change_mtu = tg3_change_mtu;
11809         dev->irq = pdev->irq;
11810 #ifdef CONFIG_NET_POLL_CONTROLLER
11811         dev->poll_controller = tg3_poll_controller;
11812 #endif
11813
11814         err = tg3_get_invariants(tp);
11815         if (err) {
11816                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11817                        "aborting.\n");
11818                 goto err_out_iounmap;
11819         }
11820
11821         /* The EPB bridge inside 5714, 5715, and 5780 and any
11822          * device behind the EPB cannot support DMA addresses > 40-bit.
11823          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11824          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11825          * do DMA address check in tg3_start_xmit().
11826          */
11827         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11828                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11829         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11830                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11831 #ifdef CONFIG_HIGHMEM
11832                 dma_mask = DMA_64BIT_MASK;
11833 #endif
11834         } else
11835                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11836
11837         /* Configure DMA attributes. */
11838         if (dma_mask > DMA_32BIT_MASK) {
11839                 err = pci_set_dma_mask(pdev, dma_mask);
11840                 if (!err) {
11841                         dev->features |= NETIF_F_HIGHDMA;
11842                         err = pci_set_consistent_dma_mask(pdev,
11843                                                           persist_dma_mask);
11844                         if (err < 0) {
11845                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11846                                        "DMA for consistent allocations\n");
11847                                 goto err_out_iounmap;
11848                         }
11849                 }
11850         }
11851         if (err || dma_mask == DMA_32BIT_MASK) {
11852                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11853                 if (err) {
11854                         printk(KERN_ERR PFX "No usable DMA configuration, "
11855                                "aborting.\n");
11856                         goto err_out_iounmap;
11857                 }
11858         }
11859
11860         tg3_init_bufmgr_config(tp);
11861
11862         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11863                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11864         }
11865         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11866             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11867             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11868             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11869             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11870                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11871         } else {
11872                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11873         }
11874
11875         /* TSO is on by default on chips that support hardware TSO.
11876          * Firmware TSO on older chips gives lower performance, so it
11877          * is off by default, but can be enabled using ethtool.
11878          */
11879         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11880                 dev->features |= NETIF_F_TSO;
11881                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11882                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11883                         dev->features |= NETIF_F_TSO6;
11884         }
11885
11886
11887         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11888             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11889             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11890                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11891                 tp->rx_pending = 63;
11892         }
11893
11894         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11895             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11896                 tp->pdev_peer = tg3_find_peer(tp);
11897
11898         err = tg3_get_device_address(tp);
11899         if (err) {
11900                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11901                        "aborting.\n");
11902                 goto err_out_iounmap;
11903         }
11904
11905         /*
11906          * Reset chip in case UNDI or EFI driver did not shutdown
11907          * DMA self test will enable WDMAC and we'll see (spurious)
11908          * pending DMA on the PCI bus at that point.
11909          */
11910         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11911             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11912                 pci_save_state(tp->pdev);
11913                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11914                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11915         }
11916
11917         err = tg3_test_dma(tp);
11918         if (err) {
11919                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11920                 goto err_out_iounmap;
11921         }
11922
11923         /* Tigon3 can do ipv4 only... and some chips have buggy
11924          * checksumming.
11925          */
11926         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11927                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11928                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11929                         dev->features |= NETIF_F_HW_CSUM;
11930                 else
11931                         dev->features |= NETIF_F_IP_CSUM;
11932                 dev->features |= NETIF_F_SG;
11933                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11934         } else
11935                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11936
11937         /* flow control autonegotiation is default behavior */
11938         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11939
11940         tg3_init_coal(tp);
11941
11942         /* Now that we have fully setup the chip, save away a snapshot
11943          * of the PCI config space.  We need to restore this after
11944          * GRC_MISC_CFG core clock resets and some resume events.
11945          */
11946         pci_save_state(tp->pdev);
11947
11948         pci_set_drvdata(pdev, dev);
11949
11950         err = register_netdev(dev);
11951         if (err) {
11952                 printk(KERN_ERR PFX "Cannot register net device, "
11953                        "aborting.\n");
11954                 goto err_out_iounmap;
11955         }
11956
11957         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
11958                dev->name,
11959                tp->board_part_number,
11960                tp->pci_chip_rev_id,
11961                tg3_phy_string(tp),
11962                tg3_bus_string(tp, str),
11963                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11964                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11965                  "10/100/1000Base-T")));
11966
11967         for (i = 0; i < 6; i++)
11968                 printk("%2.2x%c", dev->dev_addr[i],
11969                        i == 5 ? '\n' : ':');
11970
11971         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11972                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11973                "TSOcap[%d] \n",
11974                dev->name,
11975                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11976                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11977                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11978                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11979                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11980                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11981                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11982         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11983                dev->name, tp->dma_rwctrl,
11984                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11985                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11986
11987         return 0;
11988
11989 err_out_iounmap:
11990         if (tp->regs) {
11991                 iounmap(tp->regs);
11992                 tp->regs = NULL;
11993         }
11994
11995 err_out_free_dev:
11996         free_netdev(dev);
11997
11998 err_out_free_res:
11999         pci_release_regions(pdev);
12000
12001 err_out_disable_pdev:
12002         pci_disable_device(pdev);
12003         pci_set_drvdata(pdev, NULL);
12004         return err;
12005 }
12006
12007 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12008 {
12009         struct net_device *dev = pci_get_drvdata(pdev);
12010
12011         if (dev) {
12012                 struct tg3 *tp = netdev_priv(dev);
12013
12014                 flush_scheduled_work();
12015                 unregister_netdev(dev);
12016                 if (tp->regs) {
12017                         iounmap(tp->regs);
12018                         tp->regs = NULL;
12019                 }
12020                 free_netdev(dev);
12021                 pci_release_regions(pdev);
12022                 pci_disable_device(pdev);
12023                 pci_set_drvdata(pdev, NULL);
12024         }
12025 }
12026
12027 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12028 {
12029         struct net_device *dev = pci_get_drvdata(pdev);
12030         struct tg3 *tp = netdev_priv(dev);
12031         int err;
12032
12033         if (!netif_running(dev))
12034                 return 0;
12035
12036         flush_scheduled_work();
12037         tg3_netif_stop(tp);
12038
12039         del_timer_sync(&tp->timer);
12040
12041         tg3_full_lock(tp, 1);
12042         tg3_disable_ints(tp);
12043         tg3_full_unlock(tp);
12044
12045         netif_device_detach(dev);
12046
12047         tg3_full_lock(tp, 0);
12048         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12049         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12050         tg3_full_unlock(tp);
12051
12052         /* Save MSI address and data for resume.  */
12053         pci_save_state(pdev);
12054
12055         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12056         if (err) {
12057                 tg3_full_lock(tp, 0);
12058
12059                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12060                 if (tg3_restart_hw(tp, 1))
12061                         goto out;
12062
12063                 tp->timer.expires = jiffies + tp->timer_offset;
12064                 add_timer(&tp->timer);
12065
12066                 netif_device_attach(dev);
12067                 tg3_netif_start(tp);
12068
12069 out:
12070                 tg3_full_unlock(tp);
12071         }
12072
12073         return err;
12074 }
12075
12076 static int tg3_resume(struct pci_dev *pdev)
12077 {
12078         struct net_device *dev = pci_get_drvdata(pdev);
12079         struct tg3 *tp = netdev_priv(dev);
12080         int err;
12081
12082         if (!netif_running(dev))
12083                 return 0;
12084
12085         pci_restore_state(tp->pdev);
12086
12087         err = tg3_set_power_state(tp, PCI_D0);
12088         if (err)
12089                 return err;
12090
12091         netif_device_attach(dev);
12092
12093         tg3_full_lock(tp, 0);
12094
12095         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12096         err = tg3_restart_hw(tp, 1);
12097         if (err)
12098                 goto out;
12099
12100         tp->timer.expires = jiffies + tp->timer_offset;
12101         add_timer(&tp->timer);
12102
12103         tg3_netif_start(tp);
12104
12105 out:
12106         tg3_full_unlock(tp);
12107
12108         return err;
12109 }
12110
12111 static struct pci_driver tg3_driver = {
12112         .name           = DRV_MODULE_NAME,
12113         .id_table       = tg3_pci_tbl,
12114         .probe          = tg3_init_one,
12115         .remove         = __devexit_p(tg3_remove_one),
12116         .suspend        = tg3_suspend,
12117         .resume         = tg3_resume
12118 };
12119
12120 static int __init tg3_init(void)
12121 {
12122         return pci_register_driver(&tg3_driver);
12123 }
12124
12125 static void __exit tg3_cleanup(void)
12126 {
12127         pci_unregister_driver(&tg3_driver);
12128 }
12129
12130 module_init(tg3_init);
12131 module_exit(tg3_cleanup);