Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6] / arch / arm / mach-ns9xxx / board-a9m9750dev.c
1 /*
2  * arch/arm/mach-ns9xxx/board-a9m9750dev.c
3  *
4  * Copyright (C) 2006,2007 by Digi International Inc.
5  * All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published by
9  * the Free Software Foundation.
10  */
11 #include <linux/irq.h>
12
13 #include <asm/mach/map.h>
14 #include <asm/gpio.h>
15
16 #include <mach/board.h>
17 #include <mach/processor-ns9360.h>
18 #include <mach/regs-sys-ns9360.h>
19 #include <mach/regs-mem.h>
20 #include <mach/regs-bbu.h>
21 #include <mach/regs-board-a9m9750dev.h>
22
23 #include "board-a9m9750dev.h"
24
25 static struct map_desc board_a9m9750dev_io_desc[] __initdata = {
26         { /* FPGA on CS0 */
27                 .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)),
28                 .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)),
29                 .length = NS9XXX_CS0STAT_LENGTH,
30                 .type = MT_DEVICE,
31         },
32 };
33
34 void __init board_a9m9750dev_map_io(void)
35 {
36         iotable_init(board_a9m9750dev_io_desc,
37                      ARRAY_SIZE(board_a9m9750dev_io_desc));
38 }
39
40 static void a9m9750dev_fpga_ack_irq(unsigned int irq)
41 {
42         /* nothing */
43 }
44
45 static void a9m9750dev_fpga_mask_irq(unsigned int irq)
46 {
47         u8 ier;
48
49         ier = __raw_readb(FPGA_IER);
50
51         ier &= ~(1 << (irq - FPGA_IRQ(0)));
52
53         __raw_writeb(ier, FPGA_IER);
54 }
55
56 static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
57 {
58         a9m9750dev_fpga_mask_irq(irq);
59         a9m9750dev_fpga_ack_irq(irq);
60 }
61
62 static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
63 {
64         u8 ier;
65
66         ier = __raw_readb(FPGA_IER);
67
68         ier |= 1 << (irq - FPGA_IRQ(0));
69
70         __raw_writeb(ier, FPGA_IER);
71 }
72
73 static struct irq_chip a9m9750dev_fpga_chip = {
74         .ack            = a9m9750dev_fpga_ack_irq,
75         .mask           = a9m9750dev_fpga_mask_irq,
76         .mask_ack       = a9m9750dev_fpga_maskack_irq,
77         .unmask         = a9m9750dev_fpga_unmask_irq,
78 };
79
80 static void a9m9750dev_fpga_demux_handler(unsigned int irq,
81                 struct irq_desc *desc)
82 {
83         u8 stat = __raw_readb(FPGA_ISR);
84
85         desc->chip->mask_ack(irq);
86
87         while (stat != 0) {
88                 int irqno = fls(stat) - 1;
89                 struct irq_desc *fpgadesc;
90
91                 stat &= ~(1 << irqno);
92
93                 fpgadesc = irq_desc + FPGA_IRQ(irqno);
94
95                 desc_handle_irq(FPGA_IRQ(irqno), fpgadesc);
96         }
97
98         desc->chip->unmask(irq);
99 }
100
101 void __init board_a9m9750dev_init_irq(void)
102 {
103         u32 eic;
104         int i;
105
106         if (gpio_request(11, "board a9m9750dev extirq2") == 0)
107                 ns9360_gpio_configure(11, 0, 1);
108         else
109                 printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n",
110                                 __func__);
111
112         for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
113                 set_irq_chip(i, &a9m9750dev_fpga_chip);
114                 set_irq_handler(i, handle_level_irq);
115                 set_irq_flags(i, IRQF_VALID);
116         }
117
118         /* IRQ_NS9XXX_EXT2: level sensitive + active low */
119         eic = __raw_readl(SYS_EIC(2));
120         REGSET(eic, SYS_EIC, PLTY, AL);
121         REGSET(eic, SYS_EIC, LVEDG, LEVEL);
122         __raw_writel(eic, SYS_EIC(2));
123
124         set_irq_chained_handler(IRQ_NS9XXX_EXT2,
125                         a9m9750dev_fpga_demux_handler);
126 }
127
128 void __init board_a9m9750dev_init_machine(void)
129 {
130         u32 reg;
131
132         /* setup static CS0: memory base ... */
133         reg = __raw_readl(SYS_SMCSSMB(0));
134         REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12);
135         __raw_writel(reg, SYS_SMCSSMB(0));
136
137         /* ... and mask */
138         reg = __raw_readl(SYS_SMCSSMM(0));
139         REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
140         REGSET(reg, SYS_SMCSSMM, CSEx, EN);
141         __raw_writel(reg, SYS_SMCSSMM(0));
142
143         /* setup static CS0: memory configuration */
144         reg = __raw_readl(MEM_SMC(0));
145         REGSET(reg, MEM_SMC, PSMC, OFF);
146         REGSET(reg, MEM_SMC, BSMC, OFF);
147         REGSET(reg, MEM_SMC, EW, OFF);
148         REGSET(reg, MEM_SMC, PB, 1);
149         REGSET(reg, MEM_SMC, PC, AL);
150         REGSET(reg, MEM_SMC, PM, DIS);
151         REGSET(reg, MEM_SMC, MW, 8);
152         __raw_writel(reg, MEM_SMC(0));
153
154         /* setup static CS0: timing */
155         __raw_writel(0x2, MEM_SMWED(0));
156         __raw_writel(0x2, MEM_SMOED(0));
157         __raw_writel(0x6, MEM_SMRD(0));
158         __raw_writel(0x6, MEM_SMWD(0));
159 }