1 /*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
14 * Copyright (c) 2006 Linus Walleij
17 * Based on smc-ircc.c:
19 * Copyright (c) 2001 Stefani Seibold
20 * Copyright (c) 1999-2001 Dag Brattli
21 * Copyright (c) 1998-1999 Thomas Davis,
25 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
28 * This program is free software; you can redistribute it and/or
29 * modify it under the terms of the GNU General Public License as
30 * published by the Free Software Foundation; either version 2 of
31 * the License, or (at your option) any later version.
33 * This program is distributed in the hope that it will be useful,
34 * but WITHOUT ANY WARRANTY; without even the implied warranty of
35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36 * GNU General Public License for more details.
38 * You should have received a copy of the GNU General Public License
39 * along with this program; if not, write to the Free Software
40 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
43 ********************************************************************/
45 #include <linux/module.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/skbuff.h>
49 #include <linux/netdevice.h>
50 #include <linux/ioport.h>
51 #include <linux/delay.h>
52 #include <linux/slab.h>
53 #include <linux/init.h>
54 #include <linux/rtnetlink.h>
55 #include <linux/serial_reg.h>
56 #include <linux/dma-mapping.h>
57 #include <linux/pnp.h>
58 #include <linux/platform_device.h>
62 #include <asm/byteorder.h>
64 #include <linux/spinlock.h>
67 #include <linux/pci.h>
70 #include <net/irda/wrapper.h>
71 #include <net/irda/irda.h>
72 #include <net/irda/irda_device.h>
74 #include "smsc-ircc2.h"
78 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
79 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
80 MODULE_LICENSE("GPL");
82 static int smsc_nopnp = 1;
83 module_param_named(nopnp, smsc_nopnp, bool, 0);
84 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
87 static int ircc_dma = DMA_INVAL;
88 module_param(ircc_dma, int, 0);
89 MODULE_PARM_DESC(ircc_dma, "DMA channel");
92 static int ircc_irq = IRQ_INVAL;
93 module_param(ircc_irq, int, 0);
94 MODULE_PARM_DESC(ircc_irq, "IRQ line");
97 module_param(ircc_fir, int, 0);
98 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
101 module_param(ircc_sir, int, 0);
102 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
105 module_param(ircc_cfg, int, 0);
106 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
108 static int ircc_transceiver;
109 module_param(ircc_transceiver, int, 0);
110 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
115 struct smsc_ircc_subsystem_configuration {
116 unsigned short vendor; /* PCI vendor ID */
117 unsigned short device; /* PCI vendor ID */
118 unsigned short subvendor; /* PCI subsystem vendor ID */
119 unsigned short subdevice; /* PCI sybsystem device ID */
120 unsigned short sir_io; /* I/O port for SIR */
121 unsigned short fir_io; /* I/O port for FIR */
122 unsigned char fir_irq; /* FIR IRQ */
123 unsigned char fir_dma; /* FIR DMA */
124 unsigned short cfg_base; /* I/O port for chip configuration */
125 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
126 const char *name; /* name shown as info */
130 struct smsc_transceiver {
132 void (*set_for_speed)(int fir_base, u32 speed);
133 int (*probe)(int fir_base);
146 struct smsc_chip_address {
147 unsigned int cfg_base;
151 /* Private data for each instance */
152 struct smsc_ircc_cb {
153 struct net_device *netdev; /* Yes! we are some kind of netdevice */
154 struct net_device_stats stats;
155 struct irlap_cb *irlap; /* The link layer we are binded to */
157 chipio_t io; /* IrDA controller information */
158 iobuff_t tx_buff; /* Transmit buffer */
159 iobuff_t rx_buff; /* Receive buffer */
160 dma_addr_t tx_buff_dma;
161 dma_addr_t rx_buff_dma;
163 struct qos_info qos; /* QoS capabilities for this device */
165 spinlock_t lock; /* For serializing operations */
168 __u32 flags; /* Interface flags */
170 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
171 int tx_len; /* Number of frames in tx_buff */
174 struct platform_device *pldev;
179 #define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
181 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
182 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
183 #define SMSC_IRCC2_C_NET_TIMEOUT 0
184 #define SMSC_IRCC2_C_SIR_STOP 0
186 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
190 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
191 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
192 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
193 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
194 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
195 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
196 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
197 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
198 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
199 static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
200 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
201 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
202 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
203 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
204 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
205 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
206 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
207 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
208 #if SMSC_IRCC2_C_SIR_STOP
209 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
211 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
212 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
213 static int smsc_ircc_net_open(struct net_device *dev);
214 static int smsc_ircc_net_close(struct net_device *dev);
215 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
216 #if SMSC_IRCC2_C_NET_TIMEOUT
217 static void smsc_ircc_timeout(struct net_device *dev);
219 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
220 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
221 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
222 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
223 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
226 static int __init smsc_ircc_look_for_chips(void);
227 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
228 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
229 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
230 static int __init smsc_superio_fdc(unsigned short cfg_base);
231 static int __init smsc_superio_lpc(unsigned short cfg_base);
233 static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
234 static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
235 static void __init preconfigure_ali_port(struct pci_dev *dev,
236 unsigned short port);
237 static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
238 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
239 unsigned short ircc_fir,
240 unsigned short ircc_sir,
241 unsigned char ircc_dma,
242 unsigned char ircc_irq);
245 /* Transceivers specific functions */
247 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
248 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
249 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
250 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
251 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
252 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
254 /* Power Management */
256 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
257 static int smsc_ircc_resume(struct platform_device *dev);
259 static struct platform_driver smsc_ircc_driver = {
260 .suspend = smsc_ircc_suspend,
261 .resume = smsc_ircc_resume,
263 .name = SMSC_IRCC2_DRIVER_NAME,
267 /* Transceivers for SMSC-ircc */
269 static struct smsc_transceiver smsc_transceivers[] =
271 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
272 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
273 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
276 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
278 /* SMC SuperIO chipsets definitions */
280 #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
281 #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
282 #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
283 #define SIR 0 /* SuperIO Chip has only slow IRDA */
284 #define FIR 4 /* SuperIO Chip has fast IRDA */
285 #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
287 static struct smsc_chip __initdata fdc_chips_flat[] =
289 /* Base address 0x3f0 or 0x370 */
290 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
291 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
292 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
293 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
294 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
295 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
296 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
297 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
301 static struct smsc_chip __initdata fdc_chips_paged[] =
303 /* Base address 0x3f0 or 0x370 */
304 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
305 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
306 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
307 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
308 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
309 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
310 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
311 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
312 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
313 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
314 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
315 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
316 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
320 static struct smsc_chip __initdata lpc_chips_flat[] =
322 /* Base address 0x2E or 0x4E */
323 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
324 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
325 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
329 static struct smsc_chip __initdata lpc_chips_paged[] =
331 /* Base address 0x2E or 0x4E */
332 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
333 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
334 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
335 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
336 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
337 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
338 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
339 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
343 #define SMSCSIO_TYPE_FDC 1
344 #define SMSCSIO_TYPE_LPC 2
345 #define SMSCSIO_TYPE_FLAT 4
346 #define SMSCSIO_TYPE_PAGED 8
348 static struct smsc_chip_address __initdata possible_addresses[] =
350 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
353 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
354 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
360 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
361 static unsigned short dev_count;
363 static inline void register_bank(int iobase, int bank)
365 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
366 iobase + IRCC_MASTER);
369 /* PNP hotplug support */
370 static const struct pnp_device_id smsc_ircc_pnp_table[] = {
371 { .id = "SMCf010", .driver_data = 0 },
372 /* and presumably others */
375 MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
377 static int pnp_driver_registered;
379 static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev,
380 const struct pnp_device_id *dev_id)
382 unsigned int firbase, sirbase;
385 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
386 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
389 sirbase = pnp_port_start(dev, 0);
390 firbase = pnp_port_start(dev, 1);
391 dma = pnp_dma(dev, 0);
392 irq = pnp_irq(dev, 0);
394 if (smsc_ircc_open(firbase, sirbase, dma, irq))
400 static struct pnp_driver smsc_ircc_pnp_driver = {
401 .name = "smsc-ircc2",
402 .id_table = smsc_ircc_pnp_table,
403 .probe = smsc_ircc_pnp_probe,
407 /*******************************************************************************
413 *******************************************************************************/
415 static int __init smsc_ircc_legacy_probe(void)
420 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
421 /* Ignore errors from preconfiguration */
422 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
426 if (ircc_fir > 0 && ircc_sir > 0) {
427 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
428 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
430 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
435 /* try user provided configuration register base address */
437 IRDA_MESSAGE(" Overriding configuration address "
438 "0x%04x\n", ircc_cfg);
439 if (!smsc_superio_fdc(ircc_cfg))
441 if (!smsc_superio_lpc(ircc_cfg))
445 if (smsc_ircc_look_for_chips() > 0)
452 * Function smsc_ircc_init ()
454 * Initialize chip. Just try to find out how many chips we are dealing with
457 static int __init smsc_ircc_init(void)
461 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
463 ret = platform_driver_register(&smsc_ircc_driver);
465 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
471 if (smsc_nopnp || !pnp_platform_devices ||
472 ircc_cfg || ircc_fir || ircc_sir ||
473 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
474 ret = smsc_ircc_legacy_probe();
476 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
477 pnp_driver_registered = 1;
481 if (pnp_driver_registered)
482 pnp_unregister_driver(&smsc_ircc_pnp_driver);
483 platform_driver_unregister(&smsc_ircc_driver);
490 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
492 * Try to open driver instance
495 static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
497 struct smsc_ircc_cb *self;
498 struct net_device *dev;
501 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
503 err = smsc_ircc_present(fir_base, sir_base);
508 if (dev_count >= ARRAY_SIZE(dev_self)) {
509 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
514 * Allocate new instance of the driver
516 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
518 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
522 SET_MODULE_OWNER(dev);
524 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
525 #if SMSC_IRCC2_C_NET_TIMEOUT
526 dev->tx_timeout = smsc_ircc_timeout;
527 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
529 dev->open = smsc_ircc_net_open;
530 dev->stop = smsc_ircc_net_close;
531 dev->do_ioctl = smsc_ircc_net_ioctl;
532 dev->get_stats = smsc_ircc_net_get_stats;
534 self = netdev_priv(dev);
537 /* Make ifconfig display some details */
538 dev->base_addr = self->io.fir_base = fir_base;
539 dev->irq = self->io.irq = irq;
541 /* Need to store self somewhere */
542 dev_self[dev_count] = self;
543 spin_lock_init(&self->lock);
545 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
546 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
549 dma_alloc_coherent(NULL, self->rx_buff.truesize,
550 &self->rx_buff_dma, GFP_KERNEL);
551 if (self->rx_buff.head == NULL) {
552 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
558 dma_alloc_coherent(NULL, self->tx_buff.truesize,
559 &self->tx_buff_dma, GFP_KERNEL);
560 if (self->tx_buff.head == NULL) {
561 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
566 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
567 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
569 self->rx_buff.in_frame = FALSE;
570 self->rx_buff.state = OUTSIDE_FRAME;
571 self->tx_buff.data = self->tx_buff.head;
572 self->rx_buff.data = self->rx_buff.head;
574 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
575 smsc_ircc_setup_qos(self);
576 smsc_ircc_init_chip(self);
578 if (ircc_transceiver > 0 &&
579 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
580 self->transceiver = ircc_transceiver;
582 smsc_ircc_probe_transceiver(self);
584 err = register_netdev(self->netdev);
586 IRDA_ERROR("%s, Network device registration failed!\n",
591 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
593 if (IS_ERR(self->pldev)) {
594 err = PTR_ERR(self->pldev);
597 platform_set_drvdata(self->pldev, self);
599 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
605 unregister_netdev(self->netdev);
608 dma_free_coherent(NULL, self->tx_buff.truesize,
609 self->tx_buff.head, self->tx_buff_dma);
611 dma_free_coherent(NULL, self->rx_buff.truesize,
612 self->rx_buff.head, self->rx_buff_dma);
614 free_netdev(self->netdev);
615 dev_self[dev_count] = NULL;
617 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
618 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
624 * Function smsc_ircc_present(fir_base, sir_base)
626 * Check the smsc-ircc chip presence
629 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
631 unsigned char low, high, chip, config, dma, irq, version;
633 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
635 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
636 __FUNCTION__, fir_base);
640 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
642 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
643 __FUNCTION__, sir_base);
647 register_bank(fir_base, 3);
649 high = inb(fir_base + IRCC_ID_HIGH);
650 low = inb(fir_base + IRCC_ID_LOW);
651 chip = inb(fir_base + IRCC_CHIP_ID);
652 version = inb(fir_base + IRCC_VERSION);
653 config = inb(fir_base + IRCC_INTERFACE);
654 dma = config & IRCC_INTERFACE_DMA_MASK;
655 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
657 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
658 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
659 __FUNCTION__, fir_base);
662 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
663 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
664 chip & 0x0f, version, fir_base, sir_base, dma, irq);
669 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
671 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
677 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
682 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
683 unsigned int fir_base, unsigned int sir_base,
686 unsigned char config, chip_dma, chip_irq;
688 register_bank(fir_base, 3);
689 config = inb(fir_base + IRCC_INTERFACE);
690 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
691 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
693 self->io.fir_base = fir_base;
694 self->io.sir_base = sir_base;
695 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
696 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
697 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
698 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
700 if (irq != IRQ_INVAL) {
702 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
703 driver_name, chip_irq, irq);
706 self->io.irq = chip_irq;
708 if (dma != DMA_INVAL) {
710 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
711 driver_name, chip_dma, dma);
714 self->io.dma = chip_dma;
719 * Function smsc_ircc_setup_qos(self)
724 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
726 /* Initialize QoS for this device */
727 irda_init_max_qos_capabilies(&self->qos);
729 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
730 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
732 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
733 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
734 irda_qos_bits_to_value(&self->qos);
738 * Function smsc_ircc_init_chip(self)
743 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
745 int iobase = self->io.fir_base;
747 register_bank(iobase, 0);
748 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
749 outb(0x00, iobase + IRCC_MASTER);
751 register_bank(iobase, 1);
752 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
753 iobase + IRCC_SCE_CFGA);
755 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
756 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
757 iobase + IRCC_SCE_CFGB);
759 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
760 iobase + IRCC_SCE_CFGB);
762 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
763 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
765 register_bank(iobase, 4);
766 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
768 register_bank(iobase, 0);
769 outb(0, iobase + IRCC_LCR_A);
771 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
773 /* Power on device */
774 outb(0x00, iobase + IRCC_MASTER);
778 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
780 * Process IOCTL commands for this device
783 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
785 struct if_irda_req *irq = (struct if_irda_req *) rq;
786 struct smsc_ircc_cb *self;
790 IRDA_ASSERT(dev != NULL, return -1;);
792 self = netdev_priv(dev);
794 IRDA_ASSERT(self != NULL, return -1;);
796 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
799 case SIOCSBANDWIDTH: /* Set bandwidth */
800 if (!capable(CAP_NET_ADMIN))
803 /* Make sure we are the only one touching
804 * self->io.speed and the hardware - Jean II */
805 spin_lock_irqsave(&self->lock, flags);
806 smsc_ircc_change_speed(self, irq->ifr_baudrate);
807 spin_unlock_irqrestore(&self->lock, flags);
810 case SIOCSMEDIABUSY: /* Set media busy */
811 if (!capable(CAP_NET_ADMIN)) {
816 irda_device_set_media_busy(self->netdev, TRUE);
818 case SIOCGRECEIVING: /* Check if we are receiving right now */
819 irq->ifr_receiving = smsc_ircc_is_receiving(self);
823 if (!capable(CAP_NET_ADMIN)) {
827 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
837 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
839 struct smsc_ircc_cb *self = netdev_priv(dev);
844 #if SMSC_IRCC2_C_NET_TIMEOUT
846 * Function smsc_ircc_timeout (struct net_device *dev)
848 * The networking timeout management.
852 static void smsc_ircc_timeout(struct net_device *dev)
854 struct smsc_ircc_cb *self = netdev_priv(dev);
857 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
858 dev->name, self->io.speed);
859 spin_lock_irqsave(&self->lock, flags);
860 smsc_ircc_sir_start(self);
861 smsc_ircc_change_speed(self, self->io.speed);
862 dev->trans_start = jiffies;
863 netif_wake_queue(dev);
864 spin_unlock_irqrestore(&self->lock, flags);
869 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
871 * Transmits the current frame until FIFO is full, then
872 * waits until the next transmit interrupt, and continues until the
873 * frame is transmitted.
875 int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
877 struct smsc_ircc_cb *self;
881 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
883 IRDA_ASSERT(dev != NULL, return 0;);
885 self = netdev_priv(dev);
886 IRDA_ASSERT(self != NULL, return 0;);
888 netif_stop_queue(dev);
890 /* Make sure test of self->io.speed & speed change are atomic */
891 spin_lock_irqsave(&self->lock, flags);
893 /* Check if we need to change the speed */
894 speed = irda_get_next_speed(skb);
895 if (speed != self->io.speed && speed != -1) {
896 /* Check for empty frame */
899 * We send frames one by one in SIR mode (no
900 * pipelining), so at this point, if we were sending
901 * a previous frame, we just received the interrupt
902 * telling us it is finished (UART_IIR_THRI).
903 * Therefore, waiting for the transmitter to really
904 * finish draining the fifo won't take too long.
905 * And the interrupt handler is not expected to run.
907 smsc_ircc_sir_wait_hw_transmitter_finish(self);
908 smsc_ircc_change_speed(self, speed);
909 spin_unlock_irqrestore(&self->lock, flags);
913 self->new_speed = speed;
917 self->tx_buff.data = self->tx_buff.head;
919 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
920 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
921 self->tx_buff.truesize);
923 self->stats.tx_bytes += self->tx_buff.len;
925 /* Turn on transmit finished interrupt. Will fire immediately! */
926 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
928 spin_unlock_irqrestore(&self->lock, flags);
936 * Function smsc_ircc_set_fir_speed (self, baud)
938 * Change the speed of the device
941 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
943 int fir_base, ir_mode, ctrl, fast;
945 IRDA_ASSERT(self != NULL, return;);
946 fir_base = self->io.fir_base;
948 self->io.speed = speed;
953 ir_mode = IRCC_CFGA_IRDA_HDLC;
956 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
959 ir_mode = IRCC_CFGA_IRDA_HDLC;
960 ctrl = IRCC_1152 | IRCC_CRC;
961 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
962 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
966 ir_mode = IRCC_CFGA_IRDA_4PPM;
968 fast = IRCC_LCR_A_FAST;
969 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
975 /* This causes an interrupt */
976 register_bank(fir_base, 0);
977 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
980 register_bank(fir_base, 1);
981 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
983 register_bank(fir_base, 4);
984 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
988 * Function smsc_ircc_fir_start(self)
990 * Change the speed of the device
993 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
995 struct net_device *dev;
998 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1000 IRDA_ASSERT(self != NULL, return;);
1002 IRDA_ASSERT(dev != NULL, return;);
1004 fir_base = self->io.fir_base;
1006 /* Reset everything */
1008 /* Install FIR transmit handler */
1009 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
1012 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1014 /* Enable interrupt */
1015 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1017 register_bank(fir_base, 1);
1019 /* Select the TX/RX interface */
1020 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1021 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1022 fir_base + IRCC_SCE_CFGB);
1024 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1025 fir_base + IRCC_SCE_CFGB);
1027 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1029 /* Enable SCE interrupts */
1030 outb(0, fir_base + IRCC_MASTER);
1031 register_bank(fir_base, 0);
1032 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1033 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1037 * Function smsc_ircc_fir_stop(self, baud)
1039 * Change the speed of the device
1042 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1046 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1048 IRDA_ASSERT(self != NULL, return;);
1050 fir_base = self->io.fir_base;
1051 register_bank(fir_base, 0);
1052 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1053 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1058 * Function smsc_ircc_change_speed(self, baud)
1060 * Change the speed of the device
1062 * This function *must* be called with spinlock held, because it may
1063 * be called from the irq handler. - Jean II
1065 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1067 struct net_device *dev;
1068 int last_speed_was_sir;
1070 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
1072 IRDA_ASSERT(self != NULL, return;);
1075 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1080 self->io.speed = speed;
1081 last_speed_was_sir = 0;
1082 smsc_ircc_fir_start(self);
1085 if (self->io.speed == 0)
1086 smsc_ircc_sir_start(self);
1089 if (!last_speed_was_sir) speed = self->io.speed;
1092 if (self->io.speed != speed)
1093 smsc_ircc_set_transceiver_for_speed(self, speed);
1095 self->io.speed = speed;
1097 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1098 if (!last_speed_was_sir) {
1099 smsc_ircc_fir_stop(self);
1100 smsc_ircc_sir_start(self);
1102 smsc_ircc_set_sir_speed(self, speed);
1104 if (last_speed_was_sir) {
1105 #if SMSC_IRCC2_C_SIR_STOP
1106 smsc_ircc_sir_stop(self);
1108 smsc_ircc_fir_start(self);
1110 smsc_ircc_set_fir_speed(self, speed);
1113 self->tx_buff.len = 10;
1114 self->tx_buff.data = self->tx_buff.head;
1116 smsc_ircc_dma_xmit(self, 4000);
1118 /* Be ready for incoming frames */
1119 smsc_ircc_dma_receive(self);
1122 netif_wake_queue(dev);
1126 * Function smsc_ircc_set_sir_speed (self, speed)
1128 * Set speed of IrDA port to specified baudrate
1131 void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1134 int fcr; /* FIFO control reg */
1135 int lcr; /* Line control reg */
1138 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1140 IRDA_ASSERT(self != NULL, return;);
1141 iobase = self->io.sir_base;
1143 /* Update accounting for new speed */
1144 self->io.speed = speed;
1146 /* Turn off interrupts */
1147 outb(0, iobase + UART_IER);
1149 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1151 fcr = UART_FCR_ENABLE_FIFO;
1154 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1155 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1156 * about this timeout since it will always be fast enough.
1158 fcr |= self->io.speed < 38400 ?
1159 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1161 /* IrDA ports use 8N1 */
1162 lcr = UART_LCR_WLEN8;
1164 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1165 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1166 outb(divisor >> 8, iobase + UART_DLM);
1167 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1168 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1170 /* Turn on interrups */
1171 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1173 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1178 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1180 * Transmit the frame!
1183 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1185 struct smsc_ircc_cb *self;
1186 unsigned long flags;
1190 IRDA_ASSERT(dev != NULL, return 0;);
1191 self = netdev_priv(dev);
1192 IRDA_ASSERT(self != NULL, return 0;);
1194 netif_stop_queue(dev);
1196 /* Make sure test of self->io.speed & speed change are atomic */
1197 spin_lock_irqsave(&self->lock, flags);
1199 /* Check if we need to change the speed after this frame */
1200 speed = irda_get_next_speed(skb);
1201 if (speed != self->io.speed && speed != -1) {
1202 /* Check for empty frame */
1204 /* Note : you should make sure that speed changes
1205 * are not going to corrupt any outgoing frame.
1206 * Look at nsc-ircc for the gory details - Jean II */
1207 smsc_ircc_change_speed(self, speed);
1208 spin_unlock_irqrestore(&self->lock, flags);
1213 self->new_speed = speed;
1216 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1218 self->tx_buff.len = skb->len;
1219 self->tx_buff.data = self->tx_buff.head;
1221 mtt = irda_get_mtt(skb);
1226 * Compute how many BOFs (STA or PA's) we need to waste the
1227 * min turn time given the speed of the link.
1229 bofs = mtt * (self->io.speed / 1000) / 8000;
1233 smsc_ircc_dma_xmit(self, bofs);
1235 /* Transmit frame */
1236 smsc_ircc_dma_xmit(self, 0);
1239 spin_unlock_irqrestore(&self->lock, flags);
1246 * Function smsc_ircc_dma_xmit (self, bofs)
1248 * Transmit data using DMA
1251 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1253 int iobase = self->io.fir_base;
1256 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1259 register_bank(iobase, 0);
1260 outb(0x00, iobase + IRCC_LCR_B);
1262 register_bank(iobase, 1);
1263 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1264 iobase + IRCC_SCE_CFGB);
1266 self->io.direction = IO_XMIT;
1268 /* Set BOF additional count for generating the min turn time */
1269 register_bank(iobase, 4);
1270 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1271 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1272 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1274 /* Set max Tx frame size */
1275 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1276 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1278 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1280 /* Enable burst mode chip Tx DMA */
1281 register_bank(iobase, 1);
1282 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1283 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1285 /* Setup DMA controller (must be done after enabling chip DMA) */
1286 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1289 /* Enable interrupt */
1291 register_bank(iobase, 0);
1292 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1293 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1295 /* Enable transmit */
1296 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1300 * Function smsc_ircc_dma_xmit_complete (self)
1302 * The transfer of a frame in finished. This function will only be called
1303 * by the interrupt handler
1306 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1308 int iobase = self->io.fir_base;
1310 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1313 register_bank(iobase, 0);
1314 outb(0x00, iobase + IRCC_LCR_B);
1316 register_bank(iobase, 1);
1317 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1318 iobase + IRCC_SCE_CFGB);
1320 /* Check for underrun! */
1321 register_bank(iobase, 0);
1322 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1323 self->stats.tx_errors++;
1324 self->stats.tx_fifo_errors++;
1326 /* Reset error condition */
1327 register_bank(iobase, 0);
1328 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1329 outb(0x00, iobase + IRCC_MASTER);
1331 self->stats.tx_packets++;
1332 self->stats.tx_bytes += self->tx_buff.len;
1335 /* Check if it's time to change the speed */
1336 if (self->new_speed) {
1337 smsc_ircc_change_speed(self, self->new_speed);
1338 self->new_speed = 0;
1341 netif_wake_queue(self->netdev);
1345 * Function smsc_ircc_dma_receive(self)
1347 * Get ready for receiving a frame. The device will initiate a DMA
1348 * if it starts to receive a frame.
1351 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1353 int iobase = self->io.fir_base;
1355 /* Turn off chip DMA */
1356 register_bank(iobase, 1);
1357 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1358 iobase + IRCC_SCE_CFGB);
1362 register_bank(iobase, 0);
1363 outb(0x00, iobase + IRCC_LCR_B);
1365 /* Turn off chip DMA */
1366 register_bank(iobase, 1);
1367 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1368 iobase + IRCC_SCE_CFGB);
1370 self->io.direction = IO_RECV;
1371 self->rx_buff.data = self->rx_buff.head;
1373 /* Set max Rx frame size */
1374 register_bank(iobase, 4);
1375 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1376 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1378 /* Setup DMA controller */
1379 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1382 /* Enable burst mode chip Rx DMA */
1383 register_bank(iobase, 1);
1384 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1385 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1387 /* Enable interrupt */
1388 register_bank(iobase, 0);
1389 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1390 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1392 /* Enable receiver */
1393 register_bank(iobase, 0);
1394 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1395 iobase + IRCC_LCR_B);
1401 * Function smsc_ircc_dma_receive_complete(self)
1403 * Finished with receiving frames
1406 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1408 struct sk_buff *skb;
1409 int len, msgcnt, lsr;
1410 int iobase = self->io.fir_base;
1412 register_bank(iobase, 0);
1414 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1417 register_bank(iobase, 0);
1418 outb(0x00, iobase + IRCC_LCR_B);
1420 register_bank(iobase, 0);
1421 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1422 lsr= inb(iobase + IRCC_LSR);
1423 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1425 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1426 get_dma_residue(self->io.dma));
1428 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1430 /* Look for errors */
1431 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1432 self->stats.rx_errors++;
1433 if (lsr & IRCC_LSR_FRAME_ERROR)
1434 self->stats.rx_frame_errors++;
1435 if (lsr & IRCC_LSR_CRC_ERROR)
1436 self->stats.rx_crc_errors++;
1437 if (lsr & IRCC_LSR_SIZE_ERROR)
1438 self->stats.rx_length_errors++;
1439 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1440 self->stats.rx_length_errors++;
1445 len -= self->io.speed < 4000000 ? 2 : 4;
1447 if (len < 2 || len > 2050) {
1448 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1451 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1453 skb = dev_alloc_skb(len + 1);
1455 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1459 /* Make sure IP header gets aligned */
1460 skb_reserve(skb, 1);
1462 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1463 self->stats.rx_packets++;
1464 self->stats.rx_bytes += len;
1466 skb->dev = self->netdev;
1467 skb_reset_mac_header(skb);
1468 skb->protocol = htons(ETH_P_IRDA);
1473 * Function smsc_ircc_sir_receive (self)
1475 * Receive one frame from the infrared port
1478 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1483 IRDA_ASSERT(self != NULL, return;);
1485 iobase = self->io.sir_base;
1488 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1489 * async_unwrap_char will deliver all found frames
1492 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1493 inb(iobase + UART_RX));
1495 /* Make sure we don't stay here to long */
1496 if (boguscount++ > 32) {
1497 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1500 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1505 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1507 * An interrupt from the chip has arrived. Time to do some work
1510 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id)
1512 struct net_device *dev = (struct net_device *) dev_id;
1513 struct smsc_ircc_cb *self;
1514 int iobase, iir, lcra, lsr;
1515 irqreturn_t ret = IRQ_NONE;
1518 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1523 self = netdev_priv(dev);
1524 IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1526 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1527 spin_lock(&self->lock);
1529 /* Check if we should use the SIR interrupt handler */
1530 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1531 ret = smsc_ircc_interrupt_sir(dev);
1532 goto irq_ret_unlock;
1535 iobase = self->io.fir_base;
1537 register_bank(iobase, 0);
1538 iir = inb(iobase + IRCC_IIR);
1540 goto irq_ret_unlock;
1543 /* Disable interrupts */
1544 outb(0, iobase + IRCC_IER);
1545 lcra = inb(iobase + IRCC_LCR_A);
1546 lsr = inb(iobase + IRCC_LSR);
1548 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1550 if (iir & IRCC_IIR_EOM) {
1551 if (self->io.direction == IO_RECV)
1552 smsc_ircc_dma_receive_complete(self);
1554 smsc_ircc_dma_xmit_complete(self);
1556 smsc_ircc_dma_receive(self);
1559 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1560 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1563 /* Enable interrupts again */
1565 register_bank(iobase, 0);
1566 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1569 spin_unlock(&self->lock);
1575 * Function irport_interrupt_sir (irq, dev_id)
1577 * Interrupt handler for SIR modes
1579 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1581 struct smsc_ircc_cb *self = netdev_priv(dev);
1586 /* Already locked comming here in smsc_ircc_interrupt() */
1587 /*spin_lock(&self->lock);*/
1589 iobase = self->io.sir_base;
1591 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1595 /* Clear interrupt */
1596 lsr = inb(iobase + UART_LSR);
1598 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1599 __FUNCTION__, iir, lsr, iobase);
1603 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1606 /* Receive interrupt */
1607 smsc_ircc_sir_receive(self);
1610 if (lsr & UART_LSR_THRE)
1611 /* Transmitter ready for data */
1612 smsc_ircc_sir_write_wakeup(self);
1615 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1620 /* Make sure we don't stay here to long */
1621 if (boguscount++ > 100)
1624 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1626 /*spin_unlock(&self->lock);*/
1633 * Function ircc_is_receiving (self)
1635 * Return TRUE is we are currently receiving a frame
1638 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1643 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1645 IRDA_ASSERT(self != NULL, return FALSE;);
1647 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1648 get_dma_residue(self->io.dma));
1650 status = (self->rx_buff.state != OUTSIDE_FRAME);
1656 static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1660 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1661 self->netdev->name, self->netdev);
1663 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1664 __FUNCTION__, self->io.irq, error);
1669 static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1671 unsigned long flags;
1673 spin_lock_irqsave(&self->lock, flags);
1676 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1678 spin_unlock_irqrestore(&self->lock, flags);
1681 static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1683 int iobase = self->io.fir_base;
1684 unsigned long flags;
1686 spin_lock_irqsave(&self->lock, flags);
1688 register_bank(iobase, 0);
1689 outb(0, iobase + IRCC_IER);
1690 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1691 outb(0x00, iobase + IRCC_MASTER);
1693 spin_unlock_irqrestore(&self->lock, flags);
1698 * Function smsc_ircc_net_open (dev)
1703 static int smsc_ircc_net_open(struct net_device *dev)
1705 struct smsc_ircc_cb *self;
1708 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1710 IRDA_ASSERT(dev != NULL, return -1;);
1711 self = netdev_priv(dev);
1712 IRDA_ASSERT(self != NULL, return 0;);
1714 if (self->io.suspended) {
1715 IRDA_DEBUG(0, "%s(), device is suspended\n", __FUNCTION__);
1719 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1721 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1722 __FUNCTION__, self->io.irq);
1726 smsc_ircc_start_interrupts(self);
1728 /* Give self a hardware name */
1729 /* It would be cool to offer the chip revision here - Jean II */
1730 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1733 * Open new IrLAP layer instance, now that everything should be
1734 * initialized properly
1736 self->irlap = irlap_open(dev, &self->qos, hwname);
1739 * Always allocate the DMA channel after the IRQ,
1740 * and clean up on failure.
1742 if (request_dma(self->io.dma, dev->name)) {
1743 smsc_ircc_net_close(dev);
1745 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1746 __FUNCTION__, self->io.dma);
1750 netif_start_queue(dev);
1756 * Function smsc_ircc_net_close (dev)
1761 static int smsc_ircc_net_close(struct net_device *dev)
1763 struct smsc_ircc_cb *self;
1765 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1767 IRDA_ASSERT(dev != NULL, return -1;);
1768 self = netdev_priv(dev);
1769 IRDA_ASSERT(self != NULL, return 0;);
1772 netif_stop_queue(dev);
1774 /* Stop and remove instance of IrLAP */
1776 irlap_close(self->irlap);
1779 smsc_ircc_stop_interrupts(self);
1781 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1782 if (!self->io.suspended)
1783 free_irq(self->io.irq, dev);
1785 disable_dma(self->io.dma);
1786 free_dma(self->io.dma);
1791 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1793 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1795 if (!self->io.suspended) {
1796 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1799 if (netif_running(self->netdev)) {
1800 netif_device_detach(self->netdev);
1801 smsc_ircc_stop_interrupts(self);
1802 free_irq(self->io.irq, self->netdev);
1803 disable_dma(self->io.dma);
1805 self->io.suspended = 1;
1812 static int smsc_ircc_resume(struct platform_device *dev)
1814 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1816 if (self->io.suspended) {
1817 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1820 smsc_ircc_init_chip(self);
1821 if (netif_running(self->netdev)) {
1822 if (smsc_ircc_request_irq(self)) {
1824 * Don't fail resume process, just kill this
1827 unregister_netdevice(self->netdev);
1829 enable_dma(self->io.dma);
1830 smsc_ircc_start_interrupts(self);
1831 netif_device_attach(self->netdev);
1834 self->io.suspended = 0;
1841 * Function smsc_ircc_close (self)
1843 * Close driver instance
1846 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1848 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1850 IRDA_ASSERT(self != NULL, return -1;);
1852 platform_device_unregister(self->pldev);
1854 /* Remove netdevice */
1855 unregister_netdev(self->netdev);
1857 smsc_ircc_stop_interrupts(self);
1859 /* Release the PORTS that this driver is using */
1860 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1863 release_region(self->io.fir_base, self->io.fir_ext);
1865 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1868 release_region(self->io.sir_base, self->io.sir_ext);
1870 if (self->tx_buff.head)
1871 dma_free_coherent(NULL, self->tx_buff.truesize,
1872 self->tx_buff.head, self->tx_buff_dma);
1874 if (self->rx_buff.head)
1875 dma_free_coherent(NULL, self->rx_buff.truesize,
1876 self->rx_buff.head, self->rx_buff_dma);
1878 free_netdev(self->netdev);
1883 static void __exit smsc_ircc_cleanup(void)
1887 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1889 for (i = 0; i < 2; i++) {
1891 smsc_ircc_close(dev_self[i]);
1894 if (pnp_driver_registered)
1895 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1897 platform_driver_unregister(&smsc_ircc_driver);
1901 * Start SIR operations
1903 * This function *must* be called with spinlock held, because it may
1904 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1906 void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1908 struct net_device *dev;
1909 int fir_base, sir_base;
1911 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1913 IRDA_ASSERT(self != NULL, return;);
1915 IRDA_ASSERT(dev != NULL, return;);
1916 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1918 fir_base = self->io.fir_base;
1919 sir_base = self->io.sir_base;
1921 /* Reset everything */
1922 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1924 #if SMSC_IRCC2_C_SIR_STOP
1925 /*smsc_ircc_sir_stop(self);*/
1928 register_bank(fir_base, 1);
1929 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1931 /* Initialize UART */
1932 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1933 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1935 /* Turn on interrups */
1936 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1938 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1940 outb(0x00, fir_base + IRCC_MASTER);
1943 #if SMSC_IRCC2_C_SIR_STOP
1944 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1948 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1949 iobase = self->io.sir_base;
1952 outb(0, iobase + UART_MCR);
1954 /* Turn off interrupts */
1955 outb(0, iobase + UART_IER);
1960 * Function smsc_sir_write_wakeup (self)
1962 * Called by the SIR interrupt handler when there's room for more data.
1963 * If we have more packets to send, we send them here.
1966 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1972 IRDA_ASSERT(self != NULL, return;);
1974 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1976 iobase = self->io.sir_base;
1978 /* Finished with frame? */
1979 if (self->tx_buff.len > 0) {
1980 /* Write data left in transmit buffer */
1981 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1982 self->tx_buff.data, self->tx_buff.len);
1983 self->tx_buff.data += actual;
1984 self->tx_buff.len -= actual;
1987 /*if (self->tx_buff.len ==0) {*/
1990 * Now serial buffer is almost free & we can start
1991 * transmission of another packet. But first we must check
1992 * if we need to change the speed of the hardware
1994 if (self->new_speed) {
1995 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1996 __FUNCTION__, self->new_speed);
1997 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1998 smsc_ircc_change_speed(self, self->new_speed);
1999 self->new_speed = 0;
2001 /* Tell network layer that we want more frames */
2002 netif_wake_queue(self->netdev);
2004 self->stats.tx_packets++;
2006 if (self->io.speed <= 115200) {
2008 * Reset Rx FIFO to make sure that all reflected transmit data
2009 * is discarded. This is needed for half duplex operation
2011 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2012 fcr |= self->io.speed < 38400 ?
2013 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
2015 outb(fcr, iobase + UART_FCR);
2017 /* Turn on receive interrupts */
2018 outb(UART_IER_RDI, iobase + UART_IER);
2024 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2026 * Fill Tx FIFO with transmit data
2029 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2033 /* Tx FIFO should be empty! */
2034 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
2035 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
2039 /* Fill FIFO with current frame */
2040 while (fifo_size-- > 0 && actual < len) {
2041 /* Transmit next byte */
2042 outb(buf[actual], iobase + UART_TX);
2049 * Function smsc_ircc_is_receiving (self)
2051 * Returns true is we are currently receiving data
2054 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2056 return (self->rx_buff.state != OUTSIDE_FRAME);
2061 * Function smsc_ircc_probe_transceiver(self)
2063 * Tries to find the used Transceiver
2066 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2070 IRDA_ASSERT(self != NULL, return;);
2072 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2073 if (smsc_transceivers[i].probe(self->io.fir_base)) {
2074 IRDA_MESSAGE(" %s transceiver found\n",
2075 smsc_transceivers[i].name);
2076 self->transceiver= i + 1;
2080 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2081 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2083 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2088 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2090 * Set the transceiver according to the speed
2093 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2097 trx = self->transceiver;
2099 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2103 * Function smsc_ircc_wait_hw_transmitter_finish ()
2105 * Wait for the real end of HW transmission
2107 * The UART is a strict FIFO, and we get called only when we have finished
2108 * pushing data to the FIFO, so the maximum amount of time we must wait
2109 * is only for the FIFO to drain out.
2111 * We use a simple calibrated loop. We may need to adjust the loop
2112 * delay (udelay) to balance I/O traffic and latency. And we also need to
2113 * adjust the maximum timeout.
2114 * It would probably be better to wait for the proper interrupt,
2115 * but it doesn't seem to be available.
2117 * We can't use jiffies or kernel timers because :
2118 * 1) We are called from the interrupt handler, which disable softirqs,
2119 * so jiffies won't be increased
2120 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2121 * want to wait that long to detect stuck hardware.
2125 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2127 int iobase = self->io.sir_base;
2128 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2130 /* Calibrated busy loop */
2131 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2135 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
2141 * REVISIT we can be told about the device by PNP, and should use that info
2142 * instead of probing hardware and creating a platform_device ...
2145 static int __init smsc_ircc_look_for_chips(void)
2147 struct smsc_chip_address *address;
2149 unsigned int cfg_base, found;
2152 address = possible_addresses;
2154 while (address->cfg_base) {
2155 cfg_base = address->cfg_base;
2157 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
2159 if (address->type & SMSCSIO_TYPE_FDC) {
2161 if (address->type & SMSCSIO_TYPE_FLAT)
2162 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2165 if (address->type & SMSCSIO_TYPE_PAGED)
2166 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2169 if (address->type & SMSCSIO_TYPE_LPC) {
2171 if (address->type & SMSCSIO_TYPE_FLAT)
2172 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2175 if (address->type & SMSCSIO_TYPE_PAGED)
2176 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2185 * Function smsc_superio_flat (chip, base, type)
2187 * Try to get configuration of a smc SuperIO chip with flat register model
2190 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2192 unsigned short firbase, sirbase;
2196 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2198 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2201 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2202 mode = inb(cfgbase + 1);
2204 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
2206 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2207 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2209 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2210 sirbase = inb(cfgbase + 1) << 2;
2213 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2214 firbase = inb(cfgbase + 1) << 3;
2217 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2218 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2221 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2222 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2224 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2226 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2229 /* Exit configuration */
2230 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2236 * Function smsc_superio_paged (chip, base, type)
2238 * Try to get configuration of a smc SuperIO chip with paged register model
2241 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2243 unsigned short fir_io, sir_io;
2246 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2248 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2251 /* Select logical device (UART2) */
2252 outb(0x07, cfg_base);
2253 outb(0x05, cfg_base + 1);
2256 outb(0x60, cfg_base);
2257 sir_io = inb(cfg_base + 1) << 8;
2258 outb(0x61, cfg_base);
2259 sir_io |= inb(cfg_base + 1);
2262 outb(0x62, cfg_base);
2263 fir_io = inb(cfg_base + 1) << 8;
2264 outb(0x63, cfg_base);
2265 fir_io |= inb(cfg_base + 1);
2266 outb(0x2b, cfg_base); /* ??? */
2268 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2271 /* Exit configuration */
2272 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2278 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2280 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2282 outb(reg, cfg_base);
2283 return inb(cfg_base) != reg ? -1 : 0;
2286 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2288 u8 devid, xdevid, rev;
2290 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2292 /* Leave configuration */
2294 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2296 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2299 outb(reg, cfg_base);
2301 xdevid = inb(cfg_base + 1);
2303 /* Enter configuration */
2305 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2308 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2312 /* probe device ID */
2314 if (smsc_access(cfg_base, reg))
2317 devid = inb(cfg_base + 1);
2319 if (devid == 0 || devid == 0xff) /* typical values for unused port */
2322 /* probe revision ID */
2324 if (smsc_access(cfg_base, reg + 1))
2327 rev = inb(cfg_base + 1);
2329 if (rev >= 128) /* i think this will make no sense */
2332 if (devid == xdevid) /* protection against false positives */
2335 /* Check for expected device ID; are there others? */
2337 while (chip->devid != devid) {
2341 if (chip->name == NULL)
2345 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2346 devid, rev, cfg_base, type, chip->name);
2348 if (chip->rev > rev) {
2349 IRDA_MESSAGE("Revision higher than expected\n");
2353 if (chip->flags & NoIRDA)
2354 IRDA_MESSAGE("chipset does not support IRDA\n");
2359 static int __init smsc_superio_fdc(unsigned short cfg_base)
2363 if (!request_region(cfg_base, 2, driver_name)) {
2364 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2365 __FUNCTION__, cfg_base);
2367 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2368 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2371 release_region(cfg_base, 2);
2377 static int __init smsc_superio_lpc(unsigned short cfg_base)
2381 if (!request_region(cfg_base, 2, driver_name)) {
2382 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2383 __FUNCTION__, cfg_base);
2385 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2386 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2389 release_region(cfg_base, 2);
2395 * Look for some specific subsystem setups that need
2396 * pre-configuration not properly done by the BIOS (especially laptops)
2397 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2398 * and tosh2450-smcinit.c. The table lists the device entries
2399 * for ISA bridges with an LPC (Low Pin Count) controller which
2400 * handles the communication with the SMSC device. After the LPC
2401 * controller is initialized through PCI, the SMSC device is initialized
2402 * through a dedicated port in the ISA port-mapped I/O area, this latter
2403 * area is used to configure the SMSC device with default
2404 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2405 * used different sets of parameters and different control port
2406 * addresses making a subsystem device table necessary.
2409 #define PCIID_VENDOR_INTEL 0x8086
2410 #define PCIID_VENDOR_ALI 0x10b9
2411 static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2413 * Subsystems needing entries:
2414 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2415 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2416 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2420 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2422 .subvendor = 0x103c,
2423 .subdevice = 0x08bc,
2429 .preconfigure = preconfigure_through_82801,
2430 .name = "HP nx5000 family",
2433 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2435 .subvendor = 0x103c,
2436 .subdevice = 0x088c,
2437 /* Quite certain these are the same for nc8000 as for nc6000 */
2443 .preconfigure = preconfigure_through_82801,
2444 .name = "HP nc8000 family",
2447 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2449 .subvendor = 0x103c,
2450 .subdevice = 0x0890,
2456 .preconfigure = preconfigure_through_82801,
2457 .name = "HP nc6000 family",
2460 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2462 .subvendor = 0x0e11,
2463 .subdevice = 0x0860,
2464 /* I assume these are the same for x1000 as for the others */
2470 .preconfigure = preconfigure_through_82801,
2471 .name = "Compaq x1000 family",
2474 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2475 .vendor = PCIID_VENDOR_INTEL,
2477 .subvendor = 0x1179,
2478 .subdevice = 0xffff, /* 0xffff is "any" */
2484 .preconfigure = preconfigure_through_82801,
2485 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2488 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
2490 .subvendor = 0x1179,
2491 .subdevice = 0xffff, /* 0xffff is "any" */
2497 .preconfigure = preconfigure_through_82801,
2498 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2501 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2502 .vendor = PCIID_VENDOR_INTEL,
2504 .subvendor = 0x1179,
2505 .subdevice = 0xffff, /* 0xffff is "any" */
2511 .preconfigure = preconfigure_through_82801,
2512 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2515 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2516 .vendor = PCIID_VENDOR_ALI,
2518 .subvendor = 0x1179,
2519 .subdevice = 0xffff, /* 0xffff is "any" */
2525 .preconfigure = preconfigure_through_ali,
2526 .name = "Toshiba laptop with ALi ISA bridge",
2533 * This sets up the basic SMSC parameters
2534 * (FIR port, SIR port, FIR DMA, FIR IRQ)
2535 * through the chip configuration port.
2537 static int __init preconfigure_smsc_chip(struct
2538 smsc_ircc_subsystem_configuration
2541 unsigned short iobase = conf->cfg_base;
2542 unsigned char tmpbyte;
2544 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2545 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2546 tmpbyte = inb(iobase +1); // Read device ID
2548 "Detected Chip id: 0x%02x, setting up registers...\n",
2551 /* Disable UART1 and set up SIR I/O port */
2552 outb(0x24, iobase); // select CR24 - UART1 base addr
2553 outb(0x00, iobase + 1); // disable UART1
2554 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2555 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2556 tmpbyte = inb(iobase + 1);
2557 if (tmpbyte != (conf->sir_io >> 2) ) {
2558 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2559 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2563 /* Set up FIR IRQ channel for UART2 */
2564 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2565 tmpbyte = inb(iobase + 1);
2566 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2567 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2568 outb(tmpbyte, iobase + 1);
2569 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2570 if (tmpbyte != conf->fir_irq) {
2571 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2575 /* Set up FIR I/O port */
2576 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2577 outb((conf->fir_io >> 3), iobase + 1);
2578 tmpbyte = inb(iobase + 1);
2579 if (tmpbyte != (conf->fir_io >> 3) ) {
2580 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2584 /* Set up FIR DMA channel */
2585 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2586 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2587 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2588 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2589 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2593 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2594 tmpbyte = inb(iobase + 1);
2595 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2596 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2597 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2599 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2600 tmpbyte = inb(iobase + 1);
2601 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2603 /* This one was not part of tosh1800 */
2604 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2605 tmpbyte = inb(iobase + 1);
2606 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2608 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2609 tmpbyte = inb(iobase + 1);
2610 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2612 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2613 tmpbyte = inb(iobase + 1);
2614 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2616 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2621 /* 82801CAM generic registers */
2624 #define PIRQ_A_D_ROUT 0x60
2625 #define SIRQ_CNTL 0x64
2626 #define PIRQ_E_H_ROUT 0x68
2627 #define PCI_DMA_C 0x90
2628 /* LPC-specific registers */
2629 #define COM_DEC 0xe0
2630 #define GEN1_DEC 0xe4
2632 #define GEN2_DEC 0xec
2634 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2635 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2636 * They all work the same way!
2638 static int __init preconfigure_through_82801(struct pci_dev *dev,
2640 smsc_ircc_subsystem_configuration
2643 unsigned short tmpword;
2644 unsigned char tmpbyte;
2646 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2648 * Select the range for the COMA COM port (SIR)
2651 * Bit 6-4, COMB decode range
2653 * Bit 2-0, COMA decode range
2656 * 000 = 0x3f8-0x3ff (COM1)
2657 * 001 = 0x2f8-0x2ff (COM2)
2661 * 101 = 0x2e8-0x2ef (COM4)
2663 * 111 = 0x3e8-0x3ef (COM3)
2665 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2666 tmpbyte &= 0xf8; /* mask COMA bits */
2667 switch(conf->sir_io) {
2693 tmpbyte |= 0x01; /* COM2 default */
2695 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2696 pci_write_config_byte(dev, COM_DEC, tmpbyte);
2698 /* Enable Low Pin Count interface */
2699 pci_read_config_word(dev, LPC_EN, &tmpword);
2700 /* These seem to be set up at all times,
2701 * just make sure it is properly set.
2703 switch(conf->cfg_base) {
2717 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2721 tmpword &= 0xfffd; /* disable LPC COMB */
2722 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2723 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2724 pci_write_config_word(dev, LPC_EN, tmpword);
2727 * Configure LPC DMA channel
2729 * Bit 15-14: DMA channel 7 select
2730 * Bit 13-12: DMA channel 6 select
2731 * Bit 11-10: DMA channel 5 select
2733 * Bit 7-6: DMA channel 3 select
2734 * Bit 5-4: DMA channel 2 select
2735 * Bit 3-2: DMA channel 1 select
2736 * Bit 1-0: DMA channel 0 select
2737 * 00 = Reserved value
2739 * 10 = Reserved value
2742 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2743 switch(conf->fir_dma) {
2766 break; /* do not change settings */
2768 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2769 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2773 * Bit 15-4: Generic I/O range
2774 * Bit 3-1: reserved (read as 0)
2775 * Bit 0: enable GEN2 range on LPC I/F
2777 tmpword = conf->fir_io & 0xfff8;
2779 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2780 pci_write_config_word(dev, GEN2_DEC, tmpword);
2782 /* Pre-configure chip */
2783 return preconfigure_smsc_chip(conf);
2787 * Pre-configure a certain port on the ALi 1533 bridge.
2788 * This is based on reverse-engineering since ALi does not
2789 * provide any data sheet for the 1533 chip.
2791 static void __init preconfigure_ali_port(struct pci_dev *dev,
2792 unsigned short port)
2795 /* These bits obviously control the different ports */
2797 unsigned char tmpbyte;
2818 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2822 pci_read_config_byte(dev, reg, &tmpbyte);
2823 /* Turn on the right bits */
2825 pci_write_config_byte(dev, reg, tmpbyte);
2826 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2830 static int __init preconfigure_through_ali(struct pci_dev *dev,
2832 smsc_ircc_subsystem_configuration
2835 /* Configure the two ports on the ALi 1533 */
2836 preconfigure_ali_port(dev, conf->sir_io);
2837 preconfigure_ali_port(dev, conf->fir_io);
2839 /* Pre-configure chip */
2840 return preconfigure_smsc_chip(conf);
2843 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2844 unsigned short ircc_fir,
2845 unsigned short ircc_sir,
2846 unsigned char ircc_dma,
2847 unsigned char ircc_irq)
2849 struct pci_dev *dev = NULL;
2850 unsigned short ss_vendor = 0x0000;
2851 unsigned short ss_device = 0x0000;
2854 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2856 while (dev != NULL) {
2857 struct smsc_ircc_subsystem_configuration *conf;
2860 * Cache the subsystem vendor/device:
2861 * some manufacturers fail to set this for all components,
2862 * so we save it in case there is just 0x0000 0x0000 on the
2863 * device we want to check.
2865 if (dev->subsystem_vendor != 0x0000U) {
2866 ss_vendor = dev->subsystem_vendor;
2867 ss_device = dev->subsystem_device;
2869 conf = subsystem_configurations;
2870 for( ; conf->subvendor; conf++) {
2871 if(conf->vendor == dev->vendor &&
2872 conf->device == dev->device &&
2873 conf->subvendor == ss_vendor &&
2874 /* Sometimes these are cached values */
2875 (conf->subdevice == ss_device ||
2876 conf->subdevice == 0xffff)) {
2877 struct smsc_ircc_subsystem_configuration
2880 memcpy(&tmpconf, conf,
2881 sizeof(struct smsc_ircc_subsystem_configuration));
2884 * Override the default values with anything
2885 * passed in as parameter
2888 tmpconf.cfg_base = ircc_cfg;
2890 tmpconf.fir_io = ircc_fir;
2892 tmpconf.sir_io = ircc_sir;
2893 if (ircc_dma != DMA_INVAL)
2894 tmpconf.fir_dma = ircc_dma;
2895 if (ircc_irq != IRQ_INVAL)
2896 tmpconf.fir_irq = ircc_irq;
2898 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2899 if (conf->preconfigure)
2900 ret = conf->preconfigure(dev, &tmpconf);
2905 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2910 #endif // CONFIG_PCI
2912 /************************************************
2914 * Transceivers specific functions
2916 ************************************************/
2920 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2922 * Program transceiver through smsc-ircc ATC circuitry
2926 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2928 unsigned long jiffies_now, jiffies_timeout;
2931 jiffies_now = jiffies;
2932 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2935 register_bank(fir_base, 4);
2936 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2937 fir_base + IRCC_ATC);
2939 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2940 !time_after(jiffies, jiffies_timeout))
2944 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
2945 inb(fir_base + IRCC_ATC));
2949 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2951 * Probe transceiver smsc-ircc ATC circuitry
2955 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2961 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2967 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2978 fast_mode = IRCC_LCR_A_FAST;
2981 register_bank(fir_base, 0);
2982 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2986 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2992 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2998 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
3004 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
3015 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3019 /* This causes an interrupt */
3020 register_bank(fir_base, 0);
3021 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
3025 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3031 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3037 module_init(smsc_ircc_init);
3038 module_exit(smsc_ircc_cleanup);