Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6] / drivers / scsi / dc395x.h
1 /************************************************************************/
2 /*                                                                      */
3 /*      dc395x.h                                                        */
4 /*                                                                      */
5 /*      Device Driver for Tekram DC395(U/UW/F), DC315(U)                */
6 /*      PCI SCSI Bus Master Host Adapter                                */
7 /*      (SCSI chip set used Tekram ASIC TRM-S1040)                      */
8 /*                                                                      */
9 /************************************************************************/
10 #ifndef DC395x_H
11 #define DC395x_H
12
13 /************************************************************************/
14 /*                                                                      */
15 /*      Initial values                                                  */
16 /*                                                                      */
17 /************************************************************************/
18 #define DC395x_MAX_CMD_QUEUE            32
19 /* #define DC395x_MAX_QTAGS             32 */
20 #define DC395x_MAX_QTAGS                16
21 #define DC395x_MAX_SCSI_ID              16
22 #define DC395x_MAX_CMD_PER_LUN          DC395x_MAX_QTAGS
23 #define DC395x_MAX_SG_TABLESIZE         64      /* HW limitation                        */
24 #define DC395x_MAX_SG_LISTENTRY         64      /* Must be equal or lower to previous   */
25                                                 /* item                                 */
26 #define DC395x_MAX_SRB_CNT              63
27 /* #define DC395x_MAX_CAN_QUEUE         7 * DC395x_MAX_QTAGS */
28 #define DC395x_MAX_CAN_QUEUE            DC395x_MAX_SRB_CNT
29 #define DC395x_END_SCAN                 2
30 #define DC395x_SEL_TIMEOUT              153     /* 250 ms selection timeout (@ 40 MHz)  */
31 #define DC395x_MAX_RETRIES              3
32
33 #if 0
34 #define SYNC_FIRST
35 #endif
36
37 #define NORM_REC_LVL                    0
38
39 /************************************************************************/
40 /*                                                                      */
41 /*      Various definitions                                             */
42 /*                                                                      */
43 /************************************************************************/
44 #define BIT31                           0x80000000
45 #define BIT30                           0x40000000
46 #define BIT29                           0x20000000
47 #define BIT28                           0x10000000
48 #define BIT27                           0x08000000
49 #define BIT26                           0x04000000
50 #define BIT25                           0x02000000
51 #define BIT24                           0x01000000
52 #define BIT23                           0x00800000
53 #define BIT22                           0x00400000
54 #define BIT21                           0x00200000
55 #define BIT20                           0x00100000
56 #define BIT19                           0x00080000
57 #define BIT18                           0x00040000
58 #define BIT17                           0x00020000
59 #define BIT16                           0x00010000
60 #define BIT15                           0x00008000
61 #define BIT14                           0x00004000
62 #define BIT13                           0x00002000
63 #define BIT12                           0x00001000
64 #define BIT11                           0x00000800
65 #define BIT10                           0x00000400
66 #define BIT9                            0x00000200
67 #define BIT8                            0x00000100
68 #define BIT7                            0x00000080
69 #define BIT6                            0x00000040
70 #define BIT5                            0x00000020
71 #define BIT4                            0x00000010
72 #define BIT3                            0x00000008
73 #define BIT2                            0x00000004
74 #define BIT1                            0x00000002
75 #define BIT0                            0x00000001
76
77 /* UnitCtrlFlag */
78 #define UNIT_ALLOCATED                  BIT0
79 #define UNIT_INFO_CHANGED               BIT1
80 #define FORMATING_MEDIA                 BIT2
81 #define UNIT_RETRY                      BIT3
82
83 /* UnitFlags */
84 #define DASD_SUPPORT                    BIT0
85 #define SCSI_SUPPORT                    BIT1
86 #define ASPI_SUPPORT                    BIT2
87
88 /* SRBState machine definition */
89 #define SRB_FREE                        0x0000
90 #define SRB_WAIT                        0x0001
91 #define SRB_READY                       0x0002
92 #define SRB_MSGOUT                      0x0004  /* arbitration+msg_out 1st byte         */
93 #define SRB_MSGIN                       0x0008
94 #define SRB_EXTEND_MSGIN                0x0010
95 #define SRB_COMMAND                     0x0020
96 #define SRB_START_                      0x0040  /* arbitration+msg_out+command_out      */
97 #define SRB_DISCONNECT                  0x0080
98 #define SRB_DATA_XFER                   0x0100
99 #define SRB_XFERPAD                     0x0200
100 #define SRB_STATUS                      0x0400
101 #define SRB_COMPLETED                   0x0800
102 #define SRB_ABORT_SENT                  0x1000
103 #define SRB_DO_SYNC_NEGO                0x2000
104 #define SRB_DO_WIDE_NEGO                0x4000
105 #define SRB_UNEXPECT_RESEL              0x8000
106
107 /************************************************************************/
108 /*                                                                      */
109 /*      ACB Config                                                      */
110 /*                                                                      */
111 /************************************************************************/
112 #define HCC_WIDE_CARD                   0x20
113 #define HCC_SCSI_RESET                  0x10
114 #define HCC_PARITY                      0x08
115 #define HCC_AUTOTERM                    0x04
116 #define HCC_LOW8TERM                    0x02
117 #define HCC_UP8TERM                     0x01
118
119 /* ACBFlag */
120 #define RESET_DEV                       BIT0
121 #define RESET_DETECT                    BIT1
122 #define RESET_DONE                      BIT2
123
124 /* DCBFlag */
125 #define ABORT_DEV_                      BIT0
126
127 /* SRBstatus */
128 #define SRB_OK                          BIT0
129 #define ABORTION                        BIT1
130 #define OVER_RUN                        BIT2
131 #define UNDER_RUN                       BIT3
132 #define PARITY_ERROR                    BIT4
133 #define SRB_ERROR                       BIT5
134
135 /* SRBFlag */
136 #define DATAOUT                         BIT7
137 #define DATAIN                          BIT6
138 #define RESIDUAL_VALID                  BIT5
139 #define ENABLE_TIMER                    BIT4
140 #define RESET_DEV0                      BIT2
141 #define ABORT_DEV                       BIT1
142 #define AUTO_REQSENSE                   BIT0
143
144 /* Adapter status */
145 #define H_STATUS_GOOD                   0
146 #define H_SEL_TIMEOUT                   0x11
147 #define H_OVER_UNDER_RUN                0x12
148 #define H_UNEXP_BUS_FREE                0x13
149 #define H_TARGET_PHASE_F                0x14
150 #define H_INVALID_CCB_OP                0x16
151 #define H_LINK_CCB_BAD                  0x17
152 #define H_BAD_TARGET_DIR                0x18
153 #define H_DUPLICATE_CCB                 0x19
154 #define H_BAD_CCB_OR_SG                 0x1A
155 #define H_ABORT                         0x0FF
156
157 /* SCSI BUS Status byte codes */
158 #define SCSI_STAT_GOOD                  0x0     /* Good status                          */
159 #define SCSI_STAT_CHECKCOND             0x02    /* SCSI Check Condition                 */
160 #define SCSI_STAT_CONDMET               0x04    /* Condition Met                        */
161 #define SCSI_STAT_BUSY                  0x08    /* Target busy status                   */
162 #define SCSI_STAT_INTER                 0x10    /* Intermediate status                  */
163 #define SCSI_STAT_INTERCONDMET          0x14    /* Intermediate condition met           */
164 #define SCSI_STAT_RESCONFLICT           0x18    /* Reservation conflict                 */
165 #define SCSI_STAT_CMDTERM               0x22    /* Command Terminated                   */
166 #define SCSI_STAT_QUEUEFULL             0x28    /* Queue Full                           */
167 #define SCSI_STAT_UNEXP_BUS_F           0xFD    /* Unexpect Bus Free                    */
168 #define SCSI_STAT_BUS_RST_DETECT        0xFE    /* Scsi Bus Reset detected              */
169 #define SCSI_STAT_SEL_TIMEOUT           0xFF    /* Selection Time out                   */
170
171 /* Sync_Mode */
172 #define SYNC_WIDE_TAG_ATNT_DISABLE      0
173 #define SYNC_NEGO_ENABLE                BIT0
174 #define SYNC_NEGO_DONE                  BIT1
175 #define WIDE_NEGO_ENABLE                BIT2
176 #define WIDE_NEGO_DONE                  BIT3
177 #define WIDE_NEGO_STATE                 BIT4
178 #define EN_TAG_QUEUEING                 BIT5
179 #define EN_ATN_STOP                     BIT6
180
181 #define SYNC_NEGO_OFFSET                15
182
183 /* SCSI MSG BYTE */
184 #define MSG_COMPLETE                    0x00
185 #define MSG_EXTENDED                    0x01
186 #define MSG_SAVE_PTR                    0x02
187 #define MSG_RESTORE_PTR                 0x03
188 #define MSG_DISCONNECT                  0x04
189 #define MSG_INITIATOR_ERROR             0x05
190 #define MSG_ABORT                       0x06
191 #define MSG_REJECT_                     0x07
192 #define MSG_NOP                         0x08
193 #define MSG_PARITY_ERROR                0x09
194 #define MSG_LINK_CMD_COMPL              0x0A
195 #define MSG_LINK_CMD_COMPL_FLG          0x0B
196 #define MSG_BUS_RESET                   0x0C
197 #define MSG_ABORT_TAG                   0x0D
198 #define MSG_SIMPLE_QTAG                 0x20
199 #define MSG_HEAD_QTAG                   0x21
200 #define MSG_ORDER_QTAG                  0x22
201 #define MSG_IGNOREWIDE                  0x23
202 #define MSG_IDENTIFY                    0x80
203 #define MSG_HOST_ID                     0xC0
204
205 /* SCSI STATUS BYTE */
206 #define STATUS_GOOD                     0x00
207 #define CHECK_CONDITION_                0x02
208 #define STATUS_BUSY                     0x08
209 #define STATUS_INTERMEDIATE             0x10
210 #define RESERVE_CONFLICT                0x18
211
212 /* cmd->result */
213 #define STATUS_MASK_                    0xFF
214 #define MSG_MASK                        0xFF00
215 #define RETURN_MASK                     0xFF0000
216
217 /************************************************************************/
218 /*                                                                      */
219 /*      Inquiry Data format                                             */
220 /*                                                                      */
221 /************************************************************************/
222 struct ScsiInqData
223 {                                               /* INQ                                  */
224         u8 DevType;                             /* Periph Qualifier & Periph Dev Type   */
225         u8 RMB_TypeMod;                         /* rem media bit & Dev Type Modifier    */
226         u8 Vers;                                /* ISO, ECMA, & ANSI versions           */
227         u8 RDF;                                 /* AEN, TRMIOP, & response data format  */
228         u8 AddLen;                              /* length of additional data            */
229         u8 Res1;                                /* reserved                             */
230         u8 Res2;                                /* reserved                             */
231         u8 Flags;                               /* RelADr, Wbus32, Wbus16, Sync, etc.   */
232         u8 VendorID[8];                         /* Vendor Identification                */
233         u8 ProductID[16];                       /* Product Identification               */
234         u8 ProductRev[4];                       /* Product Revision                     */
235 };
236
237                                                 /* Inquiry byte 0 masks                 */
238 #define SCSI_DEVTYPE                    0x1F    /* Peripheral Device Type               */
239 #define SCSI_PERIPHQUAL                 0xE0    /* Peripheral Qualifier                 */
240                                                 /* Inquiry byte 1 mask                  */
241 #define SCSI_REMOVABLE_MEDIA            0x80    /* Removable Media bit (1=removable)    */
242                                                 /* Peripheral Device Type definitions   */
243                                                 /* See include/scsi/scsi.h              */
244 #define TYPE_NODEV              SCSI_DEVTYPE    /* Unknown or no device type            */
245 #ifndef TYPE_PRINTER                            /*                                      */
246 # define TYPE_PRINTER                   0x02    /* Printer device                       */
247 #endif                                          /*                                      */
248 #ifndef TYPE_COMM                               /*                                      */
249 # define TYPE_COMM                      0x09    /* Communications device                */
250 #endif
251
252 /************************************************************************/
253 /*                                                                      */
254 /*      Inquiry flag definitions (Inq data byte 7)                      */
255 /*                                                                      */
256 /************************************************************************/
257 #define SCSI_INQ_RELADR                 0x80    /* device supports relative addressing  */
258 #define SCSI_INQ_WBUS32                 0x40    /* device supports 32 bit data xfers    */
259 #define SCSI_INQ_WBUS16                 0x20    /* device supports 16 bit data xfers    */
260 #define SCSI_INQ_SYNC                   0x10    /* device supports synchronous xfer     */
261 #define SCSI_INQ_LINKED                 0x08    /* device supports linked commands      */
262 #define SCSI_INQ_CMDQUEUE               0x02    /* device supports command queueing     */
263 #define SCSI_INQ_SFTRE                  0x01    /* device supports soft resets          */
264
265 #define ENABLE_CE                       1
266 #define DISABLE_CE                      0
267 #define EEPROM_READ                     0x80
268
269 /************************************************************************/
270 /*                                                                      */
271 /*      The PCI configuration register offset for TRM_S1040             */
272 /*                                                                      */
273 /************************************************************************/
274 #define TRM_S1040_ID                    0x00    /* Vendor and Device ID                 */
275 #define TRM_S1040_COMMAND               0x04    /* PCI command register                 */
276 #define TRM_S1040_IOBASE                0x10    /* I/O Space base address               */
277 #define TRM_S1040_ROMBASE               0x30    /* Expansion ROM Base Address           */
278 #define TRM_S1040_INTLINE               0x3C    /* Interrupt line                       */
279
280 /************************************************************************/
281 /*                                                                      */
282 /*      The SCSI register offset for TRM_S1040                          */
283 /*                                                                      */
284 /************************************************************************/
285 #define TRM_S1040_SCSI_STATUS           0x80    /* SCSI Status (R)                      */
286 #define COMMANDPHASEDONE                0x2000  /* SCSI command phase done              */
287 #define SCSIXFERDONE                    0x0800  /* SCSI SCSI transfer done              */
288 #define SCSIXFERCNT_2_ZERO              0x0100  /* SCSI SCSI transfer count to zero     */
289 #define SCSIINTERRUPT                   0x0080  /* SCSI interrupt pending               */
290 #define COMMANDABORT                    0x0040  /* SCSI command abort                   */
291 #define SEQUENCERACTIVE                 0x0020  /* SCSI sequencer active                */
292 #define PHASEMISMATCH                   0x0010  /* SCSI phase mismatch                  */
293 #define PARITYERROR                     0x0008  /* SCSI parity error                    */
294
295 #define PHASEMASK                       0x0007  /* Phase MSG/CD/IO                      */
296 #define PH_DATA_OUT                     0x00    /* Data out phase                       */
297 #define PH_DATA_IN                      0x01    /* Data in phase                        */
298 #define PH_COMMAND                      0x02    /* Command phase                        */
299 #define PH_STATUS                       0x03    /* Status phase                         */
300 #define PH_BUS_FREE                     0x05    /* Invalid phase used as bus free       */
301 #define PH_MSG_OUT                      0x06    /* Message out phase                    */
302 #define PH_MSG_IN                       0x07    /* Message in phase                     */
303
304 #define TRM_S1040_SCSI_CONTROL          0x80    /* SCSI Control (W)                     */
305 #define DO_CLRATN                       0x0400  /* Clear ATN                            */
306 #define DO_SETATN                       0x0200  /* Set ATN                              */
307 #define DO_CMDABORT                     0x0100  /* Abort SCSI command                   */
308 #define DO_RSTMODULE                    0x0010  /* Reset SCSI chip                      */
309 #define DO_RSTSCSI                      0x0008  /* Reset SCSI bus                       */
310 #define DO_CLRFIFO                      0x0004  /* Clear SCSI transfer FIFO             */
311 #define DO_DATALATCH                    0x0002  /* Enable SCSI bus data input (latched) */
312 /* #define DO_DATALATCH                 0x0000 */       /* KG: DISable SCSI bus data latch      */
313 #define DO_HWRESELECT                   0x0001  /* Enable hardware reselection          */
314
315 #define TRM_S1040_SCSI_FIFOCNT          0x82    /* SCSI FIFO Counter 5bits(R)           */
316 #define TRM_S1040_SCSI_SIGNAL           0x83    /* SCSI low level signal (R/W)          */
317
318 #define TRM_S1040_SCSI_INTSTATUS        0x84    /* SCSI Interrupt Status (R)            */
319 #define INT_SCAM                        0x80    /* SCAM selection interrupt             */
320 #define INT_SELECT                      0x40    /* Selection interrupt                  */
321 #define INT_SELTIMEOUT                  0x20    /* Selection timeout interrupt          */
322 #define INT_DISCONNECT                  0x10    /* Bus disconnected interrupt           */
323 #define INT_RESELECTED                  0x08    /* Reselected interrupt                 */
324 #define INT_SCSIRESET                   0x04    /* SCSI reset detected interrupt        */
325 #define INT_BUSSERVICE                  0x02    /* Bus service interrupt                */
326 #define INT_CMDDONE                     0x01    /* SCSI command done interrupt          */
327
328 #define TRM_S1040_SCSI_OFFSET           0x84    /* SCSI Offset Count (W)                */
329
330 /************************************************************************/
331 /*                                                                      */
332 /*      Bit             Name            Definition                      */
333 /*      ---------       -------------   ----------------------------    */
334 /*      07-05   0       RSVD            Reversed. Always 0.             */
335 /*      04      0       OFFSET4         Reversed for LVDS. Always 0.    */
336 /*      03-00   0       OFFSET[03:00]   Offset number from 0 to 15      */
337 /*                                                                      */
338 /************************************************************************/
339
340 #define TRM_S1040_SCSI_SYNC             0x85    /* SCSI Synchronous Control (R/W)       */
341 #define LVDS_SYNC                       0x20    /* Enable LVDS synchronous              */
342 #define WIDE_SYNC                       0x10    /* Enable WIDE synchronous              */
343 #define ALT_SYNC                        0x08    /* Enable Fast-20 alternate synchronous */
344
345 /************************************************************************/
346 /*                                                                      */
347 /*      SYNCM   7    6    5    4    3       2       1       0           */
348 /*      Name    RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0     */
349 /*      Default 0    0    0    0    0       0       0       0           */
350 /*                                                                      */
351 /*      Bit             Name            Definition                      */
352 /*      ---------       -------------   ---------------------------     */
353 /*      07-06   0       RSVD            Reversed. Always read 0         */
354 /*      05      0       LVDS            Reversed. Always read 0         */
355 /*      04      0       WIDE/WSCSI      Enable wide (16-bits) SCSI      */
356 /*                                      transfer.                       */
357 /*      03      0       ALTPERD/ALTPD   Alternate (Sync./Period) mode.  */
358 /*                                                                      */
359 /*                      @@ When this bit is set,                        */
360 /*                         the synchronous period bits 2:0              */
361 /*                         in the Synchronous Mode register             */
362 /*                         are used to transfer data                    */
363 /*                         at the Fast-20 rate.                         */
364 /*                      @@ When this bit is unset,                      */
365 /*                         the synchronous period bits 2:0              */
366 /*                         in the Synchronous Mode Register             */
367 /*                         are used to transfer data                    */
368 /*                         at the Fast-10 rate (or Fast-40 w/ LVDS).    */
369 /*                                                                      */
370 /*      02-00   0       PERIOD[2:0]/    Synchronous SCSI Transfer Rate. */
371 /*                      SXPD[02:00]     These 3 bits specify            */
372 /*                                      the Synchronous SCSI Transfer   */
373 /*                                      Rate for Fast-20 and Fast-10.   */
374 /*                                      These bits are also reset       */
375 /*                                      by a SCSI Bus reset.            */
376 /*                                                                      */
377 /*      For Fast-10 bit ALTPD = 0 and LVDS = 0                          */
378 /*      and bit2,bit1,bit0 is defined as follows :                      */
379 /*                                                                      */
380 /*      000     100ns, 10.0 MHz                                         */
381 /*      001     150ns,  6.6 MHz                                         */
382 /*      010     200ns,  5.0 MHz                                         */
383 /*      011     250ns,  4.0 MHz                                         */
384 /*      100     300ns,  3.3 MHz                                         */
385 /*      101     350ns,  2.8 MHz                                         */
386 /*      110     400ns,  2.5 MHz                                         */
387 /*      111     450ns,  2.2 MHz                                         */
388 /*                                                                      */
389 /*      For Fast-20 bit ALTPD = 1 and LVDS = 0                          */
390 /*      and bit2,bit1,bit0 is defined as follows :                      */
391 /*                                                                      */
392 /*      000      50ns, 20.0 MHz                                         */
393 /*      001      75ns, 13.3 MHz                                         */
394 /*      010     100ns, 10.0 MHz                                         */
395 /*      011     125ns,  8.0 MHz                                         */
396 /*      100     150ns,  6.6 MHz                                         */
397 /*      101     175ns,  5.7 MHz                                         */
398 /*      110     200ns,  5.0 MHz                                         */
399 /*      111     250ns,  4.0 MHz   KG: Maybe 225ns, 4.4 MHz              */
400 /*                                                                      */
401 /*      For Fast-40 bit ALTPD = 0 and LVDS = 1                          */
402 /*      and bit2,bit1,bit0 is defined as follows :                      */
403 /*                                                                      */
404 /*      000      25ns, 40.0 MHz                                         */
405 /*      001      50ns, 20.0 MHz                                         */
406 /*      010      75ns, 13.3 MHz                                         */
407 /*      011     100ns, 10.0 MHz                                         */
408 /*      100     125ns,  8.0 MHz                                         */
409 /*      101     150ns,  6.6 MHz                                         */
410 /*      110     175ns,  5.7 MHz                                         */
411 /*      111     200ns,  5.0 MHz                                         */
412 /*                                                                      */
413 /************************************************************************/
414
415 #define TRM_S1040_SCSI_TARGETID         0x86    /* SCSI Target ID (R/W)                 */
416 #define TRM_S1040_SCSI_IDMSG            0x87    /* SCSI Identify Message (R)            */
417 #define TRM_S1040_SCSI_HOSTID           0x87    /* SCSI Host ID (W)                     */
418 #define TRM_S1040_SCSI_COUNTER          0x88    /* SCSI Transfer Counter 24bits(R/W)    */
419
420 #define TRM_S1040_SCSI_INTEN            0x8C    /* SCSI Interrupt Enable (R/W)          */
421 #define EN_SCAM                         0x80    /* Enable SCAM selection interrupt      */
422 #define EN_SELECT                       0x40    /* Enable selection interrupt           */
423 #define EN_SELTIMEOUT                   0x20    /* Enable selection timeout interrupt   */
424 #define EN_DISCONNECT                   0x10    /* Enable bus disconnected interrupt    */
425 #define EN_RESELECTED                   0x08    /* Enable reselected interrupt          */
426 #define EN_SCSIRESET                    0x04    /* Enable SCSI reset detected interrupt */
427 #define EN_BUSSERVICE                   0x02    /* Enable bus service interrupt         */
428 #define EN_CMDDONE                      0x01    /* Enable SCSI command done interrupt   */
429
430 #define TRM_S1040_SCSI_CONFIG0          0x8D    /* SCSI Configuration 0 (R/W)           */
431 #define PHASELATCH                      0x40    /* Enable phase latch                   */
432 #define INITIATOR                       0x20    /* Enable initiator mode                */
433 #define PARITYCHECK                     0x10    /* Enable parity check                  */
434 #define BLOCKRST                        0x01    /* Disable SCSI reset1                  */
435
436 #define TRM_S1040_SCSI_CONFIG1          0x8E    /* SCSI Configuration 1 (R/W)           */
437 #define ACTIVE_NEGPLUS                  0x10    /* Enhance active negation              */
438 #define FILTER_DISABLE                  0x08    /* Disable SCSI data filter             */
439 #define FAST_FILTER                     0x04    /* ?                                    */
440 #define ACTIVE_NEG                      0x02    /* Enable active negation               */
441
442 #define TRM_S1040_SCSI_CONFIG2          0x8F    /* SCSI Configuration 2 (R/W)           */
443 #define CFG2_WIDEFIFO                   0x02    /*                                      */
444
445 #define TRM_S1040_SCSI_COMMAND          0x90    /* SCSI Command (R/W)                   */
446 #define SCMD_COMP                       0x12    /* Command complete                     */
447 #define SCMD_SEL_ATN                    0x60    /* Selection with ATN                   */
448 #define SCMD_SEL_ATN3                   0x64    /* Selection with ATN3                  */
449 #define SCMD_SEL_ATNSTOP                0xB8    /* Selection with ATN and Stop          */
450 #define SCMD_FIFO_OUT                   0xC0    /* SCSI FIFO transfer out               */
451 #define SCMD_DMA_OUT                    0xC1    /* SCSI DMA transfer out                */
452 #define SCMD_FIFO_IN                    0xC2    /* SCSI FIFO transfer in                */
453 #define SCMD_DMA_IN                     0xC3    /* SCSI DMA transfer in                 */
454 #define SCMD_MSGACCEPT                  0xD8    /* Message accept                       */
455
456 /************************************************************************/
457 /*                                                                      */
458 /*      Code    Command Description                                     */
459 /*      ----    ----------------------------------------                */
460 /*      02      Enable reselection with FIFO                            */
461 /*      40      Select without ATN with FIFO                            */
462 /*      60      Select with ATN with FIFO                               */
463 /*      64      Select with ATN3 with FIFO                              */
464 /*      A0      Select with ATN and stop with FIFO                      */
465 /*      C0      Transfer information out with FIFO                      */
466 /*      C1      Transfer information out with DMA                       */
467 /*      C2      Transfer information in with FIFO                       */
468 /*      C3      Transfer information in with DMA                        */
469 /*      12      Initiator command complete with FIFO                    */
470 /*      50      Initiator transfer information out sequence without ATN */
471 /*              with FIFO                                               */
472 /*      70      Initiator transfer information out sequence with ATN    */
473 /*              with FIFO                                               */
474 /*      74      Initiator transfer information out sequence with ATN3   */
475 /*              with FIFO                                               */
476 /*      52      Initiator transfer information in sequence without ATN  */
477 /*              with FIFO                                               */
478 /*      72      Initiator transfer information in sequence with ATN     */
479 /*              with FIFO                                               */
480 /*      76      Initiator transfer information in sequence with ATN3    */
481 /*              with FIFO                                               */
482 /*      90      Initiator transfer information out command complete     */
483 /*              with FIFO                                               */
484 /*      92      Initiator transfer information in command complete      */
485 /*              with FIFO                                               */
486 /*      D2      Enable selection                                        */
487 /*      08      Reselection                                             */
488 /*      48      Disconnect command with FIFO                            */
489 /*      88      Terminate command with FIFO                             */
490 /*      C8      Target command complete with FIFO                       */
491 /*      18      SCAM Arbitration/ Selection                             */
492 /*      5A      Enable reselection                                      */
493 /*      98      Select without ATN with FIFO                            */
494 /*      B8      Select with ATN with FIFO                               */
495 /*      D8      Message Accepted                                        */
496 /*      58      NOP                                                     */
497 /*                                                                      */
498 /************************************************************************/
499
500 #define TRM_S1040_SCSI_TIMEOUT          0x91    /* SCSI Time Out Value (R/W)            */
501 #define TRM_S1040_SCSI_FIFO             0x98    /* SCSI FIFO (R/W)                      */
502
503 #define TRM_S1040_SCSI_TCR0             0x9C    /* SCSI Target Control 0 (R/W)          */
504 #define TCR0_WIDE_NEGO_DONE             0x8000  /* Wide nego done                       */
505 #define TCR0_SYNC_NEGO_DONE             0x4000  /* Synchronous nego done                */
506 #define TCR0_ENABLE_LVDS                0x2000  /* Enable LVDS synchronous              */
507 #define TCR0_ENABLE_WIDE                0x1000  /* Enable WIDE synchronous              */
508 #define TCR0_ENABLE_ALT                 0x0800  /* Enable alternate synchronous         */
509 #define TCR0_PERIOD_MASK                0x0700  /* Transfer rate                        */
510
511 #define TCR0_DO_WIDE_NEGO               0x0080  /* Do wide NEGO                         */
512 #define TCR0_DO_SYNC_NEGO               0x0040  /* Do sync NEGO                         */
513 #define TCR0_DISCONNECT_EN              0x0020  /* Disconnection enable                 */
514 #define TCR0_OFFSET_MASK                0x001F  /* Offset number                        */
515
516 #define TRM_S1040_SCSI_TCR1             0x9E    /* SCSI Target Control 1 (R/W)          */
517 #define MAXTAG_MASK                     0x7F00  /* Maximum tags (127)                   */
518 #define NON_TAG_BUSY                    0x0080  /* Non tag command active               */
519 #define ACTTAG_MASK                     0x007F  /* Active tags                          */
520
521 /************************************************************************/
522 /*                                                                      */
523 /*      The DMA register offset for TRM_S1040                           */
524 /*                                                                      */
525 /************************************************************************/
526 #define TRM_S1040_DMA_COMMAND           0xA0    /* DMA Command (R/W)                    */
527 #define DMACMD_SG                       0x02    /* Enable HW S/G support                */
528 #define DMACMD_DIR                      0x01    /* 1 = read from SCSI write to Host     */
529 #define XFERDATAIN_SG                   0x0103  /* Transfer data in  w/  SG             */
530 #define XFERDATAOUT_SG                  0x0102  /* Transfer data out w/  SG             */
531 #define XFERDATAIN                      0x0101  /* Transfer data in  w/o SG             */
532 #define XFERDATAOUT                     0x0100  /* Transfer data out w/o SG             */
533
534 #define TRM_S1040_DMA_FIFOCNT           0xA1    /* DMA FIFO Counter (R)                 */
535
536 #define TRM_S1040_DMA_CONTROL           0xA1    /* DMA Control (W)                      */
537 #define DMARESETMODULE                  0x10    /* Reset PCI/DMA module                 */
538 #define STOPDMAXFER                     0x08    /* Stop  DMA transfer                   */
539 #define ABORTXFER                       0x04    /* Abort DMA transfer                   */
540 #define CLRXFIFO                        0x02    /* Clear DMA transfer FIFO              */
541 #define STARTDMAXFER                    0x01    /* Start DMA transfer                   */
542
543 #define TRM_S1040_DMA_FIFOSTAT          0xA2    /* DMA FIFO Status (R)                  */
544
545 #define TRM_S1040_DMA_STATUS            0xA3    /* DMA Interrupt Status (R/W)           */
546 #define XFERPENDING                     0x80    /* Transfer pending                     */
547 #define SCSIBUSY                        0x40    /* SCSI busy                            */
548 #define GLOBALINT                       0x20    /* DMA_INTEN bit 0-4 set                */
549 #define FORCEDMACOMP                    0x10    /* Force DMA transfer complete          */
550 #define DMAXFERERROR                    0x08    /* DMA transfer error                   */
551 #define DMAXFERABORT                    0x04    /* DMA transfer abort                   */
552 #define DMAXFERCOMP                     0x02    /* Bus Master XFER Complete status      */
553 #define SCSICOMP                        0x01    /* SCSI complete interrupt              */
554
555 #define TRM_S1040_DMA_INTEN             0xA4    /* DMA Interrupt Enable (R/W)           */
556 #define EN_FORCEDMACOMP                 0x10    /* Force DMA transfer complete          */
557 #define EN_DMAXFERERROR                 0x08    /* DMA transfer error                   */
558 #define EN_DMAXFERABORT                 0x04    /* DMA transfer abort                   */
559 #define EN_DMAXFERCOMP                  0x02    /* Bus Master XFER Complete status      */
560 #define EN_SCSIINTR                     0x01    /* Enable SCSI complete interrupt       */
561
562 #define TRM_S1040_DMA_CONFIG            0xA6    /* DMA Configuration (R/W)              */
563 #define DMA_ENHANCE                     0x8000  /* Enable DMA enhance feature (SG?)     */
564 #define DMA_PCI_DUAL_ADDR               0x4000  /*                                      */
565 #define DMA_CFG_RES                     0x2000  /* Always 1                             */
566 #define DMA_AUTO_CLR_FIFO               0x1000  /* DISable DMA auto clear FIFO          */
567 #define DMA_MEM_MULTI_READ              0x0800  /*                                      */
568 #define DMA_MEM_WRITE_INVAL             0x0400  /* Memory write and invalidate          */
569 #define DMA_FIFO_CTRL                   0x0300  /* Control FIFO operation with DMA      */
570 #define DMA_FIFO_HALF_HALF              0x0200  /* Keep half filled on both read/write  */
571
572 #define TRM_S1040_DMA_XCNT              0xA8    /* DMA Transfer Counter (R/W), 24bits   */
573 #define TRM_S1040_DMA_CXCNT             0xAC    /* DMA Current Transfer Counter (R)     */
574 #define TRM_S1040_DMA_XLOWADDR          0xB0    /* DMA Transfer Physical Low Address    */
575 #define TRM_S1040_DMA_XHIGHADDR         0xB4    /* DMA Transfer Physical High Address   */
576
577 /************************************************************************/
578 /*                                                                      */
579 /*      The general register offset for TRM_S1040                       */
580 /*                                                                      */
581 /************************************************************************/
582 #define TRM_S1040_GEN_CONTROL           0xD4    /* Global Control                       */
583 #define CTRL_LED                        0x80    /* Control onboard LED                  */
584 #define EN_EEPROM                       0x10    /* Enable EEPROM programming            */
585 #define DIS_TERM                        0x08    /* Disable onboard termination          */
586 #define AUTOTERM                        0x04    /* Enable Auto SCSI terminator          */
587 #define LOW8TERM                        0x02    /* Enable Lower 8 bit SCSI terminator   */
588 #define UP8TERM                         0x01    /* Enable Upper 8 bit SCSI terminator   */
589
590 #define TRM_S1040_GEN_STATUS            0xD5    /* Global Status                        */
591 #define GTIMEOUT                        0x80    /* Global timer reach 0                 */
592 #define EXT68HIGH                       0x40    /* Higher 8 bit connected externally    */
593 #define INT68HIGH                       0x20    /* Higher 8 bit connected internally    */
594 #define CON5068                         0x10    /* External 50/68 pin connected (low)   */
595 #define CON68                           0x08    /* Internal 68 pin connected (low)      */
596 #define CON50                           0x04    /* Internal 50 pin connected (low!)     */
597 #define WIDESCSI                        0x02    /* Wide SCSI card                       */
598 #define STATUS_LOAD_DEFAULT             0x01    /*                                      */
599
600 #define TRM_S1040_GEN_NVRAM             0xD6    /* Serial NON-VOLATILE RAM port         */
601 #define NVR_BITOUT                      0x08    /* Serial data out                      */
602 #define NVR_BITIN                       0x04    /* Serial data in                       */
603 #define NVR_CLOCK                       0x02    /* Serial clock                         */
604 #define NVR_SELECT                      0x01    /* Serial select                        */
605
606 #define TRM_S1040_GEN_EDATA             0xD7    /* Parallel EEPROM data port            */
607 #define TRM_S1040_GEN_EADDRESS          0xD8    /* Parallel EEPROM address              */
608 #define TRM_S1040_GEN_TIMER             0xDB    /* Global timer                         */
609
610 /************************************************************************/
611 /*                                                                      */
612 /*      NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode        */
613 /*                                                                      */
614 /************************************************************************/
615 #define NTC_DO_WIDE_NEGO                0x20    /* Wide negotiate                       */
616 #define NTC_DO_TAG_QUEUEING             0x10    /* Enable SCSI tag queuing              */
617 #define NTC_DO_SEND_START               0x08    /* Send start command SPINUP            */
618 #define NTC_DO_DISCONNECT               0x04    /* Enable SCSI disconnect               */
619 #define NTC_DO_SYNC_NEGO                0x02    /* Sync negotiation                     */
620 #define NTC_DO_PARITY_CHK               0x01    /* (it sould define at NAC)             */
621                                                 /* Parity check enable                  */
622
623 /************************************************************************/
624 /*                                                                      */
625 /*      Nvram Initiater bits definition                                 */
626 /*                                                                      */
627 /************************************************************************/
628 #if 0
629 #define MORE2_DRV                       BIT0
630 #define GREATER_1G                      BIT1
631 #define RST_SCSI_BUS                    BIT2
632 #define ACTIVE_NEGATION                 BIT3
633 #define NO_SEEK                         BIT4
634 #define LUN_CHECK                       BIT5
635 #endif
636
637 /************************************************************************/
638 /*                                                                      */
639 /*      Nvram Adapter Cfg bits definition                               */
640 /*                                                                      */
641 /************************************************************************/
642 #define NAC_SCANLUN                     0x20    /* Include LUN as BIOS device           */
643 #define NAC_POWERON_SCSI_RESET          0x04    /* Power on reset enable                */
644 #define NAC_GREATER_1G                  0x02    /* > 1G support enable                  */
645 #define NAC_GT2DRIVES                   0x01    /* Support more than 2 drives           */
646 /* #define NAC_DO_PARITY_CHK            0x08 */ /* Parity check enable                  */
647
648 #endif