V4L/DVB (5240): Qt1010: use i2c_gate_ctrl where appropriate
[linux-2.6] / drivers / media / dvb / frontends / qt1010.c
1 /*
2  *  Driver for Quantek QT1010 silicon tuner
3  *
4  *  Copyright (C) 2006 Antti Palosaari <crope@iki.fi>
5  *                     Aapo Tahkola <aet@rasterburn.org>
6  *
7  *  This program is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License as published by
9  *  the Free Software Foundation; either version 2 of the License, or
10  *  (at your option) any later version.
11  *
12  *  This program is distributed in the hope that it will be useful,
13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *  GNU General Public License for more details.
16  *
17  *  You should have received a copy of the GNU General Public License
18  *  along with this program; if not, write to the Free Software
19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20  */
21 #include "qt1010.h"
22 #include "qt1010_priv.h"
23
24 static int debug;
25 module_param(debug, int, 0644);
26 MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
27
28 #define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "QT1010: " args); printk("\n"); }} while (0)
29
30 /* read single register */
31 static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val)
32 {
33         struct i2c_msg msg[2] = {
34                 { .addr = priv->cfg->i2c_address, .flags = 0,        .buf = &reg, .len = 1 },
35                 { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val,  .len = 1 },
36         };
37
38         if (i2c_transfer(priv->i2c, msg, 2) != 2) {
39                 printk(KERN_WARNING "qt1010 I2C read failed\n");
40                 return -EREMOTEIO;
41         }
42         return 0;
43 }
44
45 /* write single register */
46 static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val)
47 {
48         u8 buf[2] = { reg, val };
49         struct i2c_msg msg = {
50                 .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2
51         };
52
53         if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
54                 printk(KERN_WARNING "qt1010 I2C write failed\n");
55                 return -EREMOTEIO;
56         }
57         return 0;
58 }
59
60 /* dump all registers */
61 static void qt1010_dump_regs(struct qt1010_priv *priv)
62 {
63         char buf[52], buf2[4];
64         u8 reg, val;
65
66         for (reg = 0; ; reg++) {
67                 if (reg % 16 == 0) {
68                         if (reg)
69                                 printk("%s\n", buf);
70                         sprintf(buf, "%02x: ", reg);
71                 }
72                 if (qt1010_readreg(priv, reg, &val) == 0)
73                         sprintf(buf2, "%02x ", val);
74                 else
75                         strcpy(buf2, "-- ");
76                 strcat(buf, buf2);
77                 if (reg == 0x2f)
78                         break;
79         }
80         printk("%s\n", buf);
81 }
82
83 static int qt1010_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
84 {
85         struct qt1010_priv *priv;
86         int err;
87         u32 freq, div, mod1, mod2;
88         u8 i, tmpval, reg05;
89         qt1010_i2c_oper_t rd[48] = {
90                 { QT1010_WR, 0x01, 0x80 },
91                 { QT1010_WR, 0x02, 0x3f },
92                 { QT1010_WR, 0x05, 0xff }, /* 02 c write */
93                 { QT1010_WR, 0x06, 0x44 },
94                 { QT1010_WR, 0x07, 0xff }, /* 04 c write */
95                 { QT1010_WR, 0x08, 0x08 },
96                 { QT1010_WR, 0x09, 0xff }, /* 06 c write */
97                 { QT1010_WR, 0x0a, 0xff }, /* 07 c write */
98                 { QT1010_WR, 0x0b, 0xff }, /* 08 c write */
99                 { QT1010_WR, 0x0c, 0xe1 },
100                 { QT1010_WR, 0x1a, 0xff }, /* 10 c write */
101                 { QT1010_WR, 0x1b, 0x00 },
102                 { QT1010_WR, 0x1c, 0x89 },
103                 { QT1010_WR, 0x11, 0xff }, /* 13 c write */
104                 { QT1010_WR, 0x12, 0xff }, /* 14 c write */
105                 { QT1010_WR, 0x22, 0xff }, /* 15 c write */
106                 { QT1010_WR, 0x1e, 0x00 },
107                 { QT1010_WR, 0x1e, 0xd0 },
108                 { QT1010_RD, 0x22, 0xff }, /* 16 c read */
109                 { QT1010_WR, 0x1e, 0x00 },
110                 { QT1010_RD, 0x05, 0xff }, /* 20 c read */
111                 { QT1010_RD, 0x22, 0xff }, /* 21 c read */
112                 { QT1010_WR, 0x23, 0xd0 },
113                 { QT1010_WR, 0x1e, 0x00 },
114                 { QT1010_WR, 0x1e, 0xe0 },
115                 { QT1010_RD, 0x23, 0xff }, /* 25 c read */
116                 { QT1010_RD, 0x23, 0xff }, /* 26 c read */
117                 { QT1010_WR, 0x1e, 0x00 },
118                 { QT1010_WR, 0x24, 0xd0 },
119                 { QT1010_WR, 0x1e, 0x00 },
120                 { QT1010_WR, 0x1e, 0xf0 },
121                 { QT1010_RD, 0x24, 0xff }, /* 31 c read */
122                 { QT1010_WR, 0x1e, 0x00 },
123                 { QT1010_WR, 0x14, 0x7f },
124                 { QT1010_WR, 0x15, 0x7f },
125                 { QT1010_WR, 0x05, 0xff }, /* 35 c write */
126                 { QT1010_WR, 0x06, 0x00 },
127                 { QT1010_WR, 0x15, 0x1f },
128                 { QT1010_WR, 0x16, 0xff },
129                 { QT1010_WR, 0x18, 0xff },
130                 { QT1010_WR, 0x1f, 0xff }, /* 40 c write */
131                 { QT1010_WR, 0x20, 0xff }, /* 41 c write */
132                 { QT1010_WR, 0x21, 0x53 },
133                 { QT1010_WR, 0x25, 0xff }, /* 43 c write */
134                 { QT1010_WR, 0x26, 0x15 },
135                 { QT1010_WR, 0x00, 0xff }, /* 45 c write */
136                 { QT1010_WR, 0x02, 0x00 },
137                 { QT1010_WR, 0x01, 0x00 }
138         };
139
140 #define FREQ1 32000000 /* 32 MHz */
141 #define FREQ2  4000000 /* 4 MHz Quartz oscillator in the stick? */
142
143         priv = fe->tuner_priv;
144         freq = params->frequency;
145         div = (freq + QT1010_OFFSET) / QT1010_STEP;
146         freq = (div * QT1010_STEP) - QT1010_OFFSET;
147         mod1 = (freq + QT1010_OFFSET) % FREQ1;
148         mod2 = (freq + QT1010_OFFSET) % FREQ2;
149         priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0;
150         priv->frequency = freq;
151
152         if (fe->ops.i2c_gate_ctrl)
153                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
154
155         /* reg 05 base value */
156         if      (freq < 290000000) reg05 = 0x14; /* 290 MHz */
157         else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */
158         else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */
159         else                       reg05 = 0x74;
160
161         /* 0x5 */
162         rd[2].val = reg05;
163
164         /* 07 - set frequency: 32 MHz scale */
165         rd[4].val = (freq + QT1010_OFFSET) / FREQ1;
166
167         /* 09 - changes every 8/24 MHz */
168         if (mod1 < 8000000) rd[6].val = 0x1d;
169         else                rd[6].val = 0x1c;
170
171         /* 0a - set frequency: 4 MHz scale (max 28 MHz) */
172         if      (mod1 < 1*FREQ2) rd[7].val = 0x09; /*  +0 MHz */
173         else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /*  +4 MHz */
174         else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /*  +8 MHz */
175         else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */
176         else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */
177         else if (mod1 < 6*FREQ2) rd[7].val = 0x0c; /* +20 MHz */
178         else if (mod1 < 7*FREQ2) rd[7].val = 0x0b; /* +24 MHz */
179         else                     rd[7].val = 0x0a; /* +28 MHz */
180
181         /* 0b - changes every 2/2 MHz */
182         if (mod2 < 2000000) rd[8].val = 0x45;
183         else                rd[8].val = 0x44;
184
185         /* 1a - set frequency: 125 kHz scale (max 3875 kHz)*/
186         tmpval = 0x78; /* byte, overflows intentionally */
187         rd[10].val = tmpval-((mod2/QT1010_STEP)*0x08);
188
189         /* 11 */
190         rd[13].val = 0xfd; /* TODO: correct value calculation */
191
192         /* 12 */
193         rd[14].val = 0x91; /* TODO: correct value calculation */
194
195         /* 22 */
196         if      (freq < 450000000) rd[15].val = 0xd0; /* 450 MHz */
197         else if (freq < 482000000) rd[15].val = 0xd1; /* 482 MHz */
198         else if (freq < 514000000) rd[15].val = 0xd4; /* 514 MHz */
199         else if (freq < 546000000) rd[15].val = 0xd7; /* 546 MHz */
200         else if (freq < 610000000) rd[15].val = 0xda; /* 610 MHz */
201         else                       rd[15].val = 0xd0;
202
203         /* 05 */
204         rd[35].val = (reg05 & 0xf0);
205
206         /* 1f */
207         if      (mod1 <  8000000) tmpval = 0x00;
208         else if (mod1 < 12000000) tmpval = 0x01;
209         else if (mod1 < 16000000) tmpval = 0x02;
210         else if (mod1 < 24000000) tmpval = 0x03;
211         else if (mod1 < 28000000) tmpval = 0x04;
212         else                      tmpval = 0x05;
213         rd[40].val = (priv->reg1f_init_val + 0x0e + tmpval);
214
215         /* 20 */
216         if      (mod1 <  8000000) tmpval = 0x00;
217         else if (mod1 < 12000000) tmpval = 0x01;
218         else if (mod1 < 20000000) tmpval = 0x02;
219         else if (mod1 < 24000000) tmpval = 0x03;
220         else if (mod1 < 28000000) tmpval = 0x04;
221         else                      tmpval = 0x05;
222         rd[41].val = (priv->reg20_init_val + 0x0d + tmpval);
223
224         /* 25 */
225         rd[43].val = priv->reg25_init_val;
226
227         /* 00 */
228         rd[45].val = 0x92; /* TODO: correct value calculation */
229
230         dprintk("freq:%u 05:%02x 07:%02x 09:%02x 0a:%02x 0b:%02x 1a:%02x 11:%02x " \
231                 "12:%02x 22:%02x 05:%02x 1f:%02x 20:%02x 25:%02x 00:%02x", \
232                 freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, rd[8].val, \
233                 rd[10].val, rd[13].val, rd[14].val, rd[15].val, rd[35].val, \
234                 rd[40].val, rd[41].val, rd[43].val, rd[45].val);
235
236         for (i = 0; i < sizeof(rd) / sizeof(*rd); i++) {
237                 if (rd[i].oper == QT1010_WR) {
238                         err = qt1010_writereg(priv, rd[i].reg, rd[i].val);
239                 } else { /* read is required to proper locking */
240                         err = qt1010_readreg(priv, rd[i].reg, &tmpval);
241                 }
242                 if (err) return err;
243         }
244
245         if (debug)
246                 qt1010_dump_regs(priv);
247
248         if (fe->ops.i2c_gate_ctrl)
249                 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
250
251         return 0;
252 }
253
254 static int qt1010_init_meas1(struct qt1010_priv *priv, u8 oper, u8 reg, u8 reg_init_val, u8 *retval)
255 {
256         u8 i, val1, val2;
257         int err;
258
259         qt1010_i2c_oper_t i2c_data[] = {
260                 { QT1010_WR, reg, reg_init_val },
261                 { QT1010_WR, 0x1e, 0x00 },
262                 { QT1010_WR, 0x1e, oper },
263                 { QT1010_RD, reg, 0xff }
264         };
265
266         for (i = 0; i < sizeof(i2c_data) / sizeof(*i2c_data); i++) {
267                 if (i2c_data[i].oper == QT1010_WR) {
268                         err = qt1010_writereg(priv, i2c_data[i].reg, i2c_data[i].val);
269                 } else {
270                         err = qt1010_readreg(priv, i2c_data[i].reg, &val2);
271                 }
272                 if (err) return err;
273         }
274
275         do {
276                 val1 = val2;
277                 err = qt1010_readreg(priv, reg, &val2);
278                 if (err) return err;
279                 dprintk("compare reg:%02x %02x %02x", reg, val1, val2);
280         } while (val1 != val2);
281         *retval = val1;
282
283         return qt1010_writereg(priv, 0x1e, 0x00);
284 }
285
286 static u8 qt1010_init_meas2(struct qt1010_priv *priv, u8 reg_init_val, u8 *retval)
287 {
288         u8 i, val;
289         int err;
290         qt1010_i2c_oper_t i2c_data[] = {
291                 { QT1010_WR, 0x07, reg_init_val },
292                 { QT1010_WR, 0x22, 0xd0 },
293                 { QT1010_WR, 0x1e, 0x00 },
294                 { QT1010_WR, 0x1e, 0xd0 },
295                 { QT1010_RD, 0x22, 0xff },
296                 { QT1010_WR, 0x1e, 0x00 },
297                 { QT1010_WR, 0x22, 0xff }
298         };
299         for (i = 0; i < sizeof(i2c_data) / sizeof(*i2c_data); i++) {
300                 if (i2c_data[i].oper == QT1010_WR) {
301                         err = qt1010_writereg(priv, i2c_data[i].reg, i2c_data[i].val);
302                 } else {
303                         err = qt1010_readreg(priv, i2c_data[i].reg, &val);
304                 }
305                 if (err) return err;
306         }
307         *retval = val;
308         return 0;
309 }
310
311 static int qt1010_init(struct dvb_frontend *fe)
312 {
313         struct qt1010_priv *priv = fe->tuner_priv;
314         struct dvb_frontend_parameters params;
315         int err;
316         u8 i, tmpval, *valptr = NULL;
317
318         qt1010_i2c_oper_t i2c_data[] = {
319                 { QT1010_WR, 0x01, 0x80 },
320                 { QT1010_WR, 0x0d, 0x84 },
321                 { QT1010_WR, 0x0e, 0xb7 },
322                 { QT1010_WR, 0x2a, 0x23 },
323                 { QT1010_WR, 0x2c, 0xdc },
324                 { QT1010_M1, 0x25, 0x40 }, /* get reg 25 init value */
325                 { QT1010_M1, 0x81, 0xff }, /* get reg 25 init value */
326                 { QT1010_WR, 0x2b, 0x70 },
327                 { QT1010_WR, 0x2a, 0x23 },
328                 { QT1010_M1, 0x26, 0x08 },
329                 { QT1010_M1, 0x82, 0xff },
330                 { QT1010_WR, 0x05, 0x14 },
331                 { QT1010_WR, 0x06, 0x44 },
332                 { QT1010_WR, 0x07, 0x28 },
333                 { QT1010_WR, 0x08, 0x0b },
334                 { QT1010_WR, 0x11, 0xfd },
335                 { QT1010_M1, 0x22, 0x0d },
336                 { QT1010_M1, 0xd0, 0xff },
337                 { QT1010_WR, 0x06, 0x40 },
338                 { QT1010_WR, 0x16, 0xf0 },
339                 { QT1010_WR, 0x02, 0x38 },
340                 { QT1010_WR, 0x03, 0x18 },
341                 { QT1010_WR, 0x20, 0xe0 },
342                 { QT1010_M1, 0x1f, 0x20 }, /* get reg 1f init value */
343                 { QT1010_M1, 0x84, 0xff }, /* get reg 1f init value */
344                 { QT1010_RD, 0x20, 0x20 }, /* get reg 20 init value */
345                 { QT1010_WR, 0x03, 0x19 },
346                 { QT1010_WR, 0x02, 0x3f },
347                 { QT1010_WR, 0x21, 0x53 },
348                 { QT1010_RD, 0x21, 0xff },
349                 { QT1010_WR, 0x11, 0xfd },
350                 { QT1010_WR, 0x05, 0x34 },
351                 { QT1010_WR, 0x06, 0x44 },
352                 { QT1010_WR, 0x08, 0x08 }
353         };
354
355         if (fe->ops.i2c_gate_ctrl)
356                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
357
358         for (i = 0; i < sizeof(i2c_data) / sizeof(*i2c_data); i++) {
359                 switch (i2c_data[i].oper) {
360                 case QT1010_WR:
361                         err = qt1010_writereg(priv, i2c_data[i].reg, i2c_data[i].val);
362                         break;
363                 case QT1010_RD:
364                         if (i2c_data[i].val == 0x20) valptr = &priv->reg20_init_val;
365                         else valptr = &tmpval;
366                         err = qt1010_readreg(priv, i2c_data[i].reg, valptr);
367                         break;
368                 case QT1010_M1:
369                         if (i2c_data[i].val == 0x25) valptr = &priv->reg25_init_val;
370                         else if (i2c_data[i].val == 0x1f) valptr = &priv->reg1f_init_val;
371                         else valptr = &tmpval;
372                         err = qt1010_init_meas1(priv, i2c_data[i+1].reg, i2c_data[i].reg,
373                                                       i2c_data[i].val, valptr);
374                         i++;
375                         break;
376                 }
377                 if (err) return err;
378         }
379
380         for (i = 0x31; i < 0x3a; i++) /* 0x31 - 0x39 */
381                 if ((err = qt1010_init_meas2(priv, i, &tmpval)))
382                         return err;
383
384         params.frequency = 545000000; /* Sigmatek DVB-110 545000000 */
385                                       /* MSI Megasky 580 GL861 533000000 */
386         return qt1010_set_params(fe, &params);
387 }
388
389 static int qt1010_release(struct dvb_frontend *fe)
390 {
391         kfree(fe->tuner_priv);
392         fe->tuner_priv = NULL;
393         return 0;
394 }
395
396 static int qt1010_get_frequency(struct dvb_frontend *fe, u32 *frequency)
397 {
398         struct qt1010_priv *priv = fe->tuner_priv;
399         *frequency = priv->frequency;
400         return 0;
401 }
402
403 static int qt1010_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
404 {
405         struct qt1010_priv *priv = fe->tuner_priv;
406         *bandwidth = priv->bandwidth;
407         return 0;
408 }
409
410 static const struct dvb_tuner_ops qt1010_tuner_ops = {
411         .info = {
412                 .name           = "Quantek QT1010",
413                 .frequency_min  = QT1010_MIN_FREQ,
414                 .frequency_max  = QT1010_MAX_FREQ,
415                 .frequency_step = QT1010_STEP,
416         },
417
418         .release       = qt1010_release,
419         .init          = qt1010_init,
420         /* TODO: implement sleep */
421
422         .set_params    = qt1010_set_params,
423         .get_frequency = qt1010_get_frequency,
424         .get_bandwidth = qt1010_get_bandwidth
425 };
426
427 struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe,
428                                     struct i2c_adapter *i2c,
429                                     struct qt1010_config *cfg)
430 {
431         struct qt1010_priv *priv = NULL;
432         u8 id;
433
434         priv = kzalloc(sizeof(struct qt1010_priv), GFP_KERNEL);
435         if (priv == NULL)
436                 return NULL;
437
438         priv->cfg      = cfg;
439         priv->i2c      = i2c;
440
441         if (fe->ops.i2c_gate_ctrl)
442                 fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
443
444
445         /* Try to detect tuner chip. Probably this is not correct register. */
446         if (qt1010_readreg(priv, 0x29, &id) != 0 || (id != 0x39)) {
447                 kfree(priv);
448                 return NULL;
449         }
450
451         if (fe->ops.i2c_gate_ctrl)
452                 fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
453
454         printk(KERN_INFO "Quantek QT1010 successfully identified.\n");
455         memcpy(&fe->ops.tuner_ops, &qt1010_tuner_ops, sizeof(struct dvb_tuner_ops));
456
457         fe->tuner_priv = priv;
458         return fe;
459 }
460 EXPORT_SYMBOL(qt1010_attach);
461
462 MODULE_DESCRIPTION("Quantek QT1010 silicon tuner driver");
463 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
464 MODULE_AUTHOR("Aapo Tahkola <aet@rasterburn.org>");
465 MODULE_VERSION("0.1");
466 MODULE_LICENSE("GPL");