git.oblomov.eu Git - linux-2.6/blob - arch/frv/kernel/setup.c

   1 /* setup.c: FRV specific setup
   2  *
   3  * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  * - Derived from arch/m68k/kernel/setup.c
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  */
  12
  13 #include <linux/utsrelease.h>
  14 #include <linux/kernel.h>
  15 #include <linux/sched.h>
  16 #include <linux/delay.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/fs.h>
  19 #include <linux/mm.h>
  20 #include <linux/fb.h>
  21 #include <linux/console.h>
  22 #include <linux/genhd.h>
  23 #include <linux/errno.h>
  24 #include <linux/string.h>
  25 #include <linux/major.h>
  26 #include <linux/bootmem.h>
  27 #include <linux/highmem.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/serial.h>
  30 #include <linux/serial_core.h>
  31 #include <linux/serial_reg.h>
  32
  33 #include <asm/setup.h>
  34 #include <asm/irq.h>
  35 #include <asm/sections.h>
  36 #include <asm/pgalloc.h>
  37 #include <asm/busctl-regs.h>
  38 #include <asm/serial-regs.h>
  39 #include <asm/timer-regs.h>
  40 #include <asm/irc-regs.h>
  41 #include <asm/spr-regs.h>
  42 #include <asm/mb-regs.h>
  43 #include <asm/mb93493-regs.h>
  44 #include <asm/gdb-stub.h>
  45 #include <asm/io.h>
  46
  47 #ifdef CONFIG_BLK_DEV_INITRD
  48 #include <linux/blk.h>
  49 #include <asm/pgtable.h>
  50 #endif
  51
  52 #include "local.h"
  53
  54 #ifdef CONFIG_MB93090_MB00
  55 static void __init mb93090_display(void);
  56 #endif
  57 #ifdef CONFIG_MMU
  58 static void __init setup_linux_memory(void);
  59 #else
  60 static void __init setup_uclinux_memory(void);
  61 #endif
  62
  63 #ifdef CONFIG_CONSOLE
  64 extern struct consw *conswitchp;
  65 #endif
  66
  67 #ifdef CONFIG_MB93090_MB00
  68 static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux";
  69 static char __initdata mb93090_version[] = UTS_RELEASE;
  70
  71 int __nongprelbss mb93090_mb00_detected;
  72 #endif
  73
  74 const char __frv_unknown_system[] = "unknown";
  75 const char __frv_mb93091_cb10[] = "mb93091-cb10";
  76 const char __frv_mb93091_cb11[] = "mb93091-cb11";
  77 const char __frv_mb93091_cb30[] = "mb93091-cb30";
  78 const char __frv_mb93091_cb41[] = "mb93091-cb41";
  79 const char __frv_mb93091_cb60[] = "mb93091-cb60";
  80 const char __frv_mb93091_cb70[] = "mb93091-cb70";
  81 const char __frv_mb93091_cb451[] = "mb93091-cb451";
  82 const char __frv_mb93090_mb00[] = "mb93090-mb00";
  83
  84 const char __frv_mb93493[] = "mb93493";
  85
  86 const char __frv_mb93093[] = "mb93093";
  87
  88 static const char *__nongprelbss cpu_series;
  89 static const char *__nongprelbss cpu_core;
  90 static const char *__nongprelbss cpu_silicon;
  91 static const char *__nongprelbss cpu_mmu;
  92 static const char *__nongprelbss cpu_system;
  93 static const char *__nongprelbss cpu_board1;
  94 static const char *__nongprelbss cpu_board2;
  95
  96 static unsigned long __nongprelbss cpu_psr_all;
  97 static unsigned long __nongprelbss cpu_hsr0_all;
  98
  99 unsigned long __nongprelbss pdm_suspend_mode;
 100
 101 unsigned long __nongprelbss rom_length;
 102 unsigned long __nongprelbss memory_start;
 103 unsigned long __nongprelbss memory_end;
 104
 105 unsigned long __nongprelbss dma_coherent_mem_start;
 106 unsigned long __nongprelbss dma_coherent_mem_end;
 107
 108 unsigned long __initdata __sdram_old_base;
 109 unsigned long __initdata num_mappedpages;
 110
 111 struct cpuinfo_frv __nongprelbss boot_cpu_data;
 112
 113 char command_line[COMMAND_LINE_SIZE];
 114 char __initdata redboot_command_line[COMMAND_LINE_SIZE];
 115
 116 #ifdef CONFIG_PM
 117 #define __pminit
 118 #define __pminitdata
 119 #else
 120 #define __pminit __init
 121 #define __pminitdata __initdata
 122 #endif
 123
 124 struct clock_cmode {
 125         uint8_t xbus, sdram, corebus, core, dsu;
 126 };
 127
 128 #define _frac(N,D) ((N)<<4 | (D))
 129 #define _x0_16  _frac(1,6)
 130 #define _x0_25  _frac(1,4)
 131 #define _x0_33  _frac(1,3)
 132 #define _x0_375 _frac(3,8)
 133 #define _x0_5   _frac(1,2)
 134 #define _x0_66  _frac(2,3)
 135 #define _x0_75  _frac(3,4)
 136 #define _x1     _frac(1,1)
 137 #define _x1_5   _frac(3,2)
 138 #define _x2     _frac(2,1)
 139 #define _x3     _frac(3,1)
 140 #define _x4     _frac(4,1)
 141 #define _x4_5   _frac(9,2)
 142 #define _x6     _frac(6,1)
 143 #define _x8     _frac(8,1)
 144 #define _x9     _frac(9,1)
 145
 146 int __nongprelbss clock_p0_current;
 147 int __nongprelbss clock_cm_current;
 148 int __nongprelbss clock_cmode_current;
 149 #ifdef CONFIG_PM
 150 int __nongprelbss clock_cmodes_permitted;
 151 unsigned long __nongprelbss clock_bits_settable;
 152 #endif
 153
 154 static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 };
 155
 156 static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = {
 157         [4]     = {     _x1,    _x1,    _x2,    _x2,    _x0_25  },
 158         [5]     = {     _x1,    _x2,    _x4,    _x4,    _x0_5   },
 159         [8]     = {     _x1,    _x1,    _x1,    _x2,    _x0_25  },
 160         [9]     = {     _x1,    _x2,    _x2,    _x4,    _x0_5   },
 161         [11]    = {     _x1,    _x4,    _x4,    _x8,    _x1     },
 162         [12]    = {     _x1,    _x1,    _x2,    _x4,    _x0_5   },
 163         [13]    = {     _x1,    _x2,    _x4,    _x8,    _x1     },
 164 };
 165
 166 static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = {
 167         [0]     = {     _x1,    _x1,    _x1,    _x1,    _x0_5   },
 168         [1]     = {     _x1,    _x1,    _x1,    _x3,    _x0_25  },
 169         [2]     = {     _x1,    _x1,    _x2,    _x6,    _x0_5   },
 170         [3]     = {     _x1,    _x2,    _x2,    _x6,    _x0_5   },
 171         [4]     = {     _x1,    _x1,    _x2,    _x2,    _x0_16  },
 172         [8]     = {     _x1,    _x1,    _x1,    _x2,    _x0_16  },
 173         [9]     = {     _x1,    _x2,    _x2,    _x4,    _x0_33  },
 174         [12]    = {     _x1,    _x1,    _x2,    _x4,    _x0_33  },
 175         [14]    = {     _x1,    _x3,    _x3,    _x9,    _x0_75  },
 176         [15]    = {     _x1,    _x1_5,  _x1_5,  _x4_5,  _x0_375 },
 177
 178 #define CLOCK_CMODES_PERMITTED_FR405 0xd31f
 179 };
 180
 181 static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
 182         [0]     = {     _x1,    _x2,    _x2,    _x4,    _x0_33  },
 183         [1]     = {     _x1,    _x3,    _x3,    _x6,    _x0_5   },
 184         [2]     = {     _x1,    _x2,    _x4,    _x8,    _x0_66  },
 185         [3]     = {     _x1,    _x1_5,  _x3,    _x6,    _x0_5   },
 186         [4]     = {     _x1,    _x3,    _x3,    _x9,    _x0_75  },
 187         [5]     = {     _x1,    _x2,    _x2,    _x6,    _x0_5   },
 188         [6]     = {     _x1,    _x1_5,  _x1_5,  _x4_5,  _x0_375 },
 189 };
 190
 191 static const struct clock_cmode __pminitdata *clock_cmodes;
 192 static int __pminitdata clock_doubled;
 193
 194 static struct uart_port __initdata __frv_uart0 = {
 195         .uartclk                = 0,
 196         .membase                = (char *) UART0_BASE,
 197         .irq                    = IRQ_CPU_UART0,
 198         .regshift               = 3,
 199         .iotype                 = UPIO_MEM,
 200         .flags                  = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 201 };
 202
 203 static struct uart_port __initdata __frv_uart1 = {
 204         .uartclk                = 0,
 205         .membase                = (char *) UART1_BASE,
 206         .irq                    = IRQ_CPU_UART1,
 207         .regshift               = 3,
 208         .iotype                 = UPIO_MEM,
 209         .flags                  = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 210 };
 211
 212 #if 0
 213 static void __init printk_xampr(unsigned long ampr, unsigned long amlr, char i_d, int n)
 214 {
 215         unsigned long phys, virt, cxn, size;
 216
 217 #ifdef CONFIG_MMU
 218         virt = amlr & 0xffffc000;
 219         cxn = amlr & 0x3fff;
 220 #else
 221         virt = ampr & 0xffffc000;
 222         cxn = 0;
 223 #endif
 224         phys = ampr & xAMPRx_PPFN;
 225         size = 1 << (((ampr & xAMPRx_SS) >> 4) + 17);
 226
 227         printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
 228                i_d, n,
 229                virt, virt + size - 1,
 230                phys,
 231                ampr & xAMPRx_S  ? 'S' : '-',
 232                ampr & xAMPRx_C  ? 'C' : '-',
 233                ampr & DAMPRx_WP ? 'W' : '-',
 234                ampr & xAMPRx_V  ? 'V' : '-',
 235                cxn
 236                );
 237 }
 238 #endif
 239
 240 /*****************************************************************************/
 241 /*
 242  * dump the memory map
 243  */
 244 static void __init dump_memory_map(void)
 245 {
 246
 247 #if 0
 248         /* dump the protection map */
 249         printk_xampr(__get_IAMPR(0),  __get_IAMLR(0),  'I', 0);
 250         printk_xampr(__get_IAMPR(1),  __get_IAMLR(1),  'I', 1);
 251         printk_xampr(__get_IAMPR(2),  __get_IAMLR(2),  'I', 2);
 252         printk_xampr(__get_IAMPR(3),  __get_IAMLR(3),  'I', 3);
 253         printk_xampr(__get_IAMPR(4),  __get_IAMLR(4),  'I', 4);
 254         printk_xampr(__get_IAMPR(5),  __get_IAMLR(5),  'I', 5);
 255         printk_xampr(__get_IAMPR(6),  __get_IAMLR(6),  'I', 6);
 256         printk_xampr(__get_IAMPR(7),  __get_IAMLR(7),  'I', 7);
 257         printk_xampr(__get_IAMPR(8),  __get_IAMLR(8),  'I', 8);
 258         printk_xampr(__get_IAMPR(9),  __get_IAMLR(9),  'i', 9);
 259         printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
 260         printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
 261         printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
 262         printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
 263         printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
 264         printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
 265
 266         printk_xampr(__get_DAMPR(0),  __get_DAMLR(0),  'D', 0);
 267         printk_xampr(__get_DAMPR(1),  __get_DAMLR(1),  'D', 1);
 268         printk_xampr(__get_DAMPR(2),  __get_DAMLR(2),  'D', 2);
 269         printk_xampr(__get_DAMPR(3),  __get_DAMLR(3),  'D', 3);
 270         printk_xampr(__get_DAMPR(4),  __get_DAMLR(4),  'D', 4);
 271         printk_xampr(__get_DAMPR(5),  __get_DAMLR(5),  'D', 5);
 272         printk_xampr(__get_DAMPR(6),  __get_DAMLR(6),  'D', 6);
 273         printk_xampr(__get_DAMPR(7),  __get_DAMLR(7),  'D', 7);
 274         printk_xampr(__get_DAMPR(8),  __get_DAMLR(8),  'D', 8);
 275         printk_xampr(__get_DAMPR(9),  __get_DAMLR(9),  'D', 9);
 276         printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
 277         printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
 278         printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
 279         printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
 280         printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
 281         printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
 282 #endif
 283
 284 #if 0
 285         /* dump the bus controller registers */
 286         printk("LGCR: %08lx\n", __get_LGCR());
 287         printk("Master: %08lx-%08lx CR=%08lx\n",
 288                __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
 289                __get_LMAICR());
 290
 291         int loop;
 292         for (loop = 1; loop <= 7; loop++) {
 293                 unsigned long lcr = __get_LCR(loop), lsbr = __get_LSBR(loop);
 294                 printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
 295                        loop,
 296                        lsbr, lsbr + __get_LSAM(loop),
 297                        lcr & 0x80000000 ? 'r' : '-',
 298                        lcr & 0x40000000 ? 'w' : '-',
 299                        lcr & 0x08000000 ? 'b' : '-',
 300                        lcr & 0x04000000 ? 'B' : '-',
 301                        lcr & 0x02000000 ? 'C' : '-',
 302                        lcr & 0x01000000 ? 'D' : '-',
 303                        lcr & 0x00800000 ? 'W' : '-',
 304                        lcr & 0x00400000 ? 'R' : '-',
 305                        (lcr & 0x00030000) == 0x00000000 ? '4' :
 306                        (lcr & 0x00030000) == 0x00010000 ? '2' :
 307                        (lcr & 0x00030000) == 0x00020000 ? '1' :
 308                        '-'
 309                        );
 310         }
 311 #endif
 312
 313 #if 0
 314         printk("\n");
 315 #endif
 316 } /* end dump_memory_map() */
 317
 318 /*****************************************************************************/
 319 /*
 320  * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
 321  */
 322 #ifdef CONFIG_MB93091_VDK
 323 static void __init detect_mb93091(void)
 324 {
 325 #ifdef CONFIG_MB93090_MB00
 326         /* Detect CB70 without motherboard */
 327         if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) {
 328                 cpu_board1 = __frv_mb93090_mb00;
 329                 mb93090_mb00_detected = 1;
 330         }
 331 #endif
 332
 333 #ifdef CONFIG_FUJITSU_MB93493
 334         cpu_board2 = __frv_mb93493;
 335 #endif
 336
 337 } /* end detect_mb93091() */
 338 #endif
 339
 340 /*****************************************************************************/
 341 /*
 342  * determine the CPU type and set appropriate parameters
 343  *
 344  * Family     Series      CPU Core    Silicon    Imple  Vers
 345  * ----------------------------------------------------------
 346  * FR-V --+-> FR400 --+-> FR401 --+-> MB93401     02     00 [1]
 347  *        |           |           |
 348  *        |           |           +-> MB93401/A   02     01
 349  *        |           |           |
 350  *        |           |           +-> MB93403     02     02
 351  *        |           |
 352  *        |           +-> FR405 ----> MB93405     04     00
 353  *        |
 354  *        +-> FR450 ----> FR451 ----> MB93451     05     00
 355  *        |
 356  *        +-> FR500 ----> FR501 --+-> MB93501     01     01 [2]
 357  *        |                       |
 358  *        |                       +-> MB93501/A   01     02
 359  *        |
 360  *        +-> FR550 --+-> FR551 ----> MB93555     03     01
 361  *
 362  *  [1] The MB93401 is an obsolete CPU replaced by the MB93401A
 363  *  [2] The MB93501 is an obsolete CPU replaced by the MB93501A
 364  *
 365  * Imple is PSR(Processor Status Register)[31:28].
 366  * Vers is PSR(Processor Status Register)[27:24].
 367  *
 368  * A "Silicon" consists of CPU core and some on-chip peripherals.
 369  */
 370 static void __init determine_cpu(void)
 371 {
 372         unsigned long hsr0 = __get_HSR(0);
 373         unsigned long psr = __get_PSR();
 374
 375         /* work out what selectable services the CPU supports */
 376         __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM);
 377         cpu_psr_all = __get_PSR();
 378         __set_PSR(psr);
 379
 380         __set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE);
 381         cpu_hsr0_all = __get_HSR(0);
 382         __set_HSR(0, hsr0);
 383
 384         /* derive other service specs from the CPU type */
 385         cpu_series              = "unknown";
 386         cpu_core                = "unknown";
 387         cpu_silicon             = "unknown";
 388         cpu_mmu                 = "Prot";
 389         cpu_system              = __frv_unknown_system;
 390         clock_cmodes            = NULL;
 391         clock_doubled           = 0;
 392 #ifdef CONFIG_PM
 393         clock_bits_settable     = CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0;
 394 #endif
 395
 396         switch (PSR_IMPLE(psr)) {
 397         case PSR_IMPLE_FR401:
 398                 cpu_series      = "fr400";
 399                 cpu_core        = "fr401";
 400                 pdm_suspend_mode = HSR0_PDM_PLL_RUN;
 401
 402                 switch (PSR_VERSION(psr)) {
 403                 case PSR_VERSION_FR401_MB93401:
 404                         cpu_silicon     = "mb93401";
 405                         cpu_system      = __frv_mb93091_cb10;
 406                         clock_cmodes    = clock_cmodes_fr401_fr403;
 407                         clock_doubled   = 1;
 408                         break;
 409                 case PSR_VERSION_FR401_MB93401A:
 410                         cpu_silicon     = "mb93401/A";
 411                         cpu_system      = __frv_mb93091_cb11;
 412                         clock_cmodes    = clock_cmodes_fr401_fr403;
 413                         break;
 414                 case PSR_VERSION_FR401_MB93403:
 415                         cpu_silicon     = "mb93403";
 416 #ifndef CONFIG_MB93093_PDK
 417                         cpu_system      = __frv_mb93091_cb30;
 418 #else
 419                         cpu_system      = __frv_mb93093;
 420 #endif
 421                         clock_cmodes    = clock_cmodes_fr401_fr403;
 422                         break;
 423                 default:
 424                         break;
 425                 }
 426                 break;
 427
 428         case PSR_IMPLE_FR405:
 429                 cpu_series      = "fr400";
 430                 cpu_core        = "fr405";
 431                 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
 432
 433                 switch (PSR_VERSION(psr)) {
 434                 case PSR_VERSION_FR405_MB93405:
 435                         cpu_silicon     = "mb93405";
 436                         cpu_system      = __frv_mb93091_cb60;
 437                         clock_cmodes    = clock_cmodes_fr405;
 438 #ifdef CONFIG_PM
 439                         clock_bits_settable |= CLOCK_BIT_CMODE;
 440                         clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
 441 #endif
 442
 443                         /* the FPGA on the CB70 has extra registers
 444                          * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
 445                          *   how we tell the difference between it and a CB60
 446                          */
 447                         if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
 448                                 cpu_system = __frv_mb93091_cb70;
 449                         break;
 450                 default:
 451                         break;
 452                 }
 453                 break;
 454
 455         case PSR_IMPLE_FR451:
 456                 cpu_series      = "fr450";
 457                 cpu_core        = "fr451";
 458                 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
 459 #ifdef CONFIG_PM
 460                 clock_bits_settable |= CLOCK_BIT_CMODE;
 461                 clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
 462 #endif
 463                 switch (PSR_VERSION(psr)) {
 464                 case PSR_VERSION_FR451_MB93451:
 465                         cpu_silicon     = "mb93451";
 466                         cpu_mmu         = "Prot, SAT, xSAT, DAT";
 467                         cpu_system      = __frv_mb93091_cb451;
 468                         clock_cmodes    = clock_cmodes_fr405;
 469                         break;
 470                 default:
 471                         break;
 472                 }
 473                 break;
 474
 475         case PSR_IMPLE_FR501:
 476                 cpu_series      = "fr500";
 477                 cpu_core        = "fr501";
 478                 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
 479
 480                 switch (PSR_VERSION(psr)) {
 481                 case PSR_VERSION_FR501_MB93501:  cpu_silicon = "mb93501";   break;
 482                 case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
 483                 default:
 484                         break;
 485                 }
 486                 break;
 487
 488         case PSR_IMPLE_FR551:
 489                 cpu_series      = "fr550";
 490                 cpu_core        = "fr551";
 491                 pdm_suspend_mode = HSR0_PDM_PLL_RUN;
 492
 493                 switch (PSR_VERSION(psr)) {
 494                 case PSR_VERSION_FR551_MB93555:
 495                         cpu_silicon     = "mb93555";
 496                         cpu_mmu         = "Prot, SAT";
 497                         cpu_system      = __frv_mb93091_cb41;
 498                         clock_cmodes    = clock_cmodes_fr555;
 499                         clock_doubled   = 1;
 500                         break;
 501                 default:
 502                         break;
 503                 }
 504                 break;
 505
 506         default:
 507                 break;
 508         }
 509
 510         printk("- Series:%s CPU:%s Silicon:%s\n",
 511                cpu_series, cpu_core, cpu_silicon);
 512
 513 #ifdef CONFIG_MB93091_VDK
 514         detect_mb93091();
 515 #endif
 516
 517 #if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
 518         cpu_board2 = __frv_mb93493;
 519 #endif
 520
 521 } /* end determine_cpu() */
 522
 523 /*****************************************************************************/
 524 /*
 525  * calculate the bus clock speed
 526  */
 527 void __pminit determine_clocks(int verbose)
 528 {
 529         const struct clock_cmode *mode, *tmode;
 530         unsigned long clkc, psr, quot;
 531
 532         clkc = __get_CLKC();
 533         psr = __get_PSR();
 534
 535         clock_p0_current = !!(clkc & CLKC_P0);
 536         clock_cm_current = clkc & CLKC_CM;
 537         clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;
 538
 539         if (verbose)
 540                 printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);
 541
 542         /* the CB70 has some alternative ways of setting the clock speed through switches accessed
 543          * through the FPGA.  */
 544         if (cpu_system == __frv_mb93091_cb70) {
 545                 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
 546
 547                 if (clkswr & 0x1000)
 548                         __clkin_clock_speed_HZ = 60000000UL;
 549                 else
 550                         __clkin_clock_speed_HZ =
 551                                 ((clkswr >> 8) & 0xf) * 10000000 +
 552                                 ((clkswr >> 4) & 0xf) * 1000000 +
 553                                 ((clkswr     ) & 0xf) * 100000;
 554         }
 555         /* the FR451 is currently fixed at 24MHz */
 556         else if (cpu_system == __frv_mb93091_cb451) {
 557                 //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
 558                 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
 559
 560                 if (clkswr & 0x1000)
 561                         __clkin_clock_speed_HZ = 60000000UL;
 562                 else
 563                         __clkin_clock_speed_HZ =
 564                                 ((clkswr >> 8) & 0xf) * 10000000 +
 565                                 ((clkswr >> 4) & 0xf) * 1000000 +
 566                                 ((clkswr     ) & 0xf) * 100000;
 567         }
 568         /* otherwise determine the clockspeed from VDK or other registers */
 569         else {
 570                 __clkin_clock_speed_HZ = __get_CLKIN();
 571         }
 572
 573         /* look up the appropriate clock relationships table entry */
 574         mode = &undef_clock_cmode;
 575         if (clock_cmodes) {
 576                 tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
 577                 if (tmode->xbus)
 578                         mode = tmode;
 579         }
 580
 581 #define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
 582
 583         if (clock_doubled)
 584                 __clkin_clock_speed_HZ <<= 1;
 585
 586         __ext_bus_clock_speed_HZ        = CLOCK(__clkin_clock_speed_HZ, mode->xbus);
 587         __sdram_clock_speed_HZ          = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
 588         __dsu_clock_speed_HZ            = CLOCK(__clkin_clock_speed_HZ, mode->dsu);
 589
 590         switch (clkc & CLKC_CM) {
 591         case 0: /* High */
 592                 __core_bus_clock_speed_HZ       = CLOCK(__clkin_clock_speed_HZ, mode->corebus);
 593                 __core_clock_speed_HZ           = CLOCK(__clkin_clock_speed_HZ, mode->core);
 594                 break;
 595         case 1: /* Medium */
 596                 __core_bus_clock_speed_HZ       = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
 597                 __core_clock_speed_HZ           = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
 598                 break;
 599         case 2: /* Low; not supported */
 600         case 3: /* UNDEF */
 601                 printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
 602                 panic("Bye");
 603         }
 604
 605         __res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
 606         if (clkc & CLKC_P0)
 607                 __res_bus_clock_speed_HZ >>= 1;
 608
 609         if (verbose) {
 610                 printk("CLKIN: %lu.%3.3luMHz\n",
 611                        __clkin_clock_speed_HZ / 1000000,
 612                        (__clkin_clock_speed_HZ / 1000) % 1000);
 613
 614                 printk("CLKS:"
 615                        " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
 616                        __ext_bus_clock_speed_HZ / 1000000,
 617                        __res_bus_clock_speed_HZ / 1000000,
 618                        __sdram_clock_speed_HZ / 1000000,
 619                        __core_bus_clock_speed_HZ / 1000000,
 620                        __core_clock_speed_HZ / 1000000,
 621                        __dsu_clock_speed_HZ / 1000000
 622                        );
 623         }
 624
 625         /* calculate the number of __delay() loop iterations per sec (2 insn loop) */
 626         __delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);
 627
 628         /* set the serial prescaler */
 629         __serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
 630         quot = 1;
 631         while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
 632                 quot += 1;
 633
 634         /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
 635          * - we have to be careful - dividing too much can mean we can't get 115200 baud
 636          */
 637         if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
 638                 quot <<= 1;
 639
 640         __serial_clock_speed_HZ /= quot;
 641         __frv_uart0.uartclk = __serial_clock_speed_HZ;
 642         __frv_uart1.uartclk = __serial_clock_speed_HZ;
 643
 644         if (verbose)
 645                 printk("      uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);
 646
 647         while (!(__get_UART0_LSR() & UART_LSR_TEMT))
 648                 continue;
 649
 650         while (!(__get_UART1_LSR() & UART_LSR_TEMT))
 651                 continue;
 652
 653         __set_UCPVR(quot);
 654         __set_UCPSR(0);
 655 } /* end determine_clocks() */
 656
 657 /*****************************************************************************/
 658 /*
 659  * reserve some DMA consistent memory
 660  */
 661 #ifdef CONFIG_RESERVE_DMA_COHERENT
 662 static void __init reserve_dma_coherent(void)
 663 {
 664         unsigned long ampr;
 665
 666         /* find the first non-kernel memory tile and steal it */
 667 #define __steal_AMPR(r)                                         \
 668         if (__get_DAMPR(r) & xAMPRx_V) {                        \
 669                 ampr = __get_DAMPR(r);                          \
 670                 __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C);     \
 671                 __set_IAMPR(r, 0);                              \
 672                 goto found;                                     \
 673         }
 674
 675         __steal_AMPR(1);
 676         __steal_AMPR(2);
 677         __steal_AMPR(3);
 678         __steal_AMPR(4);
 679         __steal_AMPR(5);
 680         __steal_AMPR(6);
 681
 682         if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
 683                 __steal_AMPR(7);
 684                 __steal_AMPR(8);
 685                 __steal_AMPR(9);
 686                 __steal_AMPR(10);
 687                 __steal_AMPR(11);
 688                 __steal_AMPR(12);
 689                 __steal_AMPR(13);
 690                 __steal_AMPR(14);
 691         }
 692
 693         /* unable to grant any DMA consistent memory */
 694         printk("No DMA consistent memory reserved\n");
 695         return;
 696
 697  found:
 698         dma_coherent_mem_start = ampr & xAMPRx_PPFN;
 699         ampr &= xAMPRx_SS;
 700         ampr >>= 4;
 701         ampr = 1 << (ampr - 3 + 20);
 702         dma_coherent_mem_end = dma_coherent_mem_start + ampr;
 703
 704         printk("DMA consistent memory reserved %lx-%lx\n",
 705                dma_coherent_mem_start, dma_coherent_mem_end);
 706
 707 } /* end reserve_dma_coherent() */
 708 #endif
 709
 710 /*****************************************************************************/
 711 /*
 712  * calibrate the delay loop
 713  */
 714 void __init calibrate_delay(void)
 715 {
 716         loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);
 717
 718         printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
 719                loops_per_jiffy / (500000 / HZ),
 720                (loops_per_jiffy / (5000 / HZ)) % 100);
 721
 722 } /* end calibrate_delay() */
 723
 724 /*****************************************************************************/
 725 /*
 726  * look through the command line for some things we need to know immediately
 727  */
 728 static void __init parse_cmdline_early(char *cmdline)
 729 {
 730         if (!cmdline)
 731                 return;
 732
 733         while (*cmdline) {
 734                 if (*cmdline == ' ')
 735                         cmdline++;
 736
 737                 /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
 738                  * out from the SDRAM controller mask register
 739                  */
 740                 if (!memcmp(cmdline, "mem=", 4)) {
 741                         unsigned long long mem_size;
 742
 743                         mem_size = memparse(cmdline + 4, &cmdline);
 744                         memory_end = memory_start + mem_size;
 745                 }
 746
 747                 while (*cmdline && *cmdline != ' ')
 748                         cmdline++;
 749         }
 750
 751 } /* end parse_cmdline_early() */
 752
 753 /*****************************************************************************/
 754 /*
 755  *
 756  */
 757 void __init setup_arch(char **cmdline_p)
 758 {
 759 #ifdef CONFIG_MMU
 760         printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
 761 #else
 762         printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
 763 #endif
 764
 765         memcpy(saved_command_line, redboot_command_line, COMMAND_LINE_SIZE);
 766
 767         determine_cpu();
 768         determine_clocks(1);
 769
 770         /* For printk-directly-beats-on-serial-hardware hack */
 771         console_set_baud(115200);
 772 #ifdef CONFIG_GDBSTUB
 773         gdbstub_set_baud(115200);
 774 #endif
 775
 776 #ifdef CONFIG_RESERVE_DMA_COHERENT
 777         reserve_dma_coherent();
 778 #endif
 779         dump_memory_map();
 780
 781 #ifdef CONFIG_MB93090_MB00
 782         if (mb93090_mb00_detected)
 783                 mb93090_display();
 784 #endif
 785
 786         /* register those serial ports that are available */
 787 #ifdef CONFIG_FRV_ONCPU_SERIAL
 788 #ifndef CONFIG_GDBSTUB_UART0
 789         __reg(UART0_BASE + UART_IER * 8) = 0;
 790         early_serial_setup(&__frv_uart0);
 791 #endif
 792 #ifndef CONFIG_GDBSTUB_UART1
 793         __reg(UART1_BASE + UART_IER * 8) = 0;
 794         early_serial_setup(&__frv_uart1);
 795 #endif
 796 #endif
 797
 798 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
 799         /* we need to initialize the Flashrom device here since we might
 800          * do things with flash early on in the boot
 801          */
 802         flash_probe();
 803 #endif
 804
 805         /* deal with the command line - RedBoot may have passed one to the kernel */
 806         memcpy(command_line, saved_command_line, sizeof(command_line));
 807         *cmdline_p = &command_line[0];
 808         parse_cmdline_early(command_line);
 809
 810         /* set up the memory description
 811          * - by now the stack is part of the init task */
 812         printk("Memory %08lx-%08lx\n", memory_start, memory_end);
 813
 814         BUG_ON(memory_start == memory_end);
 815
 816         init_mm.start_code = (unsigned long) &_stext;
 817         init_mm.end_code = (unsigned long) &_etext;
 818         init_mm.end_data = (unsigned long) &_edata;
 819 #if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
 820         init_mm.brk = (unsigned long) &_end;
 821 #else
 822         init_mm.brk = (unsigned long) 0;
 823 #endif
 824
 825 #ifdef DEBUG
 826         printk("KERNEL -> TEXT=0x%06x-0x%06x DATA=0x%06x-0x%06x BSS=0x%06x-0x%06x\n",
 827                (int) &_stext, (int) &_etext,
 828                (int) &_sdata, (int) &_edata,
 829                (int) &_sbss, (int) &_ebss);
 830 #endif
 831
 832 #ifdef CONFIG_VT
 833 #if defined(CONFIG_VGA_CONSOLE)
 834         conswitchp = &vga_con;
 835 #elif defined(CONFIG_DUMMY_CONSOLE)
 836         conswitchp = &dummy_con;
 837 #endif
 838 #endif
 839
 840 #ifdef CONFIG_BLK_DEV_BLKMEM
 841         ROOT_DEV = MKDEV(BLKMEM_MAJOR,0);
 842 #endif
 843         /*rom_length = (unsigned long)&_flashend - (unsigned long)&_romvec;*/
 844
 845 #ifdef CONFIG_MMU
 846         setup_linux_memory();
 847 #else
 848         setup_uclinux_memory();
 849 #endif
 850
 851         /* get kmalloc into gear */
 852         paging_init();
 853
 854         /* init DMA */
 855         frv_dma_init();
 856 #ifdef DEBUG
 857         printk("Done setup_arch\n");
 858 #endif
 859
 860         /* start the decrement timer running */
 861 //      asm volatile("movgs %0,timerd" :: "r"(10000000));
 862 //      __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
 863
 864 } /* end setup_arch() */
 865
 866 #if 0
 867 /*****************************************************************************/
 868 /*
 869  *
 870  */
 871 static int __devinit setup_arch_serial(void)
 872 {
 873         /* register those serial ports that are available */
 874 #ifndef CONFIG_GDBSTUB_UART0
 875         early_serial_setup(&__frv_uart0);
 876 #endif
 877 #ifndef CONFIG_GDBSTUB_UART1
 878         early_serial_setup(&__frv_uart1);
 879 #endif
 880
 881         return 0;
 882 } /* end setup_arch_serial() */
 883
 884 late_initcall(setup_arch_serial);
 885 #endif
 886
 887 /*****************************************************************************/
 888 /*
 889  * set up the memory map for normal MMU linux
 890  */
 891 #ifdef CONFIG_MMU
 892 static void __init setup_linux_memory(void)
 893 {
 894         unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
 895
 896         kstart  = (unsigned long) &__kernel_image_start - PAGE_OFFSET;
 897         kend    = (unsigned long) &__kernel_image_end - PAGE_OFFSET;
 898
 899         kstart = kstart & PAGE_MASK;
 900         kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
 901
 902         /* give all the memory to the bootmap allocator,  tell it to put the
 903          * boot mem_map immediately following the kernel image
 904          */
 905         bootmap_size = init_bootmem_node(NODE_DATA(0),
 906                                          kend >> PAGE_SHIFT,            /* map addr */
 907                                          memory_start >> PAGE_SHIFT,    /* start of RAM */
 908                                          memory_end >> PAGE_SHIFT       /* end of RAM */
 909                                          );
 910
 911         /* pass the memory that the kernel can immediately use over to the bootmem allocator */
 912         max_mapnr = num_physpages = (memory_end - memory_start) >> PAGE_SHIFT;
 913         low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
 914         high_mem = 0;
 915
 916         if (num_physpages > low_top_pfn) {
 917 #ifdef CONFIG_HIGHMEM
 918                 high_mem = num_physpages - low_top_pfn;
 919 #else
 920                 max_mapnr = num_physpages = low_top_pfn;
 921 #endif
 922         }
 923         else {
 924                 low_top_pfn = num_physpages;
 925         }
 926
 927         min_low_pfn = memory_start >> PAGE_SHIFT;
 928         max_low_pfn = low_top_pfn;
 929         max_pfn = memory_end >> PAGE_SHIFT;
 930
 931         num_mappedpages = low_top_pfn;
 932
 933         printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT));
 934
 935         free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT);
 936
 937 #ifdef CONFIG_HIGHMEM
 938         if (high_mem)
 939                 printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT));
 940 #endif
 941
 942         /* take back the memory occupied by the kernel image and the bootmem alloc map */
 943         reserve_bootmem(kstart, kend - kstart + bootmap_size);
 944
 945         /* reserve the memory occupied by the initial ramdisk */
 946 #ifdef CONFIG_BLK_DEV_INITRD
 947         if (LOADER_TYPE && INITRD_START) {
 948                 if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) {
 949                         reserve_bootmem(INITRD_START, INITRD_SIZE);
 950                         initrd_start = INITRD_START + PAGE_OFFSET;
 951                         initrd_end = initrd_start + INITRD_SIZE;
 952                 }
 953                 else {
 954                         printk(KERN_ERR
 955                                "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
 956                                "disabling initrd\n",
 957                                INITRD_START + INITRD_SIZE,
 958                                low_top_pfn << PAGE_SHIFT);
 959                         initrd_start = 0;
 960                 }
 961         }
 962 #endif
 963
 964 } /* end setup_linux_memory() */
 965 #endif
 966
 967 /*****************************************************************************/
 968 /*
 969  * set up the memory map for uClinux
 970  */
 971 #ifndef CONFIG_MMU
 972 static void __init setup_uclinux_memory(void)
 973 {
 974 #ifdef CONFIG_PROTECT_KERNEL
 975         unsigned long dampr;
 976 #endif
 977         unsigned long kend;
 978         int bootmap_size;
 979
 980         kend = (unsigned long) &__kernel_image_end;
 981         kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
 982
 983         /* give all the memory to the bootmap allocator,  tell it to put the
 984          * boot mem_map immediately following the kernel image
 985          */
 986         bootmap_size = init_bootmem_node(NODE_DATA(0),
 987                                          kend >> PAGE_SHIFT,            /* map addr */
 988                                          memory_start >> PAGE_SHIFT,    /* start of RAM */
 989                                          memory_end >> PAGE_SHIFT       /* end of RAM */
 990                                          );
 991
 992         /* free all the usable memory */
 993         free_bootmem(memory_start, memory_end - memory_start);
 994
 995         high_memory = (void *) (memory_end & PAGE_MASK);
 996         max_mapnr = num_physpages = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
 997
 998         min_low_pfn = memory_start >> PAGE_SHIFT;
 999         max_low_pfn = memory_end >> PAGE_SHIFT;
1000         max_pfn = max_low_pfn;
1001
1002         /* now take back the bits the core kernel is occupying */
1003 #ifndef CONFIG_PROTECT_KERNEL
1004         reserve_bootmem(kend, bootmap_size);
1005         reserve_bootmem((unsigned long) &__kernel_image_start,
1006                         kend - (unsigned long) &__kernel_image_start);
1007
1008 #else
1009         dampr = __get_DAMPR(0);
1010         dampr &= xAMPRx_SS;
1011         dampr = (dampr >> 4) + 17;
1012         dampr = 1 << dampr;
1013
1014         reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr);
1015 #endif
1016
1017         /* reserve some memory to do uncached DMA through if requested */
1018 #ifdef CONFIG_RESERVE_DMA_COHERENT
1019         if (dma_coherent_mem_start)
1020                 reserve_bootmem(dma_coherent_mem_start,
1021                                 dma_coherent_mem_end - dma_coherent_mem_start);
1022 #endif
1023
1024 } /* end setup_uclinux_memory() */
1025 #endif
1026
1027 /*****************************************************************************/
1028 /*
1029  * get CPU information for use by procfs
1030  */
1031 static int show_cpuinfo(struct seq_file *m, void *v)
1032 {
1033         const char *gr, *fr, *fm, *fp, *cm, *nem, *ble;
1034 #ifdef CONFIG_PM
1035         const char *sep;
1036 #endif
1037
1038         gr  = cpu_hsr0_all & HSR0_GRHE  ? "gr0-63"      : "gr0-31";
1039         fr  = cpu_hsr0_all & HSR0_FRHE  ? "fr0-63"      : "fr0-31";
1040         fm  = cpu_psr_all  & PSR_EM     ? ", Media"     : "";
1041         fp  = cpu_psr_all  & PSR_EF     ? ", FPU"       : "";
1042         cm  = cpu_psr_all  & PSR_CM     ? ", CCCR"      : "";
1043         nem = cpu_psr_all  & PSR_NEM    ? ", NE"        : "";
1044         ble = cpu_psr_all  & PSR_BE     ? "BE"          : "LE";
1045
1046         seq_printf(m,
1047                    "CPU-Series:\t%s\n"
1048                    "CPU-Core:\t%s, %s, %s%s%s\n"
1049                    "CPU:\t\t%s\n"
1050                    "MMU:\t\t%s\n"
1051                    "FP-Media:\t%s%s%s\n"
1052                    "System:\t\t%s",
1053                    cpu_series,
1054                    cpu_core, gr, ble, cm, nem,
1055                    cpu_silicon,
1056                    cpu_mmu,
1057                    fr, fm, fp,
1058                    cpu_system);
1059
1060         if (cpu_board1)
1061                 seq_printf(m, ", %s", cpu_board1);
1062
1063         if (cpu_board2)
1064                 seq_printf(m, ", %s", cpu_board2);
1065
1066         seq_printf(m, "\n");
1067
1068 #ifdef CONFIG_PM
1069         seq_printf(m, "PM-Controls:");
1070         sep = "\t";
1071
1072         if (clock_bits_settable & CLOCK_BIT_CMODE) {
1073                 seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted);
1074                 sep = ", ";
1075         }
1076
1077         if (clock_bits_settable & CLOCK_BIT_CM) {
1078                 seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM);
1079                 sep = ", ";
1080         }
1081
1082         if (clock_bits_settable & CLOCK_BIT_P0) {
1083                 seq_printf(m, "%sp0=0x3", sep);
1084                 sep = ", ";
1085         }
1086
1087         seq_printf(m, "%ssuspend=0x22\n", sep);
1088 #endif
1089
1090         seq_printf(m,
1091                    "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
1092                    clock_cmode_current, clock_cm_current, clock_p0_current);
1093
1094 #define print_clk(TAG, VAR) \
1095         seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
1096
1097         print_clk("In",    __clkin_clock_speed_HZ);
1098         print_clk("Core",  __core_clock_speed_HZ);
1099         print_clk("SDRAM", __sdram_clock_speed_HZ);
1100         print_clk("CBus",  __core_bus_clock_speed_HZ);
1101         print_clk("Res",   __res_bus_clock_speed_HZ);
1102         print_clk("Ext",   __ext_bus_clock_speed_HZ);
1103         print_clk("DSU",   __dsu_clock_speed_HZ);
1104
1105         seq_printf(m,
1106                    "BogoMips:\t%lu.%02lu\n",
1107                    (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100);
1108
1109         return 0;
1110 } /* end show_cpuinfo() */
1111
1112 static void *c_start(struct seq_file *m, loff_t *pos)
1113 {
1114         return *pos < NR_CPUS ? (void *) 0x12345678 : NULL;
1115 }
1116
1117 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1118 {
1119         ++*pos;
1120         return c_start(m, pos);
1121 }
1122
1123 static void c_stop(struct seq_file *m, void *v)
1124 {
1125 }
1126
1127 struct seq_operations cpuinfo_op = {
1128         .start  = c_start,
1129         .next   = c_next,
1130         .stop   = c_stop,
1131         .show   = show_cpuinfo,
1132 };
1133
1134 void arch_gettod(int *year, int *mon, int *day, int *hour,
1135                  int *min, int *sec)
1136 {
1137         *year = *mon = *day = *hour = *min = *sec = 0;
1138 }
1139
1140 /*****************************************************************************/
1141 /*
1142  *
1143  */
1144 #ifdef CONFIG_MB93090_MB00
1145 static void __init mb93090_sendlcdcmd(uint32_t cmd)
1146 {
1147         unsigned long base = __addr_LCD();
1148         int loop;
1149
1150         /* request reading of the busy flag */
1151         __set_LCD(base, LCD_CMD_READ_BUSY);
1152         __set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E);
1153
1154         /* wait for the busy flag to become clear */
1155         for (loop = 10000; loop > 0; loop--)
1156                 if (!(__get_LCD(base) & 0x80))
1157                         break;
1158
1159         /* send the command */
1160         __set_LCD(base, cmd);
1161         __set_LCD(base, cmd & ~LCD_E);
1162
1163 } /* end mb93090_sendlcdcmd() */
1164
1165 /*****************************************************************************/
1166 /*
1167  * write to the MB93090 LEDs and LCD
1168  */
1169 static void __init mb93090_display(void)
1170 {
1171         const char *p;
1172
1173         __set_LEDS(0);
1174
1175         /* set up the LCD */
1176         mb93090_sendlcdcmd(LCD_CMD_CLEAR);
1177         mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
1178         mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
1179         mb93090_sendlcdcmd(LCD_CMD_HOME);
1180
1181         mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
1182         for (p = mb93090_banner; *p; p++)
1183                 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1184
1185         mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
1186         for (p = mb93090_version; *p; p++)
1187                 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1188
1189 } /* end mb93090_display() */
1190
1191 #endif // CONFIG_MB93090_MB00