2 * Pentium 4/Xeon CPU on demand clock modulation/speed scaling
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
4 * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
5 * (C) 2002 Arjan van de Ven <arjanv@redhat.com>
6 * (C) 2002 Tora T. Engstad
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 * The author(s) of this software shall not be held liable for damages
15 * of any nature resulting due to the use of this software. This
16 * software is provided AS-IS with no warranties.
18 * Date Errata Description
19 * 20020525 N44, O17 12.5% or 25% DC causes lockup
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/smp.h>
27 #include <linux/cpufreq.h>
28 #include <linux/slab.h>
29 #include <linux/cpumask.h>
30 #include <linux/sched.h> /* current / set_cpus_allowed() */
32 #include <asm/processor.h>
34 #include <asm/timex.h>
36 #include "speedstep-lib.h"
38 #define PFX "p4-clockmod: "
39 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "p4-clockmod", msg)
42 * Duty Cycle (3bits), note DC_DISABLE is not specified in
43 * intel docs i just use it to mean disable
46 DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
47 DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
53 static int has_N44_O17_errata[NR_CPUS];
54 static int has_N60_errata[NR_CPUS];
55 static unsigned int stock_freq;
56 static struct cpufreq_driver p4clockmod_driver;
57 static unsigned int cpufreq_p4_get(unsigned int cpu);
59 static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
63 if (!cpu_online(cpu) || (newstate > DC_DISABLE) || (newstate == DC_RESV))
66 rdmsr(MSR_IA32_THERM_STATUS, l, h);
69 dprintk("CPU#%d currently thermal throttled\n", cpu);
71 if (has_N44_O17_errata[cpu] && (newstate == DC_25PT || newstate == DC_DFLT))
74 rdmsr(MSR_IA32_THERM_CONTROL, l, h);
75 if (newstate == DC_DISABLE) {
76 dprintk("CPU#%d disabling modulation\n", cpu);
77 wrmsr(MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
79 dprintk("CPU#%d setting duty cycle to %d%%\n",
80 cpu, ((125 * newstate) / 10));
81 /* bits 63 - 5 : reserved
82 * bit 4 : enable/disable
83 * bits 3-1 : duty cycle
87 l = l | (1<<4) | ((newstate & 0x7)<<1);
88 wrmsr(MSR_IA32_THERM_CONTROL, l, h);
95 static struct cpufreq_frequency_table p4clockmod_table[] = {
96 {DC_RESV, CPUFREQ_ENTRY_INVALID},
105 {DC_RESV, CPUFREQ_TABLE_END},
109 static int cpufreq_p4_target(struct cpufreq_policy *policy,
110 unsigned int target_freq,
111 unsigned int relation)
113 unsigned int newstate = DC_RESV;
114 struct cpufreq_freqs freqs;
115 cpumask_t cpus_allowed;
118 if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], target_freq, relation, &newstate))
121 freqs.old = cpufreq_p4_get(policy->cpu);
122 freqs.new = stock_freq * p4clockmod_table[newstate].index / 8;
124 if (freqs.new == freqs.old)
128 for_each_cpu_mask(i, policy->cpus) {
130 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
133 /* run on each logical CPU, see section 13.15.3 of IA32 Intel Architecture Software
134 * Developer's Manual, Volume 3
136 cpus_allowed = current->cpus_allowed;
138 for_each_cpu_mask(i, policy->cpus) {
139 cpumask_t this_cpu = cpumask_of_cpu(i);
141 set_cpus_allowed(current, this_cpu);
142 BUG_ON(smp_processor_id() != i);
144 cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);
146 set_cpus_allowed(current, cpus_allowed);
149 for_each_cpu_mask(i, policy->cpus) {
151 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
158 static int cpufreq_p4_verify(struct cpufreq_policy *policy)
160 return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]);
164 static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
166 if (c->x86 == 0x06) {
167 if (cpu_has(c, X86_FEATURE_EST))
168 printk(KERN_WARNING PFX "Warning: EST-capable CPU detected. "
169 "The acpi-cpufreq module offers voltage scaling"
170 " in addition of frequency scaling. You should use "
171 "that instead of p4-clockmod, if possible.\n");
172 switch (c->x86_model) {
173 case 0x0E: /* Core */
174 case 0x0F: /* Core Duo */
175 p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
176 return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PCORE);
177 case 0x0D: /* Pentium M (Dothan) */
178 p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
180 case 0x09: /* Pentium M (Banias) */
181 return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PM);
186 printk(KERN_WARNING PFX "Unknown p4-clockmod-capable CPU. Please send an e-mail to <cpufreq@lists.linux.org.uk>\n");
190 /* on P-4s, the TSC runs with constant frequency independent whether
191 * throttling is active or not. */
192 p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
194 if (speedstep_detect_processor() == SPEEDSTEP_PROCESSOR_P4M) {
195 printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. "
196 "The speedstep-ich or acpi cpufreq modules offer "
197 "voltage scaling in addition of frequency scaling. "
198 "You should use either one instead of p4-clockmod, "
200 return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4M);
203 return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4D);
208 static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
210 struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
215 policy->cpus = cpu_sibling_map[policy->cpu];
218 /* Errata workaround */
219 cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
225 has_N44_O17_errata[policy->cpu] = 1;
226 dprintk("has errata -- disabling low frequencies\n");
230 has_N60_errata[policy->cpu] = 1;
231 dprintk("has errata -- disabling frequencies lower than 2ghz\n");
235 /* get max frequency */
236 stock_freq = cpufreq_p4_get_frequency(c);
241 for (i=1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
242 if ((i<2) && (has_N44_O17_errata[policy->cpu]))
243 p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
244 else if (has_N60_errata[policy->cpu] && ((stock_freq * i)/8) < 2000000)
245 p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
247 p4clockmod_table[i].frequency = (stock_freq * i)/8;
249 cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);
251 /* cpuinfo and default policy values */
252 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
253 policy->cpuinfo.transition_latency = 1000000; /* assumed */
254 policy->cur = stock_freq;
256 return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
260 static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
262 cpufreq_frequency_table_put_attr(policy->cpu);
266 static unsigned int cpufreq_p4_get(unsigned int cpu)
268 cpumask_t cpus_allowed;
271 cpus_allowed = current->cpus_allowed;
273 set_cpus_allowed(current, cpumask_of_cpu(cpu));
274 BUG_ON(smp_processor_id() != cpu);
276 rdmsr(MSR_IA32_THERM_CONTROL, l, h);
278 set_cpus_allowed(current, cpus_allowed);
287 return (stock_freq * l / 8);
292 static struct freq_attr* p4clockmod_attr[] = {
293 &cpufreq_freq_attr_scaling_available_freqs,
297 static struct cpufreq_driver p4clockmod_driver = {
298 .verify = cpufreq_p4_verify,
299 .target = cpufreq_p4_target,
300 .init = cpufreq_p4_cpu_init,
301 .exit = cpufreq_p4_cpu_exit,
302 .get = cpufreq_p4_get,
303 .name = "p4-clockmod",
304 .owner = THIS_MODULE,
305 .attr = p4clockmod_attr,
309 static int __init cpufreq_p4_init(void)
311 struct cpuinfo_x86 *c = cpu_data;
315 * THERM_CONTROL is architectural for IA32 now, so
316 * we can rely on the capability checks
318 if (c->x86_vendor != X86_VENDOR_INTEL)
321 if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) ||
322 !test_bit(X86_FEATURE_ACC, c->x86_capability))
325 ret = cpufreq_register_driver(&p4clockmod_driver);
327 printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");
333 static void __exit cpufreq_p4_exit(void)
335 cpufreq_unregister_driver(&p4clockmod_driver);
339 MODULE_AUTHOR ("Zwane Mwaikambo <zwane@commfireservices.com>");
340 MODULE_DESCRIPTION ("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
341 MODULE_LICENSE ("GPL");
343 late_initcall(cpufreq_p4_init);
344 module_exit(cpufreq_p4_exit);