2 * Memory copy functions for 32-bit PowerPC.
4 * Copyright (C) 1996-2005 Paul Mackerras.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/config.h>
12 #include <asm/processor.h>
13 #include <asm/cache.h>
14 #include <asm/errno.h>
15 #include <asm/ppc_asm.h>
17 #define COPY_16_BYTES \
27 #define COPY_16_BYTES_WITHEX(n) \
45 #define COPY_16_BYTES_EXCODE(n) \
47 addi r5,r5,-(16 * n); \
50 addi r5,r5,-(16 * n); \
52 .section __ex_table,"a"; \
54 .long 8 ## n ## 0b,9 ## n ## 0b; \
55 .long 8 ## n ## 1b,9 ## n ## 0b; \
56 .long 8 ## n ## 2b,9 ## n ## 0b; \
57 .long 8 ## n ## 3b,9 ## n ## 0b; \
58 .long 8 ## n ## 4b,9 ## n ## 1b; \
59 .long 8 ## n ## 5b,9 ## n ## 1b; \
60 .long 8 ## n ## 6b,9 ## n ## 1b; \
61 .long 8 ## n ## 7b,9 ## n ## 1b; \
65 .stabs "arch/powerpc/lib/",N_SO,0,0,0f
66 .stabs "copy32.S",N_SO,0,0,0f
69 CACHELINE_BYTES = L1_CACHE_BYTES
70 LG_CACHELINE_BYTES = L1_CACHE_SHIFT
71 CACHELINE_MASK = (L1_CACHE_BYTES-1)
74 * Use dcbz on the complete cache lines in the destination
75 * to set them to zero. This requires that the destination
76 * area is cacheable. -- paulus
78 _GLOBAL(cacheable_memzero)
89 clrlwi r7,r6,32-LG_CACHELINE_BYTES
91 srwi r9,r8,LG_CACHELINE_BYTES
92 addic. r9,r9,-1 /* total number of complete cachelines */
94 xori r0,r7,CACHELINE_MASK & ~3
102 #if !defined(CONFIG_8xx)
109 #if CACHE_LINE_SIZE >= 32
114 #endif /* CACHE_LINE_SIZE */
116 addi r6,r6,CACHELINE_BYTES
118 clrlwi r5,r8,32-LG_CACHELINE_BYTES
160 * This version uses dcbz on the complete cache lines in the
161 * destination area to reduce memory traffic. This requires that
162 * the destination area is cacheable.
163 * We only use this version if the source and dest don't overlap.
166 _GLOBAL(cacheable_memcpy)
167 add r7,r3,r5 /* test if the src & dst overlap */
171 crand 0,0,4 /* cr0.lt &= cr1.lt */
172 blt memcpy /* if regions overlap */
177 andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
180 cmplw 0,r5,r0 /* is this more than total to do? */
181 blt 63f /* if not much to do */
182 andi. r8,r0,3 /* get it word-aligned first */
186 70: lbz r9,4(r4) /* do some bytes */
194 72: lwzu r9,4(r4) /* do some words */
198 58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
199 clrlwi r5,r5,32-LG_CACHELINE_BYTES
204 #if !defined(CONFIG_8xx)
208 #if L1_CACHE_BYTES >= 32
210 #if L1_CACHE_BYTES >= 64
213 #if L1_CACHE_BYTES >= 128
249 beq 2f /* if less than 8 bytes to do */
250 andi. r0,r6,3 /* get dest word aligned */
281 rlwinm. r7,r5,32-3,3,31
286 _GLOBAL(backwards_memcpy)
287 rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */
317 rlwinm. r7,r5,32-3,3,31
322 _GLOBAL(__copy_tofrom_user)
326 andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
329 cmplw 0,r5,r0 /* is this more than total to do? */
330 blt 63f /* if not much to do */
331 andi. r8,r0,3 /* get it word-aligned first */
334 70: lbz r9,4(r4) /* do some bytes */
343 72: lwzu r9,4(r4) /* do some words */
347 .section __ex_table,"a"
355 58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
356 clrlwi r5,r5,32-LG_CACHELINE_BYTES
361 /* Don't use prefetch on 8xx */
364 53: COPY_16_BYTES_WITHEX(0)
367 #else /* not CONFIG_8xx */
368 /* Here we decide how far ahead to prefetch the source */
374 #if MAX_COPY_PREFETCH > 1
375 /* Heuristically, for large transfers we prefetch
376 MAX_COPY_PREFETCH cachelines ahead. For small transfers
377 we prefetch 1 cacheline ahead. */
378 cmpwi r0,MAX_COPY_PREFETCH
380 li r7,MAX_COPY_PREFETCH
383 addi r3,r3,CACHELINE_BYTES
387 addi r3,r3,CACHELINE_BYTES
388 #endif /* MAX_COPY_PREFETCH > 1 */
396 .section __ex_table,"a"
400 /* the main body of the cacheline loop */
401 COPY_16_BYTES_WITHEX(0)
402 #if L1_CACHE_BYTES >= 32
403 COPY_16_BYTES_WITHEX(1)
404 #if L1_CACHE_BYTES >= 64
405 COPY_16_BYTES_WITHEX(2)
406 COPY_16_BYTES_WITHEX(3)
407 #if L1_CACHE_BYTES >= 128
408 COPY_16_BYTES_WITHEX(4)
409 COPY_16_BYTES_WITHEX(5)
410 COPY_16_BYTES_WITHEX(6)
411 COPY_16_BYTES_WITHEX(7)
420 #endif /* CONFIG_8xx */
440 /* read fault, initial single-byte copy */
443 /* write fault, initial single-byte copy */
448 /* read fault, initial word copy */
451 /* write fault, initial word copy */
457 * this stuff handles faults in the cacheline loop and branches to either
458 * 104f (if in read part) or 105f (if in write part), after updating r5
460 COPY_16_BYTES_EXCODE(0)
461 #if L1_CACHE_BYTES >= 32
462 COPY_16_BYTES_EXCODE(1)
463 #if L1_CACHE_BYTES >= 64
464 COPY_16_BYTES_EXCODE(2)
465 COPY_16_BYTES_EXCODE(3)
466 #if L1_CACHE_BYTES >= 128
467 COPY_16_BYTES_EXCODE(4)
468 COPY_16_BYTES_EXCODE(5)
469 COPY_16_BYTES_EXCODE(6)
470 COPY_16_BYTES_EXCODE(7)
475 /* read fault in cacheline loop */
478 /* fault on dcbz (effectively a write fault) */
479 /* or write fault in cacheline loop */
481 92: li r3,LG_CACHELINE_BYTES
485 /* read fault in final word loop */
488 /* write fault in final word loop */
493 /* read fault in final byte loop */
496 /* write fault in final byte loop */
501 * At this stage the number of bytes not copied is
502 * r5 + (ctr << r3), and r9 is 0 for read or 1 for write.
507 beq 120f /* shouldn't happen */
510 /* for a read fault, first try to continue the copy one byte at a time */
517 /* then clear out the destination: r3 bytes starting at 4(r6) */
533 .section __ex_table,"a"