Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/agpgart
[linux-2.6] / arch / ppc / platforms / pmac_pic.c
1 /*
2  *  Support for the interrupt controllers found on Power Macintosh,
3  *  currently Apple's "Grand Central" interrupt controller in all
4  *  it's incarnations. OpenPIC support used on newer machines is
5  *  in a separate file
6  *
7  *  Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au)
8  *
9  *  Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
10  *
11  *  This program is free software; you can redistribute it and/or
12  *  modify it under the terms of the GNU General Public License
13  *  as published by the Free Software Foundation; either version
14  *  2 of the License, or (at your option) any later version.
15  *
16  */
17
18 #include <linux/config.h>
19 #include <linux/stddef.h>
20 #include <linux/init.h>
21 #include <linux/sched.h>
22 #include <linux/signal.h>
23 #include <linux/pci.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/adb.h>
27 #include <linux/pmu.h>
28
29 #include <asm/sections.h>
30 #include <asm/io.h>
31 #include <asm/smp.h>
32 #include <asm/prom.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/time.h>
35 #include <asm/open_pic.h>
36 #include <asm/xmon.h>
37 #include <asm/pmac_feature.h>
38 #include <asm/machdep.h>
39
40 #include "pmac_pic.h"
41
42 /*
43  * XXX this should be in xmon.h, but putting it there means xmon.h
44  * has to include <linux/interrupt.h> (to get irqreturn_t), which
45  * causes all sorts of problems.  -- paulus
46  */
47 extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
48
49 struct pmac_irq_hw {
50         unsigned int    event;
51         unsigned int    enable;
52         unsigned int    ack;
53         unsigned int    level;
54 };
55
56 /* Default addresses */
57 static volatile struct pmac_irq_hw *pmac_irq_hw[4] = {
58         (struct pmac_irq_hw *) 0xf3000020,
59         (struct pmac_irq_hw *) 0xf3000010,
60         (struct pmac_irq_hw *) 0xf4000020,
61         (struct pmac_irq_hw *) 0xf4000010,
62 };
63
64 #define GC_LEVEL_MASK           0x3ff00000
65 #define OHARE_LEVEL_MASK        0x1ff00000
66 #define HEATHROW_LEVEL_MASK     0x1ff00000
67
68 static int max_irqs;
69 static int max_real_irqs;
70 static u32 level_mask[4];
71
72 static DEFINE_SPINLOCK(pmac_pic_lock);
73
74
75 #define GATWICK_IRQ_POOL_SIZE        10
76 static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
77
78 /*
79  * Mark an irq as "lost".  This is only used on the pmac
80  * since it can lose interrupts (see pmac_set_irq_mask).
81  * -- Cort
82  */
83 void
84 __set_lost(unsigned long irq_nr, int nokick)
85 {
86         if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
87                 atomic_inc(&ppc_n_lost_interrupts);
88                 if (!nokick)
89                         set_dec(1);
90         }
91 }
92
93 static void
94 pmac_mask_and_ack_irq(unsigned int irq_nr)
95 {
96         unsigned long bit = 1UL << (irq_nr & 0x1f);
97         int i = irq_nr >> 5;
98         unsigned long flags;
99
100         if ((unsigned)irq_nr >= max_irqs)
101                 return;
102
103         clear_bit(irq_nr, ppc_cached_irq_mask);
104         if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
105                 atomic_dec(&ppc_n_lost_interrupts);
106         spin_lock_irqsave(&pmac_pic_lock, flags);
107         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
108         out_le32(&pmac_irq_hw[i]->ack, bit);
109         do {
110                 /* make sure ack gets to controller before we enable
111                    interrupts */
112                 mb();
113         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
114                 != (ppc_cached_irq_mask[i] & bit));
115         spin_unlock_irqrestore(&pmac_pic_lock, flags);
116 }
117
118 static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
119 {
120         unsigned long bit = 1UL << (irq_nr & 0x1f);
121         int i = irq_nr >> 5;
122         unsigned long flags;
123
124         if ((unsigned)irq_nr >= max_irqs)
125                 return;
126
127         spin_lock_irqsave(&pmac_pic_lock, flags);
128         /* enable unmasked interrupts */
129         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
130
131         do {
132                 /* make sure mask gets to controller before we
133                    return to user */
134                 mb();
135         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
136                 != (ppc_cached_irq_mask[i] & bit));
137
138         /*
139          * Unfortunately, setting the bit in the enable register
140          * when the device interrupt is already on *doesn't* set
141          * the bit in the flag register or request another interrupt.
142          */
143         if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
144                 __set_lost((ulong)irq_nr, nokicklost);
145         spin_unlock_irqrestore(&pmac_pic_lock, flags);
146 }
147
148 /* When an irq gets requested for the first client, if it's an
149  * edge interrupt, we clear any previous one on the controller
150  */
151 static unsigned int pmac_startup_irq(unsigned int irq_nr)
152 {
153         unsigned long bit = 1UL << (irq_nr & 0x1f);
154         int i = irq_nr >> 5;
155
156         if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
157                 out_le32(&pmac_irq_hw[i]->ack, bit);
158         set_bit(irq_nr, ppc_cached_irq_mask);
159         pmac_set_irq_mask(irq_nr, 0);
160
161         return 0;
162 }
163
164 static void pmac_mask_irq(unsigned int irq_nr)
165 {
166         clear_bit(irq_nr, ppc_cached_irq_mask);
167         pmac_set_irq_mask(irq_nr, 0);
168         mb();
169 }
170
171 static void pmac_unmask_irq(unsigned int irq_nr)
172 {
173         set_bit(irq_nr, ppc_cached_irq_mask);
174         pmac_set_irq_mask(irq_nr, 0);
175 }
176
177 static void pmac_end_irq(unsigned int irq_nr)
178 {
179         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
180             && irq_desc[irq_nr].action) {
181                 set_bit(irq_nr, ppc_cached_irq_mask);
182                 pmac_set_irq_mask(irq_nr, 1);
183         }
184 }
185
186
187 struct hw_interrupt_type pmac_pic = {
188         .typename       = " PMAC-PIC ",
189         .startup        = pmac_startup_irq,
190         .enable         = pmac_unmask_irq,
191         .disable        = pmac_mask_irq,
192         .ack            = pmac_mask_and_ack_irq,
193         .end            = pmac_end_irq,
194 };
195
196 struct hw_interrupt_type gatwick_pic = {
197         .typename       = " GATWICK  ",
198         .startup        = pmac_startup_irq,
199         .enable         = pmac_unmask_irq,
200         .disable        = pmac_mask_irq,
201         .ack            = pmac_mask_and_ack_irq,
202         .end            = pmac_end_irq,
203 };
204
205 static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
206 {
207         int irq, bits;
208
209         for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
210                 int i = irq >> 5;
211                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
212                 /* We must read level interrupts from the level register */
213                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
214                 bits &= ppc_cached_irq_mask[i];
215                 if (bits == 0)
216                         continue;
217                 irq += __ilog2(bits);
218                 __do_IRQ(irq, regs);
219                 return IRQ_HANDLED;
220         }
221         printk("gatwick irq not from gatwick pic\n");
222         return IRQ_NONE;
223 }
224
225 int
226 pmac_get_irq(struct pt_regs *regs)
227 {
228         int irq;
229         unsigned long bits = 0;
230
231 #ifdef CONFIG_SMP
232         void psurge_smp_message_recv(struct pt_regs *);
233
234         /* IPI's are a hack on the powersurge -- Cort */
235         if ( smp_processor_id() != 0 ) {
236                 psurge_smp_message_recv(regs);
237                 return -2;      /* ignore, already handled */
238         }
239 #endif /* CONFIG_SMP */
240         for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
241                 int i = irq >> 5;
242                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
243                 /* We must read level interrupts from the level register */
244                 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
245                 bits &= ppc_cached_irq_mask[i];
246                 if (bits == 0)
247                         continue;
248                 irq += __ilog2(bits);
249                 break;
250         }
251
252         return irq;
253 }
254
255 /* This routine will fix some missing interrupt values in the device tree
256  * on the gatwick mac-io controller used by some PowerBooks
257  */
258 static void __init
259 pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
260 {
261         struct device_node *node;
262         int count;
263
264         memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
265         node = gw->child;
266         count = 0;
267         while(node)
268         {
269                 /* Fix SCC */
270                 if (strcasecmp(node->name, "escc") == 0)
271                         if (node->child) {
272                                 if (node->child->n_intrs < 3) {
273                                         node->child->intrs = &gatwick_int_pool[count];
274                                         count += 3;
275                                 }
276                                 node->child->n_intrs = 3;
277                                 node->child->intrs[0].line = 15+irq_base;
278                                 node->child->intrs[1].line =  4+irq_base;
279                                 node->child->intrs[2].line =  5+irq_base;
280                                 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
281                                         node->child->intrs[0].line,
282                                         node->child->intrs[1].line,
283                                         node->child->intrs[2].line);
284                         }
285                 /* Fix media-bay & left SWIM */
286                 if (strcasecmp(node->name, "media-bay") == 0) {
287                         struct device_node* ya_node;
288
289                         if (node->n_intrs == 0)
290                                 node->intrs = &gatwick_int_pool[count++];
291                         node->n_intrs = 1;
292                         node->intrs[0].line = 29+irq_base;
293                         printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
294                                         node->intrs[0].line);
295
296                         ya_node = node->child;
297                         while(ya_node)
298                         {
299                                 if (strcasecmp(ya_node->name, "floppy") == 0) {
300                                         if (ya_node->n_intrs < 2) {
301                                                 ya_node->intrs = &gatwick_int_pool[count];
302                                                 count += 2;
303                                         }
304                                         ya_node->n_intrs = 2;
305                                         ya_node->intrs[0].line = 19+irq_base;
306                                         ya_node->intrs[1].line =  1+irq_base;
307                                         printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
308                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
309                                 }
310                                 if (strcasecmp(ya_node->name, "ata4") == 0) {
311                                         if (ya_node->n_intrs < 2) {
312                                                 ya_node->intrs = &gatwick_int_pool[count];
313                                                 count += 2;
314                                         }
315                                         ya_node->n_intrs = 2;
316                                         ya_node->intrs[0].line = 14+irq_base;
317                                         ya_node->intrs[1].line =  3+irq_base;
318                                         printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
319                                                 ya_node->intrs[0].line, ya_node->intrs[1].line);
320                                 }
321                                 ya_node = ya_node->sibling;
322                         }
323                 }
324                 node = node->sibling;
325         }
326         if (count > 10) {
327                 printk("WARNING !! Gatwick interrupt pool overflow\n");
328                 printk("  GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
329                 printk("              requested = %d\n", count);
330         }
331 }
332
333 /*
334  * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
335  * card which includes an ohare chip that acts as a second interrupt
336  * controller.  If we find this second ohare, set it up and fix the
337  * interrupt value in the device tree for the ethernet chip.
338  */
339 static int __init enable_second_ohare(void)
340 {
341         unsigned char bus, devfn;
342         unsigned short cmd;
343         unsigned long addr;
344         struct device_node *irqctrler = find_devices("pci106b,7");
345         struct device_node *ether;
346
347         if (irqctrler == NULL || irqctrler->n_addrs <= 0)
348                 return -1;
349         addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
350         pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
351         max_irqs = 64;
352         if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
353                 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
354                 if (!hose)
355                     printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
356                 else {
357                     early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
358                     cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
359                     cmd &= ~PCI_COMMAND_IO;
360                     early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
361                 }
362         }
363
364         /* Fix interrupt for the modem/ethernet combo controller. The number
365            in the device tree (27) is bogus (correct for the ethernet-only
366            board but not the combo ethernet/modem board).
367            The real interrupt is 28 on the second controller -> 28+32 = 60.
368         */
369         ether = find_devices("pci1011,14");
370         if (ether && ether->n_intrs > 0) {
371                 ether->intrs[0].line = 60;
372                 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
373                        ether->intrs[0].line);
374         }
375
376         /* Return the interrupt number of the cascade */
377         return irqctrler->intrs[0].line;
378 }
379
380 #ifdef CONFIG_POWER4
381 static irqreturn_t k2u3_action(int cpl, void *dev_id, struct pt_regs *regs)
382 {
383         int irq;
384
385         irq = openpic2_get_irq(regs);
386         if (irq != -1)
387                 __do_IRQ(irq, regs);
388         return IRQ_HANDLED;
389 }
390
391 static struct irqaction k2u3_cascade_action = {
392         .handler        = k2u3_action,
393         .flags          = 0,
394         .mask           = CPU_MASK_NONE,
395         .name           = "U3->K2 Cascade",
396 };
397 #endif /* CONFIG_POWER4 */
398
399 #ifdef CONFIG_XMON
400 static struct irqaction xmon_action = {
401         .handler        = xmon_irq,
402         .flags          = 0,
403         .mask           = CPU_MASK_NONE,
404         .name           = "NMI - XMON"
405 };
406 #endif
407
408 static struct irqaction gatwick_cascade_action = {
409         .handler        = gatwick_action,
410         .flags          = SA_INTERRUPT,
411         .mask           = CPU_MASK_NONE,
412         .name           = "cascade",
413 };
414
415 void __init pmac_pic_init(void)
416 {
417         int i;
418         struct device_node *irqctrler  = NULL;
419         struct device_node *irqctrler2 = NULL;
420         struct device_node *np;
421         unsigned long addr;
422         int irq_cascade = -1;
423
424         /* We first try to detect Apple's new Core99 chipset, since mac-io
425          * is quite different on those machines and contains an IBM MPIC2.
426          */
427         np = find_type_devices("open-pic");
428         while(np) {
429                 if (np->parent && !strcmp(np->parent->name, "u3"))
430                         irqctrler2 = np;
431                 else
432                         irqctrler = np;
433                 np = np->next;
434         }
435         if (irqctrler != NULL)
436         {
437                 if (irqctrler->n_addrs > 0)
438                 {
439                         unsigned char senses[128];
440
441                         printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n",
442                                irqctrler->addrs[0].address);
443
444                         prom_get_irq_senses(senses, 0, 128);
445                         OpenPIC_InitSenses = senses;
446                         OpenPIC_NumInitSenses = 128;
447                         ppc_md.get_irq = openpic_get_irq;
448                         pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler, 0, 0);
449                         OpenPIC_Addr = ioremap(irqctrler->addrs[0].address,
450                                                irqctrler->addrs[0].size);
451                         openpic_init(0);
452
453 #ifdef CONFIG_POWER4
454                         if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 &&
455                             irqctrler2->n_addrs > 0) {
456                                 printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
457                                        irqctrler2->addrs[0].address,
458                                        irqctrler2->intrs[0].line);
459                                 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0);
460                                 OpenPIC2_Addr = ioremap(irqctrler2->addrs[0].address,
461                                                         irqctrler2->addrs[0].size);
462                                 prom_get_irq_senses(senses, PMAC_OPENPIC2_OFFSET,
463                                                     PMAC_OPENPIC2_OFFSET+128);
464                                 OpenPIC_InitSenses = senses;
465                                 OpenPIC_NumInitSenses = 128;
466                                 openpic2_init(PMAC_OPENPIC2_OFFSET);
467
468                                 if (setup_irq(irqctrler2->intrs[0].line,
469                                               &k2u3_cascade_action))
470                                         printk("Unable to get OpenPIC IRQ for cascade\n");
471                         }
472 #endif /* CONFIG_POWER4 */
473
474 #ifdef CONFIG_XMON
475                         {
476                                 struct device_node* pswitch;
477                                 int nmi_irq;
478
479                                 pswitch = find_devices("programmer-switch");
480                                 if (pswitch && pswitch->n_intrs) {
481                                         nmi_irq = pswitch->intrs[0].line;
482                                         openpic_init_nmi_irq(nmi_irq);
483                                         setup_irq(nmi_irq, &xmon_action);
484                                 }
485                         }
486 #endif  /* CONFIG_XMON */
487                         return;
488                 }
489                 irqctrler = NULL;
490         }
491
492         /* Get the level/edge settings, assume if it's not
493          * a Grand Central nor an OHare, then it's an Heathrow
494          * (or Paddington).
495          */
496         if (find_devices("gc"))
497                 level_mask[0] = GC_LEVEL_MASK;
498         else if (find_devices("ohare")) {
499                 level_mask[0] = OHARE_LEVEL_MASK;
500                 /* We might have a second cascaded ohare */
501                 level_mask[1] = OHARE_LEVEL_MASK;
502         } else {
503                 level_mask[0] = HEATHROW_LEVEL_MASK;
504                 level_mask[1] = 0;
505                 /* We might have a second cascaded heathrow */
506                 level_mask[2] = HEATHROW_LEVEL_MASK;
507                 level_mask[3] = 0;
508         }
509
510         /*
511          * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
512          * 1998 G3 Series PowerBooks have 128,
513          * other powermacs have 32.
514          * The combo ethernet/modem card for the Powerstar powerbooks
515          * (2400/3400/3500, ohare based) has a second ohare chip
516          * effectively making a total of 64.
517          */
518         max_irqs = max_real_irqs = 32;
519         irqctrler = find_devices("mac-io");
520         if (irqctrler)
521         {
522                 max_real_irqs = 64;
523                 if (irqctrler->next)
524                         max_irqs = 128;
525                 else
526                         max_irqs = 64;
527         }
528         for ( i = 0; i < max_real_irqs ; i++ )
529                 irq_desc[i].handler = &pmac_pic;
530
531         /* get addresses of first controller */
532         if (irqctrler) {
533                 if  (irqctrler->n_addrs > 0) {
534                         addr = (unsigned long)
535                                 ioremap(irqctrler->addrs[0].address, 0x40);
536                         for (i = 0; i < 2; ++i)
537                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
538                                         (addr + (2 - i) * 0x10);
539                 }
540
541                 /* get addresses of second controller */
542                 irqctrler = irqctrler->next;
543                 if (irqctrler && irqctrler->n_addrs > 0) {
544                         addr = (unsigned long)
545                                 ioremap(irqctrler->addrs[0].address, 0x40);
546                         for (i = 2; i < 4; ++i)
547                                 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
548                                         (addr + (4 - i) * 0x10);
549                         irq_cascade = irqctrler->intrs[0].line;
550                         if (device_is_compatible(irqctrler, "gatwick"))
551                                 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
552                 }
553         } else {
554                 /* older powermacs have a GC (grand central) or ohare at
555                    f3000000, with interrupt control registers at f3000020. */
556                 addr = (unsigned long) ioremap(0xf3000000, 0x40);
557                 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
558         }
559
560         /* PowerBooks 3400 and 3500 can have a second controller in a second
561            ohare chip, on the combo ethernet/modem card */
562         if (machine_is_compatible("AAPL,3400/2400")
563              || machine_is_compatible("AAPL,3500"))
564                 irq_cascade = enable_second_ohare();
565
566         /* disable all interrupts in all controllers */
567         for (i = 0; i * 32 < max_irqs; ++i)
568                 out_le32(&pmac_irq_hw[i]->enable, 0);
569         /* mark level interrupts */
570         for (i = 0; i < max_irqs; i++)
571                 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
572                         irq_desc[i].status = IRQ_LEVEL;
573
574         /* get interrupt line of secondary interrupt controller */
575         if (irq_cascade >= 0) {
576                 printk(KERN_INFO "irq: secondary controller on irq %d\n",
577                         (int)irq_cascade);
578                 for ( i = max_real_irqs ; i < max_irqs ; i++ )
579                         irq_desc[i].handler = &gatwick_pic;
580                 setup_irq(irq_cascade, &gatwick_cascade_action);
581         }
582         printk("System has %d possible interrupts\n", max_irqs);
583         if (max_irqs != max_real_irqs)
584                 printk(KERN_DEBUG "%d interrupts on main controller\n",
585                         max_real_irqs);
586
587 #ifdef CONFIG_XMON
588         setup_irq(20, &xmon_action);
589 #endif  /* CONFIG_XMON */
590 }
591
592 #ifdef CONFIG_PM
593 /*
594  * These procedures are used in implementing sleep on the powerbooks.
595  * sleep_save_intrs() saves the states of all interrupt enables
596  * and disables all interrupts except for the nominated one.
597  * sleep_restore_intrs() restores the states of all interrupt enables.
598  */
599 unsigned long sleep_save_mask[2];
600
601 /* This used to be passed by the PMU driver but that link got
602  * broken with the new driver model. We use this tweak for now...
603  */
604 static int pmacpic_find_viaint(void)
605 {
606         int viaint = -1;
607
608 #ifdef CONFIG_ADB_PMU
609         struct device_node *np;
610
611         if (pmu_get_model() != PMU_OHARE_BASED)
612                 goto not_found;
613         np = of_find_node_by_name(NULL, "via-pmu");
614         if (np == NULL)
615                 goto not_found;
616         viaint = np->intrs[0].line;
617 #endif /* CONFIG_ADB_PMU */
618
619 not_found:
620         return viaint;
621 }
622
623 static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
624 {
625         int viaint = pmacpic_find_viaint();
626
627         sleep_save_mask[0] = ppc_cached_irq_mask[0];
628         sleep_save_mask[1] = ppc_cached_irq_mask[1];
629         ppc_cached_irq_mask[0] = 0;
630         ppc_cached_irq_mask[1] = 0;
631         if (viaint > 0)
632                 set_bit(viaint, ppc_cached_irq_mask);
633         out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
634         if (max_real_irqs > 32)
635                 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
636         (void)in_le32(&pmac_irq_hw[0]->event);
637         /* make sure mask gets to controller before we return to caller */
638         mb();
639         (void)in_le32(&pmac_irq_hw[0]->enable);
640
641         return 0;
642 }
643
644 static int pmacpic_resume(struct sys_device *sysdev)
645 {
646         int i;
647
648         out_le32(&pmac_irq_hw[0]->enable, 0);
649         if (max_real_irqs > 32)
650                 out_le32(&pmac_irq_hw[1]->enable, 0);
651         mb();
652         for (i = 0; i < max_real_irqs; ++i)
653                 if (test_bit(i, sleep_save_mask))
654                         pmac_unmask_irq(i);
655
656         return 0;
657 }
658
659 #endif /* CONFIG_PM */
660
661 static struct sysdev_class pmacpic_sysclass = {
662         set_kset_name("pmac_pic"),
663 };
664
665 static struct sys_device device_pmacpic = {
666         .id             = 0,
667         .cls            = &pmacpic_sysclass,
668 };
669
670 static struct sysdev_driver driver_pmacpic = {
671 #ifdef CONFIG_PM
672         .suspend        = &pmacpic_suspend,
673         .resume         = &pmacpic_resume,
674 #endif /* CONFIG_PM */
675 };
676
677 static int __init init_pmacpic_sysfs(void)
678 {
679         if (max_irqs == 0)
680                 return -ENODEV;
681
682         printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
683         sysdev_class_register(&pmacpic_sysclass);
684         sysdev_register(&device_pmacpic);
685         sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
686         return 0;
687 }
688
689 subsys_initcall(init_pmacpic_sysfs);
690