git.oblomov.eu Git - linux-2.6/blob - arch/ppc/platforms/pmac_smp.c

   1 /*
   2  * SMP support for power macintosh.
   3  *
   4  * We support both the old "powersurge" SMP architecture
   5  * and the current Core99 (G4 PowerMac) machines.
   6  *
   7  * Note that we don't support the very first rev. of
   8  * Apple/DayStar 2 CPUs board, the one with the funky
   9  * watchdog. Hopefully, none of these should be there except
  10  * maybe internally to Apple. I should probably still add some
  11  * code to detect this card though and disable SMP. --BenH.
  12  *
  13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
  14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
  15  *
  16  * Support for DayStar quad CPU cards
  17  * Copyright (C) XLR8, Inc. 1994-2000
  18  *
  19  *  This program is free software; you can redistribute it and/or
  20  *  modify it under the terms of the GNU General Public License
  21  *  as published by the Free Software Foundation; either version
  22  *  2 of the License, or (at your option) any later version.
  23  */
  24 #include <linux/config.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/smp.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/kernel_stat.h>
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/errno.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/cpu.h>
  37
  38 #include <asm/ptrace.h>
  39 #include <asm/atomic.h>
  40 #include <asm/irq.h>
  41 #include <asm/page.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/sections.h>
  44 #include <asm/io.h>
  45 #include <asm/prom.h>
  46 #include <asm/smp.h>
  47 #include <asm/residual.h>
  48 #include <asm/machdep.h>
  49 #include <asm/pmac_feature.h>
  50 #include <asm/time.h>
  51 #include <asm/open_pic.h>
  52 #include <asm/cacheflush.h>
  53 #include <asm/keylargo.h>
  54
  55 /*
  56  * Powersurge (old powermac SMP) support.
  57  */
  58
  59 extern void __secondary_start_pmac_0(void);
  60
  61 /* Addresses for powersurge registers */
  62 #define HAMMERHEAD_BASE         0xf8000000
  63 #define HHEAD_CONFIG            0x90
  64 #define HHEAD_SEC_INTR          0xc0
  65
  66 /* register for interrupting the primary processor on the powersurge */
  67 /* N.B. this is actually the ethernet ROM! */
  68 #define PSURGE_PRI_INTR         0xf3019000
  69
  70 /* register for storing the start address for the secondary processor */
  71 /* N.B. this is the PCI config space address register for the 1st bridge */
  72 #define PSURGE_START            0xf2800000
  73
  74 /* Daystar/XLR8 4-CPU card */
  75 #define PSURGE_QUAD_REG_ADDR    0xf8800000
  76
  77 #define PSURGE_QUAD_IRQ_SET     0
  78 #define PSURGE_QUAD_IRQ_CLR     1
  79 #define PSURGE_QUAD_IRQ_PRIMARY 2
  80 #define PSURGE_QUAD_CKSTOP_CTL  3
  81 #define PSURGE_QUAD_PRIMARY_ARB 4
  82 #define PSURGE_QUAD_BOARD_ID    6
  83 #define PSURGE_QUAD_WHICH_CPU   7
  84 #define PSURGE_QUAD_CKSTOP_RDBK 8
  85 #define PSURGE_QUAD_RESET_CTL   11
  86
  87 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
  88 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
  89 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
  90 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
  91
  92 /* virtual addresses for the above */
  93 static volatile u8 __iomem *hhead_base;
  94 static volatile u8 __iomem *quad_base;
  95 static volatile u32 __iomem *psurge_pri_intr;
  96 static volatile u8 __iomem *psurge_sec_intr;
  97 static volatile u32 __iomem *psurge_start;
  98
  99 /* values for psurge_type */
 100 #define PSURGE_NONE             -1
 101 #define PSURGE_DUAL             0
 102 #define PSURGE_QUAD_OKEE        1
 103 #define PSURGE_QUAD_COTTON      2
 104 #define PSURGE_QUAD_ICEGRASS    3
 105
 106 /* what sort of powersurge board we have */
 107 static int psurge_type = PSURGE_NONE;
 108
 109 /* L2 and L3 cache settings to pass from CPU0 to CPU1 */
 110 volatile static long int core99_l2_cache;
 111 volatile static long int core99_l3_cache;
 112
 113 /* Timebase freeze GPIO */
 114 static unsigned int core99_tb_gpio;
 115
 116 /* Sync flag for HW tb sync */
 117 static volatile int sec_tb_reset = 0;
 118 static unsigned int pri_tb_hi, pri_tb_lo;
 119 static unsigned int pri_tb_stamp;
 120
 121 static void __devinit core99_init_caches(int cpu)
 122 {
 123         if (!cpu_has_feature(CPU_FTR_L2CR))
 124                 return;
 125
 126         if (cpu == 0) {
 127                 core99_l2_cache = _get_L2CR();
 128                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
 129         } else {
 130                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
 131                 _set_L2CR(0);
 132                 _set_L2CR(core99_l2_cache);
 133                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
 134         }
 135
 136         if (!cpu_has_feature(CPU_FTR_L3CR))
 137                 return;
 138
 139         if (cpu == 0){
 140                 core99_l3_cache = _get_L3CR();
 141                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
 142         } else {
 143                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
 144                 _set_L3CR(0);
 145                 _set_L3CR(core99_l3_cache);
 146                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
 147         }
 148 }
 149
 150 /*
 151  * Set and clear IPIs for powersurge.
 152  */
 153 static inline void psurge_set_ipi(int cpu)
 154 {
 155         if (psurge_type == PSURGE_NONE)
 156                 return;
 157         if (cpu == 0)
 158                 in_be32(psurge_pri_intr);
 159         else if (psurge_type == PSURGE_DUAL)
 160                 out_8(psurge_sec_intr, 0);
 161         else
 162                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
 163 }
 164
 165 static inline void psurge_clr_ipi(int cpu)
 166 {
 167         if (cpu > 0) {
 168                 switch(psurge_type) {
 169                 case PSURGE_DUAL:
 170                         out_8(psurge_sec_intr, ~0);
 171                 case PSURGE_NONE:
 172                         break;
 173                 default:
 174                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
 175                 }
 176         }
 177 }
 178
 179 /*
 180  * On powersurge (old SMP powermac architecture) we don't have
 181  * separate IPIs for separate messages like openpic does.  Instead
 182  * we have a bitmap for each processor, where a 1 bit means that
 183  * the corresponding message is pending for that processor.
 184  * Ideally each cpu's entry would be in a different cache line.
 185  *  -- paulus.
 186  */
 187 static unsigned long psurge_smp_message[NR_CPUS];
 188
 189 void psurge_smp_message_recv(struct pt_regs *regs)
 190 {
 191         int cpu = smp_processor_id();
 192         int msg;
 193
 194         /* clear interrupt */
 195         psurge_clr_ipi(cpu);
 196
 197         if (num_online_cpus() < 2)
 198                 return;
 199
 200         /* make sure there is a message there */
 201         for (msg = 0; msg < 4; msg++)
 202                 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
 203                         smp_message_recv(msg, regs);
 204 }
 205
 206 irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
 207 {
 208         psurge_smp_message_recv(regs);
 209         return IRQ_HANDLED;
 210 }
 211
 212 static void smp_psurge_message_pass(int target, int msg)
 213 {
 214         int i;
 215
 216         if (num_online_cpus() < 2)
 217                 return;
 218
 219         for (i = 0; i < NR_CPUS; i++) {
 220                 if (!cpu_online(i))
 221                         continue;
 222                 if (target == MSG_ALL
 223                     || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
 224                     || target == i) {
 225                         set_bit(msg, &psurge_smp_message[i]);
 226                         psurge_set_ipi(i);
 227                 }
 228         }
 229 }
 230
 231 /*
 232  * Determine a quad card presence. We read the board ID register, we
 233  * force the data bus to change to something else, and we read it again.
 234  * It it's stable, then the register probably exist (ugh !)
 235  */
 236 static int __init psurge_quad_probe(void)
 237 {
 238         int type;
 239         unsigned int i;
 240
 241         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
 242         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
 243             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 244                 return PSURGE_DUAL;
 245
 246         /* looks OK, try a slightly more rigorous test */
 247         /* bogus is not necessarily cacheline-aligned,
 248            though I don't suppose that really matters.  -- paulus */
 249         for (i = 0; i < 100; i++) {
 250                 volatile u32 bogus[8];
 251                 bogus[(0+i)%8] = 0x00000000;
 252                 bogus[(1+i)%8] = 0x55555555;
 253                 bogus[(2+i)%8] = 0xFFFFFFFF;
 254                 bogus[(3+i)%8] = 0xAAAAAAAA;
 255                 bogus[(4+i)%8] = 0x33333333;
 256                 bogus[(5+i)%8] = 0xCCCCCCCC;
 257                 bogus[(6+i)%8] = 0xCCCCCCCC;
 258                 bogus[(7+i)%8] = 0x33333333;
 259                 wmb();
 260                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
 261                 mb();
 262                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 263                         return PSURGE_DUAL;
 264         }
 265         return type;
 266 }
 267
 268 static void __init psurge_quad_init(void)
 269 {
 270         int procbits;
 271
 272         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
 273         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
 274         if (psurge_type == PSURGE_QUAD_ICEGRASS)
 275                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 276         else
 277                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
 278         mdelay(33);
 279         out_8(psurge_sec_intr, ~0);
 280         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
 281         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 282         if (psurge_type != PSURGE_QUAD_ICEGRASS)
 283                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
 284         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
 285         mdelay(33);
 286         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
 287         mdelay(33);
 288         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
 289         mdelay(33);
 290 }
 291
 292 static int __init smp_psurge_probe(void)
 293 {
 294         int i, ncpus;
 295
 296         /* We don't do SMP on the PPC601 -- paulus */
 297         if (PVR_VER(mfspr(SPRN_PVR)) == 1)
 298                 return 1;
 299
 300         /*
 301          * The powersurge cpu board can be used in the generation
 302          * of powermacs that have a socket for an upgradeable cpu card,
 303          * including the 7500, 8500, 9500, 9600.
 304          * The device tree doesn't tell you if you have 2 cpus because
 305          * OF doesn't know anything about the 2nd processor.
 306          * Instead we look for magic bits in magic registers,
 307          * in the hammerhead memory controller in the case of the
 308          * dual-cpu powersurge board.  -- paulus.
 309          */
 310         if (find_devices("hammerhead") == NULL)
 311                 return 1;
 312
 313         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
 314         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
 315         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
 316
 317         psurge_type = psurge_quad_probe();
 318         if (psurge_type != PSURGE_DUAL) {
 319                 psurge_quad_init();
 320                 /* All released cards using this HW design have 4 CPUs */
 321                 ncpus = 4;
 322         } else {
 323                 iounmap(quad_base);
 324                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
 325                         /* not a dual-cpu card */
 326                         iounmap(hhead_base);
 327                         psurge_type = PSURGE_NONE;
 328                         return 1;
 329                 }
 330                 ncpus = 2;
 331         }
 332
 333         psurge_start = ioremap(PSURGE_START, 4);
 334         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
 335
 336         /* this is not actually strictly necessary -- paulus. */
 337         for (i = 1; i < ncpus; ++i)
 338                 smp_hw_index[i] = i;
 339
 340         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
 341
 342         return ncpus;
 343 }
 344
 345 static void __init smp_psurge_kick_cpu(int nr)
 346 {
 347         unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
 348         unsigned long a;
 349
 350         /* may need to flush here if secondary bats aren't setup */
 351         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
 352                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
 353         asm volatile("sync");
 354
 355         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
 356
 357         out_be32(psurge_start, start);
 358         mb();
 359
 360         psurge_set_ipi(nr);
 361         udelay(10);
 362         psurge_clr_ipi(nr);
 363
 364         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
 365 }
 366
 367 /*
 368  * With the dual-cpu powersurge board, the decrementers and timebases
 369  * of both cpus are frozen after the secondary cpu is started up,
 370  * until we give the secondary cpu another interrupt.  This routine
 371  * uses this to get the timebases synchronized.
 372  *  -- paulus.
 373  */
 374 static void __init psurge_dual_sync_tb(int cpu_nr)
 375 {
 376         int t;
 377
 378         set_dec(tb_ticks_per_jiffy);
 379         set_tb(0, 0);
 380         last_jiffy_stamp(cpu_nr) = 0;
 381
 382         if (cpu_nr > 0) {
 383                 mb();
 384                 sec_tb_reset = 1;
 385                 return;
 386         }
 387
 388         /* wait for the secondary to have reset its TB before proceeding */
 389         for (t = 10000000; t > 0 && !sec_tb_reset; --t)
 390                 ;
 391
 392         /* now interrupt the secondary, starting both TBs */
 393         psurge_set_ipi(1);
 394
 395         smp_tb_synchronized = 1;
 396 }
 397
 398 static struct irqaction psurge_irqaction = {
 399         .handler = psurge_primary_intr,
 400         .flags = SA_INTERRUPT,
 401         .mask = CPU_MASK_NONE,
 402         .name = "primary IPI",
 403 };
 404
 405 static void __init smp_psurge_setup_cpu(int cpu_nr)
 406 {
 407
 408         if (cpu_nr == 0) {
 409                 /* If we failed to start the second CPU, we should still
 410                  * send it an IPI to start the timebase & DEC or we might
 411                  * have them stuck.
 412                  */
 413                 if (num_online_cpus() < 2) {
 414                         if (psurge_type == PSURGE_DUAL)
 415                                 psurge_set_ipi(1);
 416                         return;
 417                 }
 418                 /* reset the entry point so if we get another intr we won't
 419                  * try to startup again */
 420                 out_be32(psurge_start, 0x100);
 421                 if (setup_irq(30, &psurge_irqaction))
 422                         printk(KERN_ERR "Couldn't get primary IPI interrupt");
 423         }
 424
 425         if (psurge_type == PSURGE_DUAL)
 426                 psurge_dual_sync_tb(cpu_nr);
 427 }
 428
 429 void __init smp_psurge_take_timebase(void)
 430 {
 431         /* Dummy implementation */
 432 }
 433
 434 void __init smp_psurge_give_timebase(void)
 435 {
 436         /* Dummy implementation */
 437 }
 438
 439 static int __init smp_core99_probe(void)
 440 {
 441 #ifdef CONFIG_6xx
 442         extern int powersave_nap;
 443 #endif
 444         struct device_node *cpus, *firstcpu;
 445         int i, ncpus = 0, boot_cpu = -1;
 446         u32 *tbprop = NULL;
 447
 448         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
 449         cpus = firstcpu = find_type_devices("cpu");
 450         while(cpus != NULL) {
 451                 u32 *regprop = (u32 *)get_property(cpus, "reg", NULL);
 452                 char *stateprop = (char *)get_property(cpus, "state", NULL);
 453                 if (regprop != NULL && stateprop != NULL &&
 454                     !strncmp(stateprop, "running", 7))
 455                         boot_cpu = *regprop;
 456                 ++ncpus;
 457                 cpus = cpus->next;
 458         }
 459         if (boot_cpu == -1)
 460                 printk(KERN_WARNING "Couldn't detect boot CPU !\n");
 461         if (boot_cpu != 0)
 462                 printk(KERN_WARNING "Boot CPU is %d, unsupported setup !\n", boot_cpu);
 463
 464         if (machine_is_compatible("MacRISC4")) {
 465                 extern struct smp_ops_t core99_smp_ops;
 466
 467                 core99_smp_ops.take_timebase = smp_generic_take_timebase;
 468                 core99_smp_ops.give_timebase = smp_generic_give_timebase;
 469         } else {
 470                 if (firstcpu != NULL)
 471                         tbprop = (u32 *)get_property(firstcpu, "timebase-enable", NULL);
 472                 if (tbprop)
 473                         core99_tb_gpio = *tbprop;
 474                 else
 475                         core99_tb_gpio = KL_GPIO_TB_ENABLE;
 476         }
 477
 478         if (ncpus > 1) {
 479                 openpic_request_IPIs();
 480                 for (i = 1; i < ncpus; ++i)
 481                         smp_hw_index[i] = i;
 482 #ifdef CONFIG_6xx
 483                 powersave_nap = 0;
 484 #endif
 485                 core99_init_caches(0);
 486         }
 487
 488         return ncpus;
 489 }
 490
 491 static void __devinit smp_core99_kick_cpu(int nr)
 492 {
 493         unsigned long save_vector, new_vector;
 494         unsigned long flags;
 495
 496         volatile unsigned long *vector
 497                  = ((volatile unsigned long *)(KERNELBASE+0x100));
 498         if (nr < 0 || nr > 3)
 499                 return;
 500         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
 501
 502         local_irq_save(flags);
 503         local_irq_disable();
 504
 505         /* Save reset vector */
 506         save_vector = *vector;
 507
 508         /* Setup fake reset vector that does
 509          *   b __secondary_start_pmac_0 + nr*8 - KERNELBASE
 510          */
 511         new_vector = (unsigned long) __secondary_start_pmac_0 + nr * 8;
 512         *vector = 0x48000002 + new_vector - KERNELBASE;
 513
 514         /* flush data cache and inval instruction cache */
 515         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
 516
 517         /* Put some life in our friend */
 518         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
 519
 520         /* FIXME: We wait a bit for the CPU to take the exception, I should
 521          * instead wait for the entry code to set something for me. Well,
 522          * ideally, all that crap will be done in prom.c and the CPU left
 523          * in a RAM-based wait loop like CHRP.
 524          */
 525         mdelay(1);
 526
 527         /* Restore our exception vector */
 528         *vector = save_vector;
 529         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
 530
 531         local_irq_restore(flags);
 532         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
 533 }
 534
 535 static void __devinit smp_core99_setup_cpu(int cpu_nr)
 536 {
 537         /* Setup L2/L3 */
 538         if (cpu_nr != 0)
 539                 core99_init_caches(cpu_nr);
 540
 541         /* Setup openpic */
 542         do_openpic_setup_cpu();
 543
 544         if (cpu_nr == 0) {
 545 #ifdef CONFIG_POWER4
 546                 extern void g5_phy_disable_cpu1(void);
 547
 548                 /* If we didn't start the second CPU, we must take
 549                  * it off the bus
 550                  */
 551                 if (machine_is_compatible("MacRISC4") &&
 552                     num_online_cpus() < 2)
 553                         g5_phy_disable_cpu1();
 554 #endif /* CONFIG_POWER4 */
 555                 if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
 556         }
 557 }
 558
 559 /* not __init, called in sleep/wakeup code */
 560 void smp_core99_take_timebase(void)
 561 {
 562         unsigned long flags;
 563
 564         /* tell the primary we're here */
 565         sec_tb_reset = 1;
 566         mb();
 567
 568         /* wait for the primary to set pri_tb_hi/lo */
 569         while (sec_tb_reset < 2)
 570                 mb();
 571
 572         /* set our stuff the same as the primary */
 573         local_irq_save(flags);
 574         set_dec(1);
 575         set_tb(pri_tb_hi, pri_tb_lo);
 576         last_jiffy_stamp(smp_processor_id()) = pri_tb_stamp;
 577         mb();
 578
 579         /* tell the primary we're done */
 580         sec_tb_reset = 0;
 581         mb();
 582         local_irq_restore(flags);
 583 }
 584
 585 /* not __init, called in sleep/wakeup code */
 586 void smp_core99_give_timebase(void)
 587 {
 588         unsigned long flags;
 589         unsigned int t;
 590
 591         /* wait for the secondary to be in take_timebase */
 592         for (t = 100000; t > 0 && !sec_tb_reset; --t)
 593                 udelay(10);
 594         if (!sec_tb_reset) {
 595                 printk(KERN_WARNING "Timeout waiting sync on second CPU\n");
 596                 return;
 597         }
 598
 599         /* freeze the timebase and read it */
 600         /* disable interrupts so the timebase is disabled for the
 601            shortest possible time */
 602         local_irq_save(flags);
 603         pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
 604         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
 605         mb();
 606         pri_tb_hi = get_tbu();
 607         pri_tb_lo = get_tbl();
 608         pri_tb_stamp = last_jiffy_stamp(smp_processor_id());
 609         mb();
 610
 611         /* tell the secondary we're ready */
 612         sec_tb_reset = 2;
 613         mb();
 614
 615         /* wait for the secondary to have taken it */
 616         for (t = 100000; t > 0 && sec_tb_reset; --t)
 617                 udelay(10);
 618         if (sec_tb_reset)
 619                 printk(KERN_WARNING "Timeout waiting sync(2) on second CPU\n");
 620         else
 621                 smp_tb_synchronized = 1;
 622
 623         /* Now, restart the timebase by leaving the GPIO to an open collector */
 624         pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
 625         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
 626         local_irq_restore(flags);
 627 }
 628
 629
 630 /* PowerSurge-style Macs */
 631 struct smp_ops_t psurge_smp_ops = {
 632         .message_pass   = smp_psurge_message_pass,
 633         .probe          = smp_psurge_probe,
 634         .kick_cpu       = smp_psurge_kick_cpu,
 635         .setup_cpu      = smp_psurge_setup_cpu,
 636         .give_timebase  = smp_psurge_give_timebase,
 637         .take_timebase  = smp_psurge_take_timebase,
 638 };
 639
 640 /* Core99 Macs (dual G4s) */
 641 struct smp_ops_t core99_smp_ops = {
 642         .message_pass   = smp_openpic_message_pass,
 643         .probe          = smp_core99_probe,
 644         .kick_cpu       = smp_core99_kick_cpu,
 645         .setup_cpu      = smp_core99_setup_cpu,
 646         .give_timebase  = smp_core99_give_timebase,
 647         .take_timebase  = smp_core99_take_timebase,
 648 };
 649
 650 #ifdef CONFIG_HOTPLUG_CPU
 651
 652 int __cpu_disable(void)
 653 {
 654         cpu_clear(smp_processor_id(), cpu_online_map);
 655
 656         /* XXX reset cpu affinity here */
 657         openpic_set_priority(0xf);
 658         asm volatile("mtdec %0" : : "r" (0x7fffffff));
 659         mb();
 660         udelay(20);
 661         asm volatile("mtdec %0" : : "r" (0x7fffffff));
 662         return 0;
 663 }
 664
 665 extern void low_cpu_die(void) __attribute__((noreturn)); /* in pmac_sleep.S */
 666 static int cpu_dead[NR_CPUS];
 667
 668 void cpu_die(void)
 669 {
 670         local_irq_disable();
 671         cpu_dead[smp_processor_id()] = 1;
 672         mb();
 673         low_cpu_die();
 674 }
 675
 676 void __cpu_die(unsigned int cpu)
 677 {
 678         int timeout;
 679
 680         timeout = 1000;
 681         while (!cpu_dead[cpu]) {
 682                 if (--timeout == 0) {
 683                         printk("CPU %u refused to die!\n", cpu);
 684                         break;
 685                 }
 686                 msleep(1);
 687         }
 688         cpu_callin_map[cpu] = 0;
 689         cpu_dead[cpu] = 0;
 690 }
 691
 692 #endif