3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
10 #include <linux/irq.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/config.h>
14 #include <linux/ioport.h>
15 #include <linux/smp_lock.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
19 #include <asm/errno.h>
26 static DEFINE_SPINLOCK(msi_lock);
27 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
28 static kmem_cache_t* msi_cachep;
30 static int pci_msi_enable = 1;
31 static int last_alloc_vector;
32 static int nr_released_vectors;
33 static int nr_reserved_vectors = NR_HP_RESERVED_VECTORS;
34 static int nr_msix_devices;
36 #ifndef CONFIG_X86_IO_APIC
37 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
38 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
41 static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags)
43 memset(p, 0, NR_IRQS * sizeof(struct msi_desc));
46 static int msi_cache_init(void)
48 msi_cachep = kmem_cache_create("msi_cache",
49 NR_IRQS * sizeof(struct msi_desc),
50 0, SLAB_HWCACHE_ALIGN, msi_cache_ctor, NULL);
57 static void msi_set_mask_bit(unsigned int vector, int flag)
59 struct msi_desc *entry;
61 entry = (struct msi_desc *)msi_desc[vector];
62 if (!entry || !entry->dev || !entry->mask_base)
64 switch (entry->msi_attrib.type) {
70 pos = (long)entry->mask_base;
71 pci_read_config_dword(entry->dev, pos, &mask_bits);
74 pci_write_config_dword(entry->dev, pos, mask_bits);
79 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
80 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
81 writel(flag, entry->mask_base + offset);
90 static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
92 struct msi_desc *entry;
93 struct msg_address address;
94 unsigned int irq = vector;
96 entry = (struct msi_desc *)msi_desc[vector];
97 if (!entry || !entry->dev)
100 switch (entry->msi_attrib.type) {
105 if (!(pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI)))
108 pci_read_config_dword(entry->dev, msi_lower_address_reg(pos),
109 &address.lo_address.value);
110 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
111 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) <<
112 MSI_TARGET_CPU_SHIFT);
113 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask);
114 pci_write_config_dword(entry->dev, msi_lower_address_reg(pos),
115 address.lo_address.value);
116 set_native_irq_info(irq, cpu_mask);
119 case PCI_CAP_ID_MSIX:
121 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
122 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET;
124 address.lo_address.value = readl(entry->mask_base + offset);
125 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
126 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) <<
127 MSI_TARGET_CPU_SHIFT);
128 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask);
129 writel(address.lo_address.value, entry->mask_base + offset);
130 set_native_irq_info(irq, cpu_mask);
137 #endif /* CONFIG_SMP */
139 static void mask_MSI_irq(unsigned int vector)
141 msi_set_mask_bit(vector, 1);
144 static void unmask_MSI_irq(unsigned int vector)
146 msi_set_mask_bit(vector, 0);
149 static unsigned int startup_msi_irq_wo_maskbit(unsigned int vector)
151 struct msi_desc *entry;
154 spin_lock_irqsave(&msi_lock, flags);
155 entry = msi_desc[vector];
156 if (!entry || !entry->dev) {
157 spin_unlock_irqrestore(&msi_lock, flags);
160 entry->msi_attrib.state = 1; /* Mark it active */
161 spin_unlock_irqrestore(&msi_lock, flags);
163 return 0; /* never anything pending */
166 static unsigned int startup_msi_irq_w_maskbit(unsigned int vector)
168 startup_msi_irq_wo_maskbit(vector);
169 unmask_MSI_irq(vector);
170 return 0; /* never anything pending */
173 static void shutdown_msi_irq(unsigned int vector)
175 struct msi_desc *entry;
178 spin_lock_irqsave(&msi_lock, flags);
179 entry = msi_desc[vector];
180 if (entry && entry->dev)
181 entry->msi_attrib.state = 0; /* Mark it not active */
182 spin_unlock_irqrestore(&msi_lock, flags);
185 static void end_msi_irq_wo_maskbit(unsigned int vector)
187 move_native_irq(vector);
191 static void end_msi_irq_w_maskbit(unsigned int vector)
193 move_native_irq(vector);
194 unmask_MSI_irq(vector);
198 static void do_nothing(unsigned int vector)
203 * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices,
204 * which implement the MSI-X Capability Structure.
206 static struct hw_interrupt_type msix_irq_type = {
207 .typename = "PCI-MSI-X",
208 .startup = startup_msi_irq_w_maskbit,
209 .shutdown = shutdown_msi_irq,
210 .enable = unmask_MSI_irq,
211 .disable = mask_MSI_irq,
213 .end = end_msi_irq_w_maskbit,
214 .set_affinity = set_msi_irq_affinity
218 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
219 * which implement the MSI Capability Structure with
220 * Mask-and-Pending Bits.
222 static struct hw_interrupt_type msi_irq_w_maskbit_type = {
223 .typename = "PCI-MSI",
224 .startup = startup_msi_irq_w_maskbit,
225 .shutdown = shutdown_msi_irq,
226 .enable = unmask_MSI_irq,
227 .disable = mask_MSI_irq,
229 .end = end_msi_irq_w_maskbit,
230 .set_affinity = set_msi_irq_affinity
234 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
235 * which implement the MSI Capability Structure without
236 * Mask-and-Pending Bits.
238 static struct hw_interrupt_type msi_irq_wo_maskbit_type = {
239 .typename = "PCI-MSI",
240 .startup = startup_msi_irq_wo_maskbit,
241 .shutdown = shutdown_msi_irq,
242 .enable = do_nothing,
243 .disable = do_nothing,
245 .end = end_msi_irq_wo_maskbit,
246 .set_affinity = set_msi_irq_affinity
249 static void msi_data_init(struct msg_data *msi_data,
252 memset(msi_data, 0, sizeof(struct msg_data));
253 msi_data->vector = (u8)vector;
254 msi_data->delivery_mode = MSI_DELIVERY_MODE;
255 msi_data->level = MSI_LEVEL_MODE;
256 msi_data->trigger = MSI_TRIGGER_MODE;
259 static void msi_address_init(struct msg_address *msi_address)
261 unsigned int dest_id;
263 memset(msi_address, 0, sizeof(struct msg_address));
264 msi_address->hi_address = (u32)0;
265 dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT);
266 msi_address->lo_address.u.dest_mode = MSI_DEST_MODE;
267 msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE;
268 msi_address->lo_address.u.dest_id = dest_id;
269 msi_address->lo_address.value |= (MSI_TARGET_CPU << MSI_TARGET_CPU_SHIFT);
272 static int msi_free_vector(struct pci_dev* dev, int vector, int reassign);
273 static int assign_msi_vector(void)
275 static int new_vector_avail = 1;
280 * msi_lock is provided to ensure that successful allocation of MSI
281 * vector is assigned unique among drivers.
283 spin_lock_irqsave(&msi_lock, flags);
285 if (!new_vector_avail) {
289 * vector_irq[] = -1 indicates that this specific vector is:
290 * - assigned for MSI (since MSI have no associated IRQ) or
291 * - assigned for legacy if less than 16, or
292 * - having no corresponding 1:1 vector-to-IOxAPIC IRQ mapping
293 * vector_irq[] = 0 indicates that this vector, previously
294 * assigned for MSI, is freed by hotplug removed operations.
295 * This vector will be reused for any subsequent hotplug added
297 * vector_irq[] > 0 indicates that this vector is assigned for
298 * IOxAPIC IRQs. This vector and its value provides a 1-to-1
299 * vector-to-IOxAPIC IRQ mapping.
301 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
302 if (vector_irq[vector] != 0)
304 free_vector = vector;
305 if (!msi_desc[vector])
311 spin_unlock_irqrestore(&msi_lock, flags);
314 vector_irq[free_vector] = -1;
315 nr_released_vectors--;
316 spin_unlock_irqrestore(&msi_lock, flags);
317 if (msi_desc[free_vector] != NULL) {
321 /* free all linked vectors before re-assign */
323 spin_lock_irqsave(&msi_lock, flags);
324 dev = msi_desc[free_vector]->dev;
325 tail = msi_desc[free_vector]->link.tail;
326 spin_unlock_irqrestore(&msi_lock, flags);
327 msi_free_vector(dev, tail, 1);
328 } while (free_vector != tail);
333 vector = assign_irq_vector(AUTO_ASSIGN);
334 last_alloc_vector = vector;
335 if (vector == LAST_DEVICE_VECTOR)
336 new_vector_avail = 0;
338 spin_unlock_irqrestore(&msi_lock, flags);
342 static int get_new_vector(void)
346 if ((vector = assign_msi_vector()) > 0)
347 set_intr_gate(vector, interrupt[vector]);
352 static int msi_init(void)
354 static int status = -ENOMEM;
361 printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n");
366 if ((status = msi_cache_init()) < 0) {
368 printk(KERN_WARNING "PCI: MSI cache init failed\n");
371 last_alloc_vector = assign_irq_vector(AUTO_ASSIGN);
372 if (last_alloc_vector < 0) {
374 printk(KERN_WARNING "PCI: No interrupt vectors available for MSI\n");
378 vector_irq[last_alloc_vector] = 0;
379 nr_released_vectors++;
384 static int get_msi_vector(struct pci_dev *dev)
386 return get_new_vector();
389 static struct msi_desc* alloc_msi_entry(void)
391 struct msi_desc *entry;
393 entry = kmem_cache_alloc(msi_cachep, SLAB_KERNEL);
397 memset(entry, 0, sizeof(struct msi_desc));
398 entry->link.tail = entry->link.head = 0; /* single message */
404 static void attach_msi_entry(struct msi_desc *entry, int vector)
408 spin_lock_irqsave(&msi_lock, flags);
409 msi_desc[vector] = entry;
410 spin_unlock_irqrestore(&msi_lock, flags);
413 static void irq_handler_init(int cap_id, int pos, int mask)
415 spin_lock(&irq_desc[pos].lock);
416 if (cap_id == PCI_CAP_ID_MSIX)
417 irq_desc[pos].handler = &msix_irq_type;
420 irq_desc[pos].handler = &msi_irq_wo_maskbit_type;
422 irq_desc[pos].handler = &msi_irq_w_maskbit_type;
424 spin_unlock(&irq_desc[pos].lock);
427 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
431 pci_read_config_word(dev, msi_control_reg(pos), &control);
432 if (type == PCI_CAP_ID_MSI) {
433 /* Set enabled bits to single MSI & enable MSI_enable bit */
434 msi_enable(control, 1);
435 pci_write_config_word(dev, msi_control_reg(pos), control);
437 msix_enable(control);
438 pci_write_config_word(dev, msi_control_reg(pos), control);
440 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
441 /* PCI Express Endpoint device detected */
442 pci_intx(dev, 0); /* disable intx */
446 void disable_msi_mode(struct pci_dev *dev, int pos, int type)
450 pci_read_config_word(dev, msi_control_reg(pos), &control);
451 if (type == PCI_CAP_ID_MSI) {
452 /* Set enabled bits to single MSI & enable MSI_enable bit */
453 msi_disable(control);
454 pci_write_config_word(dev, msi_control_reg(pos), control);
456 msix_disable(control);
457 pci_write_config_word(dev, msi_control_reg(pos), control);
459 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
460 /* PCI Express Endpoint device detected */
461 pci_intx(dev, 1); /* enable intx */
465 static int msi_lookup_vector(struct pci_dev *dev, int type)
470 spin_lock_irqsave(&msi_lock, flags);
471 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
472 if (!msi_desc[vector] || msi_desc[vector]->dev != dev ||
473 msi_desc[vector]->msi_attrib.type != type ||
474 msi_desc[vector]->msi_attrib.default_vector != dev->irq)
476 spin_unlock_irqrestore(&msi_lock, flags);
477 /* This pre-assigned MSI vector for this device
478 already exits. Override dev->irq with this vector */
482 spin_unlock_irqrestore(&msi_lock, flags);
487 void pci_scan_msi_device(struct pci_dev *dev)
492 if (pci_find_capability(dev, PCI_CAP_ID_MSIX) > 0)
494 else if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0)
495 nr_reserved_vectors++;
499 * msi_capability_init - configure device's MSI capability structure
500 * @dev: pointer to the pci_dev data structure of MSI device function
502 * Setup the MSI capability structure of device function with a single
503 * MSI vector, regardless of device function is capable of handling
504 * multiple messages. A return of zero indicates the successful setup
505 * of an entry zero with the new MSI vector or non-zero for otherwise.
507 static int msi_capability_init(struct pci_dev *dev)
509 struct msi_desc *entry;
510 struct msg_address address;
511 struct msg_data data;
515 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
516 pci_read_config_word(dev, msi_control_reg(pos), &control);
517 /* MSI Entry Initialization */
518 if (!(entry = alloc_msi_entry()))
521 if ((vector = get_msi_vector(dev)) < 0) {
522 kmem_cache_free(msi_cachep, entry);
525 entry->link.head = vector;
526 entry->link.tail = vector;
527 entry->msi_attrib.type = PCI_CAP_ID_MSI;
528 entry->msi_attrib.state = 0; /* Mark it not active */
529 entry->msi_attrib.entry_nr = 0;
530 entry->msi_attrib.maskbit = is_mask_bit_support(control);
531 entry->msi_attrib.default_vector = dev->irq; /* Save IOAPIC IRQ */
534 if (is_mask_bit_support(control)) {
535 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
536 is_64bit_address(control));
538 /* Replace with MSI handler */
539 irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit);
540 /* Configure MSI capability structure */
541 msi_address_init(&address);
542 msi_data_init(&data, vector);
543 entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
544 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
545 pci_write_config_dword(dev, msi_lower_address_reg(pos),
546 address.lo_address.value);
547 if (is_64bit_address(control)) {
548 pci_write_config_dword(dev,
549 msi_upper_address_reg(pos), address.hi_address);
550 pci_write_config_word(dev,
551 msi_data_reg(pos, 1), *((u32*)&data));
553 pci_write_config_word(dev,
554 msi_data_reg(pos, 0), *((u32*)&data));
555 if (entry->msi_attrib.maskbit) {
556 unsigned int maskbits, temp;
557 /* All MSIs are unmasked by default, Mask them all */
558 pci_read_config_dword(dev,
559 msi_mask_bits_reg(pos, is_64bit_address(control)),
561 temp = (1 << multi_msi_capable(control));
562 temp = ((temp - 1) & ~temp);
564 pci_write_config_dword(dev,
565 msi_mask_bits_reg(pos, is_64bit_address(control)),
568 attach_msi_entry(entry, vector);
569 /* Set MSI enabled bits */
570 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
576 * msix_capability_init - configure device's MSI-X capability
577 * @dev: pointer to the pci_dev data structure of MSI-X device function
579 * Setup the MSI-X capability structure of device function with a
580 * single MSI-X vector. A return of zero indicates the successful setup of
581 * requested MSI-X entries with allocated vectors or non-zero for otherwise.
583 static int msix_capability_init(struct pci_dev *dev,
584 struct msix_entry *entries, int nvec)
586 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
587 struct msg_address address;
588 struct msg_data data;
589 int vector, pos, i, j, nr_entries, temp = 0;
590 u32 phys_addr, table_offset;
595 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
596 /* Request & Map MSI-X table region */
597 pci_read_config_word(dev, msi_control_reg(pos), &control);
598 nr_entries = multi_msix_capable(control);
599 pci_read_config_dword(dev, msix_table_offset_reg(pos),
601 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
602 phys_addr = pci_resource_start (dev, bir);
603 phys_addr += (u32)(table_offset & ~PCI_MSIX_FLAGS_BIRMASK);
604 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
608 /* MSI-X Table Initialization */
609 for (i = 0; i < nvec; i++) {
610 entry = alloc_msi_entry();
613 if ((vector = get_msi_vector(dev)) < 0)
616 j = entries[i].entry;
617 entries[i].vector = vector;
618 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
619 entry->msi_attrib.state = 0; /* Mark it not active */
620 entry->msi_attrib.entry_nr = j;
621 entry->msi_attrib.maskbit = 1;
622 entry->msi_attrib.default_vector = dev->irq;
624 entry->mask_base = base;
626 entry->link.head = vector;
627 entry->link.tail = vector;
630 entry->link.head = temp;
631 entry->link.tail = tail->link.tail;
632 tail->link.tail = vector;
633 head->link.head = vector;
637 /* Replace with MSI-X handler */
638 irq_handler_init(PCI_CAP_ID_MSIX, vector, 1);
639 /* Configure MSI-X capability structure */
640 msi_address_init(&address);
641 msi_data_init(&data, vector);
642 entry->msi_attrib.current_cpu =
643 ((address.lo_address.u.dest_id >>
644 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
645 writel(address.lo_address.value,
646 base + j * PCI_MSIX_ENTRY_SIZE +
647 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
648 writel(address.hi_address,
649 base + j * PCI_MSIX_ENTRY_SIZE +
650 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
652 base + j * PCI_MSIX_ENTRY_SIZE +
653 PCI_MSIX_ENTRY_DATA_OFFSET);
654 attach_msi_entry(entry, vector);
658 for (; i >= 0; i--) {
659 vector = (entries + i)->vector;
660 msi_free_vector(dev, vector, 0);
661 (entries + i)->vector = 0;
665 /* Set MSI-X enabled bits */
666 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
672 * pci_enable_msi - configure device's MSI capability structure
673 * @dev: pointer to the pci_dev data structure of MSI device function
675 * Setup the MSI capability structure of device function with
676 * a single MSI vector upon its software driver call to request for
677 * MSI mode enabled on its hardware device function. A return of zero
678 * indicates the successful setup of an entry zero with the new MSI
679 * vector or non-zero for otherwise.
681 int pci_enable_msi(struct pci_dev* dev)
683 int pos, temp, status = -EINVAL;
686 if (!pci_msi_enable || !dev)
694 if ((status = msi_init()) < 0)
697 if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSI)))
700 pci_read_config_word(dev, msi_control_reg(pos), &control);
701 if (control & PCI_MSI_FLAGS_ENABLE)
702 return 0; /* Already in MSI mode */
704 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
708 spin_lock_irqsave(&msi_lock, flags);
709 if (!vector_irq[dev->irq]) {
710 msi_desc[dev->irq]->msi_attrib.state = 0;
711 vector_irq[dev->irq] = -1;
712 nr_released_vectors--;
713 spin_unlock_irqrestore(&msi_lock, flags);
714 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
717 spin_unlock_irqrestore(&msi_lock, flags);
720 /* Check whether driver already requested for MSI-X vectors */
721 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)) > 0 &&
722 !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
723 printk(KERN_INFO "PCI: %s: Can't enable MSI. "
724 "Device already has MSI-X vectors assigned\n",
729 status = msi_capability_init(dev);
732 nr_reserved_vectors--; /* Only MSI capable */
733 else if (nr_msix_devices > 0)
734 nr_msix_devices--; /* Both MSI and MSI-X capable,
735 but choose enabling MSI */
741 void pci_disable_msi(struct pci_dev* dev)
743 struct msi_desc *entry;
744 int pos, default_vector;
748 if (!dev || !(pos = pci_find_capability(dev, PCI_CAP_ID_MSI)))
751 pci_read_config_word(dev, msi_control_reg(pos), &control);
752 if (!(control & PCI_MSI_FLAGS_ENABLE))
755 spin_lock_irqsave(&msi_lock, flags);
756 entry = msi_desc[dev->irq];
757 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
758 spin_unlock_irqrestore(&msi_lock, flags);
761 if (entry->msi_attrib.state) {
762 spin_unlock_irqrestore(&msi_lock, flags);
763 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
764 "free_irq() on MSI vector %d\n",
765 pci_name(dev), dev->irq);
766 BUG_ON(entry->msi_attrib.state > 0);
768 vector_irq[dev->irq] = 0; /* free it */
769 nr_released_vectors++;
770 default_vector = entry->msi_attrib.default_vector;
771 spin_unlock_irqrestore(&msi_lock, flags);
772 /* Restore dev->irq to its default pin-assertion vector */
773 dev->irq = default_vector;
774 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
779 static int msi_free_vector(struct pci_dev* dev, int vector, int reassign)
781 struct msi_desc *entry;
782 int head, entry_nr, type;
786 spin_lock_irqsave(&msi_lock, flags);
787 entry = msi_desc[vector];
788 if (!entry || entry->dev != dev) {
789 spin_unlock_irqrestore(&msi_lock, flags);
792 type = entry->msi_attrib.type;
793 entry_nr = entry->msi_attrib.entry_nr;
794 head = entry->link.head;
795 base = entry->mask_base;
796 msi_desc[entry->link.head]->link.tail = entry->link.tail;
797 msi_desc[entry->link.tail]->link.head = entry->link.head;
800 vector_irq[vector] = 0;
801 nr_released_vectors++;
803 msi_desc[vector] = NULL;
804 spin_unlock_irqrestore(&msi_lock, flags);
806 kmem_cache_free(msi_cachep, entry);
808 if (type == PCI_CAP_ID_MSIX) {
811 entry_nr * PCI_MSIX_ENTRY_SIZE +
812 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
814 if (head == vector) {
816 * Detect last MSI-X vector to be released.
817 * Release the MSI-X memory-mapped table.
820 u32 phys_addr, table_offset;
824 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
825 pci_read_config_word(dev, msi_control_reg(pos),
827 nr_entries = multi_msix_capable(control);
828 pci_read_config_dword(dev, msix_table_offset_reg(pos),
830 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
831 phys_addr = pci_resource_start (dev, bir);
832 phys_addr += (u32)(table_offset &
833 ~PCI_MSIX_FLAGS_BIRMASK);
841 static int reroute_msix_table(int head, struct msix_entry *entries, int *nvec)
843 int vector = head, tail = 0;
844 int i, j = 0, nr_entries = 0;
848 spin_lock_irqsave(&msi_lock, flags);
849 while (head != tail) {
851 tail = msi_desc[vector]->link.tail;
852 if (entries[0].entry == msi_desc[vector]->msi_attrib.entry_nr)
856 if (*nvec > nr_entries) {
857 spin_unlock_irqrestore(&msi_lock, flags);
861 vector = ((j > 0) ? j : head);
862 for (i = 0; i < *nvec; i++) {
863 j = msi_desc[vector]->msi_attrib.entry_nr;
864 msi_desc[vector]->msi_attrib.state = 0; /* Mark it not active */
865 vector_irq[vector] = -1; /* Mark it busy */
866 nr_released_vectors--;
867 entries[i].vector = vector;
868 if (j != (entries + i)->entry) {
869 base = msi_desc[vector]->mask_base;
870 msi_desc[vector]->msi_attrib.entry_nr =
871 (entries + i)->entry;
872 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE +
873 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET), base +
874 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE +
875 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
876 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE +
877 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET), base +
878 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE +
879 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
880 writel( (readl(base + j * PCI_MSIX_ENTRY_SIZE +
881 PCI_MSIX_ENTRY_DATA_OFFSET) & 0xff00) | vector,
882 base + (entries+i)->entry*PCI_MSIX_ENTRY_SIZE +
883 PCI_MSIX_ENTRY_DATA_OFFSET);
885 vector = msi_desc[vector]->link.tail;
887 spin_unlock_irqrestore(&msi_lock, flags);
893 * pci_enable_msix - configure device's MSI-X capability structure
894 * @dev: pointer to the pci_dev data structure of MSI-X device function
895 * @entries: pointer to an array of MSI-X entries
896 * @nvec: number of MSI-X vectors requested for allocation by device driver
898 * Setup the MSI-X capability structure of device function with the number
899 * of requested vectors upon its software driver call to request for
900 * MSI-X mode enabled on its hardware device function. A return of zero
901 * indicates the successful configuration of MSI-X capability structure
902 * with new allocated MSI-X vectors. A return of < 0 indicates a failure.
903 * Or a return of > 0 indicates that driver request is exceeding the number
904 * of vectors available. Driver should use the returned value to re-send
907 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
909 int status, pos, nr_entries, free_vectors;
914 if (!pci_msi_enable || !dev || !entries)
917 if ((status = msi_init()) < 0)
920 if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)))
923 pci_read_config_word(dev, msi_control_reg(pos), &control);
924 if (control & PCI_MSIX_FLAGS_ENABLE)
925 return -EINVAL; /* Already in MSI-X mode */
927 nr_entries = multi_msix_capable(control);
928 if (nvec > nr_entries)
931 /* Check for any invalid entries */
932 for (i = 0; i < nvec; i++) {
933 if (entries[i].entry >= nr_entries)
934 return -EINVAL; /* invalid entry */
935 for (j = i + 1; j < nvec; j++) {
936 if (entries[i].entry == entries[j].entry)
937 return -EINVAL; /* duplicate entry */
941 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
944 /* Reroute MSI-X table */
945 if (reroute_msix_table(dev->irq, entries, &nr_entries)) {
946 /* #requested > #previous-assigned */
951 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
954 /* Check whether driver already requested for MSI vector */
955 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
956 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
957 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
958 "Device already has an MSI vector assigned\n",
964 spin_lock_irqsave(&msi_lock, flags);
966 * msi_lock is provided to ensure that enough vectors resources are
967 * available before granting.
969 free_vectors = pci_vector_resources(last_alloc_vector,
970 nr_released_vectors);
971 /* Ensure that each MSI/MSI-X device has one vector reserved by
972 default to avoid any MSI-X driver to take all available
974 free_vectors -= nr_reserved_vectors;
975 /* Find the average of free vectors among MSI-X devices */
976 if (nr_msix_devices > 0)
977 free_vectors /= nr_msix_devices;
978 spin_unlock_irqrestore(&msi_lock, flags);
980 if (nvec > free_vectors) {
981 if (free_vectors > 0)
987 status = msix_capability_init(dev, entries, nvec);
988 if (!status && nr_msix_devices > 0)
994 void pci_disable_msix(struct pci_dev* dev)
999 if (!dev || !(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)))
1002 pci_read_config_word(dev, msi_control_reg(pos), &control);
1003 if (!(control & PCI_MSIX_FLAGS_ENABLE))
1007 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
1008 int state, vector, head, tail = 0, warning = 0;
1009 unsigned long flags;
1011 vector = head = dev->irq;
1012 spin_lock_irqsave(&msi_lock, flags);
1013 while (head != tail) {
1014 state = msi_desc[vector]->msi_attrib.state;
1018 vector_irq[vector] = 0; /* free it */
1019 nr_released_vectors++;
1021 tail = msi_desc[vector]->link.tail;
1024 spin_unlock_irqrestore(&msi_lock, flags);
1027 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
1028 "free_irq() on all MSI-X vectors\n",
1030 BUG_ON(warning > 0);
1033 disable_msi_mode(dev,
1034 pci_find_capability(dev, PCI_CAP_ID_MSIX),
1042 * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state
1043 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1045 * Being called during hotplug remove, from which the device function
1046 * is hot-removed. All previous assigned MSI/MSI-X vectors, if
1047 * allocated for this device function, are reclaimed to unused state,
1048 * which may be used later on.
1050 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
1052 int state, pos, temp;
1053 unsigned long flags;
1055 if (!pci_msi_enable || !dev)
1058 temp = dev->irq; /* Save IOAPIC IRQ */
1059 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSI)) > 0 &&
1060 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
1061 spin_lock_irqsave(&msi_lock, flags);
1062 state = msi_desc[dev->irq]->msi_attrib.state;
1063 spin_unlock_irqrestore(&msi_lock, flags);
1065 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
1066 "called without free_irq() on MSI vector %d\n",
1067 pci_name(dev), dev->irq);
1069 } else /* Release MSI vector assigned to this device */
1070 msi_free_vector(dev, dev->irq, 0);
1071 dev->irq = temp; /* Restore IOAPIC IRQ */
1073 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)) > 0 &&
1074 !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
1075 int vector, head, tail = 0, warning = 0;
1076 void __iomem *base = NULL;
1078 vector = head = dev->irq;
1079 while (head != tail) {
1080 spin_lock_irqsave(&msi_lock, flags);
1081 state = msi_desc[vector]->msi_attrib.state;
1082 tail = msi_desc[vector]->link.tail;
1083 base = msi_desc[vector]->mask_base;
1084 spin_unlock_irqrestore(&msi_lock, flags);
1087 else if (vector != head) /* Release MSI-X vector */
1088 msi_free_vector(dev, vector, 0);
1091 msi_free_vector(dev, vector, 0);
1093 /* Force to release the MSI-X memory-mapped table */
1094 u32 phys_addr, table_offset;
1098 pci_read_config_word(dev, msi_control_reg(pos),
1100 pci_read_config_dword(dev, msix_table_offset_reg(pos),
1102 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
1103 phys_addr = pci_resource_start (dev, bir);
1104 phys_addr += (u32)(table_offset &
1105 ~PCI_MSIX_FLAGS_BIRMASK);
1107 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
1108 "called without free_irq() on all MSI-X vectors\n",
1110 BUG_ON(warning > 0);
1112 dev->irq = temp; /* Restore IOAPIC IRQ */
1116 EXPORT_SYMBOL(pci_enable_msi);
1117 EXPORT_SYMBOL(pci_disable_msi);
1118 EXPORT_SYMBOL(pci_enable_msix);
1119 EXPORT_SYMBOL(pci_disable_msix);