[POWERPC] prom.c whitespace cleanup
[linux-2.6] / arch / powerpc / boot / dts / mpc8548cds.dts
1 /*
2  * MPC8548 CDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12
13 / {
14         model = "MPC8548CDS";
15         compatible = "MPC8548CDS", "MPC85xxCDS";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         cpus {
20                 #address-cells = <1>;
21                 #size-cells = <0>;
22
23                 PowerPC,8548@0 {
24                         device_type = "cpu";
25                         reg = <0>;
26                         d-cache-line-size = <20>;       // 32 bytes
27                         i-cache-line-size = <20>;       // 32 bytes
28                         d-cache-size = <8000>;          // L1, 32K
29                         i-cache-size = <8000>;          // L1, 32K
30                         timebase-frequency = <0>;       //  33 MHz, from uboot
31                         bus-frequency = <0>;    // 166 MHz
32                         clock-frequency = <0>;  // 825 MHz, from uboot
33                         32-bit;
34                 };
35         };
36
37         memory {
38                 device_type = "memory";
39                 reg = <00000000 08000000>;      // 128M at 0x0
40         };
41
42         soc8548@e0000000 {
43                 #address-cells = <1>;
44                 #size-cells = <1>;
45                 #interrupt-cells = <2>;
46                 device_type = "soc";
47                 ranges = <00001000 e0001000 000ff000
48                           80000000 80000000 10000000
49                           e2000000 e2000000 00800000
50                           90000000 90000000 10000000
51                           e2800000 e2800000 00800000
52                           a0000000 a0000000 20000000
53                           e3000000 e3000000 01000000>;
54                 reg = <e0000000 00001000>;      // CCSRBAR
55                 bus-frequency = <0>;
56
57                 memory-controller@2000 {
58                         compatible = "fsl,8548-memory-controller";
59                         reg = <2000 1000>;
60                         interrupt-parent = <&mpic>;
61                         interrupts = <12 2>;
62                 };
63
64                 l2-cache-controller@20000 {
65                         compatible = "fsl,8548-l2-cache-controller";
66                         reg = <20000 1000>;
67                         cache-line-size = <20>; // 32 bytes
68                         cache-size = <80000>;   // L2, 512K
69                         interrupt-parent = <&mpic>;
70                         interrupts = <10 2>;
71                 };
72
73                 i2c@3000 {
74                         device_type = "i2c";
75                         compatible = "fsl-i2c";
76                         reg = <3000 100>;
77                         interrupts = <2b 2>;
78                         interrupt-parent = <&mpic>;
79                         dfsrr;
80                 };
81
82                 mdio@24520 {
83                         #address-cells = <1>;
84                         #size-cells = <0>;
85                         device_type = "mdio";
86                         compatible = "gianfar";
87                         reg = <24520 20>;
88                         phy0: ethernet-phy@0 {
89                                 interrupt-parent = <&mpic>;
90                                 interrupts = <5 1>;
91                                 reg = <0>;
92                                 device_type = "ethernet-phy";
93                         };
94                         phy1: ethernet-phy@1 {
95                                 interrupt-parent = <&mpic>;
96                                 interrupts = <5 1>;
97                                 reg = <1>;
98                                 device_type = "ethernet-phy";
99                         };
100                         phy2: ethernet-phy@2 {
101                                 interrupt-parent = <&mpic>;
102                                 interrupts = <5 1>;
103                                 reg = <2>;
104                                 device_type = "ethernet-phy";
105                         };
106                         phy3: ethernet-phy@3 {
107                                 interrupt-parent = <&mpic>;
108                                 interrupts = <5 1>;
109                                 reg = <3>;
110                                 device_type = "ethernet-phy";
111                         };
112                 };
113
114                 ethernet@24000 {
115                         #address-cells = <1>;
116                         #size-cells = <0>;
117                         device_type = "network";
118                         model = "eTSEC";
119                         compatible = "gianfar";
120                         reg = <24000 1000>;
121                         local-mac-address = [ 00 00 00 00 00 00 ];
122                         interrupts = <1d 2 1e 2 22 2>;
123                         interrupt-parent = <&mpic>;
124                         phy-handle = <&phy0>;
125                 };
126
127                 ethernet@25000 {
128                         #address-cells = <1>;
129                         #size-cells = <0>;
130                         device_type = "network";
131                         model = "eTSEC";
132                         compatible = "gianfar";
133                         reg = <25000 1000>;
134                         local-mac-address = [ 00 00 00 00 00 00 ];
135                         interrupts = <23 2 24 2 28 2>;
136                         interrupt-parent = <&mpic>;
137                         phy-handle = <&phy1>;
138                 };
139
140 /* eTSEC 3/4 are currently broken
141                 ethernet@26000 {
142                         #address-cells = <1>;
143                         #size-cells = <0>;
144                         device_type = "network";
145                         model = "eTSEC";
146                         compatible = "gianfar";
147                         reg = <26000 1000>;
148                         local-mac-address = [ 00 00 00 00 00 00 ];
149                         interrupts = <1f 2 20 2 21 2>;
150                         interrupt-parent = <&mpic>;
151                         phy-handle = <&phy2>;
152                 };
153
154                 ethernet@27000 {
155                         #address-cells = <1>;
156                         #size-cells = <0>;
157                         device_type = "network";
158                         model = "eTSEC";
159                         compatible = "gianfar";
160                         reg = <27000 1000>;
161                         local-mac-address = [ 00 00 00 00 00 00 ];
162                         interrupts = <25 2 26 2 27 2>;
163                         interrupt-parent = <&mpic>;
164                         phy-handle = <&phy3>;
165                 };
166  */
167
168                 serial@4500 {
169                         device_type = "serial";
170                         compatible = "ns16550";
171                         reg = <4500 100>;       // reg base, size
172                         clock-frequency = <0>;  // should we fill in in uboot?
173                         interrupts = <2a 2>;
174                         interrupt-parent = <&mpic>;
175                 };
176
177                 serial@4600 {
178                         device_type = "serial";
179                         compatible = "ns16550";
180                         reg = <4600 100>;       // reg base, size
181                         clock-frequency = <0>;  // should we fill in in uboot?
182                         interrupts = <2a 2>;
183                         interrupt-parent = <&mpic>;
184                 };
185
186                 global-utilities@e0000 {        //global utilities reg
187                         compatible = "fsl,mpc8548-guts";
188                         reg = <e0000 1000>;
189                         fsl,has-rstcr;
190                 };
191
192                 pci@8000 {
193                         interrupt-map-mask = <f800 0 0 7>;
194                         interrupt-map = <
195                                 /* IDSEL 0x4 (PCIX Slot 2) */
196                                 02000 0 0 1 &mpic 0 1
197                                 02000 0 0 2 &mpic 1 1
198                                 02000 0 0 3 &mpic 2 1
199                                 02000 0 0 4 &mpic 3 1
200
201                                 /* IDSEL 0x5 (PCIX Slot 3) */
202                                 02800 0 0 1 &mpic 1 1
203                                 02800 0 0 2 &mpic 2 1
204                                 02800 0 0 3 &mpic 3 1
205                                 02800 0 0 4 &mpic 0 1
206
207                                 /* IDSEL 0x6 (PCIX Slot 4) */
208                                 03000 0 0 1 &mpic 2 1
209                                 03000 0 0 2 &mpic 3 1
210                                 03000 0 0 3 &mpic 0 1
211                                 03000 0 0 4 &mpic 1 1
212
213                                 /* IDSEL 0x8 (PCIX Slot 5) */
214                                 04000 0 0 1 &mpic 0 1
215                                 04000 0 0 2 &mpic 1 1
216                                 04000 0 0 3 &mpic 2 1
217                                 04000 0 0 4 &mpic 3 1
218
219                                 /* IDSEL 0xC (Tsi310 bridge) */
220                                 06000 0 0 1 &mpic 0 1
221                                 06000 0 0 2 &mpic 1 1
222                                 06000 0 0 3 &mpic 2 1
223                                 06000 0 0 4 &mpic 3 1
224
225                                 /* IDSEL 0x14 (Slot 2) */
226                                 0a000 0 0 1 &mpic 0 1
227                                 0a000 0 0 2 &mpic 1 1
228                                 0a000 0 0 3 &mpic 2 1
229                                 0a000 0 0 4 &mpic 3 1
230
231                                 /* IDSEL 0x15 (Slot 3) */
232                                 0a800 0 0 1 &mpic 1 1
233                                 0a800 0 0 2 &mpic 2 1
234                                 0a800 0 0 3 &mpic 3 1
235                                 0a800 0 0 4 &mpic 0 1
236
237                                 /* IDSEL 0x16 (Slot 4) */
238                                 0b000 0 0 1 &mpic 2 1
239                                 0b000 0 0 2 &mpic 3 1
240                                 0b000 0 0 3 &mpic 0 1
241                                 0b000 0 0 4 &mpic 1 1
242
243                                 /* IDSEL 0x18 (Slot 5) */
244                                 0c000 0 0 1 &mpic 0 1
245                                 0c000 0 0 2 &mpic 1 1
246                                 0c000 0 0 3 &mpic 2 1
247                                 0c000 0 0 4 &mpic 3 1
248
249                                 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
250                                 0E000 0 0 1 &mpic 0 1
251                                 0E000 0 0 2 &mpic 1 1
252                                 0E000 0 0 3 &mpic 2 1
253                                 0E000 0 0 4 &mpic 3 1>;
254
255                         interrupt-parent = <&mpic>;
256                         interrupts = <18 2>;
257                         bus-range = <0 0>;
258                         ranges = <02000000 0 80000000 80000000 0 10000000
259                                   01000000 0 00000000 e2000000 0 00800000>;
260                         clock-frequency = <3f940aa>;
261                         #interrupt-cells = <1>;
262                         #size-cells = <2>;
263                         #address-cells = <3>;
264                         reg = <8000 1000>;
265                         compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
266                         device_type = "pci";
267
268                         pci_bridge@1c {
269                                 interrupt-map-mask = <f800 0 0 7>;
270                                 interrupt-map = <
271
272                                         /* IDSEL 0x00 (PrPMC Site) */
273                                         0000 0 0 1 &mpic 0 1
274                                         0000 0 0 2 &mpic 1 1
275                                         0000 0 0 3 &mpic 2 1
276                                         0000 0 0 4 &mpic 3 1
277
278                                         /* IDSEL 0x04 (VIA chip) */
279                                         2000 0 0 1 &mpic 0 1
280                                         2000 0 0 2 &mpic 1 1
281                                         2000 0 0 3 &mpic 2 1
282                                         2000 0 0 4 &mpic 3 1
283
284                                         /* IDSEL 0x05 (8139) */
285                                         2800 0 0 1 &mpic 1 1
286
287                                         /* IDSEL 0x06 (Slot 6) */
288                                         3000 0 0 1 &mpic 2 1
289                                         3000 0 0 2 &mpic 3 1
290                                         3000 0 0 3 &mpic 0 1
291                                         3000 0 0 4 &mpic 1 1
292
293                                         /* IDESL 0x07 (Slot 7) */
294                                         3800 0 0 1 &mpic 3 1
295                                         3800 0 0 2 &mpic 0 1
296                                         3800 0 0 3 &mpic 1 1
297                                         3800 0 0 4 &mpic 2 1>;
298
299                                 reg = <e000 0 0 0 0>;
300                                 #interrupt-cells = <1>;
301                                 #size-cells = <2>;
302                                 #address-cells = <3>;
303                                 ranges = <02000000 0 80000000
304                                           02000000 0 80000000
305                                           0 20000000
306                                           01000000 0 00000000
307                                           01000000 0 00000000
308                                           0 00080000>;
309                                 clock-frequency = <1fca055>;
310
311                                 isa@4 {
312                                         device_type = "isa";
313                                         #interrupt-cells = <2>;
314                                         #size-cells = <1>;
315                                         #address-cells = <2>;
316                                         reg = <2000 0 0 0 0>;
317                                         ranges = <1 0 01000000 0 0 00001000>;
318                                         interrupt-parent = <&i8259>;
319
320                                         i8259: interrupt-controller@20 {
321                                                 clock-frequency = <0>;
322                                                 interrupt-controller;
323                                                 device_type = "interrupt-controller";
324                                                 reg = <1 20 2
325                                                        1 a0 2
326                                                        1 4d0 2>;
327                                                 #address-cells = <0>;
328                                                 #interrupt-cells = <2>;
329                                                 built-in;
330                                                 compatible = "chrp,iic";
331                                                 interrupts = <0 1>;
332                                                 interrupt-parent = <&mpic>;
333                                         };
334
335                                         rtc@70 {
336                                                 compatible = "pnpPNP,b00";
337                                                 reg = <1 70 2>;
338                                         };
339                                 };
340                         };
341                 };
342
343                 pci@9000 {
344                         interrupt-map-mask = <f800 0 0 7>;
345                         interrupt-map = <
346
347                                 /* IDSEL 0x15 */
348                                 a800 0 0 1 &mpic b 1
349                                 a800 0 0 2 &mpic 1 1
350                                 a800 0 0 3 &mpic 2 1
351                                 a800 0 0 4 &mpic 3 1>;
352
353                         interrupt-parent = <&mpic>;
354                         interrupts = <19 2>;
355                         bus-range = <0 0>;
356                         ranges = <02000000 0 90000000 90000000 0 10000000
357                                   01000000 0 00000000 e2800000 0 00800000>;
358                         clock-frequency = <3f940aa>;
359                         #interrupt-cells = <1>;
360                         #size-cells = <2>;
361                         #address-cells = <3>;
362                         reg = <9000 1000>;
363                         compatible = "fsl,mpc8540-pci";
364                         device_type = "pci";
365                 };
366                 /* PCI Express */
367                 pcie@a000 {
368                         interrupt-map-mask = <f800 0 0 7>;
369                         interrupt-map = <
370
371                                 /* IDSEL 0x0 (PEX) */
372                                 00000 0 0 1 &mpic 0 1
373                                 00000 0 0 2 &mpic 1 1
374                                 00000 0 0 3 &mpic 2 1
375                                 00000 0 0 4 &mpic 3 1>;
376
377                         interrupt-parent = <&mpic>;
378                         interrupts = <1a 2>;
379                         bus-range = <0 ff>;
380                         ranges = <02000000 0 a0000000 a0000000 0 20000000
381                                   01000000 0 00000000 e3000000 0 08000000>;
382                         clock-frequency = <1fca055>;
383                         #interrupt-cells = <1>;
384                         #size-cells = <2>;
385                         #address-cells = <3>;
386                         reg = <a000 1000>;
387                         compatible = "fsl,mpc8548-pcie";
388                         device_type = "pci";
389                 };
390
391                 mpic: pic@40000 {
392                         clock-frequency = <0>;
393                         interrupt-controller;
394                         #address-cells = <0>;
395                         #interrupt-cells = <2>;
396                         reg = <40000 40000>;
397                         built-in;
398                         compatible = "chrp,open-pic";
399                         device_type = "open-pic";
400                         big-endian;
401                 };
402         };
403 };