2 * arch/arm/mach-mv78xx0/common.c
4 * Core functions for Marvell MV78xx0 SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/serial_8250.h>
15 #include <linux/mbus.h>
16 #include <linux/mv643xx_eth.h>
17 #include <linux/ata_platform.h>
18 #include <linux/ethtool.h>
19 #include <asm/mach/map.h>
20 #include <asm/mach/time.h>
21 #include <mach/mv78xx0.h>
22 #include <plat/cache-feroceon-l2.h>
23 #include <plat/ehci-orion.h>
24 #include <plat/orion_nand.h>
25 #include <plat/time.h>
29 /*****************************************************************************
31 ****************************************************************************/
32 int mv78xx0_core_index(void)
37 * Read Extra Features register.
39 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
41 return !!(extra & 0x00004000);
44 static int get_hclk(void)
49 * HCLK tick rate is configured by DEV_D[7:5] pins.
51 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
68 panic("unknown HCLK PLL setting: %.8x\n",
69 readl(SAMPLE_AT_RESET_LOW));
75 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
80 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
81 * PCLK/L2CLK by bits [19:14].
83 if (core_index == 0) {
84 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
86 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
90 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
91 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
93 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
96 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
99 *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
102 static int get_tclk(void)
107 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
109 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
117 panic("unknown TCLK PLL setting: %.8x\n",
118 readl(SAMPLE_AT_RESET_HIGH));
125 /*****************************************************************************
126 * I/O Address Mapping
127 ****************************************************************************/
128 static struct map_desc mv78xx0_io_desc[] __initdata = {
130 .virtual = MV78XX0_CORE_REGS_VIRT_BASE,
132 .length = MV78XX0_CORE_REGS_SIZE,
135 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
136 .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
137 .length = MV78XX0_PCIE_IO_SIZE * 8,
140 .virtual = MV78XX0_REGS_VIRT_BASE,
141 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
142 .length = MV78XX0_REGS_SIZE,
147 void __init mv78xx0_map_io(void)
152 * Map the right set of per-core registers depending on
153 * which core we are running on.
155 if (mv78xx0_core_index() == 0) {
156 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
158 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
160 mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
162 iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
166 /*****************************************************************************
168 ****************************************************************************/
169 static struct orion_ehci_data mv78xx0_ehci_data = {
170 .dram = &mv78xx0_mbus_dram_info,
171 .phy_version = EHCI_PHY_NA,
174 static u64 ehci_dmamask = 0xffffffffUL;
177 /*****************************************************************************
179 ****************************************************************************/
180 static struct resource mv78xx0_ehci0_resources[] = {
182 .start = USB0_PHYS_BASE,
183 .end = USB0_PHYS_BASE + 0x0fff,
184 .flags = IORESOURCE_MEM,
186 .start = IRQ_MV78XX0_USB_0,
187 .end = IRQ_MV78XX0_USB_0,
188 .flags = IORESOURCE_IRQ,
192 static struct platform_device mv78xx0_ehci0 = {
193 .name = "orion-ehci",
196 .dma_mask = &ehci_dmamask,
197 .coherent_dma_mask = 0xffffffff,
198 .platform_data = &mv78xx0_ehci_data,
200 .resource = mv78xx0_ehci0_resources,
201 .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources),
204 void __init mv78xx0_ehci0_init(void)
206 platform_device_register(&mv78xx0_ehci0);
210 /*****************************************************************************
212 ****************************************************************************/
213 static struct resource mv78xx0_ehci1_resources[] = {
215 .start = USB1_PHYS_BASE,
216 .end = USB1_PHYS_BASE + 0x0fff,
217 .flags = IORESOURCE_MEM,
219 .start = IRQ_MV78XX0_USB_1,
220 .end = IRQ_MV78XX0_USB_1,
221 .flags = IORESOURCE_IRQ,
225 static struct platform_device mv78xx0_ehci1 = {
226 .name = "orion-ehci",
229 .dma_mask = &ehci_dmamask,
230 .coherent_dma_mask = 0xffffffff,
231 .platform_data = &mv78xx0_ehci_data,
233 .resource = mv78xx0_ehci1_resources,
234 .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources),
237 void __init mv78xx0_ehci1_init(void)
239 platform_device_register(&mv78xx0_ehci1);
243 /*****************************************************************************
245 ****************************************************************************/
246 static struct resource mv78xx0_ehci2_resources[] = {
248 .start = USB2_PHYS_BASE,
249 .end = USB2_PHYS_BASE + 0x0fff,
250 .flags = IORESOURCE_MEM,
252 .start = IRQ_MV78XX0_USB_2,
253 .end = IRQ_MV78XX0_USB_2,
254 .flags = IORESOURCE_IRQ,
258 static struct platform_device mv78xx0_ehci2 = {
259 .name = "orion-ehci",
262 .dma_mask = &ehci_dmamask,
263 .coherent_dma_mask = 0xffffffff,
264 .platform_data = &mv78xx0_ehci_data,
266 .resource = mv78xx0_ehci2_resources,
267 .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources),
270 void __init mv78xx0_ehci2_init(void)
272 platform_device_register(&mv78xx0_ehci2);
276 /*****************************************************************************
278 ****************************************************************************/
279 struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
281 .dram = &mv78xx0_mbus_dram_info,
284 static struct resource mv78xx0_ge00_shared_resources[] = {
287 .start = GE00_PHYS_BASE + 0x2000,
288 .end = GE00_PHYS_BASE + 0x3fff,
289 .flags = IORESOURCE_MEM,
291 .name = "ge err irq",
292 .start = IRQ_MV78XX0_GE_ERR,
293 .end = IRQ_MV78XX0_GE_ERR,
294 .flags = IORESOURCE_IRQ,
298 static struct platform_device mv78xx0_ge00_shared = {
299 .name = MV643XX_ETH_SHARED_NAME,
302 .platform_data = &mv78xx0_ge00_shared_data,
304 .num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
305 .resource = mv78xx0_ge00_shared_resources,
308 static struct resource mv78xx0_ge00_resources[] = {
311 .start = IRQ_MV78XX0_GE00_SUM,
312 .end = IRQ_MV78XX0_GE00_SUM,
313 .flags = IORESOURCE_IRQ,
317 static struct platform_device mv78xx0_ge00 = {
318 .name = MV643XX_ETH_NAME,
321 .resource = mv78xx0_ge00_resources,
324 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
326 eth_data->shared = &mv78xx0_ge00_shared;
327 mv78xx0_ge00.dev.platform_data = eth_data;
329 platform_device_register(&mv78xx0_ge00_shared);
330 platform_device_register(&mv78xx0_ge00);
334 /*****************************************************************************
336 ****************************************************************************/
337 struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
339 .dram = &mv78xx0_mbus_dram_info,
340 .shared_smi = &mv78xx0_ge00_shared,
343 static struct resource mv78xx0_ge01_shared_resources[] = {
346 .start = GE01_PHYS_BASE + 0x2000,
347 .end = GE01_PHYS_BASE + 0x3fff,
348 .flags = IORESOURCE_MEM,
352 static struct platform_device mv78xx0_ge01_shared = {
353 .name = MV643XX_ETH_SHARED_NAME,
356 .platform_data = &mv78xx0_ge01_shared_data,
359 .resource = mv78xx0_ge01_shared_resources,
362 static struct resource mv78xx0_ge01_resources[] = {
365 .start = IRQ_MV78XX0_GE01_SUM,
366 .end = IRQ_MV78XX0_GE01_SUM,
367 .flags = IORESOURCE_IRQ,
371 static struct platform_device mv78xx0_ge01 = {
372 .name = MV643XX_ETH_NAME,
375 .resource = mv78xx0_ge01_resources,
378 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
380 eth_data->shared = &mv78xx0_ge01_shared;
381 mv78xx0_ge01.dev.platform_data = eth_data;
383 platform_device_register(&mv78xx0_ge01_shared);
384 platform_device_register(&mv78xx0_ge01);
388 /*****************************************************************************
390 ****************************************************************************/
391 struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
393 .dram = &mv78xx0_mbus_dram_info,
394 .shared_smi = &mv78xx0_ge00_shared,
397 static struct resource mv78xx0_ge10_shared_resources[] = {
400 .start = GE10_PHYS_BASE + 0x2000,
401 .end = GE10_PHYS_BASE + 0x3fff,
402 .flags = IORESOURCE_MEM,
406 static struct platform_device mv78xx0_ge10_shared = {
407 .name = MV643XX_ETH_SHARED_NAME,
410 .platform_data = &mv78xx0_ge10_shared_data,
413 .resource = mv78xx0_ge10_shared_resources,
416 static struct resource mv78xx0_ge10_resources[] = {
419 .start = IRQ_MV78XX0_GE10_SUM,
420 .end = IRQ_MV78XX0_GE10_SUM,
421 .flags = IORESOURCE_IRQ,
425 static struct platform_device mv78xx0_ge10 = {
426 .name = MV643XX_ETH_NAME,
429 .resource = mv78xx0_ge10_resources,
432 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
436 eth_data->shared = &mv78xx0_ge10_shared;
437 mv78xx0_ge10.dev.platform_data = eth_data;
440 * On the Z0, ge10 and ge11 are internally connected back
441 * to back, and not brought out.
443 mv78xx0_pcie_id(&dev, &rev);
444 if (dev == MV78X00_Z0_DEV_ID) {
445 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
446 eth_data->speed = SPEED_1000;
447 eth_data->duplex = DUPLEX_FULL;
450 platform_device_register(&mv78xx0_ge10_shared);
451 platform_device_register(&mv78xx0_ge10);
455 /*****************************************************************************
457 ****************************************************************************/
458 struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
460 .dram = &mv78xx0_mbus_dram_info,
461 .shared_smi = &mv78xx0_ge00_shared,
464 static struct resource mv78xx0_ge11_shared_resources[] = {
467 .start = GE11_PHYS_BASE + 0x2000,
468 .end = GE11_PHYS_BASE + 0x3fff,
469 .flags = IORESOURCE_MEM,
473 static struct platform_device mv78xx0_ge11_shared = {
474 .name = MV643XX_ETH_SHARED_NAME,
477 .platform_data = &mv78xx0_ge11_shared_data,
480 .resource = mv78xx0_ge11_shared_resources,
483 static struct resource mv78xx0_ge11_resources[] = {
486 .start = IRQ_MV78XX0_GE11_SUM,
487 .end = IRQ_MV78XX0_GE11_SUM,
488 .flags = IORESOURCE_IRQ,
492 static struct platform_device mv78xx0_ge11 = {
493 .name = MV643XX_ETH_NAME,
496 .resource = mv78xx0_ge11_resources,
499 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
503 eth_data->shared = &mv78xx0_ge11_shared;
504 mv78xx0_ge11.dev.platform_data = eth_data;
507 * On the Z0, ge10 and ge11 are internally connected back
508 * to back, and not brought out.
510 mv78xx0_pcie_id(&dev, &rev);
511 if (dev == MV78X00_Z0_DEV_ID) {
512 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
513 eth_data->speed = SPEED_1000;
514 eth_data->duplex = DUPLEX_FULL;
517 platform_device_register(&mv78xx0_ge11_shared);
518 platform_device_register(&mv78xx0_ge11);
522 /*****************************************************************************
524 ****************************************************************************/
525 static struct resource mv78xx0_sata_resources[] = {
528 .start = SATA_PHYS_BASE,
529 .end = SATA_PHYS_BASE + 0x5000 - 1,
530 .flags = IORESOURCE_MEM,
533 .start = IRQ_MV78XX0_SATA,
534 .end = IRQ_MV78XX0_SATA,
535 .flags = IORESOURCE_IRQ,
539 static struct platform_device mv78xx0_sata = {
543 .coherent_dma_mask = 0xffffffff,
545 .num_resources = ARRAY_SIZE(mv78xx0_sata_resources),
546 .resource = mv78xx0_sata_resources,
549 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
551 sata_data->dram = &mv78xx0_mbus_dram_info;
552 mv78xx0_sata.dev.platform_data = sata_data;
553 platform_device_register(&mv78xx0_sata);
557 /*****************************************************************************
559 ****************************************************************************/
560 static struct plat_serial8250_port mv78xx0_uart0_data[] = {
562 .mapbase = UART0_PHYS_BASE,
563 .membase = (char *)UART0_VIRT_BASE,
564 .irq = IRQ_MV78XX0_UART_0,
565 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
573 static struct resource mv78xx0_uart0_resources[] = {
575 .start = UART0_PHYS_BASE,
576 .end = UART0_PHYS_BASE + 0xff,
577 .flags = IORESOURCE_MEM,
579 .start = IRQ_MV78XX0_UART_0,
580 .end = IRQ_MV78XX0_UART_0,
581 .flags = IORESOURCE_IRQ,
585 static struct platform_device mv78xx0_uart0 = {
586 .name = "serial8250",
589 .platform_data = mv78xx0_uart0_data,
591 .resource = mv78xx0_uart0_resources,
592 .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources),
595 void __init mv78xx0_uart0_init(void)
597 platform_device_register(&mv78xx0_uart0);
601 /*****************************************************************************
603 ****************************************************************************/
604 static struct plat_serial8250_port mv78xx0_uart1_data[] = {
606 .mapbase = UART1_PHYS_BASE,
607 .membase = (char *)UART1_VIRT_BASE,
608 .irq = IRQ_MV78XX0_UART_1,
609 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
617 static struct resource mv78xx0_uart1_resources[] = {
619 .start = UART1_PHYS_BASE,
620 .end = UART1_PHYS_BASE + 0xff,
621 .flags = IORESOURCE_MEM,
623 .start = IRQ_MV78XX0_UART_1,
624 .end = IRQ_MV78XX0_UART_1,
625 .flags = IORESOURCE_IRQ,
629 static struct platform_device mv78xx0_uart1 = {
630 .name = "serial8250",
633 .platform_data = mv78xx0_uart1_data,
635 .resource = mv78xx0_uart1_resources,
636 .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources),
639 void __init mv78xx0_uart1_init(void)
641 platform_device_register(&mv78xx0_uart1);
645 /*****************************************************************************
647 ****************************************************************************/
648 static struct plat_serial8250_port mv78xx0_uart2_data[] = {
650 .mapbase = UART2_PHYS_BASE,
651 .membase = (char *)UART2_VIRT_BASE,
652 .irq = IRQ_MV78XX0_UART_2,
653 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
661 static struct resource mv78xx0_uart2_resources[] = {
663 .start = UART2_PHYS_BASE,
664 .end = UART2_PHYS_BASE + 0xff,
665 .flags = IORESOURCE_MEM,
667 .start = IRQ_MV78XX0_UART_2,
668 .end = IRQ_MV78XX0_UART_2,
669 .flags = IORESOURCE_IRQ,
673 static struct platform_device mv78xx0_uart2 = {
674 .name = "serial8250",
677 .platform_data = mv78xx0_uart2_data,
679 .resource = mv78xx0_uart2_resources,
680 .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources),
683 void __init mv78xx0_uart2_init(void)
685 platform_device_register(&mv78xx0_uart2);
689 /*****************************************************************************
691 ****************************************************************************/
692 static struct plat_serial8250_port mv78xx0_uart3_data[] = {
694 .mapbase = UART3_PHYS_BASE,
695 .membase = (char *)UART3_VIRT_BASE,
696 .irq = IRQ_MV78XX0_UART_3,
697 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
705 static struct resource mv78xx0_uart3_resources[] = {
707 .start = UART3_PHYS_BASE,
708 .end = UART3_PHYS_BASE + 0xff,
709 .flags = IORESOURCE_MEM,
711 .start = IRQ_MV78XX0_UART_3,
712 .end = IRQ_MV78XX0_UART_3,
713 .flags = IORESOURCE_IRQ,
717 static struct platform_device mv78xx0_uart3 = {
718 .name = "serial8250",
721 .platform_data = mv78xx0_uart3_data,
723 .resource = mv78xx0_uart3_resources,
724 .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources),
727 void __init mv78xx0_uart3_init(void)
729 platform_device_register(&mv78xx0_uart3);
733 /*****************************************************************************
735 ****************************************************************************/
736 static void mv78xx0_timer_init(void)
738 orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
741 struct sys_timer mv78xx0_timer = {
742 .init = mv78xx0_timer_init,
746 /*****************************************************************************
748 ****************************************************************************/
749 static char * __init mv78xx0_id(void)
753 mv78xx0_pcie_id(&dev, &rev);
755 if (dev == MV78X00_Z0_DEV_ID) {
756 if (rev == MV78X00_REV_Z0)
759 return "MV78X00-Rev-Unsupported";
760 } else if (dev == MV78100_DEV_ID) {
761 if (rev == MV78100_REV_A0)
764 return "MV78100-Rev-Unsupported";
765 } else if (dev == MV78200_DEV_ID) {
766 if (rev == MV78100_REV_A0)
769 return "MV78200-Rev-Unsupported";
771 return "Device-Unknown";
775 static int __init is_l2_writethrough(void)
777 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
780 void __init mv78xx0_init(void)
788 core_index = mv78xx0_core_index();
790 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
793 printk(KERN_INFO "%s ", mv78xx0_id());
794 printk("core #%d, ", core_index);
795 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
796 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
797 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
798 printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
800 mv78xx0_setup_cpu_mbus();
802 #ifdef CONFIG_CACHE_FEROCEON_L2
803 feroceon_l2_init(is_l2_writethrough());
806 mv78xx0_ge00_shared_data.t_clk = tclk;
807 mv78xx0_ge01_shared_data.t_clk = tclk;
808 mv78xx0_ge10_shared_data.t_clk = tclk;
809 mv78xx0_ge11_shared_data.t_clk = tclk;
810 mv78xx0_uart0_data[0].uartclk = tclk;
811 mv78xx0_uart1_data[0].uartclk = tclk;
812 mv78xx0_uart2_data[0].uartclk = tclk;
813 mv78xx0_uart3_data[0].uartclk = tclk;