Merge commit 'linus/master' into HEAD
[linux-2.6] / arch / arm / mach-u300 / clock.c
1 /*
2  *
3  * arch/arm/mach-u300/clock.c
4  *
5  *
6  * Copyright (C) 2007-2009 ST-Ericsson AB
7  * License terms: GNU General Public License (GPL) version 2
8  * Define clocks in the app platform.
9  * Author: Linus Walleij <linus.walleij@stericsson.com>
10  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11  *
12  */
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/string.h>
19 #include <linux/clk.h>
20 #include <linux/mutex.h>
21 #include <linux/spinlock.h>
22 #include <linux/debugfs.h>
23 #include <linux/device.h>
24 #include <linux/init.h>
25 #include <linux/timer.h>
26 #include <linux/io.h>
27
28 #include <asm/clkdev.h>
29 #include <mach/hardware.h>
30 #include <mach/syscon.h>
31
32 #include "clock.h"
33
34 /*
35  * TODO:
36  * - move all handling of the CCR register into this file and create
37  *   a spinlock for the CCR register
38  * - switch to the clkdevice lookup mechanism that maps clocks to
39  *   device ID:s instead when it becomes available in kernel 2.6.29.
40  * - implement rate get/set for all clocks that need it.
41  */
42
43 /*
44  * Syscon clock I/O registers lock so clock requests don't collide
45  * NOTE: this is a local lock only used to lock access to clock and
46  * reset registers in syscon.
47  */
48 static DEFINE_SPINLOCK(syscon_clkreg_lock);
49 static DEFINE_SPINLOCK(syscon_resetreg_lock);
50
51 /*
52  * The clocking hierarchy currently looks like this.
53  * NOTE: the idea is NOT to show how the clocks are routed on the chip!
54  * The ideas is to show dependencies, so a clock higher up in the
55  * hierarchy has to be on in order for another clock to be on. Now,
56  * both CPU and DMA can actually be on top of the hierarchy, and that
57  * is not modeled currently. Instead we have the backbone AMBA bus on
58  * top. This bus cannot be programmed in any way but conceptually it
59  * needs to be active for the bridges and devices to transport data.
60  *
61  * Please be aware that a few clocks are hw controlled, which mean that
62  * the hw itself can turn on/off or change the rate of the clock when
63  * needed!
64  *
65  *  AMBA bus
66  *  |
67  *  +- CPU
68  *  +- NANDIF NAND Flash interface
69  *  +- SEMI Shared Memory interface
70  *  +- ISP Image Signal Processor (U335 only)
71  *  +- CDS (U335 only)
72  *  +- DMA Direct Memory Access Controller
73  *  +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
74  *  +- APEX
75  *  +- VIDEO_ENC AVE2/3 Video Encoder
76  *  +- XGAM Graphics Accelerator Controller
77  *  +- AHB
78  *  |
79  *  +- ahb:0 AHB Bridge
80  *  |  |
81  *  |  +- ahb:1 INTCON Interrupt controller
82  *  |  +- ahb:3 MSPRO  Memory Stick Pro controller
83  *  |  +- ahb:4 EMIF   External Memory interface
84  *  |
85  *  +- fast:0 FAST bridge
86  *  |  |
87  *  |  +- fast:1 MMCSD MMC/SD card reader controller
88  *  |  +- fast:2 I2S0  PCM I2S channel 0 controller
89  *  |  +- fast:3 I2S1  PCM I2S channel 1 controller
90  *  |  +- fast:4 I2C0  I2C channel 0 controller
91  *  |  +- fast:5 I2C1  I2C channel 1 controller
92  *  |  +- fast:6 SPI   SPI controller
93  *  |  +- fast:7 UART1 Secondary UART (U335 only)
94  *  |
95  *  +- slow:0 SLOW bridge
96  *     |
97  *     +- slow:1 SYSCON (not possible to control)
98  *     +- slow:2 WDOG Watchdog
99  *     +- slow:3 UART0 primary UART
100  *     +- slow:4 TIMER_APP Application timer - used in Linux
101  *     +- slow:5 KEYPAD controller
102  *     +- slow:6 GPIO controller
103  *     +- slow:7 RTC controller
104  *     +- slow:8 BT Bus Tracer (not used currently)
105  *     +- slow:9 EH Event Handler (not used currently)
106  *     +- slow:a TIMER_ACC Access style timer (not used currently)
107  *     +- slow:b PPM (U335 only, what is that?)
108  */
109
110 /*
111  * Reset control functions. We remember if a block has been
112  * taken out of reset and don't remove the reset assertion again
113  * and vice versa. Currently we only remove resets so the
114  * enablement function is defined out.
115  */
116 static void syscon_block_reset_enable(struct clk *clk)
117 {
118         u16 val;
119         unsigned long iflags;
120
121         /* Not all blocks support resetting */
122         if (!clk->res_reg || !clk->res_mask)
123                 return;
124         spin_lock_irqsave(&syscon_resetreg_lock, iflags);
125         val = readw(clk->res_reg);
126         val |= clk->res_mask;
127         writew(val, clk->res_reg);
128         spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
129         clk->reset = true;
130 }
131
132 static void syscon_block_reset_disable(struct clk *clk)
133 {
134         u16 val;
135         unsigned long iflags;
136
137         /* Not all blocks support resetting */
138         if (!clk->res_reg || !clk->res_mask)
139                 return;
140         spin_lock_irqsave(&syscon_resetreg_lock, iflags);
141         val = readw(clk->res_reg);
142         val &= ~clk->res_mask;
143         writew(val, clk->res_reg);
144         spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
145         clk->reset = false;
146 }
147
148 int __clk_get(struct clk *clk)
149 {
150         u16 val;
151
152         /* The MMC and MSPRO clocks need some special set-up */
153         if (!strcmp(clk->name, "MCLK")) {
154                 /* Set default MMC clock divisor to 18.9 MHz */
155                 writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
156                 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
157                 /* Disable the MMC feedback clock */
158                 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
159                 /* Disable MSPRO frequency */
160                 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
161                 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
162         }
163         if (!strcmp(clk->name, "MSPRO")) {
164                 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
165                 /* Disable the MMC feedback clock */
166                 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
167                 /* Enable MSPRO frequency */
168                 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
169                 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
170         }
171         return 1;
172 }
173 EXPORT_SYMBOL(__clk_get);
174
175 void __clk_put(struct clk *clk)
176 {
177 }
178 EXPORT_SYMBOL(__clk_put);
179
180 static void syscon_clk_disable(struct clk *clk)
181 {
182         unsigned long iflags;
183
184         /* Don't touch the hardware controlled clocks */
185         if (clk->hw_ctrld)
186                 return;
187
188         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
189         writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR);
190         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
191 }
192
193 static void syscon_clk_enable(struct clk *clk)
194 {
195         unsigned long iflags;
196
197         /* Don't touch the hardware controlled clocks */
198         if (clk->hw_ctrld)
199                 return;
200
201         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
202         writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER);
203         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
204 }
205
206 static u16 syscon_clk_get_rate(void)
207 {
208         u16 val;
209         unsigned long iflags;
210
211         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
212         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
213         val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
214         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
215         return val;
216 }
217
218 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
219 static void enable_i2s0_vcxo(void)
220 {
221         u16 val;
222         unsigned long iflags;
223
224         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
225         /* Set I2S0 to use the VCXO 26 MHz clock */
226         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
227         val |= U300_SYSCON_CCR_TURN_VCXO_ON;
228         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
229         val |= U300_SYSCON_CCR_I2S0_USE_VCXO;
230         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
231         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
232         val |= U300_SYSCON_CEFR_I2S0_CLK_EN;
233         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
234         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
235 }
236
237 static void enable_i2s1_vcxo(void)
238 {
239         u16 val;
240         unsigned long iflags;
241
242         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
243         /* Set I2S1 to use the VCXO 26 MHz clock */
244         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
245         val |= U300_SYSCON_CCR_TURN_VCXO_ON;
246         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
247         val |= U300_SYSCON_CCR_I2S1_USE_VCXO;
248         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
249         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
250         val |= U300_SYSCON_CEFR_I2S1_CLK_EN;
251         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
252         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
253 }
254
255 static void disable_i2s0_vcxo(void)
256 {
257         u16 val;
258         unsigned long iflags;
259
260         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
261         /* Disable I2S0 use of the VCXO 26 MHz clock */
262         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
263         val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
264         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
265         /* Deactivate VCXO if noone else is using VCXO */
266         if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
267                 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
268         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
269         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
270         val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
271         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
272         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
273 }
274
275 static void disable_i2s1_vcxo(void)
276 {
277         u16 val;
278         unsigned long iflags;
279
280         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
281         /* Disable I2S1 use of the VCXO 26 MHz clock */
282         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
283         val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
284         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
285         /* Deactivate VCXO if noone else is using VCXO */
286         if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
287                 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
288         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
289         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
290         val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
291         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
292         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
293 }
294 #endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
295
296
297 static void syscon_clk_rate_set_mclk(unsigned long rate)
298 {
299         u16 val;
300         u32 reg;
301         unsigned long iflags;
302
303         switch (rate) {
304         case 18900000:
305                 val = 0x0054;
306                 break;
307         case 20800000:
308                 val = 0x0044;
309                 break;
310         case 23100000:
311                 val = 0x0043;
312                 break;
313         case 26000000:
314                 val = 0x0033;
315                 break;
316         case 29700000:
317                 val = 0x0032;
318                 break;
319         case 34700000:
320                 val = 0x0022;
321                 break;
322         case 41600000:
323                 val = 0x0021;
324                 break;
325         case 52000000:
326                 val = 0x0011;
327                 break;
328         case 104000000:
329                 val = 0x0000;
330                 break;
331         default:
332                 printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n",
333                        rate);
334                 return;
335         }
336
337         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
338         reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
339                 ~U300_SYSCON_MMF0R_MASK;
340         writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
341         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
342 }
343
344 void syscon_clk_rate_set_cpuclk(unsigned long rate)
345 {
346         u16 val;
347         unsigned long iflags;
348
349         switch (rate) {
350         case 13000000:
351                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
352                 break;
353         case 52000000:
354                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
355                 break;
356         case 104000000:
357                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
358                 break;
359         case 208000000:
360                 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
361                 break;
362         default:
363                 return;
364         }
365         spin_lock_irqsave(&syscon_clkreg_lock, iflags);
366         val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) &
367                 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
368         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
369         spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
370 }
371 EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk);
372
373 void clk_disable(struct clk *clk)
374 {
375         unsigned long iflags;
376
377         spin_lock_irqsave(&clk->lock, iflags);
378         if (clk->usecount > 0 && !(--clk->usecount)) {
379                 /* some blocks lack clocking registers and cannot be disabled */
380                 if (clk->disable)
381                         clk->disable(clk);
382                 if (likely((u32)clk->parent))
383                         clk_disable(clk->parent);
384         }
385 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
386         if (unlikely(!strcmp(clk->name, "I2S0")))
387                 disable_i2s0_vcxo();
388         if (unlikely(!strcmp(clk->name, "I2S1")))
389                 disable_i2s1_vcxo();
390 #endif
391         spin_unlock_irqrestore(&clk->lock, iflags);
392 }
393 EXPORT_SYMBOL(clk_disable);
394
395 int clk_enable(struct clk *clk)
396 {
397         int ret = 0;
398         unsigned long iflags;
399
400         spin_lock_irqsave(&clk->lock, iflags);
401         if (clk->usecount++ == 0) {
402                 if (likely((u32)clk->parent))
403                         ret = clk_enable(clk->parent);
404
405                 if (unlikely(ret != 0))
406                         clk->usecount--;
407                 else {
408                         /* remove reset line (we never enable reset again) */
409                         syscon_block_reset_disable(clk);
410                         /* clocks without enable function are always on */
411                         if (clk->enable)
412                                 clk->enable(clk);
413 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
414                         if (unlikely(!strcmp(clk->name, "I2S0")))
415                                 enable_i2s0_vcxo();
416                         if (unlikely(!strcmp(clk->name, "I2S1")))
417                                 enable_i2s1_vcxo();
418 #endif
419                 }
420         }
421         spin_unlock_irqrestore(&clk->lock, iflags);
422         return ret;
423
424 }
425 EXPORT_SYMBOL(clk_enable);
426
427 /* Returns the clock rate in Hz */
428 static unsigned long clk_get_rate_cpuclk(struct clk *clk)
429 {
430         u16 val;
431
432         val = syscon_clk_get_rate();
433
434         switch (val) {
435         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
436         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
437                 return 13000000;
438         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
439                 return 52000000;
440         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
441                 return 104000000;
442         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
443                 return 208000000;
444         default:
445                 break;
446         }
447         return clk->rate;
448 }
449
450 static unsigned long clk_get_rate_ahb_clk(struct clk *clk)
451 {
452         u16 val;
453
454         val = syscon_clk_get_rate();
455
456         switch (val) {
457         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
458         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
459                 return 6500000;
460         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
461                 return 26000000;
462         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
463         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
464                 return 52000000;
465         default:
466                 break;
467         }
468         return clk->rate;
469
470 }
471
472 static unsigned long clk_get_rate_emif_clk(struct clk *clk)
473 {
474         u16 val;
475
476         val = syscon_clk_get_rate();
477
478         switch (val) {
479         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
480         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
481                 return 13000000;
482         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
483                 return 52000000;
484         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
485         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
486                 return 104000000;
487         default:
488                 break;
489         }
490         return clk->rate;
491
492 }
493
494 static unsigned long clk_get_rate_xgamclk(struct clk *clk)
495 {
496         u16 val;
497
498         val = syscon_clk_get_rate();
499
500         switch (val) {
501         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
502         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
503                 return 6500000;
504         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
505                 return 26000000;
506         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
507         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
508                 return 52000000;
509         default:
510                 break;
511         }
512
513         return clk->rate;
514 }
515
516 static unsigned long clk_get_rate_mclk(struct clk *clk)
517 {
518         u16 val;
519
520         val = syscon_clk_get_rate();
521
522         switch (val) {
523         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
524                 /*
525                  * Here, the 208 MHz PLL gets shut down and the always
526                  * on 13 MHz PLL used for RTC etc kicks into use
527                  * instead.
528                  */
529                 return 13000000;
530         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
531         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
532         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
533         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
534         {
535                 /*
536                  * This clock is under program control. The register is
537                  * divided in two nybbles, bit 7-4 gives cycles-1 to count
538                  * high, bit 3-0 gives cycles-1 to count low. Distribute
539                  * these with no more than 1 cycle difference between
540                  * low and high and add low and high to get the actual
541                  * divisor. The base PLL is 208 MHz. Writing 0x00 will
542                  * divide by 1 and 1 so the highest frequency possible
543                  * is 104 MHz.
544                  *
545                  * e.g. 0x54 =>
546                  * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
547                  */
548                 u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
549                         U300_SYSCON_MMF0R_MASK;
550                 switch (val) {
551                 case 0x0054:
552                         return 18900000;
553                 case 0x0044:
554                         return 20800000;
555                 case 0x0043:
556                         return 23100000;
557                 case 0x0033:
558                         return 26000000;
559                 case 0x0032:
560                         return 29700000;
561                 case 0x0022:
562                         return 34700000;
563                 case 0x0021:
564                         return 41600000;
565                 case 0x0011:
566                         return 52000000;
567                 case 0x0000:
568                         return 104000000;
569                 default:
570                         break;
571                 }
572         }
573         default:
574                 break;
575         }
576
577         return clk->rate;
578 }
579
580 static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk)
581 {
582         u16 val;
583
584         val = syscon_clk_get_rate();
585
586         switch (val) {
587         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
588         case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
589                 return 13000000;
590         case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
591         case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
592         case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
593                 return 26000000;
594         default:
595                 break;
596         }
597
598         return clk->rate;
599 }
600
601 unsigned long clk_get_rate(struct clk *clk)
602 {
603         if (clk->get_rate)
604                 return clk->get_rate(clk);
605         else
606                 return clk->rate;
607 }
608 EXPORT_SYMBOL(clk_get_rate);
609
610 static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
611 {
612         if (rate >= 18900000)
613                 return 18900000;
614         if (rate >= 20800000)
615                 return 20800000;
616         if (rate >= 23100000)
617                 return 23100000;
618         if (rate >= 26000000)
619                 return 26000000;
620         if (rate >= 29700000)
621                 return 29700000;
622         if (rate >= 34700000)
623                 return 34700000;
624         if (rate >= 41600000)
625                 return 41600000;
626         if (rate >= 52000000)
627                 return 52000000;
628         return -EINVAL;
629 }
630
631 static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
632 {
633         if (rate >= 13000000)
634                 return 13000000;
635         if (rate >= 52000000)
636                 return 52000000;
637         if (rate >= 104000000)
638                 return 104000000;
639         if (rate >= 208000000)
640                 return 208000000;
641         return -EINVAL;
642 }
643
644 /*
645  * This adjusts a requested rate to the closest exact rate
646  * a certain clock can provide. For a fixed clock it's
647  * mostly clk->rate.
648  */
649 long clk_round_rate(struct clk *clk, unsigned long rate)
650 {
651         /* TODO: get apropriate switches for EMIFCLK, AHBCLK and MCLK */
652         /* Else default to fixed value */
653
654         if (clk->round_rate) {
655                 return (long) clk->round_rate(clk, rate);
656         } else {
657                 printk(KERN_ERR "clock: Failed to round rate of %s\n",
658                        clk->name);
659         }
660         return (long) clk->rate;
661 }
662 EXPORT_SYMBOL(clk_round_rate);
663
664 static int clk_set_rate_mclk(struct clk *clk, unsigned long rate)
665 {
666         syscon_clk_rate_set_mclk(clk_round_rate(clk, rate));
667         return 0;
668 }
669
670 static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate)
671 {
672         syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate));
673         return 0;
674 }
675
676 int clk_set_rate(struct clk *clk, unsigned long rate)
677 {
678         /* TODO: set for EMIFCLK and AHBCLK */
679         /* Else assume the clock is fixed and fail */
680         if (clk->set_rate) {
681                 return clk->set_rate(clk, rate);
682         } else {
683                 printk(KERN_ERR "clock: Failed to set %s to %ld hz\n",
684                        clk->name, rate);
685                 return -EINVAL;
686         }
687 }
688 EXPORT_SYMBOL(clk_set_rate);
689
690 /*
691  * Clock definitions. The clock parents are set to respective
692  * bridge and the clock framework makes sure that the clocks have
693  * parents activated and are brought out of reset when in use.
694  *
695  * Clocks that have hw_ctrld = true are hw controlled, and the hw
696  * can by itself turn these clocks on and off.
697  * So in other words, we don't really have to care about them.
698  */
699
700 static struct clk amba_clk = {
701         .name       = "AMBA",
702         .rate       = 52000000, /* this varies! */
703         .hw_ctrld   = true,
704         .reset      = false,
705 };
706
707 /*
708  * These blocks are connected directly to the AMBA bus
709  * with no bridge.
710  */
711
712 static struct clk cpu_clk = {
713         .name       = "CPU",
714         .parent     = &amba_clk,
715         .rate       = 208000000, /* this varies! */
716         .hw_ctrld   = true,
717         .reset      = true,
718         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
719         .res_mask   = U300_SYSCON_RRR_CPU_RESET_EN,
720         .set_rate   = clk_set_rate_cpuclk,
721         .get_rate   = clk_get_rate_cpuclk,
722         .round_rate = clk_round_rate_cpuclk,
723 };
724
725 static struct clk nandif_clk = {
726         .name       = "NANDIF",
727         .parent     = &amba_clk,
728         .hw_ctrld   = false,
729         .reset      = true,
730         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
731         .res_mask   = U300_SYSCON_RRR_NANDIF_RESET_EN,
732         .clk_val    = U300_SYSCON_SBCER_NANDIF_CLK_EN,
733         .enable     = syscon_clk_enable,
734         .disable    = syscon_clk_disable,
735 };
736
737 static struct clk semi_clk = {
738         .name       = "SEMI",
739         .parent     = &amba_clk,
740         .rate       = 0, /* FIXME */
741         /* It is not possible to reset SEMI */
742         .hw_ctrld   = false,
743         .reset      = false,
744         .clk_val    = U300_SYSCON_SBCER_SEMI_CLK_EN,
745         .enable     = syscon_clk_enable,
746         .disable    = syscon_clk_disable,
747 };
748
749 #ifdef CONFIG_MACH_U300_BS335
750 static struct clk isp_clk = {
751         .name       = "ISP",
752         .parent     = &amba_clk,
753         .rate       = 0, /* FIXME */
754         .hw_ctrld   = false,
755         .reset      = true,
756         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
757         .res_mask   = U300_SYSCON_RRR_ISP_RESET_EN,
758         .clk_val    = U300_SYSCON_SBCER_ISP_CLK_EN,
759         .enable     = syscon_clk_enable,
760         .disable    = syscon_clk_disable,
761 };
762
763 static struct clk cds_clk = {
764         .name       = "CDS",
765         .parent     = &amba_clk,
766         .rate       = 0, /* FIXME */
767         .hw_ctrld   = false,
768         .reset      = true,
769         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
770         .res_mask   = U300_SYSCON_RRR_CDS_RESET_EN,
771         .clk_val    = U300_SYSCON_SBCER_CDS_CLK_EN,
772         .enable     = syscon_clk_enable,
773         .disable    = syscon_clk_disable,
774 };
775 #endif
776
777 static struct clk dma_clk = {
778         .name       = "DMA",
779         .parent     = &amba_clk,
780         .rate       = 52000000, /* this varies! */
781         .hw_ctrld   = true,
782         .reset      = true,
783         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
784         .res_mask   = U300_SYSCON_RRR_DMAC_RESET_EN,
785         .clk_val    = U300_SYSCON_SBCER_DMAC_CLK_EN,
786         .enable     = syscon_clk_enable,
787         .disable    = syscon_clk_disable,
788 };
789
790 static struct clk aaif_clk = {
791         .name       = "AAIF",
792         .parent     = &amba_clk,
793         .rate       = 52000000, /* this varies! */
794         .hw_ctrld   = true,
795         .reset      = true,
796         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
797         .res_mask   = U300_SYSCON_RRR_AAIF_RESET_EN,
798         .clk_val    = U300_SYSCON_SBCER_AAIF_CLK_EN,
799         .enable     = syscon_clk_enable,
800         .disable    = syscon_clk_disable,
801 };
802
803 static struct clk apex_clk = {
804         .name       = "APEX",
805         .parent     = &amba_clk,
806         .rate       = 0, /* FIXME */
807         .hw_ctrld   = true,
808         .reset      = true,
809         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
810         .res_mask   = U300_SYSCON_RRR_APEX_RESET_EN,
811         .clk_val    = U300_SYSCON_SBCER_APEX_CLK_EN,
812         .enable     = syscon_clk_enable,
813         .disable    = syscon_clk_disable,
814 };
815
816 static struct clk video_enc_clk = {
817         .name       = "VIDEO_ENC",
818         .parent     = &amba_clk,
819         .rate       = 208000000, /* this varies! */
820         .hw_ctrld   = false,
821         .reset      = false,
822         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
823         /* This has XGAM in the name but refers to the video encoder */
824         .res_mask   = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN,
825         .clk_val    = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN,
826         .enable     = syscon_clk_enable,
827         .disable    = syscon_clk_disable,
828 };
829
830 static struct clk xgam_clk = {
831         .name       = "XGAMCLK",
832         .parent     = &amba_clk,
833         .rate       = 52000000, /* this varies! */
834         .hw_ctrld   = false,
835         .reset      = true,
836         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
837         .res_mask   = U300_SYSCON_RRR_XGAM_RESET_EN,
838         .clk_val    = U300_SYSCON_SBCER_XGAM_CLK_EN,
839         .get_rate   = clk_get_rate_xgamclk,
840         .enable     = syscon_clk_enable,
841         .disable    = syscon_clk_disable,
842 };
843
844 /* This clock is used to activate the video encoder */
845 static struct clk ahb_clk = {
846         .name       = "AHB",
847         .parent     = &amba_clk,
848         .rate       = 52000000, /* this varies! */
849         .hw_ctrld   = false, /* This one is set to false due to HW bug */
850         .reset      = true,
851         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
852         .res_mask   = U300_SYSCON_RRR_AHB_RESET_EN,
853         .clk_val    = U300_SYSCON_SBCER_AHB_CLK_EN,
854         .enable     = syscon_clk_enable,
855         .disable    = syscon_clk_disable,
856         .get_rate   = clk_get_rate_ahb_clk,
857 };
858
859
860 /*
861  * Clocks on the AHB bridge
862  */
863
864 static struct clk ahb_subsys_clk = {
865         .name       = "AHB_SUBSYS",
866         .parent     = &amba_clk,
867         .rate       = 52000000, /* this varies! */
868         .hw_ctrld   = true,
869         .reset      = false,
870         .clk_val    = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
871         .enable     = syscon_clk_enable,
872         .disable    = syscon_clk_disable,
873         .get_rate   = clk_get_rate_ahb_clk,
874 };
875
876 static struct clk intcon_clk = {
877         .name       = "INTCON",
878         .parent     = &ahb_subsys_clk,
879         .rate       = 52000000, /* this varies! */
880         .hw_ctrld   = false,
881         .reset      = true,
882         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
883         .res_mask   = U300_SYSCON_RRR_INTCON_RESET_EN,
884         /* INTCON can be reset but not clock-gated */
885 };
886
887 static struct clk mspro_clk = {
888         .name       = "MSPRO",
889         .parent     = &ahb_subsys_clk,
890         .rate       = 0, /* FIXME */
891         .hw_ctrld   = false,
892         .reset      = true,
893         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
894         .res_mask   = U300_SYSCON_RRR_MSPRO_RESET_EN,
895         .clk_val    = U300_SYSCON_SBCER_MSPRO_CLK_EN,
896         .enable     = syscon_clk_enable,
897         .disable    = syscon_clk_disable,
898 };
899
900 static struct clk emif_clk = {
901         .name       = "EMIF",
902         .parent     = &ahb_subsys_clk,
903         .rate       = 104000000, /* this varies! */
904         .hw_ctrld   = false,
905         .reset      = true,
906         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
907         .res_mask   = U300_SYSCON_RRR_EMIF_RESET_EN,
908         .clk_val    = U300_SYSCON_SBCER_EMIF_CLK_EN,
909         .enable     = syscon_clk_enable,
910         .disable    = syscon_clk_disable,
911         .get_rate   = clk_get_rate_emif_clk,
912 };
913
914
915 /*
916  * Clocks on the FAST bridge
917  */
918 static struct clk fast_clk = {
919         .name       = "FAST_BRIDGE",
920         .parent     = &amba_clk,
921         .rate       = 13000000, /* this varies! */
922         .hw_ctrld   = true,
923         .reset      = true,
924         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
925         .res_mask   = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE,
926         .clk_val    = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
927         .enable     = syscon_clk_enable,
928         .disable    = syscon_clk_disable,
929 };
930
931 static struct clk mmcsd_clk = {
932         .name       = "MCLK",
933         .parent     = &fast_clk,
934         .rate       = 18900000, /* this varies! */
935         .hw_ctrld   = false,
936         .reset      = true,
937         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
938         .res_mask   = U300_SYSCON_RFR_MMC_RESET_ENABLE,
939         .clk_val    = U300_SYSCON_SBCER_MMC_CLK_EN,
940         .get_rate   = clk_get_rate_mclk,
941         .set_rate   = clk_set_rate_mclk,
942         .round_rate = clk_round_rate_mclk,
943         .disable    = syscon_clk_disable,
944         .enable     = syscon_clk_enable,
945 };
946
947 static struct clk i2s0_clk = {
948         .name       = "i2s0",
949         .parent     = &fast_clk,
950         .rate       = 26000000, /* this varies! */
951         .hw_ctrld   = true,
952         .reset      = true,
953         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
954         .res_mask   = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE,
955         .clk_val    = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN,
956         .enable     = syscon_clk_enable,
957         .disable    = syscon_clk_disable,
958         .get_rate   = clk_get_rate_i2s_i2c_spi,
959 };
960
961 static struct clk i2s1_clk = {
962         .name       = "i2s1",
963         .parent     = &fast_clk,
964         .rate       = 26000000, /* this varies! */
965         .hw_ctrld   = true,
966         .reset      = true,
967         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
968         .res_mask   = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE,
969         .clk_val    = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN,
970         .enable     = syscon_clk_enable,
971         .disable    = syscon_clk_disable,
972         .get_rate   = clk_get_rate_i2s_i2c_spi,
973 };
974
975 static struct clk i2c0_clk = {
976         .name       = "I2C0",
977         .parent     = &fast_clk,
978         .rate       = 26000000, /* this varies! */
979         .hw_ctrld   = false,
980         .reset      = true,
981         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
982         .res_mask   = U300_SYSCON_RFR_I2C0_RESET_ENABLE,
983         .clk_val    = U300_SYSCON_SBCER_I2C0_CLK_EN,
984         .enable     = syscon_clk_enable,
985         .disable    = syscon_clk_disable,
986         .get_rate   = clk_get_rate_i2s_i2c_spi,
987 };
988
989 static struct clk i2c1_clk = {
990         .name       = "I2C1",
991         .parent     = &fast_clk,
992         .rate       = 26000000, /* this varies! */
993         .hw_ctrld   = false,
994         .reset      = true,
995         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
996         .res_mask   = U300_SYSCON_RFR_I2C1_RESET_ENABLE,
997         .clk_val    = U300_SYSCON_SBCER_I2C1_CLK_EN,
998         .enable     = syscon_clk_enable,
999         .disable    = syscon_clk_disable,
1000         .get_rate   = clk_get_rate_i2s_i2c_spi,
1001 };
1002
1003 static struct clk spi_clk = {
1004         .name       = "SPI",
1005         .parent     = &fast_clk,
1006         .rate       = 26000000, /* this varies! */
1007         .hw_ctrld   = false,
1008         .reset      = true,
1009         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1010         .res_mask   = U300_SYSCON_RFR_SPI_RESET_ENABLE,
1011         .clk_val    = U300_SYSCON_SBCER_SPI_CLK_EN,
1012         .enable     = syscon_clk_enable,
1013         .disable    = syscon_clk_disable,
1014         .get_rate   = clk_get_rate_i2s_i2c_spi,
1015 };
1016
1017 #ifdef CONFIG_MACH_U300_BS335
1018 static struct clk uart1_clk = {
1019         .name       = "UART1",
1020         .parent     = &fast_clk,
1021         .rate       = 13000000,
1022         .hw_ctrld   = false,
1023         .reset      = true,
1024         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1025         .res_mask   = U300_SYSCON_RFR_UART1_RESET_ENABLE,
1026         .clk_val    = U300_SYSCON_SBCER_UART1_CLK_EN,
1027         .enable     = syscon_clk_enable,
1028         .disable    = syscon_clk_disable,
1029 };
1030 #endif
1031
1032
1033 /*
1034  * Clocks on the SLOW bridge
1035  */
1036 static struct clk slow_clk = {
1037         .name       = "SLOW_BRIDGE",
1038         .parent     = &amba_clk,
1039         .rate       = 13000000,
1040         .hw_ctrld   = true,
1041         .reset      = true,
1042         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1043         .res_mask   = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN,
1044         .clk_val    = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
1045         .enable     = syscon_clk_enable,
1046         .disable    = syscon_clk_disable,
1047 };
1048
1049 /* TODO: implement SYSCON clock? */
1050
1051 static struct clk wdog_clk = {
1052         .name       = "WDOG",
1053         .parent     = &slow_clk,
1054         .hw_ctrld   = false,
1055         .rate       = 32768,
1056         .reset      = false,
1057         /* This is always on, cannot be enabled/disabled or reset */
1058 };
1059
1060 /* This one is hardwired to PLL13 */
1061 static struct clk uart_clk = {
1062         .name       = "UARTCLK",
1063         .parent     = &slow_clk,
1064         .rate       = 13000000,
1065         .hw_ctrld   = false,
1066         .reset      = true,
1067         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1068         .res_mask   = U300_SYSCON_RSR_UART_RESET_EN,
1069         .clk_val    = U300_SYSCON_SBCER_UART_CLK_EN,
1070         .enable     = syscon_clk_enable,
1071         .disable    = syscon_clk_disable,
1072 };
1073
1074 static struct clk keypad_clk = {
1075         .name       = "KEYPAD",
1076         .parent     = &slow_clk,
1077         .rate       = 32768,
1078         .hw_ctrld   = false,
1079         .reset      = true,
1080         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1081         .res_mask   = U300_SYSCON_RSR_KEYPAD_RESET_EN,
1082         .clk_val    = U300_SYSCON_SBCER_KEYPAD_CLK_EN,
1083         .enable     = syscon_clk_enable,
1084         .disable    = syscon_clk_disable,
1085 };
1086
1087 static struct clk gpio_clk = {
1088         .name       = "GPIO",
1089         .parent     = &slow_clk,
1090         .rate       = 13000000,
1091         .hw_ctrld   = true,
1092         .reset      = true,
1093         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1094         .res_mask   = U300_SYSCON_RSR_GPIO_RESET_EN,
1095         .clk_val    = U300_SYSCON_SBCER_GPIO_CLK_EN,
1096         .enable     = syscon_clk_enable,
1097         .disable    = syscon_clk_disable,
1098 };
1099
1100 static struct clk rtc_clk = {
1101         .name       = "RTC",
1102         .parent     = &slow_clk,
1103         .rate       = 32768,
1104         .hw_ctrld   = true,
1105         .reset      = true,
1106         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1107         .res_mask   = U300_SYSCON_RSR_RTC_RESET_EN,
1108         /* This clock is always on, cannot be enabled/disabled */
1109 };
1110
1111 static struct clk bustr_clk = {
1112         .name       = "BUSTR",
1113         .parent     = &slow_clk,
1114         .rate       = 13000000,
1115         .hw_ctrld   = true,
1116         .reset      = true,
1117         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1118         .res_mask   = U300_SYSCON_RSR_BTR_RESET_EN,
1119         .clk_val    = U300_SYSCON_SBCER_BTR_CLK_EN,
1120         .enable     = syscon_clk_enable,
1121         .disable    = syscon_clk_disable,
1122 };
1123
1124 static struct clk evhist_clk = {
1125         .name       = "EVHIST",
1126         .parent     = &slow_clk,
1127         .rate       = 13000000,
1128         .hw_ctrld   = true,
1129         .reset      = true,
1130         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1131         .res_mask   = U300_SYSCON_RSR_EH_RESET_EN,
1132         .clk_val    = U300_SYSCON_SBCER_EH_CLK_EN,
1133         .enable     = syscon_clk_enable,
1134         .disable    = syscon_clk_disable,
1135 };
1136
1137 static struct clk timer_clk = {
1138         .name       = "TIMER",
1139         .parent     = &slow_clk,
1140         .rate       = 13000000,
1141         .hw_ctrld   = true,
1142         .reset      = true,
1143         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1144         .res_mask   = U300_SYSCON_RSR_ACC_TMR_RESET_EN,
1145         .clk_val    = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
1146         .enable     = syscon_clk_enable,
1147         .disable    = syscon_clk_disable,
1148 };
1149
1150 static struct clk app_timer_clk = {
1151         .name       = "TIMER_APP",
1152         .parent     = &slow_clk,
1153         .rate       = 13000000,
1154         .hw_ctrld   = true,
1155         .reset      = true,
1156         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1157         .res_mask   = U300_SYSCON_RSR_APP_TMR_RESET_EN,
1158         .clk_val    = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
1159         .enable     = syscon_clk_enable,
1160         .disable    = syscon_clk_disable,
1161 };
1162
1163 #ifdef CONFIG_MACH_U300_BS335
1164 static struct clk ppm_clk = {
1165         .name       = "PPM",
1166         .parent     = &slow_clk,
1167         .rate       = 0, /* FIXME */
1168         .hw_ctrld   = true, /* TODO: Look up if it is hw ctrld or not */
1169         .reset      = true,
1170         .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1171         .res_mask   = U300_SYSCON_RSR_PPM_RESET_EN,
1172         .clk_val    = U300_SYSCON_SBCER_PPM_CLK_EN,
1173         .enable     = syscon_clk_enable,
1174         .disable    = syscon_clk_disable,
1175 };
1176 #endif
1177
1178 #define DEF_LOOKUP(devid, clkref)               \
1179         {                                       \
1180         .dev_id = devid,                        \
1181         .clk = clkref,                          \
1182         }
1183
1184 /*
1185  * Here we only define clocks that are meaningful to
1186  * look up through clockdevice.
1187  */
1188 static struct clk_lookup lookups[] = {
1189         /* Connected directly to the AMBA bus */
1190         DEF_LOOKUP("amba", &amba_clk),
1191         DEF_LOOKUP("cpu", &cpu_clk),
1192         DEF_LOOKUP("nandif", &nandif_clk),
1193         DEF_LOOKUP("semi", &semi_clk),
1194 #ifdef CONFIG_MACH_U300_BS335
1195         DEF_LOOKUP("isp", &isp_clk),
1196         DEF_LOOKUP("cds", &cds_clk),
1197 #endif
1198         DEF_LOOKUP("dma", &dma_clk),
1199         DEF_LOOKUP("aaif", &aaif_clk),
1200         DEF_LOOKUP("apex", &apex_clk),
1201         DEF_LOOKUP("video_enc", &video_enc_clk),
1202         DEF_LOOKUP("xgam", &xgam_clk),
1203         DEF_LOOKUP("ahb", &ahb_clk),
1204         /* AHB bridge clocks */
1205         DEF_LOOKUP("ahb", &ahb_subsys_clk),
1206         DEF_LOOKUP("intcon", &intcon_clk),
1207         DEF_LOOKUP("mspro", &mspro_clk),
1208         DEF_LOOKUP("pl172", &emif_clk),
1209         /* FAST bridge clocks */
1210         DEF_LOOKUP("fast", &fast_clk),
1211         DEF_LOOKUP("mmci", &mmcsd_clk),
1212         /*
1213          * The .0 and .1 identifiers on these comes from the platform device
1214          * .id field and are assigned when the platform devices are registered.
1215          */
1216         DEF_LOOKUP("i2s.0", &i2s0_clk),
1217         DEF_LOOKUP("i2s.1", &i2s1_clk),
1218         DEF_LOOKUP("stddci2c.0", &i2c0_clk),
1219         DEF_LOOKUP("stddci2c.1", &i2c1_clk),
1220         DEF_LOOKUP("pl022", &spi_clk),
1221 #ifdef CONFIG_MACH_U300_BS335
1222         DEF_LOOKUP("uart1", &uart1_clk),
1223 #endif
1224         /* SLOW bridge clocks */
1225         DEF_LOOKUP("slow", &slow_clk),
1226         DEF_LOOKUP("wdog", &wdog_clk),
1227         DEF_LOOKUP("uart0", &uart_clk),
1228         DEF_LOOKUP("apptimer", &app_timer_clk),
1229         DEF_LOOKUP("keypad", &keypad_clk),
1230         DEF_LOOKUP("u300-gpio", &gpio_clk),
1231         DEF_LOOKUP("rtc0", &rtc_clk),
1232         DEF_LOOKUP("bustr", &bustr_clk),
1233         DEF_LOOKUP("evhist", &evhist_clk),
1234         DEF_LOOKUP("timer", &timer_clk),
1235 #ifdef CONFIG_MACH_U300_BS335
1236         DEF_LOOKUP("ppm", &ppm_clk),
1237 #endif
1238 };
1239
1240 static void __init clk_register(void)
1241 {
1242         int i;
1243
1244         /* Register the lookups */
1245         for (i = 0; i < ARRAY_SIZE(lookups); i++)
1246                 clkdev_add(&lookups[i]);
1247 }
1248
1249 /*
1250  * These are the clocks for cells registered as primecell drivers
1251  * on the AMBA bus. These must be on during AMBA device registration
1252  * since the bus probe will attempt to read magic configuration
1253  * registers for these devices. If they are deactivated these probes
1254  * will fail.
1255  *
1256  *
1257  * Please note that on emif, both RAM and NAND is connected in dual
1258  * RAM phones. On single RAM phones, ram is on semi and NAND on emif.
1259  *
1260  */
1261 void u300_clock_primecells(void)
1262 {
1263         clk_enable(&intcon_clk);
1264         clk_enable(&uart_clk);
1265 #ifdef CONFIG_MACH_U300_BS335
1266         clk_enable(&uart1_clk);
1267 #endif
1268         clk_enable(&spi_clk);
1269
1270         clk_enable(&mmcsd_clk);
1271
1272 }
1273 EXPORT_SYMBOL(u300_clock_primecells);
1274
1275 void u300_unclock_primecells(void)
1276 {
1277
1278         clk_disable(&intcon_clk);
1279         clk_disable(&uart_clk);
1280 #ifdef CONFIG_MACH_U300_BS335
1281         clk_disable(&uart1_clk);
1282 #endif
1283         clk_disable(&spi_clk);
1284         clk_disable(&mmcsd_clk);
1285
1286 }
1287 EXPORT_SYMBOL(u300_unclock_primecells);
1288
1289 /*
1290  * The interrupt controller is enabled before the clock API is registered.
1291  */
1292 void u300_enable_intcon_clock(void)
1293 {
1294         clk_enable(&intcon_clk);
1295 }
1296 EXPORT_SYMBOL(u300_enable_intcon_clock);
1297
1298 /*
1299  * The timer is enabled before the clock API is registered.
1300  */
1301 void u300_enable_timer_clock(void)
1302 {
1303         clk_enable(&app_timer_clk);
1304 }
1305 EXPORT_SYMBOL(u300_enable_timer_clock);
1306
1307 #if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
1308 /*
1309  * The following makes it possible to view the status (especially
1310  * reference count and reset status) for the clocks in the platform
1311  * by looking into the special file <debugfs>/u300_clocks
1312  */
1313
1314 /* A list of all clocks in the platform */
1315 static struct clk *clks[] = {
1316         /* Top node clock for the AMBA bus */
1317         &amba_clk,
1318         /* Connected directly to the AMBA bus */
1319         &cpu_clk,
1320         &nandif_clk,
1321         &semi_clk,
1322 #ifdef CONFIG_MACH_U300_BS335
1323         &isp_clk,
1324         &cds_clk,
1325 #endif
1326         &dma_clk,
1327         &aaif_clk,
1328         &apex_clk,
1329         &video_enc_clk,
1330         &xgam_clk,
1331         &ahb_clk,
1332
1333         /* AHB bridge clocks */
1334         &ahb_subsys_clk,
1335         &intcon_clk,
1336         &mspro_clk,
1337         &emif_clk,
1338         /* FAST bridge clocks */
1339         &fast_clk,
1340         &mmcsd_clk,
1341         &i2s0_clk,
1342         &i2s1_clk,
1343         &i2c0_clk,
1344         &i2c1_clk,
1345         &spi_clk,
1346 #ifdef CONFIG_MACH_U300_BS335
1347         &uart1_clk,
1348 #endif
1349         /* SLOW bridge clocks */
1350         &slow_clk,
1351         &wdog_clk,
1352         &uart_clk,
1353         &app_timer_clk,
1354         &keypad_clk,
1355         &gpio_clk,
1356         &rtc_clk,
1357         &bustr_clk,
1358         &evhist_clk,
1359         &timer_clk,
1360 #ifdef CONFIG_MACH_U300_BS335
1361         &ppm_clk,
1362 #endif
1363 };
1364
1365 static int u300_clocks_show(struct seq_file *s, void *data)
1366 {
1367         struct clk *clk;
1368         int i;
1369
1370         seq_printf(s, "CLOCK           DEVICE          RESET STATE\t" \
1371                    "ACTIVE\tUSERS\tHW CTRL FREQ\n");
1372         seq_printf(s, "---------------------------------------------" \
1373                    "-----------------------------------------\n");
1374         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1375                 clk = clks[i];
1376                 if (clk != ERR_PTR(-ENOENT)) {
1377                         /* Format clock and device name nicely */
1378                         char cdp[33];
1379                         int chars;
1380
1381                         chars = snprintf(&cdp[0], 17, "%s", clk->name);
1382                         while (chars < 16) {
1383                                 cdp[chars] = ' ';
1384                                 chars++;
1385                         }
1386                         chars = snprintf(&cdp[16], 17, "%s", clk->dev ?
1387                                          dev_name(clk->dev) : "N/A");
1388                         while (chars < 16) {
1389                                 cdp[chars+16] = ' ';
1390                                 chars++;
1391                         }
1392                         cdp[32] = '\0';
1393                         if (clk->get_rate)
1394                                 seq_printf(s,
1395                                            "%s%s\t%s\t%d\t%s\t%lu Hz\n",
1396                                            &cdp[0],
1397                                            clk->reset ?
1398                                            "ASSERTED" : "RELEASED",
1399                                            clk->usecount ? "ON" : "OFF",
1400                                            clk->usecount,
1401                                            clk->hw_ctrld  ? "YES" : "NO ",
1402                                            clk->get_rate(clk));
1403                         else
1404                                 seq_printf(s,
1405                                            "%s%s\t%s\t%d\t%s\t" \
1406                                            "(unknown rate)\n",
1407                                            &cdp[0],
1408                                            clk->reset ?
1409                                            "ASSERTED" : "RELEASED",
1410                                            clk->usecount ? "ON" : "OFF",
1411                                            clk->usecount,
1412                                            clk->hw_ctrld  ? "YES" : "NO ");
1413                 }
1414         }
1415         return 0;
1416 }
1417
1418 static int u300_clocks_open(struct inode *inode, struct file *file)
1419 {
1420         return single_open(file, u300_clocks_show, NULL);
1421 }
1422
1423 static const struct file_operations u300_clocks_operations = {
1424         .open           = u300_clocks_open,
1425         .read           = seq_read,
1426         .llseek         = seq_lseek,
1427         .release        = single_release,
1428 };
1429
1430 static void init_clk_read_procfs(void)
1431 {
1432         /* Expose a simple debugfs interface to view all clocks */
1433         (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO,
1434                                    NULL, NULL, &u300_clocks_operations);
1435 }
1436 #else
1437 static inline void init_clk_read_procfs(void)
1438 {
1439 }
1440 #endif
1441
1442 static int __init u300_clock_init(void)
1443 {
1444         u16 val;
1445
1446         /*
1447          * FIXME: shall all this powermanagement stuff really live here???
1448          */
1449
1450         /* Set system to run at PLL208, max performance, a known state. */
1451         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1452         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1453         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1454         /* Wait for the PLL208 to lock if not locked in yet */
1455         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1456                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1457
1458         /* Power management enable */
1459         val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1460         val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
1461         writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1462
1463         clk_register();
1464
1465         init_clk_read_procfs();
1466
1467         /*
1468          * Some of these may be on when we boot the system so make sure they
1469          * are turned OFF.
1470          */
1471         syscon_block_reset_enable(&timer_clk);
1472         timer_clk.disable(&timer_clk);
1473
1474         /*
1475          * These shall be turned on by default when we boot the system
1476          * so make sure they are ON. (Adding CPU here is a bit too much.)
1477          * These clocks will be claimed by drivers later.
1478          */
1479         syscon_block_reset_disable(&semi_clk);
1480         syscon_block_reset_disable(&emif_clk);
1481         semi_clk.enable(&semi_clk);
1482         emif_clk.enable(&emif_clk);
1483
1484         return 0;
1485 }
1486 /* initialize clocking early to be available later in the boot */
1487 core_initcall(u300_clock_init);