git.oblomov.eu Git - linux-2.6/blob - arch/mips/sibyte/sb1250/irq.c

   1 /*
   2  * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/linkage.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/smp.h>
  24 #include <linux/mm.h>
  25 #include <linux/slab.h>
  26 #include <linux/kernel_stat.h>
  27
  28 #include <asm/errno.h>
  29 #include <asm/signal.h>
  30 #include <asm/system.h>
  31 #include <asm/time.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/sibyte/sb1250_regs.h>
  35 #include <asm/sibyte/sb1250_int.h>
  36 #include <asm/sibyte/sb1250_uart.h>
  37 #include <asm/sibyte/sb1250_scd.h>
  38 #include <asm/sibyte/sb1250.h>
  39
  40 /*
  41  * These are the routines that handle all the low level interrupt stuff.
  42  * Actions handled here are: initialization of the interrupt map, requesting of
  43  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  44  * for interrupt lines
  45  */
  46
  47
  48 static void end_sb1250_irq(unsigned int irq);
  49 static void enable_sb1250_irq(unsigned int irq);
  50 static void disable_sb1250_irq(unsigned int irq);
  51 static void ack_sb1250_irq(unsigned int irq);
  52 #ifdef CONFIG_SMP
  53 static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask);
  54 #endif
  55
  56 #ifdef CONFIG_SIBYTE_HAS_LDT
  57 extern unsigned long ldt_eoi_space;
  58 #endif
  59
  60 static struct irq_chip sb1250_irq_type = {
  61         .name = "SB1250-IMR",
  62         .ack = ack_sb1250_irq,
  63         .mask = disable_sb1250_irq,
  64         .mask_ack = ack_sb1250_irq,
  65         .unmask = enable_sb1250_irq,
  66         .end = end_sb1250_irq,
  67 #ifdef CONFIG_SMP
  68         .set_affinity = sb1250_set_affinity
  69 #endif
  70 };
  71
  72 /* Store the CPU id (not the logical number) */
  73 int sb1250_irq_owner[SB1250_NR_IRQS];
  74
  75 DEFINE_SPINLOCK(sb1250_imr_lock);
  76
  77 void sb1250_mask_irq(int cpu, int irq)
  78 {
  79         unsigned long flags;
  80         u64 cur_ints;
  81
  82         spin_lock_irqsave(&sb1250_imr_lock, flags);
  83         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
  84                                         R_IMR_INTERRUPT_MASK));
  85         cur_ints |= (((u64) 1) << irq);
  86         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
  87                                         R_IMR_INTERRUPT_MASK));
  88         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
  89 }
  90
  91 void sb1250_unmask_irq(int cpu, int irq)
  92 {
  93         unsigned long flags;
  94         u64 cur_ints;
  95
  96         spin_lock_irqsave(&sb1250_imr_lock, flags);
  97         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
  98                                         R_IMR_INTERRUPT_MASK));
  99         cur_ints &= ~(((u64) 1) << irq);
 100         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 101                                         R_IMR_INTERRUPT_MASK));
 102         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 103 }
 104
 105 #ifdef CONFIG_SMP
 106 static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
 107 {
 108         int i = 0, old_cpu, cpu, int_on;
 109         u64 cur_ints;
 110         unsigned long flags;
 111
 112         i = cpumask_first(mask);
 113
 114         if (cpumask_weight(mask) > 1) {
 115                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
 116                 return;
 117         }
 118
 119         /* Convert logical CPU to physical CPU */
 120         cpu = cpu_logical_map(i);
 121
 122         /* Protect against other affinity changers and IMR manipulation */
 123         spin_lock_irqsave(&sb1250_imr_lock, flags);
 124
 125         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 126         old_cpu = sb1250_irq_owner[irq];
 127         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
 128                                         R_IMR_INTERRUPT_MASK));
 129         int_on = !(cur_ints & (((u64) 1) << irq));
 130         if (int_on) {
 131                 /* If it was on, mask it */
 132                 cur_ints |= (((u64) 1) << irq);
 133                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
 134                                         R_IMR_INTERRUPT_MASK));
 135         }
 136         sb1250_irq_owner[irq] = cpu;
 137         if (int_on) {
 138                 /* unmask for the new CPU */
 139                 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 140                                         R_IMR_INTERRUPT_MASK));
 141                 cur_ints &= ~(((u64) 1) << irq);
 142                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 143                                         R_IMR_INTERRUPT_MASK));
 144         }
 145         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 146 }
 147 #endif
 148
 149 /*****************************************************************************/
 150
 151 static void disable_sb1250_irq(unsigned int irq)
 152 {
 153         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 154 }
 155
 156 static void enable_sb1250_irq(unsigned int irq)
 157 {
 158         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 159 }
 160
 161
 162 static void ack_sb1250_irq(unsigned int irq)
 163 {
 164 #ifdef CONFIG_SIBYTE_HAS_LDT
 165         u64 pending;
 166
 167         /*
 168          * If the interrupt was an HT interrupt, now is the time to
 169          * clear it.  NOTE: we assume the HT bridge was set up to
 170          * deliver the interrupts to all CPUs (which makes affinity
 171          * changing easier for us)
 172          */
 173         pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
 174                                                     R_IMR_LDT_INTERRUPT)));
 175         pending &= ((u64)1 << (irq));
 176         if (pending) {
 177                 int i;
 178                 for (i=0; i<NR_CPUS; i++) {
 179                         int cpu;
 180 #ifdef CONFIG_SMP
 181                         cpu = cpu_logical_map(i);
 182 #else
 183                         cpu = i;
 184 #endif
 185                         /*
 186                          * Clear for all CPUs so an affinity switch
 187                          * doesn't find an old status
 188                          */
 189                         __raw_writeq(pending,
 190                                      IOADDR(A_IMR_REGISTER(cpu,
 191                                                 R_IMR_LDT_INTERRUPT_CLR)));
 192                 }
 193
 194                 /*
 195                  * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 196                  * Pass 2, the LDT world may be edge-triggered, but
 197                  * this EOI shouldn't hurt.  If they are
 198                  * level-sensitive, the EOI is required.
 199                  */
 200                 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
 201         }
 202 #endif
 203         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 204 }
 205
 206
 207 static void end_sb1250_irq(unsigned int irq)
 208 {
 209         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 210                 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 211         }
 212 }
 213
 214
 215 void __init init_sb1250_irqs(void)
 216 {
 217         int i;
 218
 219         for (i = 0; i < SB1250_NR_IRQS; i++) {
 220                 set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
 221                 sb1250_irq_owner[i] = 0;
 222         }
 223 }
 224
 225
 226 /*
 227  *  arch_init_irq is called early in the boot sequence from init/main.c via
 228  *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 229  *  installing the handler that will be responsible for dispatching interrupts
 230  *  to the "right" place.
 231  */
 232 /*
 233  * For now, map all interrupts to IP[2].  We could save
 234  * some cycles by parceling out system interrupts to different
 235  * IP lines, but keep it simple for bringup.  We'll also direct
 236  * all interrupts to a single CPU; we should probably route
 237  * PCI and LDT to one cpu and everything else to the other
 238  * to balance the load a bit.
 239  *
 240  * On the second cpu, everything is set to IP5, which is
 241  * ignored, EXCEPT the mailbox interrupt.  That one is
 242  * set to IP[2] so it is handled.  This is needed so we
 243  * can do cross-cpu function calls, as requred by SMP
 244  */
 245
 246 #define IMR_IP2_VAL     K_INT_MAP_I0
 247 #define IMR_IP3_VAL     K_INT_MAP_I1
 248 #define IMR_IP4_VAL     K_INT_MAP_I2
 249 #define IMR_IP5_VAL     K_INT_MAP_I3
 250 #define IMR_IP6_VAL     K_INT_MAP_I4
 251
 252 void __init arch_init_irq(void)
 253 {
 254
 255         unsigned int i;
 256         u64 tmp;
 257         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 258                 STATUSF_IP1 | STATUSF_IP0;
 259
 260         /* Default everything to IP2 */
 261         for (i = 0; i < SB1250_NR_IRQS; i++) {  /* was I0 */
 262                 __raw_writeq(IMR_IP2_VAL,
 263                              IOADDR(A_IMR_REGISTER(0,
 264                                                    R_IMR_INTERRUPT_MAP_BASE) +
 265                                     (i << 3)));
 266                 __raw_writeq(IMR_IP2_VAL,
 267                              IOADDR(A_IMR_REGISTER(1,
 268                                                    R_IMR_INTERRUPT_MAP_BASE) +
 269                                     (i << 3)));
 270         }
 271
 272         init_sb1250_irqs();
 273
 274         /*
 275          * Map the high 16 bits of the mailbox registers to IP[3], for
 276          * inter-cpu messages
 277          */
 278         /* Was I1 */
 279         __raw_writeq(IMR_IP3_VAL,
 280                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 281                             (K_INT_MBOX_0 << 3)));
 282         __raw_writeq(IMR_IP3_VAL,
 283                      IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
 284                             (K_INT_MBOX_0 << 3)));
 285
 286         /* Clear the mailboxes.  The firmware may leave them dirty */
 287         __raw_writeq(0xffffffffffffffffULL,
 288                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
 289         __raw_writeq(0xffffffffffffffffULL,
 290                      IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
 291
 292         /* Mask everything except the mailbox registers for both cpus */
 293         tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
 294         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
 295         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
 296
 297         /*
 298          * Note that the timer interrupts are also mapped, but this is
 299          * done in sb1250_time_init().  Also, the profiling driver
 300          * does its own management of IP7.
 301          */
 302
 303         /* Enable necessary IPs, disable the rest */
 304         change_c0_status(ST0_IM, imask);
 305 }
 306
 307 extern void sb1250_mailbox_interrupt(void);
 308
 309 static inline void dispatch_ip2(void)
 310 {
 311         unsigned int cpu = smp_processor_id();
 312         unsigned long long mask;
 313
 314         /*
 315          * Default...we've hit an IP[2] interrupt, which means we've got to
 316          * check the 1250 interrupt registers to figure out what to do.  Need
 317          * to detect which CPU we're on, now that smp_affinity is supported.
 318          */
 319         mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
 320                                   R_IMR_INTERRUPT_STATUS_BASE)));
 321         if (mask)
 322                 do_IRQ(fls64(mask) - 1);
 323 }
 324
 325 asmlinkage void plat_irq_dispatch(void)
 326 {
 327         unsigned int cpu = smp_processor_id();
 328         unsigned int pending;
 329
 330         /*
 331          * What a pain. We have to be really careful saving the upper 32 bits
 332          * of any * register across function calls if we don't want them
 333          * trashed--since were running in -o32, the calling routing never saves
 334          * the full 64 bits of a register across a function call.  Being the
 335          * interrupt handler, we're guaranteed that interrupts are disabled
 336          * during this code so we don't have to worry about random interrupts
 337          * blasting the high 32 bits.
 338          */
 339
 340         pending = read_c0_cause() & read_c0_status() & ST0_IM;
 341
 342         if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
 343                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
 344         else if (pending & CAUSEF_IP4)
 345                 do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */
 346
 347 #ifdef CONFIG_SMP
 348         else if (pending & CAUSEF_IP3)
 349                 sb1250_mailbox_interrupt();
 350 #endif
 351
 352         else if (pending & CAUSEF_IP2)
 353                 dispatch_ip2();
 354         else
 355                 spurious_interrupt();
 356 }