git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/wireless.h>
  35 #include <net/mac80211.h>
  36 #include <linux/etherdevice.h>
  37 #include <asm/unaligned.h>
  38
  39 #include "iwl-eeprom.h"
  40 #include "iwl-dev.h"
  41 #include "iwl-core.h"
  42 #include "iwl-io.h"
  43 #include "iwl-sta.h"
  44 #include "iwl-helpers.h"
  45 #include "iwl-5000-hw.h"
  46
  47 /* Highest firmware API version supported */
  48 #define IWL5000_UCODE_API_MAX 1
  49 #define IWL5150_UCODE_API_MAX 1
  50
  51 /* Lowest firmware API version supported */
  52 #define IWL5000_UCODE_API_MIN 1
  53 #define IWL5150_UCODE_API_MIN 1
  54
  55 #define IWL5000_FW_PRE "iwlwifi-5000-"
  56 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
  57 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
  58
  59 #define IWL5150_FW_PRE "iwlwifi-5150-"
  60 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
  61 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
  62
  63 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  64         IWL_TX_FIFO_AC3,
  65         IWL_TX_FIFO_AC2,
  66         IWL_TX_FIFO_AC1,
  67         IWL_TX_FIFO_AC0,
  68         IWL50_CMD_FIFO_NUM,
  69         IWL_TX_FIFO_HCCA_1,
  70         IWL_TX_FIFO_HCCA_2
  71 };
  72
  73 /* FIXME: same implementation as 4965 */
  74 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
  75 {
  76         int ret = 0;
  77         unsigned long flags;
  78
  79         spin_lock_irqsave(&priv->lock, flags);
  80
  81         /* set stop master bit */
  82         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  83
  84         ret = iwl_poll_bit(priv, CSR_RESET,
  85                                   CSR_RESET_REG_FLAG_MASTER_DISABLED,
  86                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  87         if (ret < 0)
  88                 goto out;
  89
  90 out:
  91         spin_unlock_irqrestore(&priv->lock, flags);
  92         IWL_DEBUG_INFO("stop master\n");
  93
  94         return ret;
  95 }
  96
  97
  98 static int iwl5000_apm_init(struct iwl_priv *priv)
  99 {
 100         int ret = 0;
 101
 102         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 103                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 104
 105         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
 106         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 107                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 108
 109         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 110         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 111
 112         /* enable HAP INTA to move device L1a -> L0s */
 113         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 114                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 115
 116         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 117
 118         /* set "initialization complete" bit to move adapter
 119          * D0U* --> D0A* state */
 120         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 121
 122         /* wait for clock stabilization */
 123         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 124                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 125                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 126         if (ret < 0) {
 127                 IWL_DEBUG_INFO("Failed to init the card\n");
 128                 return ret;
 129         }
 130
 131         ret = iwl_grab_nic_access(priv);
 132         if (ret)
 133                 return ret;
 134
 135         /* enable DMA */
 136         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 137
 138         udelay(20);
 139
 140         /* disable L1-Active */
 141         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 142                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 143
 144         iwl_release_nic_access(priv);
 145
 146         return ret;
 147 }
 148
 149 /* FIXME: this is identical to 4965 */
 150 static void iwl5000_apm_stop(struct iwl_priv *priv)
 151 {
 152         unsigned long flags;
 153
 154         iwl5000_apm_stop_master(priv);
 155
 156         spin_lock_irqsave(&priv->lock, flags);
 157
 158         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 159
 160         udelay(10);
 161
 162         /* clear "init complete"  move adapter D0A* --> D0U state */
 163         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 164
 165         spin_unlock_irqrestore(&priv->lock, flags);
 166 }
 167
 168
 169 static int iwl5000_apm_reset(struct iwl_priv *priv)
 170 {
 171         int ret = 0;
 172         unsigned long flags;
 173
 174         iwl5000_apm_stop_master(priv);
 175
 176         spin_lock_irqsave(&priv->lock, flags);
 177
 178         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 179
 180         udelay(10);
 181
 182
 183         /* FIXME: put here L1A -L0S w/a */
 184
 185         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 186
 187         /* set "initialization complete" bit to move adapter
 188          * D0U* --> D0A* state */
 189         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 190
 191         /* wait for clock stabilization */
 192         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 193                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 194                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 195         if (ret < 0) {
 196                 IWL_DEBUG_INFO("Failed to init the card\n");
 197                 goto out;
 198         }
 199
 200         ret = iwl_grab_nic_access(priv);
 201         if (ret)
 202                 goto out;
 203
 204         /* enable DMA */
 205         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 206
 207         udelay(20);
 208
 209         /* disable L1-Active */
 210         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 211                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 212
 213         iwl_release_nic_access(priv);
 214
 215 out:
 216         spin_unlock_irqrestore(&priv->lock, flags);
 217
 218         return ret;
 219 }
 220
 221
 222 static void iwl5000_nic_config(struct iwl_priv *priv)
 223 {
 224         unsigned long flags;
 225         u16 radio_cfg;
 226         u16 link;
 227
 228         spin_lock_irqsave(&priv->lock, flags);
 229
 230         pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
 231
 232         /* L1 is enabled by BIOS */
 233         if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
 234                 /* disable L0S disabled L1A enabled */
 235                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 236         else
 237                 /* L0S enabled L1A disabled */
 238                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 239
 240         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 241
 242         /* write radio config values to register */
 243         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 244                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 245                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 246                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 247                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 248
 249         /* set CSR_HW_CONFIG_REG for uCode use */
 250         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 251                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 252                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 253
 254         /* W/A : NIC is stuck in a reset state after Early PCIe power off
 255          * (PCIe power is lost before PERST# is asserted),
 256          * causing ME FW to lose ownership and not being able to obtain it back.
 257          */
 258         iwl_grab_nic_access(priv);
 259         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 260                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 261                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 262         iwl_release_nic_access(priv);
 263
 264         spin_unlock_irqrestore(&priv->lock, flags);
 265 }
 266
 267
 268
 269 /*
 270  * EEPROM
 271  */
 272 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 273 {
 274         u16 offset = 0;
 275
 276         if ((address & INDIRECT_ADDRESS) == 0)
 277                 return address;
 278
 279         switch (address & INDIRECT_TYPE_MSK) {
 280         case INDIRECT_HOST:
 281                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 282                 break;
 283         case INDIRECT_GENERAL:
 284                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 285                 break;
 286         case INDIRECT_REGULATORY:
 287                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 288                 break;
 289         case INDIRECT_CALIBRATION:
 290                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 291                 break;
 292         case INDIRECT_PROCESS_ADJST:
 293                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 294                 break;
 295         case INDIRECT_OTHERS:
 296                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 297                 break;
 298         default:
 299                 IWL_ERROR("illegal indirect type: 0x%X\n",
 300                 address & INDIRECT_TYPE_MSK);
 301                 break;
 302         }
 303
 304         /* translate the offset from words to byte */
 305         return (address & ADDRESS_MSK) + (offset << 1);
 306 }
 307
 308 static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 309 {
 310         struct iwl_eeprom_calib_hdr {
 311                 u8 version;
 312                 u8 pa_type;
 313                 u16 voltage;
 314         } *hdr;
 315
 316         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 317                                                         EEPROM_5000_CALIB_ALL);
 318         return hdr->version;
 319
 320 }
 321
 322 static void iwl5000_gain_computation(struct iwl_priv *priv,
 323                 u32 average_noise[NUM_RX_CHAINS],
 324                 u16 min_average_noise_antenna_i,
 325                 u32 min_average_noise)
 326 {
 327         int i;
 328         s32 delta_g;
 329         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 330
 331         /* Find Gain Code for the antennas B and C */
 332         for (i = 1; i < NUM_RX_CHAINS; i++) {
 333                 if ((data->disconn_array[i])) {
 334                         data->delta_gain_code[i] = 0;
 335                         continue;
 336                 }
 337                 delta_g = (1000 * ((s32)average_noise[0] -
 338                         (s32)average_noise[i])) / 1500;
 339                 /* bound gain by 2 bits value max, 3rd bit is sign */
 340                 data->delta_gain_code[i] =
 341                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 342
 343                 if (delta_g < 0)
 344                         /* set negative sign */
 345                         data->delta_gain_code[i] |= (1 << 2);
 346         }
 347
 348         IWL_DEBUG_CALIB("Delta gains: ANT_B = %d  ANT_C = %d\n",
 349                         data->delta_gain_code[1], data->delta_gain_code[2]);
 350
 351         if (!data->radio_write) {
 352                 struct iwl_calib_chain_noise_gain_cmd cmd;
 353
 354                 memset(&cmd, 0, sizeof(cmd));
 355
 356                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 357                 cmd.hdr.first_group = 0;
 358                 cmd.hdr.groups_num = 1;
 359                 cmd.hdr.data_valid = 1;
 360                 cmd.delta_gain_1 = data->delta_gain_code[1];
 361                 cmd.delta_gain_2 = data->delta_gain_code[2];
 362                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 363                         sizeof(cmd), &cmd, NULL);
 364
 365                 data->radio_write = 1;
 366                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 367         }
 368
 369         data->chain_noise_a = 0;
 370         data->chain_noise_b = 0;
 371         data->chain_noise_c = 0;
 372         data->chain_signal_a = 0;
 373         data->chain_signal_b = 0;
 374         data->chain_signal_c = 0;
 375         data->beacon_count = 0;
 376 }
 377
 378 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 379 {
 380         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 381         int ret;
 382
 383         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 384                 struct iwl_calib_chain_noise_reset_cmd cmd;
 385                 memset(&cmd, 0, sizeof(cmd));
 386
 387                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 388                 cmd.hdr.first_group = 0;
 389                 cmd.hdr.groups_num = 1;
 390                 cmd.hdr.data_valid = 1;
 391                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 392                                         sizeof(cmd), &cmd);
 393                 if (ret)
 394                         IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
 395                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 396                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
 397         }
 398 }
 399
 400 static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 401                         __le32 *tx_flags)
 402 {
 403         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
 404             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
 405                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 406         else
 407                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 408 }
 409
 410 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 411         .min_nrg_cck = 95,
 412         .max_nrg_cck = 0,
 413         .auto_corr_min_ofdm = 90,
 414         .auto_corr_min_ofdm_mrc = 170,
 415         .auto_corr_min_ofdm_x1 = 120,
 416         .auto_corr_min_ofdm_mrc_x1 = 240,
 417
 418         .auto_corr_max_ofdm = 120,
 419         .auto_corr_max_ofdm_mrc = 210,
 420         .auto_corr_max_ofdm_x1 = 155,
 421         .auto_corr_max_ofdm_mrc_x1 = 290,
 422
 423         .auto_corr_min_cck = 125,
 424         .auto_corr_max_cck = 200,
 425         .auto_corr_min_cck_mrc = 170,
 426         .auto_corr_max_cck_mrc = 400,
 427         .nrg_th_cck = 95,
 428         .nrg_th_ofdm = 95,
 429 };
 430
 431 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 432                                            size_t offset)
 433 {
 434         u32 address = eeprom_indirect_address(priv, offset);
 435         BUG_ON(address >= priv->cfg->eeprom_size);
 436         return &priv->eeprom[address];
 437 }
 438
 439 static s32 iwl5150_get_ct_threshold(struct iwl_priv *priv)
 440 {
 441         const s32 volt2temp_coef = -5;
 442         u16 *temp_calib = (u16 *)iwl_eeprom_query_addr(priv,
 443                                                 EEPROM_5000_TEMPERATURE);
 444         /* offset =  temperate -  voltage / coef */
 445         s32 offset = temp_calib[0] - temp_calib[1] / volt2temp_coef;
 446         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD) - offset;
 447         return threshold * volt2temp_coef;
 448 }
 449
 450 /*
 451  *  Calibration
 452  */
 453 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 454 {
 455         struct iwl_calib_xtal_freq_cmd cmd;
 456         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 457
 458         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 459         cmd.hdr.first_group = 0;
 460         cmd.hdr.groups_num = 1;
 461         cmd.hdr.data_valid = 1;
 462         cmd.cap_pin1 = (u8)xtal_calib[0];
 463         cmd.cap_pin2 = (u8)xtal_calib[1];
 464         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 465                              (u8 *)&cmd, sizeof(cmd));
 466 }
 467
 468 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 469 {
 470         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 471         struct iwl_host_cmd cmd = {
 472                 .id = CALIBRATION_CFG_CMD,
 473                 .len = sizeof(struct iwl_calib_cfg_cmd),
 474                 .data = &calib_cfg_cmd,
 475         };
 476
 477         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 478         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 479         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 480         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 481         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 482
 483         return iwl_send_cmd(priv, &cmd);
 484 }
 485
 486 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 487                              struct iwl_rx_mem_buffer *rxb)
 488 {
 489         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 490         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 491         int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
 492         int index;
 493
 494         /* reduce the size of the length field itself */
 495         len -= 4;
 496
 497         /* Define the order in which the results will be sent to the runtime
 498          * uCode. iwl_send_calib_results sends them in a row according to their
 499          * index. We sort them here */
 500         switch (hdr->op_code) {
 501         case IWL_PHY_CALIBRATE_DC_CMD:
 502                 index = IWL_CALIB_DC;
 503                 break;
 504         case IWL_PHY_CALIBRATE_LO_CMD:
 505                 index = IWL_CALIB_LO;
 506                 break;
 507         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 508                 index = IWL_CALIB_TX_IQ;
 509                 break;
 510         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 511                 index = IWL_CALIB_TX_IQ_PERD;
 512                 break;
 513         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 514                 index = IWL_CALIB_BASE_BAND;
 515                 break;
 516         default:
 517                 IWL_ERROR("Unknown calibration notification %d\n",
 518                           hdr->op_code);
 519                 return;
 520         }
 521         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 522 }
 523
 524 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 525                                struct iwl_rx_mem_buffer *rxb)
 526 {
 527         IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
 528         queue_work(priv->workqueue, &priv->restart);
 529 }
 530
 531 /*
 532  * ucode
 533  */
 534 static int iwl5000_load_section(struct iwl_priv *priv,
 535                                 struct fw_desc *image,
 536                                 u32 dst_addr)
 537 {
 538         int ret = 0;
 539         unsigned long flags;
 540
 541         dma_addr_t phy_addr = image->p_addr;
 542         u32 byte_cnt = image->len;
 543
 544         spin_lock_irqsave(&priv->lock, flags);
 545         ret = iwl_grab_nic_access(priv);
 546         if (ret) {
 547                 spin_unlock_irqrestore(&priv->lock, flags);
 548                 return ret;
 549         }
 550
 551         iwl_write_direct32(priv,
 552                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 553                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 554
 555         iwl_write_direct32(priv,
 556                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 557
 558         iwl_write_direct32(priv,
 559                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 560                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 561
 562         iwl_write_direct32(priv,
 563                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 564                 (iwl_get_dma_hi_addr(phy_addr)
 565                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 566
 567         iwl_write_direct32(priv,
 568                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 569                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 570                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 571                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 572
 573         iwl_write_direct32(priv,
 574                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 575                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 576                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 577                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 578
 579         iwl_release_nic_access(priv);
 580         spin_unlock_irqrestore(&priv->lock, flags);
 581         return 0;
 582 }
 583
 584 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 585                 struct fw_desc *inst_image,
 586                 struct fw_desc *data_image)
 587 {
 588         int ret = 0;
 589
 590         ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND);
 591         if (ret)
 592                 return ret;
 593
 594         IWL_DEBUG_INFO("INST uCode section being loaded...\n");
 595         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 596                                         priv->ucode_write_complete, 5 * HZ);
 597         if (ret == -ERESTARTSYS) {
 598                 IWL_ERROR("Could not load the INST uCode section due "
 599                         "to interrupt\n");
 600                 return ret;
 601         }
 602         if (!ret) {
 603                 IWL_ERROR("Could not load the INST uCode section\n");
 604                 return -ETIMEDOUT;
 605         }
 606
 607         priv->ucode_write_complete = 0;
 608
 609         ret = iwl5000_load_section(
 610                 priv, data_image, RTC_DATA_LOWER_BOUND);
 611         if (ret)
 612                 return ret;
 613
 614         IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
 615
 616         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 617                                 priv->ucode_write_complete, 5 * HZ);
 618         if (ret == -ERESTARTSYS) {
 619                 IWL_ERROR("Could not load the INST uCode section due "
 620                         "to interrupt\n");
 621                 return ret;
 622         } else if (!ret) {
 623                 IWL_ERROR("Could not load the DATA uCode section\n");
 624                 return -ETIMEDOUT;
 625         } else
 626                 ret = 0;
 627
 628         priv->ucode_write_complete = 0;
 629
 630         return ret;
 631 }
 632
 633 static int iwl5000_load_ucode(struct iwl_priv *priv)
 634 {
 635         int ret = 0;
 636
 637         /* check whether init ucode should be loaded, or rather runtime ucode */
 638         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 639                 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
 640                 ret = iwl5000_load_given_ucode(priv,
 641                         &priv->ucode_init, &priv->ucode_init_data);
 642                 if (!ret) {
 643                         IWL_DEBUG_INFO("Init ucode load complete.\n");
 644                         priv->ucode_type = UCODE_INIT;
 645                 }
 646         } else {
 647                 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
 648                         "Loading runtime ucode...\n");
 649                 ret = iwl5000_load_given_ucode(priv,
 650                         &priv->ucode_code, &priv->ucode_data);
 651                 if (!ret) {
 652                         IWL_DEBUG_INFO("Runtime ucode load complete.\n");
 653                         priv->ucode_type = UCODE_RT;
 654                 }
 655         }
 656
 657         return ret;
 658 }
 659
 660 static void iwl5000_init_alive_start(struct iwl_priv *priv)
 661 {
 662         int ret = 0;
 663
 664         /* Check alive response for "valid" sign from uCode */
 665         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 666                 /* We had an error bringing up the hardware, so take it
 667                  * all the way back down so we can try again */
 668                 IWL_DEBUG_INFO("Initialize Alive failed.\n");
 669                 goto restart;
 670         }
 671
 672         /* initialize uCode was loaded... verify inst image.
 673          * This is a paranoid check, because we would not have gotten the
 674          * "initialize" alive if code weren't properly loaded.  */
 675         if (iwl_verify_ucode(priv)) {
 676                 /* Runtime instruction load was bad;
 677                  * take it all the way back down so we can try again */
 678                 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
 679                 goto restart;
 680         }
 681
 682         iwl_clear_stations_table(priv);
 683         ret = priv->cfg->ops->lib->alive_notify(priv);
 684         if (ret) {
 685                 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
 686                 goto restart;
 687         }
 688
 689         iwl5000_send_calib_cfg(priv);
 690         return;
 691
 692 restart:
 693         /* real restart (first load init_ucode) */
 694         queue_work(priv->workqueue, &priv->restart);
 695 }
 696
 697 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 698                                 int txq_id, u32 index)
 699 {
 700         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 701                         (index & 0xff) | (txq_id << 8));
 702         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 703 }
 704
 705 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 706                                         struct iwl_tx_queue *txq,
 707                                         int tx_fifo_id, int scd_retry)
 708 {
 709         int txq_id = txq->q.id;
 710         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 711
 712         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 713                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 714                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 715                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 716                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 717
 718         txq->sched_retry = scd_retry;
 719
 720         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
 721                        active ? "Activate" : "Deactivate",
 722                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 723 }
 724
 725 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
 726 {
 727         struct iwl_wimax_coex_cmd coex_cmd;
 728
 729         memset(&coex_cmd, 0, sizeof(coex_cmd));
 730
 731         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 732                                 sizeof(coex_cmd), &coex_cmd);
 733 }
 734
 735 static int iwl5000_alive_notify(struct iwl_priv *priv)
 736 {
 737         u32 a;
 738         unsigned long flags;
 739         int ret;
 740         int i, chan;
 741         u32 reg_val;
 742
 743         spin_lock_irqsave(&priv->lock, flags);
 744
 745         ret = iwl_grab_nic_access(priv);
 746         if (ret) {
 747                 spin_unlock_irqrestore(&priv->lock, flags);
 748                 return ret;
 749         }
 750
 751         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 752         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 753         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 754                 a += 4)
 755                 iwl_write_targ_mem(priv, a, 0);
 756         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 757                 a += 4)
 758                 iwl_write_targ_mem(priv, a, 0);
 759         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 760                 iwl_write_targ_mem(priv, a, 0);
 761
 762         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 763                        priv->scd_bc_tbls.dma >> 10);
 764
 765         /* Enable DMA channel */
 766         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 767                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 768                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 769                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 770
 771         /* Update FH chicken bits */
 772         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 773         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 774                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 775
 776         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 777                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 778         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 779
 780         /* initiate the queues */
 781         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 782                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 783                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 784                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 785                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 786                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 787                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 788                                 sizeof(u32),
 789                                 ((SCD_WIN_SIZE <<
 790                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 791                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 792                                 ((SCD_FRAME_LIMIT <<
 793                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 794                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 795         }
 796
 797         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 798                         IWL_MASK(0, priv->hw_params.max_txq_num));
 799
 800         /* Activate all Tx DMA/FIFO channels */
 801         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 802
 803         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 804
 805         /* map qos queues to fifos one-to-one */
 806         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 807                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 808                 iwl_txq_ctx_activate(priv, i);
 809                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 810         }
 811         /* TODO - need to initialize those FIFOs inside the loop above,
 812          * not only mark them as active */
 813         iwl_txq_ctx_activate(priv, 4);
 814         iwl_txq_ctx_activate(priv, 7);
 815         iwl_txq_ctx_activate(priv, 8);
 816         iwl_txq_ctx_activate(priv, 9);
 817
 818         iwl_release_nic_access(priv);
 819         spin_unlock_irqrestore(&priv->lock, flags);
 820
 821
 822         iwl5000_send_wimax_coex(priv);
 823
 824         iwl5000_set_Xtal_calib(priv);
 825         iwl_send_calib_results(priv);
 826
 827         return 0;
 828 }
 829
 830 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 831 {
 832         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 833             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 834                 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
 835                           IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 836                 return -EINVAL;
 837         }
 838
 839         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 840         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
 841         priv->hw_params.scd_bc_tbls_size =
 842                         IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
 843         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 844         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 845         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 846         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 847         priv->hw_params.max_bsm_size = 0;
 848         priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
 849                                         BIT(IEEE80211_BAND_5GHZ);
 850         priv->hw_params.sens = &iwl5000_sensitivity;
 851
 852         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 853         case CSR_HW_REV_TYPE_5100:
 854                 priv->hw_params.tx_chains_num = 1;
 855                 priv->hw_params.rx_chains_num = 2;
 856                 priv->hw_params.valid_tx_ant = ANT_B;
 857                 priv->hw_params.valid_rx_ant = ANT_AB;
 858                 break;
 859         case CSR_HW_REV_TYPE_5150:
 860                 priv->hw_params.tx_chains_num = 1;
 861                 priv->hw_params.rx_chains_num = 2;
 862                 priv->hw_params.valid_tx_ant = ANT_A;
 863                 priv->hw_params.valid_rx_ant = ANT_AB;
 864                 break;
 865         case CSR_HW_REV_TYPE_5300:
 866         case CSR_HW_REV_TYPE_5350:
 867                 priv->hw_params.tx_chains_num = 3;
 868                 priv->hw_params.rx_chains_num = 3;
 869                 priv->hw_params.valid_tx_ant = ANT_ABC;
 870                 priv->hw_params.valid_rx_ant = ANT_ABC;
 871                 break;
 872         }
 873
 874         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 875         case CSR_HW_REV_TYPE_5100:
 876         case CSR_HW_REV_TYPE_5300:
 877         case CSR_HW_REV_TYPE_5350:
 878                 /* 5X00 and 5350 wants in Celsius */
 879                 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
 880                 break;
 881         case CSR_HW_REV_TYPE_5150:
 882                 /* 5150 wants in Kelvin */
 883                 priv->hw_params.ct_kill_threshold =
 884                                 iwl5150_get_ct_threshold(priv);
 885                 break;
 886         }
 887
 888         /* Set initial calibration set */
 889         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 890         case CSR_HW_REV_TYPE_5100:
 891         case CSR_HW_REV_TYPE_5300:
 892         case CSR_HW_REV_TYPE_5350:
 893                 priv->hw_params.calib_init_cfg =
 894                         BIT(IWL_CALIB_XTAL)             |
 895                         BIT(IWL_CALIB_LO)               |
 896                         BIT(IWL_CALIB_TX_IQ)            |
 897                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 898                         BIT(IWL_CALIB_BASE_BAND);
 899                 break;
 900         case CSR_HW_REV_TYPE_5150:
 901                 priv->hw_params.calib_init_cfg =
 902                         BIT(IWL_CALIB_DC)               |
 903                         BIT(IWL_CALIB_LO)               |
 904                         BIT(IWL_CALIB_TX_IQ)            |
 905                         BIT(IWL_CALIB_BASE_BAND);
 906
 907                 break;
 908         }
 909
 910
 911         return 0;
 912 }
 913
 914 /**
 915  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 916  */
 917 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 918                                             struct iwl_tx_queue *txq,
 919                                             u16 byte_cnt)
 920 {
 921         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 922         int write_ptr = txq->q.write_ptr;
 923         int txq_id = txq->q.id;
 924         u8 sec_ctl = 0;
 925         u8 sta_id = 0;
 926         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 927         __le16 bc_ent;
 928
 929         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 930
 931         if (txq_id != IWL_CMD_QUEUE_NUM) {
 932                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 933                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 934
 935                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 936                 case TX_CMD_SEC_CCM:
 937                         len += CCMP_MIC_LEN;
 938                         break;
 939                 case TX_CMD_SEC_TKIP:
 940                         len += TKIP_ICV_LEN;
 941                         break;
 942                 case TX_CMD_SEC_WEP:
 943                         len += WEP_IV_LEN + WEP_ICV_LEN;
 944                         break;
 945                 }
 946         }
 947
 948         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
 949
 950         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 951
 952         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 953                 scd_bc_tbl[txq_id].
 954                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 955 }
 956
 957 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 958                                            struct iwl_tx_queue *txq)
 959 {
 960         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 961         int txq_id = txq->q.id;
 962         int read_ptr = txq->q.read_ptr;
 963         u8 sta_id = 0;
 964         __le16 bc_ent;
 965
 966         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 967
 968         if (txq_id != IWL_CMD_QUEUE_NUM)
 969                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 970
 971         bc_ent =  cpu_to_le16(1 | (sta_id << 12));
 972         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 973
 974         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 975                 scd_bc_tbl[txq_id].
 976                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =  bc_ent;
 977 }
 978
 979 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 980                                         u16 txq_id)
 981 {
 982         u32 tbl_dw_addr;
 983         u32 tbl_dw;
 984         u16 scd_q2ratid;
 985
 986         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 987
 988         tbl_dw_addr = priv->scd_base_addr +
 989                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 990
 991         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 992
 993         if (txq_id & 0x1)
 994                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 995         else
 996                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 997
 998         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 999
1000         return 0;
1001 }
1002 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
1003 {
1004         /* Simply stop the queue, but don't change any configuration;
1005          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1006         iwl_write_prph(priv,
1007                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
1008                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1009                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1010 }
1011
1012 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1013                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1014 {
1015         unsigned long flags;
1016         int ret;
1017         u16 ra_tid;
1018
1019         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1020             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1021                 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1022                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1023                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1024                 return -EINVAL;
1025         }
1026
1027         ra_tid = BUILD_RAxTID(sta_id, tid);
1028
1029         /* Modify device's station table to Tx this TID */
1030         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1031
1032         spin_lock_irqsave(&priv->lock, flags);
1033         ret = iwl_grab_nic_access(priv);
1034         if (ret) {
1035                 spin_unlock_irqrestore(&priv->lock, flags);
1036                 return ret;
1037         }
1038
1039         /* Stop this Tx queue before configuring it */
1040         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1041
1042         /* Map receiver-address / traffic-ID to this queue */
1043         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1044
1045         /* Set this queue as a chain-building queue */
1046         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1047
1048         /* enable aggregations for the queue */
1049         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1050
1051         /* Place first TFD at index corresponding to start sequence number.
1052          * Assumes that ssn_idx is valid (!= 0xFFF) */
1053         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1054         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1055         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1056
1057         /* Set up Tx window size and frame limit for this queue */
1058         iwl_write_targ_mem(priv, priv->scd_base_addr +
1059                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1060                         sizeof(u32),
1061                         ((SCD_WIN_SIZE <<
1062                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1063                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1064                         ((SCD_FRAME_LIMIT <<
1065                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1066                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1067
1068         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1069
1070         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1071         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1072
1073         iwl_release_nic_access(priv);
1074         spin_unlock_irqrestore(&priv->lock, flags);
1075
1076         return 0;
1077 }
1078
1079 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1080                                    u16 ssn_idx, u8 tx_fifo)
1081 {
1082         int ret;
1083
1084         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1085             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1086                 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1087                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1088                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1089                 return -EINVAL;
1090         }
1091
1092         ret = iwl_grab_nic_access(priv);
1093         if (ret)
1094                 return ret;
1095
1096         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1097
1098         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1099
1100         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1101         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1102         /* supposes that ssn_idx is valid (!= 0xFFF) */
1103         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1104
1105         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1106         iwl_txq_ctx_deactivate(priv, txq_id);
1107         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1108
1109         iwl_release_nic_access(priv);
1110
1111         return 0;
1112 }
1113
1114 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1115 {
1116         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1117         memcpy(data, cmd, size);
1118         return size;
1119 }
1120
1121
1122 /*
1123  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1124  * must be called under priv->lock and mac access
1125  */
1126 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1127 {
1128         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1129 }
1130
1131
1132 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1133 {
1134         return le32_to_cpup((__le32 *)&tx_resp->status +
1135                             tx_resp->frame_count) & MAX_SN;
1136 }
1137
1138 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1139                                       struct iwl_ht_agg *agg,
1140                                       struct iwl5000_tx_resp *tx_resp,
1141                                       int txq_id, u16 start_idx)
1142 {
1143         u16 status;
1144         struct agg_tx_status *frame_status = &tx_resp->status;
1145         struct ieee80211_tx_info *info = NULL;
1146         struct ieee80211_hdr *hdr = NULL;
1147         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1148         int i, sh, idx;
1149         u16 seq;
1150
1151         if (agg->wait_for_ba)
1152                 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1153
1154         agg->frame_count = tx_resp->frame_count;
1155         agg->start_idx = start_idx;
1156         agg->rate_n_flags = rate_n_flags;
1157         agg->bitmap = 0;
1158
1159         /* # frames attempted by Tx command */
1160         if (agg->frame_count == 1) {
1161                 /* Only one frame was attempted; no block-ack will arrive */
1162                 status = le16_to_cpu(frame_status[0].status);
1163                 idx = start_idx;
1164
1165                 /* FIXME: code repetition */
1166                 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1167                                    agg->frame_count, agg->start_idx, idx);
1168
1169                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1170                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1171                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1172                 info->flags |= iwl_is_tx_success(status) ?
1173                                         IEEE80211_TX_STAT_ACK : 0;
1174                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1175
1176                 /* FIXME: code repetition end */
1177
1178                 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1179                                     status & 0xff, tx_resp->failure_frame);
1180                 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
1181
1182                 agg->wait_for_ba = 0;
1183         } else {
1184                 /* Two or more frames were attempted; expect block-ack */
1185                 u64 bitmap = 0;
1186                 int start = agg->start_idx;
1187
1188                 /* Construct bit-map of pending frames within Tx window */
1189                 for (i = 0; i < agg->frame_count; i++) {
1190                         u16 sc;
1191                         status = le16_to_cpu(frame_status[i].status);
1192                         seq  = le16_to_cpu(frame_status[i].sequence);
1193                         idx = SEQ_TO_INDEX(seq);
1194                         txq_id = SEQ_TO_QUEUE(seq);
1195
1196                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1197                                       AGG_TX_STATE_ABORT_MSK))
1198                                 continue;
1199
1200                         IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1201                                            agg->frame_count, txq_id, idx);
1202
1203                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1204
1205                         sc = le16_to_cpu(hdr->seq_ctrl);
1206                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1207                                 IWL_ERROR("BUG_ON idx doesn't match seq control"
1208                                           " idx=%d, seq_idx=%d, seq=%d\n",
1209                                           idx, SEQ_TO_SN(sc),
1210                                           hdr->seq_ctrl);
1211                                 return -1;
1212                         }
1213
1214                         IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1215                                            i, idx, SEQ_TO_SN(sc));
1216
1217                         sh = idx - start;
1218                         if (sh > 64) {
1219                                 sh = (start - idx) + 0xff;
1220                                 bitmap = bitmap << sh;
1221                                 sh = 0;
1222                                 start = idx;
1223                         } else if (sh < -64)
1224                                 sh  = 0xff - (start - idx);
1225                         else if (sh < 0) {
1226                                 sh = start - idx;
1227                                 start = idx;
1228                                 bitmap = bitmap << sh;
1229                                 sh = 0;
1230                         }
1231                         bitmap |= 1ULL << sh;
1232                         IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1233                                            start, (unsigned long long)bitmap);
1234                 }
1235
1236                 agg->bitmap = bitmap;
1237                 agg->start_idx = start;
1238                 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1239                                    agg->frame_count, agg->start_idx,
1240                                    (unsigned long long)agg->bitmap);
1241
1242                 if (bitmap)
1243                         agg->wait_for_ba = 1;
1244         }
1245         return 0;
1246 }
1247
1248 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1249                                 struct iwl_rx_mem_buffer *rxb)
1250 {
1251         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1252         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1253         int txq_id = SEQ_TO_QUEUE(sequence);
1254         int index = SEQ_TO_INDEX(sequence);
1255         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1256         struct ieee80211_tx_info *info;
1257         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1258         u32  status = le16_to_cpu(tx_resp->status.status);
1259         int tid;
1260         int sta_id;
1261         int freed;
1262
1263         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1264                 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1265                           "is out of range [0-%d] %d %d\n", txq_id,
1266                           index, txq->q.n_bd, txq->q.write_ptr,
1267                           txq->q.read_ptr);
1268                 return;
1269         }
1270
1271         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1272         memset(&info->status, 0, sizeof(info->status));
1273
1274         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1275         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1276
1277         if (txq->sched_retry) {
1278                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1279                 struct iwl_ht_agg *agg = NULL;
1280
1281                 agg = &priv->stations[sta_id].tid[tid].agg;
1282
1283                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1284
1285                 /* check if BAR is needed */
1286                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1287                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1288
1289                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1290                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1291                         IWL_DEBUG_TX_REPLY("Retry scheduler reclaim "
1292                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1293                                         scd_ssn , index, txq_id, txq->swq_id);
1294
1295                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1296                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1297
1298                         if (priv->mac80211_registered &&
1299                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1300                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1301                                 if (agg->state == IWL_AGG_OFF)
1302                                         ieee80211_wake_queue(priv->hw, txq_id);
1303                                 else
1304                                         ieee80211_wake_queue(priv->hw,
1305                                                              txq->swq_id);
1306                         }
1307                 }
1308         } else {
1309                 BUG_ON(txq_id != txq->swq_id);
1310
1311                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1312                 info->flags |= iwl_is_tx_success(status) ?
1313                                         IEEE80211_TX_STAT_ACK : 0;
1314                 iwl_hwrate_to_tx_control(priv,
1315                                         le32_to_cpu(tx_resp->rate_n_flags),
1316                                         info);
1317
1318                 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags "
1319                                    "0x%x retries %d\n",
1320                                    txq_id,
1321                                    iwl_get_tx_fail_reason(status), status,
1322                                    le32_to_cpu(tx_resp->rate_n_flags),
1323                                    tx_resp->failure_frame);
1324
1325                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1326                 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1327                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1328
1329                 if (priv->mac80211_registered &&
1330                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1331                         ieee80211_wake_queue(priv->hw, txq_id);
1332         }
1333
1334         if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1335                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1336
1337         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1338                 IWL_ERROR("TODO:  Implement Tx ABORT REQUIRED!!!\n");
1339 }
1340
1341 /* Currently 5000 is the superset of everything */
1342 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1343 {
1344         return len;
1345 }
1346
1347 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1348 {
1349         /* in 5000 the tx power calibration is done in uCode */
1350         priv->disable_tx_power_cal = 1;
1351 }
1352
1353 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1354 {
1355         /* init calibration handlers */
1356         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1357                                         iwl5000_rx_calib_result;
1358         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1359                                         iwl5000_rx_calib_complete;
1360         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1361 }
1362
1363
1364 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1365 {
1366         return (addr >= RTC_DATA_LOWER_BOUND) &&
1367                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1368 }
1369
1370 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1371 {
1372         int ret = 0;
1373         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1374         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1375         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1376
1377         if ((rxon1->flags == rxon2->flags) &&
1378             (rxon1->filter_flags == rxon2->filter_flags) &&
1379             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1380             (rxon1->ofdm_ht_single_stream_basic_rates ==
1381              rxon2->ofdm_ht_single_stream_basic_rates) &&
1382             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1383              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1384             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1385              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1386             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1387             (rxon1->rx_chain == rxon2->rx_chain) &&
1388             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1389                 IWL_DEBUG_INFO("Using current RXON_ASSOC.  Not resending.\n");
1390                 return 0;
1391         }
1392
1393         rxon_assoc.flags = priv->staging_rxon.flags;
1394         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1395         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1396         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1397         rxon_assoc.reserved1 = 0;
1398         rxon_assoc.reserved2 = 0;
1399         rxon_assoc.reserved3 = 0;
1400         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1401             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1402         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1403             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1404         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1405         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1406                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1407         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1408
1409         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1410                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1411         if (ret)
1412                 return ret;
1413
1414         return ret;
1415 }
1416 static int  iwl5000_send_tx_power(struct iwl_priv *priv)
1417 {
1418         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1419
1420         /* half dBm need to multiply */
1421         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1422         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1423         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1424         return  iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1425                                        sizeof(tx_power_cmd), &tx_power_cmd,
1426                                        NULL);
1427 }
1428
1429 static void iwl5000_temperature(struct iwl_priv *priv)
1430 {
1431         /* store temperature from statistics (in Celsius) */
1432         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1433 }
1434
1435 /* Calc max signal level (dBm) among 3 possible receivers */
1436 static int iwl5000_calc_rssi(struct iwl_priv *priv,
1437                              struct iwl_rx_phy_res *rx_resp)
1438 {
1439         /* data from PHY/DSP regarding signal strength, etc.,
1440          *   contents are always there, not configurable by host
1441          */
1442         struct iwl5000_non_cfg_phy *ncphy =
1443                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1444         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1445         u8 agc;
1446
1447         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1448         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1449
1450         /* Find max rssi among 3 possible receivers.
1451          * These values are measured by the digital signal processor (DSP).
1452          * They should stay fairly constant even as the signal strength varies,
1453          *   if the radio's automatic gain control (AGC) is working right.
1454          * AGC value (see below) will provide the "interesting" info.
1455          */
1456         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1457         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1458         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1459         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1460         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1461
1462         max_rssi = max_t(u32, rssi_a, rssi_b);
1463         max_rssi = max_t(u32, max_rssi, rssi_c);
1464
1465         IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1466                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1467
1468         /* dBm = max_rssi dB - agc dB - constant.
1469          * Higher AGC (higher radio gain) means lower signal. */
1470         return max_rssi - agc - IWL_RSSI_OFFSET;
1471 }
1472
1473 static struct iwl_hcmd_ops iwl5000_hcmd = {
1474         .rxon_assoc = iwl5000_send_rxon_assoc,
1475 };
1476
1477 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1478         .get_hcmd_size = iwl5000_get_hcmd_size,
1479         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1480         .gain_computation = iwl5000_gain_computation,
1481         .chain_noise_reset = iwl5000_chain_noise_reset,
1482         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1483         .calc_rssi = iwl5000_calc_rssi,
1484 };
1485
1486 static struct iwl_lib_ops iwl5000_lib = {
1487         .set_hw_params = iwl5000_hw_set_hw_params,
1488         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1489         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1490         .txq_set_sched = iwl5000_txq_set_sched,
1491         .txq_agg_enable = iwl5000_txq_agg_enable,
1492         .txq_agg_disable = iwl5000_txq_agg_disable,
1493         .rx_handler_setup = iwl5000_rx_handler_setup,
1494         .setup_deferred_work = iwl5000_setup_deferred_work,
1495         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1496         .load_ucode = iwl5000_load_ucode,
1497         .init_alive_start = iwl5000_init_alive_start,
1498         .alive_notify = iwl5000_alive_notify,
1499         .send_tx_power = iwl5000_send_tx_power,
1500         .temperature = iwl5000_temperature,
1501         .update_chain_flags = iwl_update_chain_flags,
1502         .apm_ops = {
1503                 .init = iwl5000_apm_init,
1504                 .reset = iwl5000_apm_reset,
1505                 .stop = iwl5000_apm_stop,
1506                 .config = iwl5000_nic_config,
1507                 .set_pwr_src = iwl_set_pwr_src,
1508         },
1509         .eeprom_ops = {
1510                 .regulatory_bands = {
1511                         EEPROM_5000_REG_BAND_1_CHANNELS,
1512                         EEPROM_5000_REG_BAND_2_CHANNELS,
1513                         EEPROM_5000_REG_BAND_3_CHANNELS,
1514                         EEPROM_5000_REG_BAND_4_CHANNELS,
1515                         EEPROM_5000_REG_BAND_5_CHANNELS,
1516                         EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1517                         EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1518                 },
1519                 .verify_signature  = iwlcore_eeprom_verify_signature,
1520                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1521                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1522                 .calib_version  = iwl5000_eeprom_calib_version,
1523                 .query_addr = iwl5000_eeprom_query_addr,
1524         },
1525 };
1526
1527 static struct iwl_ops iwl5000_ops = {
1528         .lib = &iwl5000_lib,
1529         .hcmd = &iwl5000_hcmd,
1530         .utils = &iwl5000_hcmd_utils,
1531 };
1532
1533 static struct iwl_mod_params iwl50_mod_params = {
1534         .num_of_queues = IWL50_NUM_QUEUES,
1535         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1536         .enable_qos = 1,
1537         .amsdu_size_8K = 1,
1538         .restart_fw = 1,
1539         /* the rest are 0 by default */
1540 };
1541
1542
1543 struct iwl_cfg iwl5300_agn_cfg = {
1544         .name = "5300AGN",
1545         .fw_name_pre = IWL5000_FW_PRE,
1546         .ucode_api_max = IWL5000_UCODE_API_MAX,
1547         .ucode_api_min = IWL5000_UCODE_API_MIN,
1548         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1549         .ops = &iwl5000_ops,
1550         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1551         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1552         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1553         .mod_params = &iwl50_mod_params,
1554 };
1555
1556 struct iwl_cfg iwl5100_bg_cfg = {
1557         .name = "5100BG",
1558         .fw_name_pre = IWL5000_FW_PRE,
1559         .ucode_api_max = IWL5000_UCODE_API_MAX,
1560         .ucode_api_min = IWL5000_UCODE_API_MIN,
1561         .sku = IWL_SKU_G,
1562         .ops = &iwl5000_ops,
1563         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1564         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1565         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1566         .mod_params = &iwl50_mod_params,
1567 };
1568
1569 struct iwl_cfg iwl5100_abg_cfg = {
1570         .name = "5100ABG",
1571         .fw_name_pre = IWL5000_FW_PRE,
1572         .ucode_api_max = IWL5000_UCODE_API_MAX,
1573         .ucode_api_min = IWL5000_UCODE_API_MIN,
1574         .sku = IWL_SKU_A|IWL_SKU_G,
1575         .ops = &iwl5000_ops,
1576         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1577         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1578         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1579         .mod_params = &iwl50_mod_params,
1580 };
1581
1582 struct iwl_cfg iwl5100_agn_cfg = {
1583         .name = "5100AGN",
1584         .fw_name_pre = IWL5000_FW_PRE,
1585         .ucode_api_max = IWL5000_UCODE_API_MAX,
1586         .ucode_api_min = IWL5000_UCODE_API_MIN,
1587         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1588         .ops = &iwl5000_ops,
1589         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1590         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1591         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1592         .mod_params = &iwl50_mod_params,
1593 };
1594
1595 struct iwl_cfg iwl5350_agn_cfg = {
1596         .name = "5350AGN",
1597         .fw_name_pre = IWL5000_FW_PRE,
1598         .ucode_api_max = IWL5000_UCODE_API_MAX,
1599         .ucode_api_min = IWL5000_UCODE_API_MIN,
1600         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1601         .ops = &iwl5000_ops,
1602         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1603         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1604         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1605         .mod_params = &iwl50_mod_params,
1606 };
1607
1608 struct iwl_cfg iwl5150_agn_cfg = {
1609         .name = "5150AGN",
1610         .fw_name_pre = IWL5150_FW_PRE,
1611         .ucode_api_max = IWL5150_UCODE_API_MAX,
1612         .ucode_api_min = IWL5150_UCODE_API_MIN,
1613         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1614         .ops = &iwl5000_ops,
1615         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1616         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1617         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1618         .mod_params = &iwl50_mod_params,
1619 };
1620
1621 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1622 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1623
1624 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1625 MODULE_PARM_DESC(disable50,
1626                   "manually disable the 50XX radio (default 0 [radio on])");
1627 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1628 MODULE_PARM_DESC(swcrypto50,
1629                   "using software crypto engine (default 0 [hardware])\n");
1630 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1631 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1632 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1633 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1634 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1635 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
1636 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1637 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1638 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1639 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1640 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1641 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");