Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/shaggy...
[linux-2.6] / drivers / infiniband / hw / ipath / ipath_init_chip.c
1 /*
2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4  *
5  * This software is available to you under a choice of one of two
6  * licenses.  You may choose to be licensed under the terms of the GNU
7  * General Public License (GPL) Version 2, available from the file
8  * COPYING in the main directory of this source tree, or the
9  * OpenIB.org BSD license below:
10  *
11  *     Redistribution and use in source and binary forms, with or
12  *     without modification, are permitted provided that the following
13  *     conditions are met:
14  *
15  *      - Redistributions of source code must retain the above
16  *        copyright notice, this list of conditions and the following
17  *        disclaimer.
18  *
19  *      - Redistributions in binary form must reproduce the above
20  *        copyright notice, this list of conditions and the following
21  *        disclaimer in the documentation and/or other materials
22  *        provided with the distribution.
23  *
24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31  * SOFTWARE.
32  */
33
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/vmalloc.h>
37
38 #include "ipath_kernel.h"
39 #include "ipath_common.h"
40
41 /*
42  * min buffers we want to have per port, after driver
43  */
44 #define IPATH_MIN_USER_PORT_BUFCNT 8
45
46 /*
47  * Number of ports we are configured to use (to allow for more pio
48  * buffers per port, etc.)  Zero means use chip value.
49  */
50 static ushort ipath_cfgports;
51
52 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
53 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
54
55 /*
56  * Number of buffers reserved for driver (verbs and layered drivers.)
57  * Reserved at end of buffer list.   Initialized based on
58  * number of PIO buffers if not set via module interface.
59  * The problem with this is that it's global, but we'll use different
60  * numbers for different chip types.  So the default value is not
61  * very useful.  I've redefined it for the 1.3 release so that it's
62  * zero unless set by the user to something else, in which case we
63  * try to respect it.
64  */
65 static ushort ipath_kpiobufs;
66
67 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
68
69 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
70                   &ipath_kpiobufs, S_IWUSR | S_IRUGO);
71 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
72
73 /**
74  * create_port0_egr - allocate the eager TID buffers
75  * @dd: the infinipath device
76  *
77  * This code is now quite different for user and kernel, because
78  * the kernel uses skb's, for the accelerated network performance.
79  * This is the kernel (port0) version.
80  *
81  * Allocate the eager TID buffers and program them into infinipath.
82  * We use the network layer alloc_skb() allocator to allocate the
83  * memory, and either use the buffers as is for things like verbs
84  * packets, or pass the buffers up to the ipath layered driver and
85  * thence the network layer, replacing them as we do so (see
86  * ipath_rcv_layer()).
87  */
88 static int create_port0_egr(struct ipath_devdata *dd)
89 {
90         unsigned e, egrcnt;
91         struct ipath_skbinfo *skbinfo;
92         int ret;
93
94         egrcnt = dd->ipath_rcvegrcnt;
95
96         skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
97         if (skbinfo == NULL) {
98                 ipath_dev_err(dd, "allocation error for eager TID "
99                               "skb array\n");
100                 ret = -ENOMEM;
101                 goto bail;
102         }
103         for (e = 0; e < egrcnt; e++) {
104                 /*
105                  * This is a bit tricky in that we allocate extra
106                  * space for 2 bytes of the 14 byte ethernet header.
107                  * These two bytes are passed in the ipath header so
108                  * the rest of the data is word aligned.  We allocate
109                  * 4 bytes so that the data buffer stays word aligned.
110                  * See ipath_kreceive() for more details.
111                  */
112                 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
113                 if (!skbinfo[e].skb) {
114                         ipath_dev_err(dd, "SKB allocation error for "
115                                       "eager TID %u\n", e);
116                         while (e != 0)
117                                 dev_kfree_skb(skbinfo[--e].skb);
118                         vfree(skbinfo);
119                         ret = -ENOMEM;
120                         goto bail;
121                 }
122         }
123         /*
124          * After loop above, so we can test non-NULL to see if ready
125          * to use at receive, etc.
126          */
127         dd->ipath_port0_skbinfo = skbinfo;
128
129         for (e = 0; e < egrcnt; e++) {
130                 dd->ipath_port0_skbinfo[e].phys =
131                   ipath_map_single(dd->pcidev,
132                                    dd->ipath_port0_skbinfo[e].skb->data,
133                                    dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
134                 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
135                                     ((char __iomem *) dd->ipath_kregbase +
136                                      dd->ipath_rcvegrbase), 0,
137                                     dd->ipath_port0_skbinfo[e].phys);
138         }
139
140         ret = 0;
141
142 bail:
143         return ret;
144 }
145
146 static int bringup_link(struct ipath_devdata *dd)
147 {
148         u64 val, ibc;
149         int ret = 0;
150
151         /* hold IBC in reset */
152         dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
153         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
154                          dd->ipath_control);
155
156         /*
157          * Note that prior to try 14 or 15 of IB, the credit scaling
158          * wasn't working, because it was swapped for writes with the
159          * 1 bit default linkstate field
160          */
161
162         /* ignore pbc and align word */
163         val = dd->ipath_piosize2k - 2 * sizeof(u32);
164         /*
165          * for ICRC, which we only send in diag test pkt mode, and we
166          * don't need to worry about that for mtu
167          */
168         val += 1;
169         /*
170          * Set the IBC maxpktlength to the size of our pio buffers the
171          * maxpktlength is in words.  This is *not* the IB data MTU.
172          */
173         ibc = (val / sizeof(u32)) << INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
174         /* in KB */
175         ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
176         /*
177          * How often flowctrl sent.  More or less in usecs; balance against
178          * watermark value, so that in theory senders always get a flow
179          * control update in time to not let the IB link go idle.
180          */
181         ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
182         /* max error tolerance */
183         ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
184         /* use "real" buffer space for */
185         ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
186         /* IB credit flow control. */
187         ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
188         /* initially come up waiting for TS1, without sending anything. */
189         dd->ipath_ibcctrl = ibc;
190         /*
191          * Want to start out with both LINKCMD and LINKINITCMD in NOP
192          * (0 and 0).  Don't put linkinitcmd in ipath_ibcctrl, want that
193          * to stay a NOP
194          */
195         ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
196                 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
197         ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
198                    (unsigned long long) ibc);
199         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
200
201         // be sure chip saw it
202         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
203
204         ret = dd->ipath_f_bringup_serdes(dd);
205
206         if (ret)
207                 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
208                          "not usable\n");
209         else {
210                 /* enable IBC */
211                 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
212                 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
213                                  dd->ipath_control);
214         }
215
216         return ret;
217 }
218
219 static int init_chip_first(struct ipath_devdata *dd,
220                            struct ipath_portdata **pdp)
221 {
222         struct ipath_portdata *pd = NULL;
223         int ret = 0;
224         u64 val;
225
226         /*
227          * skip cfgports stuff because we are not allocating memory,
228          * and we don't want problems if the portcnt changed due to
229          * cfgports.  We do still check and report a difference, if
230          * not same (should be impossible).
231          */
232         dd->ipath_portcnt =
233                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
234         if (!ipath_cfgports)
235                 dd->ipath_cfgports = dd->ipath_portcnt;
236         else if (ipath_cfgports <= dd->ipath_portcnt) {
237                 dd->ipath_cfgports = ipath_cfgports;
238                 ipath_dbg("Configured to use %u ports out of %u in chip\n",
239                           dd->ipath_cfgports, dd->ipath_portcnt);
240         } else {
241                 dd->ipath_cfgports = dd->ipath_portcnt;
242                 ipath_dbg("Tried to configured to use %u ports; chip "
243                           "only supports %u\n", ipath_cfgports,
244                           dd->ipath_portcnt);
245         }
246         /*
247          * Allocate full portcnt array, rather than just cfgports, because
248          * cleanup iterates across all possible ports.
249          */
250         dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
251                                GFP_KERNEL);
252
253         if (!dd->ipath_pd) {
254                 ipath_dev_err(dd, "Unable to allocate portdata array, "
255                               "failing\n");
256                 ret = -ENOMEM;
257                 goto done;
258         }
259
260         dd->ipath_lastegrheads = kzalloc(sizeof(*dd->ipath_lastegrheads)
261                                          * dd->ipath_cfgports,
262                                          GFP_KERNEL);
263         dd->ipath_lastrcvhdrqtails =
264                 kzalloc(sizeof(*dd->ipath_lastrcvhdrqtails)
265                         * dd->ipath_cfgports, GFP_KERNEL);
266
267         if (!dd->ipath_lastegrheads || !dd->ipath_lastrcvhdrqtails) {
268                 ipath_dev_err(dd, "Unable to allocate head arrays, "
269                               "failing\n");
270                 ret = -ENOMEM;
271                 goto done;
272         }
273
274         dd->ipath_pd[0] = kzalloc(sizeof(*pd), GFP_KERNEL);
275
276         if (!dd->ipath_pd[0]) {
277                 ipath_dev_err(dd, "Unable to allocate portdata for port "
278                               "0, failing\n");
279                 ret = -ENOMEM;
280                 goto done;
281         }
282         pd = dd->ipath_pd[0];
283         pd->port_dd = dd;
284         pd->port_port = 0;
285         pd->port_cnt = 1;
286         /* The port 0 pkey table is used by the layer interface. */
287         pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
288         dd->ipath_rcvtidcnt =
289                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
290         dd->ipath_rcvtidbase =
291                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
292         dd->ipath_rcvegrcnt =
293                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
294         dd->ipath_rcvegrbase =
295                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
296         dd->ipath_palign =
297                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
298         dd->ipath_piobufbase =
299                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
300         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
301         dd->ipath_piosize2k = val & ~0U;
302         dd->ipath_piosize4k = val >> 32;
303         dd->ipath_ibmtu = 4096; /* default to largest legal MTU */
304         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
305         dd->ipath_piobcnt2k = val & ~0U;
306         dd->ipath_piobcnt4k = val >> 32;
307         dd->ipath_pio2kbase =
308                 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
309                                  (dd->ipath_piobufbase & 0xffffffff));
310         if (dd->ipath_piobcnt4k) {
311                 dd->ipath_pio4kbase = (u32 __iomem *)
312                         (((char __iomem *) dd->ipath_kregbase) +
313                          (dd->ipath_piobufbase >> 32));
314                 /*
315                  * 4K buffers take 2 pages; we use roundup just to be
316                  * paranoid; we calculate it once here, rather than on
317                  * ever buf allocate
318                  */
319                 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
320                                           dd->ipath_palign);
321                 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
322                           "(%x aligned)\n",
323                           dd->ipath_piobcnt2k, dd->ipath_piosize2k,
324                           dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
325                           dd->ipath_piosize4k, dd->ipath_pio4kbase,
326                           dd->ipath_4kalign);
327         }
328         else ipath_dbg("%u 2k piobufs @ %p\n",
329                        dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
330
331         spin_lock_init(&dd->ipath_tid_lock);
332
333 done:
334         *pdp = pd;
335         return ret;
336 }
337
338 /**
339  * init_chip_reset - re-initialize after a reset, or enable
340  * @dd: the infinipath device
341  * @pdp: output for port data
342  *
343  * sanity check at least some of the values after reset, and
344  * ensure no receive or transmit (explictly, in case reset
345  * failed
346  */
347 static int init_chip_reset(struct ipath_devdata *dd,
348                            struct ipath_portdata **pdp)
349 {
350         struct ipath_portdata *pd;
351         u32 rtmp;
352
353         *pdp = pd = dd->ipath_pd[0];
354         /* ensure chip does no sends or receives while we re-initialize */
355         dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U;
356         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, 0);
357         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 0);
358         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0);
359
360         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
361         if (dd->ipath_portcnt != rtmp)
362                 dev_info(&dd->pcidev->dev, "portcnt was %u before "
363                          "reset, now %u, using original\n",
364                          dd->ipath_portcnt, rtmp);
365         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
366         if (rtmp != dd->ipath_rcvtidcnt)
367                 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
368                          "reset, now %u, using original\n",
369                          dd->ipath_rcvtidcnt, rtmp);
370         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
371         if (rtmp != dd->ipath_rcvtidbase)
372                 dev_info(&dd->pcidev->dev, "tidbase was %u before "
373                          "reset, now %u, using original\n",
374                          dd->ipath_rcvtidbase, rtmp);
375         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
376         if (rtmp != dd->ipath_rcvegrcnt)
377                 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
378                          "reset, now %u, using original\n",
379                          dd->ipath_rcvegrcnt, rtmp);
380         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
381         if (rtmp != dd->ipath_rcvegrbase)
382                 dev_info(&dd->pcidev->dev, "egrbase was %u before "
383                          "reset, now %u, using original\n",
384                          dd->ipath_rcvegrbase, rtmp);
385
386         return 0;
387 }
388
389 static int init_pioavailregs(struct ipath_devdata *dd)
390 {
391         int ret;
392
393         dd->ipath_pioavailregs_dma = dma_alloc_coherent(
394                 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
395                 GFP_KERNEL);
396         if (!dd->ipath_pioavailregs_dma) {
397                 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
398                               "in memory\n");
399                 ret = -ENOMEM;
400                 goto done;
401         }
402
403         /*
404          * we really want L2 cache aligned, but for current CPUs of
405          * interest, they are the same.
406          */
407         dd->ipath_statusp = (u64 *)
408                 ((char *)dd->ipath_pioavailregs_dma +
409                  ((2 * L1_CACHE_BYTES +
410                    dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
411         /* copy the current value now that it's really allocated */
412         *dd->ipath_statusp = dd->_ipath_status;
413         /*
414          * setup buffer to hold freeze msg, accessible to apps,
415          * following statusp
416          */
417         dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
418         /* and its length */
419         dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
420
421         ret = 0;
422
423 done:
424         return ret;
425 }
426
427 /**
428  * init_shadow_tids - allocate the shadow TID array
429  * @dd: the infinipath device
430  *
431  * allocate the shadow TID array, so we can ipath_munlock previous
432  * entries.  It may make more sense to move the pageshadow to the
433  * port data structure, so we only allocate memory for ports actually
434  * in use, since we at 8k per port, now.
435  */
436 static void init_shadow_tids(struct ipath_devdata *dd)
437 {
438         struct page **pages;
439         dma_addr_t *addrs;
440
441         pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
442                         sizeof(struct page *));
443         if (!pages) {
444                 ipath_dev_err(dd, "failed to allocate shadow page * "
445                               "array, no expected sends!\n");
446                 dd->ipath_pageshadow = NULL;
447                 return;
448         }
449
450         addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
451                         sizeof(dma_addr_t));
452         if (!addrs) {
453                 ipath_dev_err(dd, "failed to allocate shadow dma handle "
454                               "array, no expected sends!\n");
455                 vfree(dd->ipath_pageshadow);
456                 dd->ipath_pageshadow = NULL;
457                 return;
458         }
459
460         memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt *
461                sizeof(struct page *));
462
463         dd->ipath_pageshadow = pages;
464         dd->ipath_physshadow = addrs;
465 }
466
467 static void enable_chip(struct ipath_devdata *dd,
468                         struct ipath_portdata *pd, int reinit)
469 {
470         u32 val;
471         int i;
472
473         if (!reinit)
474                 init_waitqueue_head(&ipath_state_wait);
475
476         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
477                          dd->ipath_rcvctrl);
478
479         /* Enable PIO send, and update of PIOavail regs to memory. */
480         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
481                 INFINIPATH_S_PIOBUFAVAILUPD;
482         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
483                          dd->ipath_sendctrl);
484
485         /*
486          * enable port 0 receive, and receive interrupt.  other ports
487          * done as user opens and inits them.
488          */
489         dd->ipath_rcvctrl = INFINIPATH_R_TAILUPD |
490                 (1ULL << INFINIPATH_R_PORTENABLE_SHIFT) |
491                 (1ULL << INFINIPATH_R_INTRAVAIL_SHIFT);
492         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
493                          dd->ipath_rcvctrl);
494
495         /*
496          * now ready for use.  this should be cleared whenever we
497          * detect a reset, or initiate one.
498          */
499         dd->ipath_flags |= IPATH_INITTED;
500
501         /*
502          * init our shadow copies of head from tail values, and write
503          * head values to match.
504          */
505         val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
506         (void)ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
507         dd->ipath_port0head = ipath_read_ureg32(dd, ur_rcvhdrtail, 0);
508
509         /* Initialize so we interrupt on next packet received */
510         (void)ipath_write_ureg(dd, ur_rcvhdrhead,
511                                dd->ipath_rhdrhead_intr_off |
512                                dd->ipath_port0head, 0);
513
514         /*
515          * by now pioavail updates to memory should have occurred, so
516          * copy them into our working/shadow registers; this is in
517          * case something went wrong with abort, but mostly to get the
518          * initial values of the generation bit correct.
519          */
520         for (i = 0; i < dd->ipath_pioavregs; i++) {
521                 __le64 val;
522
523                 /*
524                  * Chip Errata bug 6641; even and odd qwords>3 are swapped.
525                  */
526                 if (i > 3) {
527                         if (i & 1)
528                                 val = dd->ipath_pioavailregs_dma[i - 1];
529                         else
530                                 val = dd->ipath_pioavailregs_dma[i + 1];
531                 }
532                 else
533                         val = dd->ipath_pioavailregs_dma[i];
534                 dd->ipath_pioavailshadow[i] = le64_to_cpu(val);
535         }
536         /* can get counters, stats, etc. */
537         dd->ipath_flags |= IPATH_PRESENT;
538 }
539
540 static int init_housekeeping(struct ipath_devdata *dd,
541                              struct ipath_portdata **pdp, int reinit)
542 {
543         char boardn[32];
544         int ret = 0;
545
546         /*
547          * have to clear shadow copies of registers at init that are
548          * not otherwise set here, or all kinds of bizarre things
549          * happen with driver on chip reset
550          */
551         dd->ipath_rcvhdrsize = 0;
552
553         /*
554          * Don't clear ipath_flags as 8bit mode was set before
555          * entering this func. However, we do set the linkstate to
556          * unknown, so we can watch for a transition.
557          * PRESENT is set because we want register reads to work,
558          * and the kernel infrastructure saw it in config space;
559          * We clear it if we have failures.
560          */
561         dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
562         dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
563                              IPATH_LINKDOWN | IPATH_LINKINIT);
564
565         ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
566         dd->ipath_revision =
567                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
568
569         /*
570          * set up fundamental info we need to use the chip; we assume
571          * if the revision reg and these regs are OK, we don't need to
572          * special case the rest
573          */
574         dd->ipath_sregbase =
575                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
576         dd->ipath_cregbase =
577                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
578         dd->ipath_uregbase =
579                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
580         ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
581                    "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
582                    dd->ipath_uregbase, dd->ipath_cregbase);
583         if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
584             || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
585             || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
586             || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
587                 ipath_dev_err(dd, "Register read failures from chip, "
588                               "giving up initialization\n");
589                 dd->ipath_flags &= ~IPATH_PRESENT;
590                 ret = -ENODEV;
591                 goto done;
592         }
593
594         /* clear the initial reset flag, in case first driver load */
595         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
596                          INFINIPATH_E_RESET);
597
598         if (reinit)
599                 ret = init_chip_reset(dd, pdp);
600         else
601                 ret = init_chip_first(dd, pdp);
602
603         if (ret)
604                 goto done;
605
606         ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, "
607                    "%u egrtids\n", (unsigned long long) dd->ipath_revision,
608                    dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt,
609                    dd->ipath_rcvegrcnt);
610
611         if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
612              INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
613                 ipath_dev_err(dd, "Driver only handles version %d, "
614                               "chip swversion is %d (%llx), failng\n",
615                               IPATH_CHIP_SWVERSION,
616                               (int)(dd->ipath_revision >>
617                                     INFINIPATH_R_SOFTWARE_SHIFT) &
618                               INFINIPATH_R_SOFTWARE_MASK,
619                               (unsigned long long) dd->ipath_revision);
620                 ret = -ENOSYS;
621                 goto done;
622         }
623         dd->ipath_majrev = (u8) ((dd->ipath_revision >>
624                                   INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
625                                  INFINIPATH_R_CHIPREVMAJOR_MASK);
626         dd->ipath_minrev = (u8) ((dd->ipath_revision >>
627                                   INFINIPATH_R_CHIPREVMINOR_SHIFT) &
628                                  INFINIPATH_R_CHIPREVMINOR_MASK);
629         dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
630                                     INFINIPATH_R_BOARDID_SHIFT) &
631                                    INFINIPATH_R_BOARDID_MASK);
632
633         ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
634
635         snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
636                  "Driver %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
637                  "SW Compat %u\n",
638                  IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
639                  (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
640                  INFINIPATH_R_ARCH_MASK,
641                  dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
642                  (unsigned)(dd->ipath_revision >>
643                             INFINIPATH_R_SOFTWARE_SHIFT) &
644                  INFINIPATH_R_SOFTWARE_MASK);
645
646         ipath_dbg("%s", dd->ipath_boardversion);
647
648 done:
649         return ret;
650 }
651
652
653 /**
654  * ipath_init_chip - do the actual initialization sequence on the chip
655  * @dd: the infinipath device
656  * @reinit: reinitializing, so don't allocate new memory
657  *
658  * Do the actual initialization sequence on the chip.  This is done
659  * both from the init routine called from the PCI infrastructure, and
660  * when we reset the chip, or detect that it was reset internally,
661  * or it's administratively re-enabled.
662  *
663  * Memory allocation here and in called routines is only done in
664  * the first case (reinit == 0).  We have to be careful, because even
665  * without memory allocation, we need to re-write all the chip registers
666  * TIDs, etc. after the reset or enable has completed.
667  */
668 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
669 {
670         int ret = 0, i;
671         u32 val32, kpiobufs;
672         u64 val;
673         struct ipath_portdata *pd = NULL; /* keep gcc4 happy */
674         gfp_t gfp_flags = GFP_USER | __GFP_COMP;
675
676         ret = init_housekeeping(dd, &pd, reinit);
677         if (ret)
678                 goto done;
679
680         /*
681          * we ignore most issues after reporting them, but have to specially
682          * handle hardware-disabled chips.
683          */
684         if (ret == 2) {
685                 /* unique error, known to ipath_init_one */
686                 ret = -EPERM;
687                 goto done;
688         }
689
690         /*
691          * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
692          * but then it no longer nicely fits power of two, and since
693          * we now use routines that backend onto __get_free_pages, the
694          * rest would be wasted.
695          */
696         dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt;
697         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
698                          dd->ipath_rcvhdrcnt);
699
700         /*
701          * Set up the shadow copies of the piobufavail registers,
702          * which we compare against the chip registers for now, and
703          * the in memory DMA'ed copies of the registers.  This has to
704          * be done early, before we calculate lastport, etc.
705          */
706         val = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
707         /*
708          * calc number of pioavail registers, and save it; we have 2
709          * bits per buffer.
710          */
711         dd->ipath_pioavregs = ALIGN(val, sizeof(u64) * BITS_PER_BYTE / 2)
712                 / (sizeof(u64) * BITS_PER_BYTE / 2);
713         if (ipath_kpiobufs == 0) {
714                 /* not set by user (this is default) */
715                 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) > 128)
716                         kpiobufs = 32;
717                 else
718                         kpiobufs = 16;
719         }
720         else
721                 kpiobufs = ipath_kpiobufs;
722
723         if (kpiobufs >
724             (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
725              (dd->ipath_cfgports * IPATH_MIN_USER_PORT_BUFCNT))) {
726                 i = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
727                         (dd->ipath_cfgports * IPATH_MIN_USER_PORT_BUFCNT);
728                 if (i < 0)
729                         i = 0;
730                 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs for "
731                          "kernel leaves too few for %d user ports "
732                          "(%d each); using %u\n", kpiobufs,
733                          dd->ipath_cfgports - 1,
734                          IPATH_MIN_USER_PORT_BUFCNT, i);
735                 /*
736                  * shouldn't change ipath_kpiobufs, because could be
737                  * different for different devices...
738                  */
739                 kpiobufs = i;
740         }
741         dd->ipath_lastport_piobuf =
742                 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - kpiobufs;
743         dd->ipath_pbufsport = dd->ipath_cfgports > 1
744                 ? dd->ipath_lastport_piobuf / (dd->ipath_cfgports - 1)
745                 : 0;
746         val32 = dd->ipath_lastport_piobuf -
747                 (dd->ipath_pbufsport * (dd->ipath_cfgports - 1));
748         if (val32 > 0) {
749                 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
750                           "add to kernel\n", dd->ipath_pbufsport, val32);
751                 dd->ipath_lastport_piobuf -= val32;
752                 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
753                           dd->ipath_pbufsport, val32);
754         }
755         dd->ipath_lastpioindex = dd->ipath_lastport_piobuf;
756         ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
757                    "each for %u user ports\n", kpiobufs,
758                    dd->ipath_piobcnt2k + dd->ipath_piobcnt4k,
759                    dd->ipath_pbufsport, dd->ipath_cfgports - 1);
760
761         dd->ipath_f_early_init(dd);
762
763         /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
764          * done after early_init */
765         dd->ipath_hdrqlast =
766                 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
767         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
768                          dd->ipath_rcvhdrentsize);
769         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
770                          dd->ipath_rcvhdrsize);
771
772         if (!reinit) {
773                 ret = init_pioavailregs(dd);
774                 init_shadow_tids(dd);
775                 if (ret)
776                         goto done;
777         }
778
779         (void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
780                                dd->ipath_pioavailregs_phys);
781         /*
782          * this is to detect s/w errors, which the h/w works around by
783          * ignoring the low 6 bits of address, if it wasn't aligned.
784          */
785         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
786         if (val != dd->ipath_pioavailregs_phys) {
787                 ipath_dev_err(dd, "Catastrophic software error, "
788                               "SendPIOAvailAddr written as %lx, "
789                               "read back as %llx\n",
790                               (unsigned long) dd->ipath_pioavailregs_phys,
791                               (unsigned long long) val);
792                 ret = -EINVAL;
793                 goto done;
794         }
795
796         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
797
798         /*
799          * make sure we are not in freeze, and PIO send enabled, so
800          * writes to pbc happen
801          */
802         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
803         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
804                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
805         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
806         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
807                          INFINIPATH_S_PIOENABLE);
808
809         /*
810          * before error clears, since we expect serdes pll errors during
811          * this, the first time after reset
812          */
813         if (bringup_link(dd)) {
814                 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
815                 ret = -ENETDOWN;
816                 goto done;
817         }
818
819         /*
820          * clear any "expected" hwerrs from reset and/or initialization
821          * clear any that aren't enabled (at least this once), and then
822          * set the enable mask
823          */
824         dd->ipath_f_init_hwerrors(dd);
825         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
826                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
827         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
828                          dd->ipath_hwerrmask);
829
830         dd->ipath_maskederrs = dd->ipath_ignorederrs;
831         /* clear all */
832         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
833         /* enable errors that are masked, at least this first time. */
834         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
835                          ~dd->ipath_maskederrs);
836         /* clear any interrups up to this point (ints still not enabled) */
837         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
838
839         /*
840          * Set up the port 0 (kernel) rcvhdr q and egr TIDs.  If doing
841          * re-init, the simplest way to handle this is to free
842          * existing, and re-allocate.
843          */
844         if (reinit) {
845                 struct ipath_portdata *pd = dd->ipath_pd[0];
846                 dd->ipath_pd[0] = NULL;
847                 ipath_free_pddata(dd, pd);
848         }
849         dd->ipath_f_tidtemplate(dd);
850         ret = ipath_create_rcvhdrq(dd, pd);
851         if (!ret) {
852                 dd->ipath_hdrqtailptr =
853                         (volatile __le64 *)pd->port_rcvhdrtail_kvaddr;
854                 ret = create_port0_egr(dd);
855         }
856         if (ret)
857                 ipath_dev_err(dd, "failed to allocate port 0 (kernel) "
858                               "rcvhdrq and/or egr bufs\n");
859         else
860                 enable_chip(dd, pd, reinit);
861
862
863         if (!ret && !reinit) {
864             /* used when we close a port, for DMA already in flight at close */
865                 dd->ipath_dummy_hdrq = dma_alloc_coherent(
866                         &dd->pcidev->dev, pd->port_rcvhdrq_size,
867                         &dd->ipath_dummy_hdrq_phys,
868                         gfp_flags);
869                 if (!dd->ipath_dummy_hdrq ) {
870                         dev_info(&dd->pcidev->dev,
871                                 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
872                                 pd->port_rcvhdrq_size);
873                         /* fallback to just 0'ing */
874                         dd->ipath_dummy_hdrq_phys = 0UL;
875                 }
876         }
877
878         /*
879          * cause retrigger of pending interrupts ignored during init,
880          * even if we had errors
881          */
882         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
883
884         if(!dd->ipath_stats_timer_active) {
885                 /*
886                  * first init, or after an admin disable/enable
887                  * set up stats retrieval timer, even if we had errors
888                  * in last portion of setup
889                  */
890                 init_timer(&dd->ipath_stats_timer);
891                 dd->ipath_stats_timer.function = ipath_get_faststats;
892                 dd->ipath_stats_timer.data = (unsigned long) dd;
893                 /* every 5 seconds; */
894                 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
895                 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
896                 add_timer(&dd->ipath_stats_timer);
897                 dd->ipath_stats_timer_active = 1;
898         }
899
900 done:
901         if (!ret) {
902                 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
903                 if (!dd->ipath_f_intrsetup(dd)) {
904                         /* now we can enable all interrupts from the chip */
905                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
906                                          -1LL);
907                         /* force re-interrupt of any pending interrupts. */
908                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
909                                          0ULL);
910                         /* chip is usable; mark it as initialized */
911                         *dd->ipath_statusp |= IPATH_STATUS_INITTED;
912                 } else
913                         ipath_dev_err(dd, "No interrupts enabled, couldn't "
914                                       "setup interrupt address\n");
915
916                 if (dd->ipath_cfgports > ipath_stats.sps_nports)
917                         /*
918                          * sps_nports is a global, so, we set it to
919                          * the highest number of ports of any of the
920                          * chips we find; we never decrement it, at
921                          * least for now.  Since this might have changed
922                          * over disable/enable or prior to reset, always
923                          * do the check and potentially adjust.
924                          */
925                         ipath_stats.sps_nports = dd->ipath_cfgports;
926         } else
927                 ipath_dbg("Failed (%d) to initialize chip\n", ret);
928
929         /* if ret is non-zero, we probably should do some cleanup
930            here... */
931         return ret;
932 }
933
934 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
935 {
936         struct ipath_devdata *dd;
937         unsigned long flags;
938         unsigned short val;
939         int ret;
940
941         ret = ipath_parse_ushort(str, &val);
942
943         spin_lock_irqsave(&ipath_devs_lock, flags);
944
945         if (ret < 0)
946                 goto bail;
947
948         if (val == 0) {
949                 ret = -EINVAL;
950                 goto bail;
951         }
952
953         list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
954                 if (dd->ipath_kregbase)
955                         continue;
956                 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
957                            (dd->ipath_cfgports *
958                             IPATH_MIN_USER_PORT_BUFCNT)))
959                 {
960                         ipath_dev_err(
961                                 dd,
962                                 "Allocating %d PIO bufs for kernel leaves "
963                                 "too few for %d user ports (%d each)\n",
964                                 val, dd->ipath_cfgports - 1,
965                                 IPATH_MIN_USER_PORT_BUFCNT);
966                         ret = -EINVAL;
967                         goto bail;
968                 }
969                 dd->ipath_lastport_piobuf =
970                         dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
971         }
972
973         ipath_kpiobufs = val;
974         ret = 0;
975 bail:
976         spin_unlock_irqrestore(&ipath_devs_lock, flags);
977
978         return ret;
979 }