git.oblomov.eu Git - linux-2.6/blob - arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * File:         arch/blackfin/mach-common/ints-priority.c
   3  *
   4  * Description:  Set up the interrupt priorities
   5  *
   6  * Modified:
   7  *               1996 Roman Zippel
   8  *               1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *               2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
  10  *               2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
  11  *               2003 Metrowerks/Motorola
  12  *               2003 Bas Vermeulen <bas@buyways.nl>
  13  *               Copyright 2004-2008 Analog Devices Inc.
  14  *
  15  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License as published by
  19  * the Free Software Foundation; either version 2 of the License, or
  20  * (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, see the file COPYING, or write
  29  * to the Free Software Foundation, Inc.,
  30  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  31  */
  32
  33 #include <linux/module.h>
  34 #include <linux/kernel_stat.h>
  35 #include <linux/seq_file.h>
  36 #include <linux/irq.h>
  37 #ifdef CONFIG_KGDB
  38 #include <linux/kgdb.h>
  39 #endif
  40 #include <asm/traps.h>
  41 #include <asm/blackfin.h>
  42 #include <asm/gpio.h>
  43 #include <asm/irq_handler.h>
  44
  45 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
  46
  47 #ifdef BF537_FAMILY
  48 # define BF537_GENERIC_ERROR_INT_DEMUX
  49 #else
  50 # undef BF537_GENERIC_ERROR_INT_DEMUX
  51 #endif
  52
  53 /*
  54  * NOTES:
  55  * - we have separated the physical Hardware interrupt from the
  56  * levels that the LINUX kernel sees (see the description in irq.h)
  57  * -
  58  */
  59
  60 #ifndef CONFIG_SMP
  61 /* Initialize this to an actual value to force it into the .data
  62  * section so that we know it is properly initialized at entry into
  63  * the kernel but before bss is initialized to zero (which is where
  64  * it would live otherwise).  The 0x1f magic represents the IRQs we
  65  * cannot actually mask out in hardware.
  66  */
  67 unsigned long bfin_irq_flags = 0x1f;
  68 EXPORT_SYMBOL(bfin_irq_flags);
  69 #endif
  70
  71 /* The number of spurious interrupts */
  72 atomic_t num_spurious;
  73
  74 #ifdef CONFIG_PM
  75 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  76 unsigned vr_wakeup;
  77 #endif
  78
  79 struct ivgx {
  80         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  81         unsigned int irqno;
  82         /* corresponding bit in the SIC_ISR register */
  83         unsigned int isrflag;
  84 } ivg_table[NR_PERI_INTS];
  85
  86 struct ivg_slice {
  87         /* position of first irq in ivg_table for given ivg */
  88         struct ivgx *ifirst;
  89         struct ivgx *istop;
  90 } ivg7_13[IVG13 - IVG7 + 1];
  91
  92
  93 /*
  94  * Search SIC_IAR and fill tables with the irqvalues
  95  * and their positions in the SIC_ISR register.
  96  */
  97 static void __init search_IAR(void)
  98 {
  99         unsigned ivg, irq_pos = 0;
 100         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
 101                 int irqn;
 102
 103                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
 104
 105                 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
 106                         int iar_shift = (irqn & 7) * 4;
 107                                 if (ivg == (0xf &
 108 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
 109         || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
 110                              bfin_read32((unsigned long *)SIC_IAR0 +
 111                                          ((irqn % 32) >> 3) + ((irqn / 32) *
 112                                          ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
 113 #else
 114                              bfin_read32((unsigned long *)SIC_IAR0 +
 115                                          (irqn >> 3)) >> iar_shift)) {
 116 #endif
 117                                 ivg_table[irq_pos].irqno = IVG7 + irqn;
 118                                 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
 119                                 ivg7_13[ivg].istop++;
 120                                 irq_pos++;
 121                         }
 122                 }
 123         }
 124 }
 125
 126 /*
 127  * This is for core internal IRQs
 128  */
 129
 130 static void bfin_ack_noop(unsigned int irq)
 131 {
 132         /* Dummy function.  */
 133 }
 134
 135 static void bfin_core_mask_irq(unsigned int irq)
 136 {
 137         bfin_irq_flags &= ~(1 << irq);
 138         if (!irqs_disabled())
 139                 local_irq_enable();
 140 }
 141
 142 static void bfin_core_unmask_irq(unsigned int irq)
 143 {
 144         bfin_irq_flags |= 1 << irq;
 145         /*
 146          * If interrupts are enabled, IMASK must contain the same value
 147          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 148          * are currently disabled we need not do anything; one of the
 149          * callers will take care of setting IMASK to the proper value
 150          * when reenabling interrupts.
 151          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 152          * what we need.
 153          */
 154         if (!irqs_disabled())
 155                 local_irq_enable();
 156         return;
 157 }
 158
 159 static void bfin_internal_mask_irq(unsigned int irq)
 160 {
 161 #ifdef CONFIG_BF53x
 162         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 163                              ~(1 << SIC_SYSIRQ(irq)));
 164 #else
 165         unsigned mask_bank, mask_bit;
 166         mask_bank = SIC_SYSIRQ(irq) / 32;
 167         mask_bit = SIC_SYSIRQ(irq) % 32;
 168         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 169                              ~(1 << mask_bit));
 170 #ifdef CONFIG_SMP
 171         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 172                              ~(1 << mask_bit));
 173 #endif
 174 #endif
 175 }
 176
 177 static void bfin_internal_unmask_irq(unsigned int irq)
 178 {
 179 #ifdef CONFIG_BF53x
 180         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 181                              (1 << SIC_SYSIRQ(irq)));
 182 #else
 183         unsigned mask_bank, mask_bit;
 184         mask_bank = SIC_SYSIRQ(irq) / 32;
 185         mask_bit = SIC_SYSIRQ(irq) % 32;
 186         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
 187                              (1 << mask_bit));
 188 #ifdef CONFIG_SMP
 189         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
 190                              (1 << mask_bit));
 191 #endif
 192 #endif
 193 }
 194
 195 #ifdef CONFIG_PM
 196 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 197 {
 198         u32 bank, bit, wakeup = 0;
 199         unsigned long flags;
 200         bank = SIC_SYSIRQ(irq) / 32;
 201         bit = SIC_SYSIRQ(irq) % 32;
 202
 203         switch (irq) {
 204 #ifdef IRQ_RTC
 205         case IRQ_RTC:
 206         wakeup |= WAKE;
 207         break;
 208 #endif
 209 #ifdef IRQ_CAN0_RX
 210         case IRQ_CAN0_RX:
 211         wakeup |= CANWE;
 212         break;
 213 #endif
 214 #ifdef IRQ_CAN1_RX
 215         case IRQ_CAN1_RX:
 216         wakeup |= CANWE;
 217         break;
 218 #endif
 219 #ifdef IRQ_USB_INT0
 220         case IRQ_USB_INT0:
 221         wakeup |= USBWE;
 222         break;
 223 #endif
 224 #ifdef IRQ_KEY
 225         case IRQ_KEY:
 226         wakeup |= KPADWE;
 227         break;
 228 #endif
 229 #ifdef CONFIG_BF54x
 230         case IRQ_CNT:
 231         wakeup |= ROTWE;
 232         break;
 233 #endif
 234         default:
 235         break;
 236         }
 237
 238         local_irq_save(flags);
 239
 240         if (state) {
 241                 bfin_sic_iwr[bank] |= (1 << bit);
 242                 vr_wakeup  |= wakeup;
 243
 244         } else {
 245                 bfin_sic_iwr[bank] &= ~(1 << bit);
 246                 vr_wakeup  &= ~wakeup;
 247         }
 248
 249         local_irq_restore(flags);
 250
 251         return 0;
 252 }
 253 #endif
 254
 255 static struct irq_chip bfin_core_irqchip = {
 256         .name = "CORE",
 257         .ack = bfin_ack_noop,
 258         .mask = bfin_core_mask_irq,
 259         .unmask = bfin_core_unmask_irq,
 260 };
 261
 262 static struct irq_chip bfin_internal_irqchip = {
 263         .name = "INTN",
 264         .ack = bfin_ack_noop,
 265         .mask = bfin_internal_mask_irq,
 266         .unmask = bfin_internal_unmask_irq,
 267         .mask_ack = bfin_internal_mask_irq,
 268         .disable = bfin_internal_mask_irq,
 269         .enable = bfin_internal_unmask_irq,
 270 #ifdef CONFIG_PM
 271         .set_wake = bfin_internal_set_wake,
 272 #endif
 273 };
 274
 275 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
 276 static int error_int_mask;
 277
 278 static void bfin_generic_error_mask_irq(unsigned int irq)
 279 {
 280         error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
 281
 282         if (!error_int_mask)
 283                 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
 284 }
 285
 286 static void bfin_generic_error_unmask_irq(unsigned int irq)
 287 {
 288         bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
 289         error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
 290 }
 291
 292 static struct irq_chip bfin_generic_error_irqchip = {
 293         .name = "ERROR",
 294         .ack = bfin_ack_noop,
 295         .mask_ack = bfin_generic_error_mask_irq,
 296         .mask = bfin_generic_error_mask_irq,
 297         .unmask = bfin_generic_error_unmask_irq,
 298 };
 299
 300 static void bfin_demux_error_irq(unsigned int int_err_irq,
 301                                  struct irq_desc *inta_desc)
 302 {
 303         int irq = 0;
 304
 305 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 306         if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
 307                 irq = IRQ_MAC_ERROR;
 308         else
 309 #endif
 310         if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
 311                 irq = IRQ_SPORT0_ERROR;
 312         else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
 313                 irq = IRQ_SPORT1_ERROR;
 314         else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
 315                 irq = IRQ_PPI_ERROR;
 316         else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
 317                 irq = IRQ_CAN_ERROR;
 318         else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
 319                 irq = IRQ_SPI_ERROR;
 320         else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
 321                  (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
 322                 irq = IRQ_UART0_ERROR;
 323         else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
 324                  (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
 325                 irq = IRQ_UART1_ERROR;
 326
 327         if (irq) {
 328                 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
 329                         struct irq_desc *desc = irq_desc + irq;
 330                         desc->handle_irq(irq, desc);
 331                 } else {
 332
 333                         switch (irq) {
 334                         case IRQ_PPI_ERROR:
 335                                 bfin_write_PPI_STATUS(PPI_ERR_MASK);
 336                                 break;
 337 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 338                         case IRQ_MAC_ERROR:
 339                                 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
 340                                 break;
 341 #endif
 342                         case IRQ_SPORT0_ERROR:
 343                                 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
 344                                 break;
 345
 346                         case IRQ_SPORT1_ERROR:
 347                                 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
 348                                 break;
 349
 350                         case IRQ_CAN_ERROR:
 351                                 bfin_write_CAN_GIS(CAN_ERR_MASK);
 352                                 break;
 353
 354                         case IRQ_SPI_ERROR:
 355                                 bfin_write_SPI_STAT(SPI_ERR_MASK);
 356                                 break;
 357
 358                         default:
 359                                 break;
 360                         }
 361
 362                         pr_debug("IRQ %d:"
 363                                  " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
 364                                  irq);
 365                 }
 366         } else
 367                 printk(KERN_ERR
 368                        "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
 369                        " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
 370                        __func__, __FILE__, __LINE__);
 371
 372 }
 373 #endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
 374
 375 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 376 {
 377         struct irq_desc *desc = irq_desc + irq;
 378         /* May not call generic set_irq_handler() due to spinlock
 379            recursion. */
 380         desc->handle_irq = handle;
 381 }
 382
 383 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 384 extern void bfin_gpio_irq_prepare(unsigned gpio);
 385
 386 #if !defined(CONFIG_BF54x)
 387
 388 static void bfin_gpio_ack_irq(unsigned int irq)
 389 {
 390         /* AFAIK ack_irq in case mask_ack is provided
 391          * get's only called for edge sense irqs
 392          */
 393         set_gpio_data(irq_to_gpio(irq), 0);
 394 }
 395
 396 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 397 {
 398         struct irq_desc *desc = irq_desc + irq;
 399         u32 gpionr = irq_to_gpio(irq);
 400
 401         if (desc->handle_irq == handle_edge_irq)
 402                 set_gpio_data(gpionr, 0);
 403
 404         set_gpio_maska(gpionr, 0);
 405 }
 406
 407 static void bfin_gpio_mask_irq(unsigned int irq)
 408 {
 409         set_gpio_maska(irq_to_gpio(irq), 0);
 410 }
 411
 412 static void bfin_gpio_unmask_irq(unsigned int irq)
 413 {
 414         set_gpio_maska(irq_to_gpio(irq), 1);
 415 }
 416
 417 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 418 {
 419         u32 gpionr = irq_to_gpio(irq);
 420
 421         if (__test_and_set_bit(gpionr, gpio_enabled))
 422                 bfin_gpio_irq_prepare(gpionr);
 423
 424         bfin_gpio_unmask_irq(irq);
 425
 426         return 0;
 427 }
 428
 429 static void bfin_gpio_irq_shutdown(unsigned int irq)
 430 {
 431         u32 gpionr = irq_to_gpio(irq);
 432
 433         bfin_gpio_mask_irq(irq);
 434         __clear_bit(gpionr, gpio_enabled);
 435         bfin_gpio_irq_free(gpionr);
 436 }
 437
 438 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 439 {
 440         int ret;
 441         char buf[16];
 442         u32 gpionr = irq_to_gpio(irq);
 443
 444         if (type == IRQ_TYPE_PROBE) {
 445                 /* only probe unenabled GPIO interrupt lines */
 446                 if (__test_bit(gpionr, gpio_enabled))
 447                         return 0;
 448                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 449         }
 450
 451         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 452                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 453
 454                 snprintf(buf, 16, "gpio-irq%d", irq);
 455                 ret = bfin_gpio_irq_request(gpionr, buf);
 456                 if (ret)
 457                         return ret;
 458
 459                 if (__test_and_set_bit(gpionr, gpio_enabled))
 460                         bfin_gpio_irq_prepare(gpionr);
 461
 462         } else {
 463                 __clear_bit(gpionr, gpio_enabled);
 464                 return 0;
 465         }
 466
 467         set_gpio_inen(gpionr, 0);
 468         set_gpio_dir(gpionr, 0);
 469
 470         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 471             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 472                 set_gpio_both(gpionr, 1);
 473         else
 474                 set_gpio_both(gpionr, 0);
 475
 476         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 477                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 478         else
 479                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 480
 481         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 482                 set_gpio_edge(gpionr, 1);
 483                 set_gpio_inen(gpionr, 1);
 484                 set_gpio_data(gpionr, 0);
 485
 486         } else {
 487                 set_gpio_edge(gpionr, 0);
 488                 set_gpio_inen(gpionr, 1);
 489         }
 490
 491         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 492                 bfin_set_irq_handler(irq, handle_edge_irq);
 493         else
 494                 bfin_set_irq_handler(irq, handle_level_irq);
 495
 496         return 0;
 497 }
 498
 499 #ifdef CONFIG_PM
 500 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 501 {
 502         unsigned gpio = irq_to_gpio(irq);
 503
 504         if (state)
 505                 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
 506         else
 507                 gpio_pm_wakeup_free(gpio);
 508
 509         return 0;
 510 }
 511 #endif
 512
 513 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 514                                 struct irq_desc *desc)
 515 {
 516         unsigned int i, gpio, mask, irq, search = 0;
 517
 518         switch (inta_irq) {
 519 #if defined(CONFIG_BF53x)
 520         case IRQ_PROG_INTA:
 521                 irq = IRQ_PF0;
 522                 search = 1;
 523                 break;
 524 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
 525         case IRQ_MAC_RX:
 526                 irq = IRQ_PH0;
 527                 break;
 528 # endif
 529 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
 530         case IRQ_PORTF_INTA:
 531                 irq = IRQ_PF0;
 532                 break;
 533 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 534         case IRQ_PORTF_INTA:
 535                 irq = IRQ_PF0;
 536                 break;
 537         case IRQ_PORTG_INTA:
 538                 irq = IRQ_PG0;
 539                 break;
 540         case IRQ_PORTH_INTA:
 541                 irq = IRQ_PH0;
 542                 break;
 543 #elif defined(CONFIG_BF561)
 544         case IRQ_PROG0_INTA:
 545                 irq = IRQ_PF0;
 546                 break;
 547         case IRQ_PROG1_INTA:
 548                 irq = IRQ_PF16;
 549                 break;
 550         case IRQ_PROG2_INTA:
 551                 irq = IRQ_PF32;
 552                 break;
 553 #endif
 554         default:
 555                 BUG();
 556                 return;
 557         }
 558
 559         if (search) {
 560                 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
 561                         irq += i;
 562
 563                         mask = get_gpiop_data(i) & get_gpiop_maska(i);
 564
 565                         while (mask) {
 566                                 if (mask & 1) {
 567                                         desc = irq_desc + irq;
 568                                         desc->handle_irq(irq, desc);
 569                                 }
 570                                 irq++;
 571                                 mask >>= 1;
 572                         }
 573                 }
 574         } else {
 575                         gpio = irq_to_gpio(irq);
 576                         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 577
 578                         do {
 579                                 if (mask & 1) {
 580                                         desc = irq_desc + irq;
 581                                         desc->handle_irq(irq, desc);
 582                                 }
 583                                 irq++;
 584                                 mask >>= 1;
 585                         } while (mask);
 586         }
 587
 588 }
 589
 590 #else                           /* CONFIG_BF54x */
 591
 592 #define NR_PINT_SYS_IRQS        4
 593 #define NR_PINT_BITS            32
 594 #define NR_PINTS                160
 595 #define IRQ_NOT_AVAIL           0xFF
 596
 597 #define PINT_2_BANK(x)          ((x) >> 5)
 598 #define PINT_2_BIT(x)           ((x) & 0x1F)
 599 #define PINT_BIT(x)             (1 << (PINT_2_BIT(x)))
 600
 601 static unsigned char irq2pint_lut[NR_PINTS];
 602 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
 603
 604 struct pin_int_t {
 605         unsigned int mask_set;
 606         unsigned int mask_clear;
 607         unsigned int request;
 608         unsigned int assign;
 609         unsigned int edge_set;
 610         unsigned int edge_clear;
 611         unsigned int invert_set;
 612         unsigned int invert_clear;
 613         unsigned int pinstate;
 614         unsigned int latch;
 615 };
 616
 617 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
 618         (struct pin_int_t *)PINT0_MASK_SET,
 619         (struct pin_int_t *)PINT1_MASK_SET,
 620         (struct pin_int_t *)PINT2_MASK_SET,
 621         (struct pin_int_t *)PINT3_MASK_SET,
 622 };
 623
 624 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 625 {
 626         unsigned int irq_base;
 627
 628         if (bank < 2) {         /*PA-PB */
 629                 irq_base = IRQ_PA0 + bmap * 16;
 630         } else {                /*PC-PJ */
 631                 irq_base = IRQ_PC0 + bmap * 16;
 632         }
 633
 634         return irq_base;
 635 }
 636
 637         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 638 void init_pint_lut(void)
 639 {
 640         u16 bank, bit, irq_base, bit_pos;
 641         u32 pint_assign;
 642         u8 bmap;
 643
 644         memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
 645
 646         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
 647
 648                 pint_assign = pint[bank]->assign;
 649
 650                 for (bit = 0; bit < NR_PINT_BITS; bit++) {
 651
 652                         bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
 653
 654                         irq_base = get_irq_base(bank, bmap);
 655
 656                         irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
 657                         bit_pos = bit + bank * NR_PINT_BITS;
 658
 659                         pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
 660                         irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
 661                 }
 662         }
 663 }
 664
 665 static void bfin_gpio_ack_irq(unsigned int irq)
 666 {
 667         struct irq_desc *desc = irq_desc + irq;
 668         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 669         u32 pintbit = PINT_BIT(pint_val);
 670         u32 bank = PINT_2_BANK(pint_val);
 671
 672         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 673                 if (pint[bank]->invert_set & pintbit)
 674                         pint[bank]->invert_clear = pintbit;
 675                 else
 676                         pint[bank]->invert_set = pintbit;
 677         }
 678         pint[bank]->request = pintbit;
 679
 680 }
 681
 682 static void bfin_gpio_mask_ack_irq(unsigned int irq)
 683 {
 684         struct irq_desc *desc = irq_desc + irq;
 685         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 686         u32 pintbit = PINT_BIT(pint_val);
 687         u32 bank = PINT_2_BANK(pint_val);
 688
 689         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
 690                 if (pint[bank]->invert_set & pintbit)
 691                         pint[bank]->invert_clear = pintbit;
 692                 else
 693                         pint[bank]->invert_set = pintbit;
 694         }
 695
 696         pint[bank]->request = pintbit;
 697         pint[bank]->mask_clear = pintbit;
 698 }
 699
 700 static void bfin_gpio_mask_irq(unsigned int irq)
 701 {
 702         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 703
 704         pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
 705 }
 706
 707 static void bfin_gpio_unmask_irq(unsigned int irq)
 708 {
 709         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 710         u32 pintbit = PINT_BIT(pint_val);
 711         u32 bank = PINT_2_BANK(pint_val);
 712
 713         pint[bank]->request = pintbit;
 714         pint[bank]->mask_set = pintbit;
 715 }
 716
 717 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
 718 {
 719         u32 gpionr = irq_to_gpio(irq);
 720         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 721
 722         if (pint_val == IRQ_NOT_AVAIL) {
 723                 printk(KERN_ERR
 724                 "GPIO IRQ %d :Not in PINT Assign table "
 725                 "Reconfigure Interrupt to Port Assignemt\n", irq);
 726                 return -ENODEV;
 727         }
 728
 729         if (__test_and_set_bit(gpionr, gpio_enabled))
 730                 bfin_gpio_irq_prepare(gpionr);
 731
 732         bfin_gpio_unmask_irq(irq);
 733
 734         return 0;
 735 }
 736
 737 static void bfin_gpio_irq_shutdown(unsigned int irq)
 738 {
 739         u32 gpionr = irq_to_gpio(irq);
 740
 741         bfin_gpio_mask_irq(irq);
 742         __clear_bit(gpionr, gpio_enabled);
 743         bfin_gpio_irq_free(gpionr);
 744 }
 745
 746 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
 747 {
 748         int ret;
 749         char buf[16];
 750         u32 gpionr = irq_to_gpio(irq);
 751         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 752         u32 pintbit = PINT_BIT(pint_val);
 753         u32 bank = PINT_2_BANK(pint_val);
 754
 755         if (pint_val == IRQ_NOT_AVAIL)
 756                 return -ENODEV;
 757
 758         if (type == IRQ_TYPE_PROBE) {
 759                 /* only probe unenabled GPIO interrupt lines */
 760                 if (__test_bit(gpionr, gpio_enabled))
 761                         return 0;
 762                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 763         }
 764
 765         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 766                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 767
 768                 snprintf(buf, 16, "gpio-irq%d", irq);
 769                 ret = bfin_gpio_irq_request(gpionr, buf);
 770                 if (ret)
 771                         return ret;
 772
 773                 if (__test_and_set_bit(gpionr, gpio_enabled))
 774                         bfin_gpio_irq_prepare(gpionr);
 775
 776         } else {
 777                 __clear_bit(gpionr, gpio_enabled);
 778                 return 0;
 779         }
 780
 781         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 782                 pint[bank]->invert_set = pintbit;       /* low or falling edge denoted by one */
 783         else
 784                 pint[bank]->invert_clear = pintbit;     /* high or rising edge denoted by zero */
 785
 786         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 787             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 788                 if (gpio_get_value(gpionr))
 789                         pint[bank]->invert_set = pintbit;
 790                 else
 791                         pint[bank]->invert_clear = pintbit;
 792         }
 793
 794         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 795                 pint[bank]->edge_set = pintbit;
 796                 bfin_set_irq_handler(irq, handle_edge_irq);
 797         } else {
 798                 pint[bank]->edge_clear = pintbit;
 799                 bfin_set_irq_handler(irq, handle_level_irq);
 800         }
 801
 802         return 0;
 803 }
 804
 805 #ifdef CONFIG_PM
 806 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
 807 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
 808
 809 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
 810 {
 811         u32 pint_irq;
 812         u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
 813         u32 bank = PINT_2_BANK(pint_val);
 814         u32 pintbit = PINT_BIT(pint_val);
 815
 816         switch (bank) {
 817         case 0:
 818                 pint_irq = IRQ_PINT0;
 819                 break;
 820         case 2:
 821                 pint_irq = IRQ_PINT2;
 822                 break;
 823         case 3:
 824                 pint_irq = IRQ_PINT3;
 825                 break;
 826         case 1:
 827                 pint_irq = IRQ_PINT1;
 828                 break;
 829         default:
 830                 return -EINVAL;
 831         }
 832
 833         bfin_internal_set_wake(pint_irq, state);
 834
 835         if (state)
 836                 pint_wakeup_masks[bank] |= pintbit;
 837         else
 838                 pint_wakeup_masks[bank] &= ~pintbit;
 839
 840         return 0;
 841 }
 842
 843 u32 bfin_pm_setup(void)
 844 {
 845         u32 val, i;
 846
 847         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
 848                 val = pint[i]->mask_clear;
 849                 pint_saved_masks[i] = val;
 850                 if (val ^ pint_wakeup_masks[i]) {
 851                         pint[i]->mask_clear = val;
 852                         pint[i]->mask_set = pint_wakeup_masks[i];
 853                 }
 854         }
 855
 856         return 0;
 857 }
 858
 859 void bfin_pm_restore(void)
 860 {
 861         u32 i, val;
 862
 863         for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
 864                 val = pint_saved_masks[i];
 865                 if (val ^ pint_wakeup_masks[i]) {
 866                         pint[i]->mask_clear = pint[i]->mask_clear;
 867                         pint[i]->mask_set = val;
 868                 }
 869         }
 870 }
 871 #endif
 872
 873 static void bfin_demux_gpio_irq(unsigned int inta_irq,
 874                                 struct irq_desc *desc)
 875 {
 876         u32 bank, pint_val;
 877         u32 request, irq;
 878
 879         switch (inta_irq) {
 880         case IRQ_PINT0:
 881                 bank = 0;
 882                 break;
 883         case IRQ_PINT2:
 884                 bank = 2;
 885                 break;
 886         case IRQ_PINT3:
 887                 bank = 3;
 888                 break;
 889         case IRQ_PINT1:
 890                 bank = 1;
 891                 break;
 892         default:
 893                 return;
 894         }
 895
 896         pint_val = bank * NR_PINT_BITS;
 897
 898         request = pint[bank]->request;
 899
 900         while (request) {
 901                 if (request & 1) {
 902                         irq = pint2irq_lut[pint_val] + SYS_IRQS;
 903                         desc = irq_desc + irq;
 904                         desc->handle_irq(irq, desc);
 905                 }
 906                 pint_val++;
 907                 request >>= 1;
 908         }
 909
 910 }
 911 #endif
 912
 913 static struct irq_chip bfin_gpio_irqchip = {
 914         .name = "GPIO",
 915         .ack = bfin_gpio_ack_irq,
 916         .mask = bfin_gpio_mask_irq,
 917         .mask_ack = bfin_gpio_mask_ack_irq,
 918         .unmask = bfin_gpio_unmask_irq,
 919         .disable = bfin_gpio_mask_irq,
 920         .enable = bfin_gpio_unmask_irq,
 921         .set_type = bfin_gpio_irq_type,
 922         .startup = bfin_gpio_irq_startup,
 923         .shutdown = bfin_gpio_irq_shutdown,
 924 #ifdef CONFIG_PM
 925         .set_wake = bfin_gpio_set_wake,
 926 #endif
 927 };
 928
 929 void __cpuinit init_exception_vectors(void)
 930 {
 931         /* cannot program in software:
 932          * evt0 - emulation (jtag)
 933          * evt1 - reset
 934          */
 935         bfin_write_EVT2(evt_nmi);
 936         bfin_write_EVT3(trap);
 937         bfin_write_EVT5(evt_ivhw);
 938         bfin_write_EVT6(evt_timer);
 939         bfin_write_EVT7(evt_evt7);
 940         bfin_write_EVT8(evt_evt8);
 941         bfin_write_EVT9(evt_evt9);
 942         bfin_write_EVT10(evt_evt10);
 943         bfin_write_EVT11(evt_evt11);
 944         bfin_write_EVT12(evt_evt12);
 945         bfin_write_EVT13(evt_evt13);
 946         bfin_write_EVT14(evt14_softirq);
 947         bfin_write_EVT15(evt_system_call);
 948         CSYNC();
 949 }
 950
 951 /*
 952  * This function should be called during kernel startup to initialize
 953  * the BFin IRQ handling routines.
 954  */
 955
 956 int __init init_arch_irq(void)
 957 {
 958         int irq;
 959         unsigned long ilat = 0;
 960         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
 961 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
 962         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
 963         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
 964         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
 965 # ifdef CONFIG_BF54x
 966         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
 967 # endif
 968 # ifdef CONFIG_SMP
 969         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
 970         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
 971 # endif
 972 #else
 973         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
 974 #endif
 975
 976         local_irq_disable();
 977
 978 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
 979         /* Clear EMAC Interrupt Status bits so we can demux it later */
 980         bfin_write_EMAC_SYSTAT(-1);
 981 #endif
 982
 983 #ifdef CONFIG_BF54x
 984 # ifdef CONFIG_PINTx_REASSIGN
 985         pint[0]->assign = CONFIG_PINT0_ASSIGN;
 986         pint[1]->assign = CONFIG_PINT1_ASSIGN;
 987         pint[2]->assign = CONFIG_PINT2_ASSIGN;
 988         pint[3]->assign = CONFIG_PINT3_ASSIGN;
 989 # endif
 990         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 991         init_pint_lut();
 992 #endif
 993
 994         for (irq = 0; irq <= SYS_IRQS; irq++) {
 995                 if (irq <= IRQ_CORETMR)
 996                         set_irq_chip(irq, &bfin_core_irqchip);
 997                 else
 998                         set_irq_chip(irq, &bfin_internal_irqchip);
 999
1000                 switch (irq) {
1001 #if defined(CONFIG_BF53x)
1002                 case IRQ_PROG_INTA:
1003 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1004                 case IRQ_MAC_RX:
1005 # endif
1006 #elif defined(CONFIG_BF54x)
1007                 case IRQ_PINT0:
1008                 case IRQ_PINT1:
1009                 case IRQ_PINT2:
1010                 case IRQ_PINT3:
1011 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1012                 case IRQ_PORTF_INTA:
1013                 case IRQ_PORTG_INTA:
1014                 case IRQ_PORTH_INTA:
1015 #elif defined(CONFIG_BF561)
1016                 case IRQ_PROG0_INTA:
1017                 case IRQ_PROG1_INTA:
1018                 case IRQ_PROG2_INTA:
1019 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1020                 case IRQ_PORTF_INTA:
1021 #endif
1022
1023                         set_irq_chained_handler(irq,
1024                                                 bfin_demux_gpio_irq);
1025                         break;
1026 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1027                 case IRQ_GENERIC_ERROR:
1028                         set_irq_handler(irq, bfin_demux_error_irq);
1029
1030                         break;
1031 #endif
1032 #ifdef CONFIG_TICK_SOURCE_SYSTMR0
1033                 case IRQ_TIMER0:
1034                         set_irq_handler(irq, handle_percpu_irq);
1035                         break;
1036 #endif
1037 #ifdef CONFIG_SMP
1038                 case IRQ_SUPPLE_0:
1039                 case IRQ_SUPPLE_1:
1040                         set_irq_handler(irq, handle_percpu_irq);
1041                         break;
1042 #endif
1043                 default:
1044                         set_irq_handler(irq, handle_simple_irq);
1045                         break;
1046                 }
1047         }
1048
1049 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1050         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1051                 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1052                                          handle_level_irq);
1053 #endif
1054
1055         /* if configured as edge, then will be changed to do_edge_IRQ */
1056         for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1057                 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1058                                          handle_level_irq);
1059
1060
1061         bfin_write_IMASK(0);
1062         CSYNC();
1063         ilat = bfin_read_ILAT();
1064         CSYNC();
1065         bfin_write_ILAT(ilat);
1066         CSYNC();
1067
1068         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1069         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1070          * local_irq_enable()
1071          */
1072         program_IAR();
1073         /* Therefore it's better to setup IARs before interrupts enabled */
1074         search_IAR();
1075
1076         /* Enable interrupts IVG7-15 */
1077         bfin_irq_flags |= IMASK_IVG15 |
1078             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1079             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1080
1081 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1082         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1083         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1084 #if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1085         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1086          * will screw up the bootrom as it relies on MDMA0/1 waking it
1087          * up from IDLE instructions.  See this report for more info:
1088          * http://blackfin.uclinux.org/gf/tracker/4323
1089          */
1090         if (ANOMALY_05000435)
1091                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1092         else
1093                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1094 #else
1095         bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1096 #endif
1097 # ifdef CONFIG_BF54x
1098         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1099 # endif
1100 #else
1101         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1102 #endif
1103
1104         return 0;
1105 }
1106
1107 #ifdef CONFIG_DO_IRQ_L1
1108 __attribute__((l1_text))
1109 #endif
1110 void do_irq(int vec, struct pt_regs *fp)
1111 {
1112         if (vec == EVT_IVTMR_P) {
1113                 vec = IRQ_CORETMR;
1114         } else {
1115                 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1116                 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1117 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1118         || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1119                 unsigned long sic_status[3];
1120
1121                 if (smp_processor_id()) {
1122 #ifdef CONFIG_SMP
1123                         /* This will be optimized out in UP mode. */
1124                         sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1125                         sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1126 #endif
1127                 } else {
1128                         sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1129                         sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1130                 }
1131 #ifdef CONFIG_BF54x
1132                 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1133 #endif
1134                 for (;; ivg++) {
1135                         if (ivg >= ivg_stop) {
1136                                 atomic_inc(&num_spurious);
1137                                 return;
1138                         }
1139                         if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1140                                 break;
1141                 }
1142 #else
1143                 unsigned long sic_status;
1144
1145                 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1146
1147                 for (;; ivg++) {
1148                         if (ivg >= ivg_stop) {
1149                                 atomic_inc(&num_spurious);
1150                                 return;
1151                         } else if (sic_status & ivg->isrflag)
1152                                 break;
1153                 }
1154 #endif
1155                 vec = ivg->irqno;
1156         }
1157         asm_do_IRQ(vec, fp);
1158 }