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   1 /*
   2  *  Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  *
   9  *  Todo: - add support for the OF persistent properties
  10  */
  11 #include <linux/config.h>
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/stddef.h>
  15 #include <linux/string.h>
  16 #include <linux/nvram.h>
  17 #include <linux/init.h>
  18 #include <linux/slab.h>
  19 #include <linux/delay.h>
  20 #include <linux/errno.h>
  21 #include <linux/adb.h>
  22 #include <linux/pmu.h>
  23 #include <linux/bootmem.h>
  24 #include <linux/completion.h>
  25 #include <linux/spinlock.h>
  26 #include <asm/sections.h>
  27 #include <asm/io.h>
  28 #include <asm/system.h>
  29 #include <asm/prom.h>
  30 #include <asm/machdep.h>
  31 #include <asm/nvram.h>
  32
  33 #define DEBUG
  34
  35 #ifdef DEBUG
  36 #define DBG(x...) printk(x)
  37 #else
  38 #define DBG(x...)
  39 #endif
  40
  41 #define NVRAM_SIZE              0x2000  /* 8kB of non-volatile RAM */
  42
  43 #define CORE99_SIGNATURE        0x5a
  44 #define CORE99_ADLER_START      0x14
  45
  46 /* On Core99, nvram is either a sharp, a micron or an AMD flash */
  47 #define SM_FLASH_STATUS_DONE    0x80
  48 #define SM_FLASH_STATUS_ERR     0x38
  49
  50 #define SM_FLASH_CMD_ERASE_CONFIRM      0xd0
  51 #define SM_FLASH_CMD_ERASE_SETUP        0x20
  52 #define SM_FLASH_CMD_RESET              0xff
  53 #define SM_FLASH_CMD_WRITE_SETUP        0x40
  54 #define SM_FLASH_CMD_CLEAR_STATUS       0x50
  55 #define SM_FLASH_CMD_READ_STATUS        0x70
  56
  57 /* CHRP NVRAM header */
  58 struct chrp_header {
  59   u8            signature;
  60   u8            cksum;
  61   u16           len;
  62   char          name[12];
  63   u8            data[0];
  64 };
  65
  66 struct core99_header {
  67   struct chrp_header    hdr;
  68   u32                   adler;
  69   u32                   generation;
  70   u32                   reserved[2];
  71 };
  72
  73 /*
  74  * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
  75  */
  76 static int nvram_naddrs;
  77 static volatile unsigned char *nvram_data;
  78 static int is_core_99;
  79 static int core99_bank = 0;
  80 static int nvram_partitions[3];
  81 // XXX Turn that into a sem
  82 static DEFINE_SPINLOCK(nv_lock);
  83
  84 extern int pmac_newworld;
  85 extern int system_running;
  86
  87 static int (*core99_write_bank)(int bank, u8* datas);
  88 static int (*core99_erase_bank)(int bank);
  89
  90 static char *nvram_image;
  91
  92
  93 static unsigned char core99_nvram_read_byte(int addr)
  94 {
  95         if (nvram_image == NULL)
  96                 return 0xff;
  97         return nvram_image[addr];
  98 }
  99
 100 static void core99_nvram_write_byte(int addr, unsigned char val)
 101 {
 102         if (nvram_image == NULL)
 103                 return;
 104         nvram_image[addr] = val;
 105 }
 106
 107 static ssize_t core99_nvram_read(char *buf, size_t count, loff_t *index)
 108 {
 109         int i;
 110
 111         if (nvram_image == NULL)
 112                 return -ENODEV;
 113         if (*index > NVRAM_SIZE)
 114                 return 0;
 115
 116         i = *index;
 117         if (i + count > NVRAM_SIZE)
 118                 count = NVRAM_SIZE - i;
 119
 120         memcpy(buf, &nvram_image[i], count);
 121         *index = i + count;
 122         return count;
 123 }
 124
 125 static ssize_t core99_nvram_write(char *buf, size_t count, loff_t *index)
 126 {
 127         int i;
 128
 129         if (nvram_image == NULL)
 130                 return -ENODEV;
 131         if (*index > NVRAM_SIZE)
 132                 return 0;
 133
 134         i = *index;
 135         if (i + count > NVRAM_SIZE)
 136                 count = NVRAM_SIZE - i;
 137
 138         memcpy(&nvram_image[i], buf, count);
 139         *index = i + count;
 140         return count;
 141 }
 142
 143 static ssize_t core99_nvram_size(void)
 144 {
 145         if (nvram_image == NULL)
 146                 return -ENODEV;
 147         return NVRAM_SIZE;
 148 }
 149
 150 #ifdef CONFIG_PPC32
 151 static volatile unsigned char *nvram_addr;
 152 static int nvram_mult;
 153
 154 static unsigned char direct_nvram_read_byte(int addr)
 155 {
 156         return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
 157 }
 158
 159 static void direct_nvram_write_byte(int addr, unsigned char val)
 160 {
 161         out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
 162 }
 163
 164
 165 static unsigned char indirect_nvram_read_byte(int addr)
 166 {
 167         unsigned char val;
 168         unsigned long flags;
 169
 170         spin_lock_irqsave(&nv_lock, flags);
 171         out_8(nvram_addr, addr >> 5);
 172         val = in_8(&nvram_data[(addr & 0x1f) << 4]);
 173         spin_unlock_irqrestore(&nv_lock, flags);
 174
 175         return val;
 176 }
 177
 178 static void indirect_nvram_write_byte(int addr, unsigned char val)
 179 {
 180         unsigned long flags;
 181
 182         spin_lock_irqsave(&nv_lock, flags);
 183         out_8(nvram_addr, addr >> 5);
 184         out_8(&nvram_data[(addr & 0x1f) << 4], val);
 185         spin_unlock_irqrestore(&nv_lock, flags);
 186 }
 187
 188
 189 #ifdef CONFIG_ADB_PMU
 190
 191 static void pmu_nvram_complete(struct adb_request *req)
 192 {
 193         if (req->arg)
 194                 complete((struct completion *)req->arg);
 195 }
 196
 197 static unsigned char pmu_nvram_read_byte(int addr)
 198 {
 199         struct adb_request req;
 200         DECLARE_COMPLETION(req_complete);
 201
 202         req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
 203         if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
 204                         (addr >> 8) & 0xff, addr & 0xff))
 205                 return 0xff;
 206         if (system_state == SYSTEM_RUNNING)
 207                 wait_for_completion(&req_complete);
 208         while (!req.complete)
 209                 pmu_poll();
 210         return req.reply[0];
 211 }
 212
 213 static void pmu_nvram_write_byte(int addr, unsigned char val)
 214 {
 215         struct adb_request req;
 216         DECLARE_COMPLETION(req_complete);
 217
 218         req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
 219         if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
 220                         (addr >> 8) & 0xff, addr & 0xff, val))
 221                 return;
 222         if (system_state == SYSTEM_RUNNING)
 223                 wait_for_completion(&req_complete);
 224         while (!req.complete)
 225                 pmu_poll();
 226 }
 227
 228 #endif /* CONFIG_ADB_PMU */
 229 #endif /* CONFIG_PPC32 */
 230
 231 static u8 chrp_checksum(struct chrp_header* hdr)
 232 {
 233         u8 *ptr;
 234         u16 sum = hdr->signature;
 235         for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
 236                 sum += *ptr;
 237         while (sum > 0xFF)
 238                 sum = (sum & 0xFF) + (sum>>8);
 239         return sum;
 240 }
 241
 242 static u32 core99_calc_adler(u8 *buffer)
 243 {
 244         int cnt;
 245         u32 low, high;
 246
 247         buffer += CORE99_ADLER_START;
 248         low = 1;
 249         high = 0;
 250         for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
 251                 if ((cnt % 5000) == 0) {
 252                         high  %= 65521UL;
 253                         high %= 65521UL;
 254                 }
 255                 low += buffer[cnt];
 256                 high += low;
 257         }
 258         low  %= 65521UL;
 259         high %= 65521UL;
 260
 261         return (high << 16) | low;
 262 }
 263
 264 static u32 core99_check(u8* datas)
 265 {
 266         struct core99_header* hdr99 = (struct core99_header*)datas;
 267
 268         if (hdr99->hdr.signature != CORE99_SIGNATURE) {
 269                 DBG("Invalid signature\n");
 270                 return 0;
 271         }
 272         if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
 273                 DBG("Invalid checksum\n");
 274                 return 0;
 275         }
 276         if (hdr99->adler != core99_calc_adler(datas)) {
 277                 DBG("Invalid adler\n");
 278                 return 0;
 279         }
 280         return hdr99->generation;
 281 }
 282
 283 static int sm_erase_bank(int bank)
 284 {
 285         int stat, i;
 286         unsigned long timeout;
 287
 288         u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
 289
 290         DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
 291
 292         out_8(base, SM_FLASH_CMD_ERASE_SETUP);
 293         out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
 294         timeout = 0;
 295         do {
 296                 if (++timeout > 1000000) {
 297                         printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n");
 298                         break;
 299                 }
 300                 out_8(base, SM_FLASH_CMD_READ_STATUS);
 301                 stat = in_8(base);
 302         } while (!(stat & SM_FLASH_STATUS_DONE));
 303
 304         out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
 305         out_8(base, SM_FLASH_CMD_RESET);
 306
 307         for (i=0; i<NVRAM_SIZE; i++)
 308                 if (base[i] != 0xff) {
 309                         printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
 310                         return -ENXIO;
 311                 }
 312         return 0;
 313 }
 314
 315 static int sm_write_bank(int bank, u8* datas)
 316 {
 317         int i, stat = 0;
 318         unsigned long timeout;
 319
 320         u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
 321
 322         DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
 323
 324         for (i=0; i<NVRAM_SIZE; i++) {
 325                 out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
 326                 udelay(1);
 327                 out_8(base+i, datas[i]);
 328                 timeout = 0;
 329                 do {
 330                         if (++timeout > 1000000) {
 331                                 printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
 332                                 break;
 333                         }
 334                         out_8(base, SM_FLASH_CMD_READ_STATUS);
 335                         stat = in_8(base);
 336                 } while (!(stat & SM_FLASH_STATUS_DONE));
 337                 if (!(stat & SM_FLASH_STATUS_DONE))
 338                         break;
 339         }
 340         out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
 341         out_8(base, SM_FLASH_CMD_RESET);
 342         for (i=0; i<NVRAM_SIZE; i++)
 343                 if (base[i] != datas[i]) {
 344                         printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
 345                         return -ENXIO;
 346                 }
 347         return 0;
 348 }
 349
 350 static int amd_erase_bank(int bank)
 351 {
 352         int i, stat = 0;
 353         unsigned long timeout;
 354
 355         u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
 356
 357         DBG("nvram: AMD Erasing bank %d...\n", bank);
 358
 359         /* Unlock 1 */
 360         out_8(base+0x555, 0xaa);
 361         udelay(1);
 362         /* Unlock 2 */
 363         out_8(base+0x2aa, 0x55);
 364         udelay(1);
 365
 366         /* Sector-Erase */
 367         out_8(base+0x555, 0x80);
 368         udelay(1);
 369         out_8(base+0x555, 0xaa);
 370         udelay(1);
 371         out_8(base+0x2aa, 0x55);
 372         udelay(1);
 373         out_8(base, 0x30);
 374         udelay(1);
 375
 376         timeout = 0;
 377         do {
 378                 if (++timeout > 1000000) {
 379                         printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
 380                         break;
 381                 }
 382                 stat = in_8(base) ^ in_8(base);
 383         } while (stat != 0);
 384
 385         /* Reset */
 386         out_8(base, 0xf0);
 387         udelay(1);
 388
 389         for (i=0; i<NVRAM_SIZE; i++)
 390                 if (base[i] != 0xff) {
 391                         printk(KERN_ERR "nvram: AMD flash erase failed !\n");
 392                         return -ENXIO;
 393                 }
 394         return 0;
 395 }
 396
 397 static int amd_write_bank(int bank, u8* datas)
 398 {
 399         int i, stat = 0;
 400         unsigned long timeout;
 401
 402         u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
 403
 404         DBG("nvram: AMD Writing bank %d...\n", bank);
 405
 406         for (i=0; i<NVRAM_SIZE; i++) {
 407                 /* Unlock 1 */
 408                 out_8(base+0x555, 0xaa);
 409                 udelay(1);
 410                 /* Unlock 2 */
 411                 out_8(base+0x2aa, 0x55);
 412                 udelay(1);
 413
 414                 /* Write single word */
 415                 out_8(base+0x555, 0xa0);
 416                 udelay(1);
 417                 out_8(base+i, datas[i]);
 418
 419                 timeout = 0;
 420                 do {
 421                         if (++timeout > 1000000) {
 422                                 printk(KERN_ERR "nvram: AMD flash write timeout !\n");
 423                                 break;
 424                         }
 425                         stat = in_8(base) ^ in_8(base);
 426                 } while (stat != 0);
 427                 if (stat != 0)
 428                         break;
 429         }
 430
 431         /* Reset */
 432         out_8(base, 0xf0);
 433         udelay(1);
 434
 435         for (i=0; i<NVRAM_SIZE; i++)
 436                 if (base[i] != datas[i]) {
 437                         printk(KERN_ERR "nvram: AMD flash write failed !\n");
 438                         return -ENXIO;
 439                 }
 440         return 0;
 441 }
 442
 443 static void __init lookup_partitions(void)
 444 {
 445         u8 buffer[17];
 446         int i, offset;
 447         struct chrp_header* hdr;
 448
 449         if (pmac_newworld) {
 450                 nvram_partitions[pmac_nvram_OF] = -1;
 451                 nvram_partitions[pmac_nvram_XPRAM] = -1;
 452                 nvram_partitions[pmac_nvram_NR] = -1;
 453                 hdr = (struct chrp_header *)buffer;
 454
 455                 offset = 0;
 456                 buffer[16] = 0;
 457                 do {
 458                         for (i=0;i<16;i++)
 459                                 buffer[i] = ppc_md.nvram_read_val(offset+i);
 460                         if (!strcmp(hdr->name, "common"))
 461                                 nvram_partitions[pmac_nvram_OF] = offset + 0x10;
 462                         if (!strcmp(hdr->name, "APL,MacOS75")) {
 463                                 nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
 464                                 nvram_partitions[pmac_nvram_NR] = offset + 0x110;
 465                         }
 466                         offset += (hdr->len * 0x10);
 467                 } while(offset < NVRAM_SIZE);
 468         } else {
 469                 nvram_partitions[pmac_nvram_OF] = 0x1800;
 470                 nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
 471                 nvram_partitions[pmac_nvram_NR] = 0x1400;
 472         }
 473         DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
 474         DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
 475         DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
 476 }
 477
 478 static void core99_nvram_sync(void)
 479 {
 480         struct core99_header* hdr99;
 481         unsigned long flags;
 482
 483         if (!is_core_99 || !nvram_data || !nvram_image)
 484                 return;
 485
 486         spin_lock_irqsave(&nv_lock, flags);
 487         if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
 488                 NVRAM_SIZE))
 489                 goto bail;
 490
 491         DBG("Updating nvram...\n");
 492
 493         hdr99 = (struct core99_header*)nvram_image;
 494         hdr99->generation++;
 495         hdr99->hdr.signature = CORE99_SIGNATURE;
 496         hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
 497         hdr99->adler = core99_calc_adler(nvram_image);
 498         core99_bank = core99_bank ? 0 : 1;
 499         if (core99_erase_bank)
 500                 if (core99_erase_bank(core99_bank)) {
 501                         printk("nvram: Error erasing bank %d\n", core99_bank);
 502                         goto bail;
 503                 }
 504         if (core99_write_bank)
 505                 if (core99_write_bank(core99_bank, nvram_image))
 506                         printk("nvram: Error writing bank %d\n", core99_bank);
 507  bail:
 508         spin_unlock_irqrestore(&nv_lock, flags);
 509
 510 #ifdef DEBUG
 511         mdelay(2000);
 512 #endif
 513 }
 514
 515 static int __init core99_nvram_setup(struct device_node *dp, unsigned long addr)
 516 {
 517         int i;
 518         u32 gen_bank0, gen_bank1;
 519
 520         if (nvram_naddrs < 1) {
 521                 printk(KERN_ERR "nvram: no address\n");
 522                 return -EINVAL;
 523         }
 524         nvram_image = alloc_bootmem(NVRAM_SIZE);
 525         if (nvram_image == NULL) {
 526                 printk(KERN_ERR "nvram: can't allocate ram image\n");
 527                 return -ENOMEM;
 528         }
 529         nvram_data = ioremap(addr, NVRAM_SIZE*2);
 530         nvram_naddrs = 1; /* Make sure we get the correct case */
 531
 532         DBG("nvram: Checking bank 0...\n");
 533
 534         gen_bank0 = core99_check((u8 *)nvram_data);
 535         gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
 536         core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
 537
 538         DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
 539         DBG("nvram: Active bank is: %d\n", core99_bank);
 540
 541         for (i=0; i<NVRAM_SIZE; i++)
 542                 nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
 543
 544         ppc_md.nvram_read_val   = core99_nvram_read_byte;
 545         ppc_md.nvram_write_val  = core99_nvram_write_byte;
 546         ppc_md.nvram_read       = core99_nvram_read;
 547         ppc_md.nvram_write      = core99_nvram_write;
 548         ppc_md.nvram_size       = core99_nvram_size;
 549         ppc_md.nvram_sync       = core99_nvram_sync;
 550         ppc_md.machine_shutdown = core99_nvram_sync;
 551         /*
 552          * Maybe we could be smarter here though making an exclusive list
 553          * of known flash chips is a bit nasty as older OF didn't provide us
 554          * with a useful "compatible" entry. A solution would be to really
 555          * identify the chip using flash id commands and base ourselves on
 556          * a list of known chips IDs
 557          */
 558         if (device_is_compatible(dp, "amd-0137")) {
 559                 core99_erase_bank = amd_erase_bank;
 560                 core99_write_bank = amd_write_bank;
 561         } else {
 562                 core99_erase_bank = sm_erase_bank;
 563                 core99_write_bank = sm_write_bank;
 564         }
 565         return 0;
 566 }
 567
 568 int __init pmac_nvram_init(void)
 569 {
 570         struct device_node *dp;
 571         struct resource r1, r2;
 572         unsigned int s1 = 0, s2 = 0;
 573         int err = 0;
 574
 575         nvram_naddrs = 0;
 576
 577         dp = of_find_node_by_name(NULL, "nvram");
 578         if (dp == NULL) {
 579                 printk(KERN_ERR "Can't find NVRAM device\n");
 580                 return -ENODEV;
 581         }
 582
 583         /* Try to obtain an address */
 584         if (of_address_to_resource(dp, 0, &r1) == 0) {
 585                 nvram_naddrs = 1;
 586                 s1 = (r1.end - r1.start) + 1;
 587                 if (of_address_to_resource(dp, 1, &r2) == 0) {
 588                         nvram_naddrs = 2;
 589                         s2 = (r2.end - r2.start) + 1;
 590                 }
 591         }
 592
 593         is_core_99 = device_is_compatible(dp, "nvram,flash");
 594         if (is_core_99) {
 595                 err = core99_nvram_setup(dp, r1.start);
 596                 goto bail;
 597         }
 598
 599 #ifdef CONFIG_PPC32
 600         if (_machine == _MACH_chrp && nvram_naddrs == 1) {
 601                 nvram_data = ioremap(r1.start, s1);
 602                 nvram_mult = 1;
 603                 ppc_md.nvram_read_val   = direct_nvram_read_byte;
 604                 ppc_md.nvram_write_val  = direct_nvram_write_byte;
 605         } else if (nvram_naddrs == 1) {
 606                 nvram_data = ioremap(r1.start, s1);
 607                 nvram_mult = (s1 + NVRAM_SIZE - 1) / NVRAM_SIZE;
 608                 ppc_md.nvram_read_val   = direct_nvram_read_byte;
 609                 ppc_md.nvram_write_val  = direct_nvram_write_byte;
 610         } else if (nvram_naddrs == 2) {
 611                 nvram_addr = ioremap(r1.start, s1);
 612                 nvram_data = ioremap(r2.start, s2);
 613                 ppc_md.nvram_read_val   = indirect_nvram_read_byte;
 614                 ppc_md.nvram_write_val  = indirect_nvram_write_byte;
 615         } else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
 616 #ifdef CONFIG_ADB_PMU
 617                 nvram_naddrs = -1;
 618                 ppc_md.nvram_read_val   = pmu_nvram_read_byte;
 619                 ppc_md.nvram_write_val  = pmu_nvram_write_byte;
 620 #endif /* CONFIG_ADB_PMU */
 621         } else {
 622                 printk(KERN_ERR "Incompatible type of NVRAM\n");
 623                 err = -ENXIO;
 624         }
 625 #endif /* CONFIG_PPC32 */
 626 bail:
 627         of_node_put(dp);
 628         if (err == 0)
 629                 lookup_partitions();
 630         return err;
 631 }
 632
 633 int pmac_get_partition(int partition)
 634 {
 635         return nvram_partitions[partition];
 636 }
 637
 638 u8 pmac_xpram_read(int xpaddr)
 639 {
 640         int offset = pmac_get_partition(pmac_nvram_XPRAM);
 641
 642         if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
 643                 return 0xff;
 644
 645         return ppc_md.nvram_read_val(xpaddr + offset);
 646 }
 647
 648 void pmac_xpram_write(int xpaddr, u8 data)
 649 {
 650         int offset = pmac_get_partition(pmac_nvram_XPRAM);
 651
 652         if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
 653                 return;
 654
 655         ppc_md.nvram_write_val(xpaddr + offset, data);
 656 }
 657
 658 EXPORT_SYMBOL(pmac_get_partition);
 659 EXPORT_SYMBOL(pmac_xpram_read);
 660 EXPORT_SYMBOL(pmac_xpram_write);