git.oblomov.eu Git - linux-2.6/blob - arch/x86/include/asm/system.h

   1 #ifndef _ASM_X86_SYSTEM_H
   2 #define _ASM_X86_SYSTEM_H
   3
   4 #include <asm/asm.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <asm/cmpxchg.h>
   8 #include <asm/nops.h>
   9
  10 #include <linux/kernel.h>
  11 #include <linux/irqflags.h>
  12
  13 /* entries in ARCH_DLINFO: */
  14 #ifdef CONFIG_IA32_EMULATION
  15 # define AT_VECTOR_SIZE_ARCH 2
  16 #else
  17 # define AT_VECTOR_SIZE_ARCH 1
  18 #endif
  19
  20 struct task_struct; /* one of the stranger aspects of C forward declarations */
  21 struct task_struct *__switch_to(struct task_struct *prev,
  22                                 struct task_struct *next);
  23
  24 #ifdef CONFIG_X86_32
  25
  26 /*
  27  * Saving eflags is important. It switches not only IOPL between tasks,
  28  * it also protects other tasks from NT leaking through sysenter etc.
  29  */
  30 #define switch_to(prev, next, last)                                     \
  31 do {                                                                    \
  32         /*                                                              \
  33          * Context-switching clobbers all registers, so we clobber      \
  34          * them explicitly, via unused output variables.                \
  35          * (EAX and EBP is not listed because EBP is saved/restored     \
  36          * explicitly for wchan access and EAX is the return value of   \
  37          * __switch_to())                                               \
  38          */                                                             \
  39         unsigned long ebx, ecx, edx, esi, edi;                          \
  40                                                                         \
  41         asm volatile("pushfl\n\t"               /* save    flags */     \
  42                      "pushl %%ebp\n\t"          /* save    EBP   */     \
  43                      "movl %%esp,%[prev_sp]\n\t"        /* save    ESP   */ \
  44                      "movl %[next_sp],%%esp\n\t"        /* restore ESP   */ \
  45                      "movl $1f,%[prev_ip]\n\t"  /* save    EIP   */     \
  46                      "pushl %[next_ip]\n\t"     /* restore EIP   */     \
  47                      "jmp __switch_to\n"        /* regparm call  */     \
  48                      "1:\t"                                             \
  49                      "popl %%ebp\n\t"           /* restore EBP   */     \
  50                      "popfl\n"                  /* restore flags */     \
  51                                                                         \
  52                      /* output parameters */                            \
  53                      : [prev_sp] "=m" (prev->thread.sp),                \
  54                        [prev_ip] "=m" (prev->thread.ip),                \
  55                        "=a" (last),                                     \
  56                                                                         \
  57                        /* clobbered output registers: */                \
  58                        "=b" (ebx), "=c" (ecx), "=d" (edx),              \
  59                        "=S" (esi), "=D" (edi)                           \
  60                                                                         \
  61                        /* input parameters: */                          \
  62                      : [next_sp]  "m" (next->thread.sp),                \
  63                        [next_ip]  "m" (next->thread.ip),                \
  64                                                                         \
  65                        /* regparm parameters for __switch_to(): */      \
  66                        [prev]     "a" (prev),                           \
  67                        [next]     "d" (next)                            \
  68                                                                         \
  69                      : /* reloaded segment registers */                 \
  70                         "memory");                                      \
  71 } while (0)
  72
  73 /*
  74  * disable hlt during certain critical i/o operations
  75  */
  76 #define HAVE_DISABLE_HLT
  77 #else
  78 #define __SAVE(reg, offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  79 #define __RESTORE(reg, offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  80
  81 /* frame pointer must be last for get_wchan */
  82 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  83 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
  84
  85 #define __EXTRA_CLOBBER  \
  86         , "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
  87           "r12", "r13", "r14", "r15"
  88
  89 #ifdef CONFIG_CC_STACKPROTECTOR
  90 #define __switch_canary                                                   \
  91         "movq %P[task_canary](%%rsi),%%r8\n\t"                            \
  92         "movq %%r8,"__percpu_arg([gs_canary])"\n\t"
  93 #define __switch_canary_oparam                                            \
  94         , [gs_canary] "=m" (per_cpu_var(irq_stack_union.stack_canary))
  95 #define __switch_canary_iparam                                            \
  96         , [task_canary] "i" (offsetof(struct task_struct, stack_canary))
  97 #else   /* CC_STACKPROTECTOR */
  98 #define __switch_canary
  99 #define __switch_canary_oparam
 100 #define __switch_canary_iparam
 101 #endif  /* CC_STACKPROTECTOR */
 102
 103 /* Save restore flags to clear handle leaking NT */
 104 #define switch_to(prev, next, last) \
 105         asm volatile(SAVE_CONTEXT                                         \
 106              "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
 107              "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
 108              "call __switch_to\n\t"                                       \
 109              ".globl thread_return\n"                                     \
 110              "thread_return:\n\t"                                         \
 111              "movq "__percpu_arg([current_task])",%%rsi\n\t"              \
 112              __switch_canary                                              \
 113              "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
 114              "movq %%rax,%%rdi\n\t"                                       \
 115              "testl  %[_tif_fork],%P[ti_flags](%%r8)\n\t"         \
 116              "jnz   ret_from_fork\n\t"                                    \
 117              RESTORE_CONTEXT                                              \
 118              : "=a" (last)                                                \
 119                __switch_canary_oparam                                     \
 120              : [next] "S" (next), [prev] "D" (prev),                      \
 121                [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
 122                [ti_flags] "i" (offsetof(struct thread_info, flags)),      \
 123                [_tif_fork] "i" (_TIF_FORK),                               \
 124                [thread_info] "i" (offsetof(struct task_struct, stack)),   \
 125                [current_task] "m" (per_cpu_var(current_task))             \
 126                __switch_canary_iparam                                     \
 127              : "memory", "cc" __EXTRA_CLOBBER)
 128 #endif
 129
 130 #ifdef __KERNEL__
 131 #define _set_base(addr, base) do { unsigned long __pr; \
 132 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 133         "rorl $16,%%edx\n\t" \
 134         "movb %%dl,%2\n\t" \
 135         "movb %%dh,%3" \
 136         :"=&d" (__pr) \
 137         :"m" (*((addr)+2)), \
 138          "m" (*((addr)+4)), \
 139          "m" (*((addr)+7)), \
 140          "0" (base) \
 141         ); } while (0)
 142
 143 #define _set_limit(addr, limit) do { unsigned long __lr; \
 144 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 145         "rorl $16,%%edx\n\t" \
 146         "movb %2,%%dh\n\t" \
 147         "andb $0xf0,%%dh\n\t" \
 148         "orb %%dh,%%dl\n\t" \
 149         "movb %%dl,%2" \
 150         :"=&d" (__lr) \
 151         :"m" (*(addr)), \
 152          "m" (*((addr)+6)), \
 153          "0" (limit) \
 154         ); } while (0)
 155
 156 #define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
 157 #define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
 158
 159 extern void native_load_gs_index(unsigned);
 160
 161 /*
 162  * Load a segment. Fall back on loading the zero
 163  * segment if something goes wrong..
 164  */
 165 #define loadsegment(seg, value)                 \
 166         asm volatile("\n"                       \
 167                      "1:\t"                     \
 168                      "movl %k0,%%" #seg "\n"    \
 169                      "2:\n"                     \
 170                      ".section .fixup,\"ax\"\n" \
 171                      "3:\t"                     \
 172                      "movl %k1, %%" #seg "\n\t" \
 173                      "jmp 2b\n"                 \
 174                      ".previous\n"              \
 175                      _ASM_EXTABLE(1b,3b)        \
 176                      : :"r" (value), "r" (0) : "memory")
 177
 178
 179 /*
 180  * Save a segment register away
 181  */
 182 #define savesegment(seg, value)                         \
 183         asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
 184
 185 static inline unsigned long get_limit(unsigned long segment)
 186 {
 187         unsigned long __limit;
 188         asm("lsll %1,%0" : "=r" (__limit) : "r" (segment));
 189         return __limit + 1;
 190 }
 191
 192 static inline void native_clts(void)
 193 {
 194         asm volatile("clts");
 195 }
 196
 197 /*
 198  * Volatile isn't enough to prevent the compiler from reordering the
 199  * read/write functions for the control registers and messing everything up.
 200  * A memory clobber would solve the problem, but would prevent reordering of
 201  * all loads stores around it, which can hurt performance. Solution is to
 202  * use a variable and mimic reads and writes to it to enforce serialization
 203  */
 204 static unsigned long __force_order;
 205
 206 static inline unsigned long native_read_cr0(void)
 207 {
 208         unsigned long val;
 209         asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
 210         return val;
 211 }
 212
 213 static inline void native_write_cr0(unsigned long val)
 214 {
 215         asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
 216 }
 217
 218 static inline unsigned long native_read_cr2(void)
 219 {
 220         unsigned long val;
 221         asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
 222         return val;
 223 }
 224
 225 static inline void native_write_cr2(unsigned long val)
 226 {
 227         asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
 228 }
 229
 230 static inline unsigned long native_read_cr3(void)
 231 {
 232         unsigned long val;
 233         asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
 234         return val;
 235 }
 236
 237 static inline void native_write_cr3(unsigned long val)
 238 {
 239         asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
 240 }
 241
 242 static inline unsigned long native_read_cr4(void)
 243 {
 244         unsigned long val;
 245         asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
 246         return val;
 247 }
 248
 249 static inline unsigned long native_read_cr4_safe(void)
 250 {
 251         unsigned long val;
 252         /* This could fault if %cr4 does not exist. In x86_64, a cr4 always
 253          * exists, so it will never fail. */
 254 #ifdef CONFIG_X86_32
 255         asm volatile("1: mov %%cr4, %0\n"
 256                      "2:\n"
 257                      _ASM_EXTABLE(1b, 2b)
 258                      : "=r" (val), "=m" (__force_order) : "0" (0));
 259 #else
 260         val = native_read_cr4();
 261 #endif
 262         return val;
 263 }
 264
 265 static inline void native_write_cr4(unsigned long val)
 266 {
 267         asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
 268 }
 269
 270 #ifdef CONFIG_X86_64
 271 static inline unsigned long native_read_cr8(void)
 272 {
 273         unsigned long cr8;
 274         asm volatile("movq %%cr8,%0" : "=r" (cr8));
 275         return cr8;
 276 }
 277
 278 static inline void native_write_cr8(unsigned long val)
 279 {
 280         asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
 281 }
 282 #endif
 283
 284 static inline void native_wbinvd(void)
 285 {
 286         asm volatile("wbinvd": : :"memory");
 287 }
 288
 289 #ifdef CONFIG_PARAVIRT
 290 #include <asm/paravirt.h>
 291 #else
 292 #define read_cr0()      (native_read_cr0())
 293 #define write_cr0(x)    (native_write_cr0(x))
 294 #define read_cr2()      (native_read_cr2())
 295 #define write_cr2(x)    (native_write_cr2(x))
 296 #define read_cr3()      (native_read_cr3())
 297 #define write_cr3(x)    (native_write_cr3(x))
 298 #define read_cr4()      (native_read_cr4())
 299 #define read_cr4_safe() (native_read_cr4_safe())
 300 #define write_cr4(x)    (native_write_cr4(x))
 301 #define wbinvd()        (native_wbinvd())
 302 #ifdef CONFIG_X86_64
 303 #define read_cr8()      (native_read_cr8())
 304 #define write_cr8(x)    (native_write_cr8(x))
 305 #define load_gs_index   native_load_gs_index
 306 #endif
 307
 308 /* Clear the 'TS' bit */
 309 #define clts()          (native_clts())
 310
 311 #endif/* CONFIG_PARAVIRT */
 312
 313 #define stts() write_cr0(read_cr0() | X86_CR0_TS)
 314
 315 #endif /* __KERNEL__ */
 316
 317 static inline void clflush(volatile void *__p)
 318 {
 319         asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
 320 }
 321
 322 #define nop() asm volatile ("nop")
 323
 324 void disable_hlt(void);
 325 void enable_hlt(void);
 326
 327 void cpu_idle_wait(void);
 328
 329 extern unsigned long arch_align_stack(unsigned long sp);
 330 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 331
 332 void default_idle(void);
 333
 334 void stop_this_cpu(void *dummy);
 335
 336 /*
 337  * Force strict CPU ordering.
 338  * And yes, this is required on UP too when we're talking
 339  * to devices.
 340  */
 341 #ifdef CONFIG_X86_32
 342 /*
 343  * Some non-Intel clones support out of order store. wmb() ceases to be a
 344  * nop for these.
 345  */
 346 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 347 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 348 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 349 #else
 350 #define mb()    asm volatile("mfence":::"memory")
 351 #define rmb()   asm volatile("lfence":::"memory")
 352 #define wmb()   asm volatile("sfence" ::: "memory")
 353 #endif
 354
 355 /**
 356  * read_barrier_depends - Flush all pending reads that subsequents reads
 357  * depend on.
 358  *
 359  * No data-dependent reads from memory-like regions are ever reordered
 360  * over this barrier.  All reads preceding this primitive are guaranteed
 361  * to access memory (but not necessarily other CPUs' caches) before any
 362  * reads following this primitive that depend on the data return by
 363  * any of the preceding reads.  This primitive is much lighter weight than
 364  * rmb() on most CPUs, and is never heavier weight than is
 365  * rmb().
 366  *
 367  * These ordering constraints are respected by both the local CPU
 368  * and the compiler.
 369  *
 370  * Ordering is not guaranteed by anything other than these primitives,
 371  * not even by data dependencies.  See the documentation for
 372  * memory_barrier() for examples and URLs to more information.
 373  *
 374  * For example, the following code would force ordering (the initial
 375  * value of "a" is zero, "b" is one, and "p" is "&a"):
 376  *
 377  * <programlisting>
 378  *      CPU 0                           CPU 1
 379  *
 380  *      b = 2;
 381  *      memory_barrier();
 382  *      p = &b;                         q = p;
 383  *                                      read_barrier_depends();
 384  *                                      d = *q;
 385  * </programlisting>
 386  *
 387  * because the read of "*q" depends on the read of "p" and these
 388  * two reads are separated by a read_barrier_depends().  However,
 389  * the following code, with the same initial values for "a" and "b":
 390  *
 391  * <programlisting>
 392  *      CPU 0                           CPU 1
 393  *
 394  *      a = 2;
 395  *      memory_barrier();
 396  *      b = 3;                          y = b;
 397  *                                      read_barrier_depends();
 398  *                                      x = a;
 399  * </programlisting>
 400  *
 401  * does not enforce ordering, since there is no data dependency between
 402  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 403  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 404  * in cases like this where there are no data dependencies.
 405  **/
 406
 407 #define read_barrier_depends()  do { } while (0)
 408
 409 #ifdef CONFIG_SMP
 410 #define smp_mb()        mb()
 411 #ifdef CONFIG_X86_PPRO_FENCE
 412 # define smp_rmb()      rmb()
 413 #else
 414 # define smp_rmb()      barrier()
 415 #endif
 416 #ifdef CONFIG_X86_OOSTORE
 417 # define smp_wmb()      wmb()
 418 #else
 419 # define smp_wmb()      barrier()
 420 #endif
 421 #define smp_read_barrier_depends()      read_barrier_depends()
 422 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
 423 #else
 424 #define smp_mb()        barrier()
 425 #define smp_rmb()       barrier()
 426 #define smp_wmb()       barrier()
 427 #define smp_read_barrier_depends()      do { } while (0)
 428 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 429 #endif
 430
 431 /*
 432  * Stop RDTSC speculation. This is needed when you need to use RDTSC
 433  * (or get_cycles or vread that possibly accesses the TSC) in a defined
 434  * code region.
 435  *
 436  * (Could use an alternative three way for this if there was one.)
 437  */
 438 static inline void rdtsc_barrier(void)
 439 {
 440         alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
 441         alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
 442 }
 443
 444 #endif /* _ASM_X86_SYSTEM_H */