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   1 /*
   2  * $Id: synclinkmp.c,v 4.34 2005/03/04 15:07:10 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/config.h>
  38 #include <linux/module.h>
  39 #include <linux/errno.h>
  40 #include <linux/signal.h>
  41 #include <linux/sched.h>
  42 #include <linux/timer.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/pci.h>
  45 #include <linux/tty.h>
  46 #include <linux/tty_flip.h>
  47 #include <linux/serial.h>
  48 #include <linux/major.h>
  49 #include <linux/string.h>
  50 #include <linux/fcntl.h>
  51 #include <linux/ptrace.h>
  52 #include <linux/ioport.h>
  53 #include <linux/mm.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <asm/serial.h>
  59 #include <linux/delay.h>
  60 #include <linux/ioctl.h>
  61
  62 #include <asm/system.h>
  63 #include <asm/io.h>
  64 #include <asm/irq.h>
  65 #include <asm/dma.h>
  66 #include <linux/bitops.h>
  67 #include <asm/types.h>
  68 #include <linux/termios.h>
  69 #include <linux/workqueue.h>
  70 #include <linux/hdlc.h>
  71
  72 #ifdef CONFIG_HDLC_MODULE
  73 #define CONFIG_HDLC 1
  74 #endif
  75
  76 #define GET_USER(error,value,addr) error = get_user(value,addr)
  77 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  78 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  79 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  80
  81 #include <asm/uaccess.h>
  82
  83 #include "linux/synclink.h"
  84
  85 static MGSL_PARAMS default_params = {
  86         MGSL_MODE_HDLC,                 /* unsigned long mode */
  87         0,                              /* unsigned char loopback; */
  88         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  89         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  90         0,                              /* unsigned long clock_speed; */
  91         0xff,                           /* unsigned char addr_filter; */
  92         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  93         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  94         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  95         9600,                           /* unsigned long data_rate; */
  96         8,                              /* unsigned char data_bits; */
  97         1,                              /* unsigned char stop_bits; */
  98         ASYNC_PARITY_NONE               /* unsigned char parity; */
  99 };
 100
 101 /* size in bytes of DMA data buffers */
 102 #define SCABUFSIZE      1024
 103 #define SCA_MEM_SIZE    0x40000
 104 #define SCA_BASE_SIZE   512
 105 #define SCA_REG_SIZE    16
 106 #define SCA_MAX_PORTS   4
 107 #define SCAMAXDESC      128
 108
 109 #define BUFFERLISTSIZE  4096
 110
 111 /* SCA-I style DMA buffer descriptor */
 112 typedef struct _SCADESC
 113 {
 114         u16     next;           /* lower l6 bits of next descriptor addr */
 115         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 116         u8      buf_base;       /* upper 8 bits of buffer addr */
 117         u8      pad1;
 118         u16     length;         /* length of buffer */
 119         u8      status;         /* status of buffer */
 120         u8      pad2;
 121 } SCADESC, *PSCADESC;
 122
 123 typedef struct _SCADESC_EX
 124 {
 125         /* device driver bookkeeping section */
 126         char    *virt_addr;     /* virtual address of data buffer */
 127         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 128 } SCADESC_EX, *PSCADESC_EX;
 129
 130 /* The queue of BH actions to be performed */
 131
 132 #define BH_RECEIVE  1
 133 #define BH_TRANSMIT 2
 134 #define BH_STATUS   4
 135
 136 #define IO_PIN_SHUTDOWN_LIMIT 100
 137
 138 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 139
 140 struct  _input_signal_events {
 141         int     ri_up;
 142         int     ri_down;
 143         int     dsr_up;
 144         int     dsr_down;
 145         int     dcd_up;
 146         int     dcd_down;
 147         int     cts_up;
 148         int     cts_down;
 149 };
 150
 151 /*
 152  * Device instance data structure
 153  */
 154 typedef struct _synclinkmp_info {
 155         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 156         int                     magic;
 157         int                     flags;
 158         int                     count;          /* count of opens */
 159         int                     line;
 160         unsigned short          close_delay;
 161         unsigned short          closing_wait;   /* time to wait before closing */
 162
 163         struct mgsl_icount      icount;
 164
 165         struct tty_struct       *tty;
 166         int                     timeout;
 167         int                     x_char;         /* xon/xoff character */
 168         int                     blocked_open;   /* # of blocked opens */
 169         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 170         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 171         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 172         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 173         unsigned char           *tx_buf;
 174         int                     tx_put;
 175         int                     tx_get;
 176         int                     tx_count;
 177
 178         wait_queue_head_t       open_wait;
 179         wait_queue_head_t       close_wait;
 180
 181         wait_queue_head_t       status_event_wait_q;
 182         wait_queue_head_t       event_wait_q;
 183         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 184         struct _synclinkmp_info *next_device;   /* device list link */
 185         struct timer_list       status_timer;   /* input signal status check timer */
 186
 187         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 188         struct work_struct task;                        /* task structure for scheduling bh */
 189
 190         u32 max_frame_size;                     /* as set by device config */
 191
 192         u32 pending_bh;
 193
 194         int bh_running;                         /* Protection from multiple */
 195         int isr_overflow;
 196         int bh_requested;
 197
 198         int dcd_chkcount;                       /* check counts to prevent */
 199         int cts_chkcount;                       /* too many IRQs if a signal */
 200         int dsr_chkcount;                       /* is floating */
 201         int ri_chkcount;
 202
 203         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 204         unsigned long buffer_list_phys;
 205
 206         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 207         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 208         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 209         unsigned int current_rx_buf;
 210
 211         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 212         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 213         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 214         unsigned int last_tx_buf;
 215
 216         unsigned char *tmp_rx_buf;
 217         unsigned int tmp_rx_buf_count;
 218
 219         int rx_enabled;
 220         int rx_overflow;
 221
 222         int tx_enabled;
 223         int tx_active;
 224         u32 idle_mode;
 225
 226         unsigned char ie0_value;
 227         unsigned char ie1_value;
 228         unsigned char ie2_value;
 229         unsigned char ctrlreg_value;
 230         unsigned char old_signals;
 231
 232         char device_name[25];                   /* device instance name */
 233
 234         int port_count;
 235         int adapter_num;
 236         int port_num;
 237
 238         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 239
 240         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 241
 242         unsigned int irq_level;                 /* interrupt level */
 243         unsigned long irq_flags;
 244         int irq_requested;                      /* nonzero if IRQ requested */
 245
 246         MGSL_PARAMS params;                     /* communications parameters */
 247
 248         unsigned char serial_signals;           /* current serial signal states */
 249
 250         int irq_occurred;                       /* for diagnostics use */
 251         unsigned int init_error;                /* Initialization startup error */
 252
 253         u32 last_mem_alloc;
 254         unsigned char* memory_base;             /* shared memory address (PCI only) */
 255         u32 phys_memory_base;
 256         int shared_mem_requested;
 257
 258         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 259         u32 phys_sca_base;
 260         u32 sca_offset;
 261         int sca_base_requested;
 262
 263         unsigned char* lcr_base;                /* local config registers (PCI only) */
 264         u32 phys_lcr_base;
 265         u32 lcr_offset;
 266         int lcr_mem_requested;
 267
 268         unsigned char* statctrl_base;           /* status/control register memory */
 269         u32 phys_statctrl_base;
 270         u32 statctrl_offset;
 271         int sca_statctrl_requested;
 272
 273         u32 misc_ctrl_value;
 274         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 275         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 276         BOOLEAN drop_rts_on_tx_done;
 277
 278         struct  _input_signal_events    input_signal_events;
 279
 280         /* SPPP/Cisco HDLC device parts */
 281         int netcount;
 282         int dosyncppp;
 283         spinlock_t netlock;
 284
 285 #ifdef CONFIG_HDLC
 286         struct net_device *netdev;
 287 #endif
 288
 289 } SLMP_INFO;
 290
 291 #define MGSL_MAGIC 0x5401
 292
 293 /*
 294  * define serial signal status change macros
 295  */
 296 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 297 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 298 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 299 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 300
 301 /* Common Register macros */
 302 #define LPR     0x00
 303 #define PABR0   0x02
 304 #define PABR1   0x03
 305 #define WCRL    0x04
 306 #define WCRM    0x05
 307 #define WCRH    0x06
 308 #define DPCR    0x08
 309 #define DMER    0x09
 310 #define ISR0    0x10
 311 #define ISR1    0x11
 312 #define ISR2    0x12
 313 #define IER0    0x14
 314 #define IER1    0x15
 315 #define IER2    0x16
 316 #define ITCR    0x18
 317 #define INTVR   0x1a
 318 #define IMVR    0x1c
 319
 320 /* MSCI Register macros */
 321 #define TRB     0x20
 322 #define TRBL    0x20
 323 #define TRBH    0x21
 324 #define SR0     0x22
 325 #define SR1     0x23
 326 #define SR2     0x24
 327 #define SR3     0x25
 328 #define FST     0x26
 329 #define IE0     0x28
 330 #define IE1     0x29
 331 #define IE2     0x2a
 332 #define FIE     0x2b
 333 #define CMD     0x2c
 334 #define MD0     0x2e
 335 #define MD1     0x2f
 336 #define MD2     0x30
 337 #define CTL     0x31
 338 #define SA0     0x32
 339 #define SA1     0x33
 340 #define IDL     0x34
 341 #define TMC     0x35
 342 #define RXS     0x36
 343 #define TXS     0x37
 344 #define TRC0    0x38
 345 #define TRC1    0x39
 346 #define RRC     0x3a
 347 #define CST0    0x3c
 348 #define CST1    0x3d
 349
 350 /* Timer Register Macros */
 351 #define TCNT    0x60
 352 #define TCNTL   0x60
 353 #define TCNTH   0x61
 354 #define TCONR   0x62
 355 #define TCONRL  0x62
 356 #define TCONRH  0x63
 357 #define TMCS    0x64
 358 #define TEPR    0x65
 359
 360 /* DMA Controller Register macros */
 361 #define DARL    0x80
 362 #define DARH    0x81
 363 #define DARB    0x82
 364 #define BAR     0x80
 365 #define BARL    0x80
 366 #define BARH    0x81
 367 #define BARB    0x82
 368 #define SAR     0x84
 369 #define SARL    0x84
 370 #define SARH    0x85
 371 #define SARB    0x86
 372 #define CPB     0x86
 373 #define CDA     0x88
 374 #define CDAL    0x88
 375 #define CDAH    0x89
 376 #define EDA     0x8a
 377 #define EDAL    0x8a
 378 #define EDAH    0x8b
 379 #define BFL     0x8c
 380 #define BFLL    0x8c
 381 #define BFLH    0x8d
 382 #define BCR     0x8e
 383 #define BCRL    0x8e
 384 #define BCRH    0x8f
 385 #define DSR     0x90
 386 #define DMR     0x91
 387 #define FCT     0x93
 388 #define DIR     0x94
 389 #define DCMD    0x95
 390
 391 /* combine with timer or DMA register address */
 392 #define TIMER0  0x00
 393 #define TIMER1  0x08
 394 #define TIMER2  0x10
 395 #define TIMER3  0x18
 396 #define RXDMA   0x00
 397 #define TXDMA   0x20
 398
 399 /* SCA Command Codes */
 400 #define NOOP            0x00
 401 #define TXRESET         0x01
 402 #define TXENABLE        0x02
 403 #define TXDISABLE       0x03
 404 #define TXCRCINIT       0x04
 405 #define TXCRCEXCL       0x05
 406 #define TXEOM           0x06
 407 #define TXABORT         0x07
 408 #define MPON            0x08
 409 #define TXBUFCLR        0x09
 410 #define RXRESET         0x11
 411 #define RXENABLE        0x12
 412 #define RXDISABLE       0x13
 413 #define RXCRCINIT       0x14
 414 #define RXREJECT        0x15
 415 #define SEARCHMP        0x16
 416 #define RXCRCEXCL       0x17
 417 #define RXCRCCALC       0x18
 418 #define CHRESET         0x21
 419 #define HUNT            0x31
 420
 421 /* DMA command codes */
 422 #define SWABORT         0x01
 423 #define FEICLEAR        0x02
 424
 425 /* IE0 */
 426 #define TXINTE          BIT7
 427 #define RXINTE          BIT6
 428 #define TXRDYE          BIT1
 429 #define RXRDYE          BIT0
 430
 431 /* IE1 & SR1 */
 432 #define UDRN    BIT7
 433 #define IDLE    BIT6
 434 #define SYNCD   BIT4
 435 #define FLGD    BIT4
 436 #define CCTS    BIT3
 437 #define CDCD    BIT2
 438 #define BRKD    BIT1
 439 #define ABTD    BIT1
 440 #define GAPD    BIT1
 441 #define BRKE    BIT0
 442 #define IDLD    BIT0
 443
 444 /* IE2 & SR2 */
 445 #define EOM     BIT7
 446 #define PMP     BIT6
 447 #define SHRT    BIT6
 448 #define PE      BIT5
 449 #define ABT     BIT5
 450 #define FRME    BIT4
 451 #define RBIT    BIT4
 452 #define OVRN    BIT3
 453 #define CRCE    BIT2
 454
 455
 456 /*
 457  * Global linked list of SyncLink devices
 458  */
 459 static SLMP_INFO *synclinkmp_device_list = NULL;
 460 static int synclinkmp_adapter_count = -1;
 461 static int synclinkmp_device_count = 0;
 462
 463 /*
 464  * Set this param to non-zero to load eax with the
 465  * .text section address and breakpoint on module load.
 466  * This is useful for use with gdb and add-symbol-file command.
 467  */
 468 static int break_on_load=0;
 469
 470 /*
 471  * Driver major number, defaults to zero to get auto
 472  * assigned major number. May be forced as module parameter.
 473  */
 474 static int ttymajor=0;
 475
 476 /*
 477  * Array of user specified options for ISA adapters.
 478  */
 479 static int debug_level = 0;
 480 static int maxframe[MAX_DEVICES] = {0,};
 481 static int dosyncppp[MAX_DEVICES] = {0,};
 482
 483 module_param(break_on_load, bool, 0);
 484 module_param(ttymajor, int, 0);
 485 module_param(debug_level, int, 0);
 486 module_param_array(maxframe, int, NULL, 0);
 487 module_param_array(dosyncppp, int, NULL, 0);
 488
 489 static char *driver_name = "SyncLink MultiPort driver";
 490 static char *driver_version = "$Revision: 4.34 $";
 491
 492 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 493 static void synclinkmp_remove_one(struct pci_dev *dev);
 494
 495 static struct pci_device_id synclinkmp_pci_tbl[] = {
 496         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 497         { 0, }, /* terminate list */
 498 };
 499 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 500
 501 MODULE_LICENSE("GPL");
 502
 503 static struct pci_driver synclinkmp_pci_driver = {
 504         .name           = "synclinkmp",
 505         .id_table       = synclinkmp_pci_tbl,
 506         .probe          = synclinkmp_init_one,
 507         .remove         = __devexit_p(synclinkmp_remove_one),
 508 };
 509
 510
 511 static struct tty_driver *serial_driver;
 512
 513 /* number of characters left in xmit buffer before we ask for more */
 514 #define WAKEUP_CHARS 256
 515
 516
 517 /* tty callbacks */
 518
 519 static int  open(struct tty_struct *tty, struct file * filp);
 520 static void close(struct tty_struct *tty, struct file * filp);
 521 static void hangup(struct tty_struct *tty);
 522 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 523
 524 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 525 static void put_char(struct tty_struct *tty, unsigned char ch);
 526 static void send_xchar(struct tty_struct *tty, char ch);
 527 static void wait_until_sent(struct tty_struct *tty, int timeout);
 528 static int  write_room(struct tty_struct *tty);
 529 static void flush_chars(struct tty_struct *tty);
 530 static void flush_buffer(struct tty_struct *tty);
 531 static void tx_hold(struct tty_struct *tty);
 532 static void tx_release(struct tty_struct *tty);
 533
 534 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 535 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 536 static int  chars_in_buffer(struct tty_struct *tty);
 537 static void throttle(struct tty_struct * tty);
 538 static void unthrottle(struct tty_struct * tty);
 539 static void set_break(struct tty_struct *tty, int break_state);
 540
 541 #ifdef CONFIG_HDLC
 542 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 543 static void hdlcdev_tx_done(SLMP_INFO *info);
 544 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 545 static int  hdlcdev_init(SLMP_INFO *info);
 546 static void hdlcdev_exit(SLMP_INFO *info);
 547 #endif
 548
 549 /* ioctl handlers */
 550
 551 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 552 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 553 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 554 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 555 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 556 static int  tx_enable(SLMP_INFO *info, int enable);
 557 static int  tx_abort(SLMP_INFO *info);
 558 static int  rx_enable(SLMP_INFO *info, int enable);
 559 static int  map_status(int signals);
 560 static int  modem_input_wait(SLMP_INFO *info,int arg);
 561 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 562 static int  tiocmget(struct tty_struct *tty, struct file *file);
 563 static int  tiocmset(struct tty_struct *tty, struct file *file,
 564                      unsigned int set, unsigned int clear);
 565 static void set_break(struct tty_struct *tty, int break_state);
 566
 567 static void add_device(SLMP_INFO *info);
 568 static void device_init(int adapter_num, struct pci_dev *pdev);
 569 static int  claim_resources(SLMP_INFO *info);
 570 static void release_resources(SLMP_INFO *info);
 571
 572 static int  startup(SLMP_INFO *info);
 573 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 574 static void shutdown(SLMP_INFO *info);
 575 static void program_hw(SLMP_INFO *info);
 576 static void change_params(SLMP_INFO *info);
 577
 578 static int  init_adapter(SLMP_INFO *info);
 579 static int  register_test(SLMP_INFO *info);
 580 static int  irq_test(SLMP_INFO *info);
 581 static int  loopback_test(SLMP_INFO *info);
 582 static int  adapter_test(SLMP_INFO *info);
 583 static int  memory_test(SLMP_INFO *info);
 584
 585 static void reset_adapter(SLMP_INFO *info);
 586 static void reset_port(SLMP_INFO *info);
 587 static void async_mode(SLMP_INFO *info);
 588 static void hdlc_mode(SLMP_INFO *info);
 589
 590 static void rx_stop(SLMP_INFO *info);
 591 static void rx_start(SLMP_INFO *info);
 592 static void rx_reset_buffers(SLMP_INFO *info);
 593 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 594 static int  rx_get_frame(SLMP_INFO *info);
 595
 596 static void tx_start(SLMP_INFO *info);
 597 static void tx_stop(SLMP_INFO *info);
 598 static void tx_load_fifo(SLMP_INFO *info);
 599 static void tx_set_idle(SLMP_INFO *info);
 600 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 601
 602 static void get_signals(SLMP_INFO *info);
 603 static void set_signals(SLMP_INFO *info);
 604 static void enable_loopback(SLMP_INFO *info, int enable);
 605 static void set_rate(SLMP_INFO *info, u32 data_rate);
 606
 607 static int  bh_action(SLMP_INFO *info);
 608 static void bh_handler(void* Context);
 609 static void bh_receive(SLMP_INFO *info);
 610 static void bh_transmit(SLMP_INFO *info);
 611 static void bh_status(SLMP_INFO *info);
 612 static void isr_timer(SLMP_INFO *info);
 613 static void isr_rxint(SLMP_INFO *info);
 614 static void isr_rxrdy(SLMP_INFO *info);
 615 static void isr_txint(SLMP_INFO *info);
 616 static void isr_txrdy(SLMP_INFO *info);
 617 static void isr_rxdmaok(SLMP_INFO *info);
 618 static void isr_rxdmaerror(SLMP_INFO *info);
 619 static void isr_txdmaok(SLMP_INFO *info);
 620 static void isr_txdmaerror(SLMP_INFO *info);
 621 static void isr_io_pin(SLMP_INFO *info, u16 status);
 622
 623 static int  alloc_dma_bufs(SLMP_INFO *info);
 624 static void free_dma_bufs(SLMP_INFO *info);
 625 static int  alloc_buf_list(SLMP_INFO *info);
 626 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 627 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 628 static void free_tmp_rx_buf(SLMP_INFO *info);
 629
 630 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 631 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 632 static void tx_timeout(unsigned long context);
 633 static void status_timeout(unsigned long context);
 634
 635 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 636 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 637 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 638 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 639 static unsigned char read_status_reg(SLMP_INFO * info);
 640 static void write_control_reg(SLMP_INFO * info);
 641
 642
 643 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 644 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 645 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 646
 647 static u32 misc_ctrl_value = 0x007e4040;
 648 static u32 lcr1_brdr_value = 0x00800029;
 649
 650 static u32 read_ahead_count = 8;
 651
 652 /* DPCR, DMA Priority Control
 653  *
 654  * 07..05  Not used, must be 0
 655  * 04      BRC, bus release condition: 0=all transfers complete
 656  *              1=release after 1 xfer on all channels
 657  * 03      CCC, channel change condition: 0=every cycle
 658  *              1=after each channel completes all xfers
 659  * 02..00  PR<2..0>, priority 100=round robin
 660  *
 661  * 00000100 = 0x00
 662  */
 663 static unsigned char dma_priority = 0x04;
 664
 665 // Number of bytes that can be written to shared RAM
 666 // in a single write operation
 667 static u32 sca_pci_load_interval = 64;
 668
 669 /*
 670  * 1st function defined in .text section. Calling this function in
 671  * init_module() followed by a breakpoint allows a remote debugger
 672  * (gdb) to get the .text address for the add-symbol-file command.
 673  * This allows remote debugging of dynamically loadable modules.
 674  */
 675 static void* synclinkmp_get_text_ptr(void);
 676 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 677
 678 static inline int sanity_check(SLMP_INFO *info,
 679                                char *name, const char *routine)
 680 {
 681 #ifdef SANITY_CHECK
 682         static const char *badmagic =
 683                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 684         static const char *badinfo =
 685                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 686
 687         if (!info) {
 688                 printk(badinfo, name, routine);
 689                 return 1;
 690         }
 691         if (info->magic != MGSL_MAGIC) {
 692                 printk(badmagic, name, routine);
 693                 return 1;
 694         }
 695 #else
 696         if (!info)
 697                 return 1;
 698 #endif
 699         return 0;
 700 }
 701
 702 /**
 703  * line discipline callback wrappers
 704  *
 705  * The wrappers maintain line discipline references
 706  * while calling into the line discipline.
 707  *
 708  * ldisc_receive_buf  - pass receive data to line discipline
 709  */
 710
 711 static void ldisc_receive_buf(struct tty_struct *tty,
 712                               const __u8 *data, char *flags, int count)
 713 {
 714         struct tty_ldisc *ld;
 715         if (!tty)
 716                 return;
 717         ld = tty_ldisc_ref(tty);
 718         if (ld) {
 719                 if (ld->receive_buf)
 720                         ld->receive_buf(tty, data, flags, count);
 721                 tty_ldisc_deref(ld);
 722         }
 723 }
 724
 725 /* tty callbacks */
 726
 727 /* Called when a port is opened.  Init and enable port.
 728  */
 729 static int open(struct tty_struct *tty, struct file *filp)
 730 {
 731         SLMP_INFO *info;
 732         int retval, line;
 733         unsigned long flags;
 734
 735         line = tty->index;
 736         if ((line < 0) || (line >= synclinkmp_device_count)) {
 737                 printk("%s(%d): open with invalid line #%d.\n",
 738                         __FILE__,__LINE__,line);
 739                 return -ENODEV;
 740         }
 741
 742         info = synclinkmp_device_list;
 743         while(info && info->line != line)
 744                 info = info->next_device;
 745         if (sanity_check(info, tty->name, "open"))
 746                 return -ENODEV;
 747         if ( info->init_error ) {
 748                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 749                         __FILE__,__LINE__,info->device_name,info->init_error);
 750                 return -ENODEV;
 751         }
 752
 753         tty->driver_data = info;
 754         info->tty = tty;
 755
 756         if (debug_level >= DEBUG_LEVEL_INFO)
 757                 printk("%s(%d):%s open(), old ref count = %d\n",
 758                          __FILE__,__LINE__,tty->driver->name, info->count);
 759
 760         /* If port is closing, signal caller to try again */
 761         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 762                 if (info->flags & ASYNC_CLOSING)
 763                         interruptible_sleep_on(&info->close_wait);
 764                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 765                         -EAGAIN : -ERESTARTSYS);
 766                 goto cleanup;
 767         }
 768
 769         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 770
 771         spin_lock_irqsave(&info->netlock, flags);
 772         if (info->netcount) {
 773                 retval = -EBUSY;
 774                 spin_unlock_irqrestore(&info->netlock, flags);
 775                 goto cleanup;
 776         }
 777         info->count++;
 778         spin_unlock_irqrestore(&info->netlock, flags);
 779
 780         if (info->count == 1) {
 781                 /* 1st open on this device, init hardware */
 782                 retval = startup(info);
 783                 if (retval < 0)
 784                         goto cleanup;
 785         }
 786
 787         retval = block_til_ready(tty, filp, info);
 788         if (retval) {
 789                 if (debug_level >= DEBUG_LEVEL_INFO)
 790                         printk("%s(%d):%s block_til_ready() returned %d\n",
 791                                  __FILE__,__LINE__, info->device_name, retval);
 792                 goto cleanup;
 793         }
 794
 795         if (debug_level >= DEBUG_LEVEL_INFO)
 796                 printk("%s(%d):%s open() success\n",
 797                          __FILE__,__LINE__, info->device_name);
 798         retval = 0;
 799
 800 cleanup:
 801         if (retval) {
 802                 if (tty->count == 1)
 803                         info->tty = NULL; /* tty layer will release tty struct */
 804                 if(info->count)
 805                         info->count--;
 806         }
 807
 808         return retval;
 809 }
 810
 811 /* Called when port is closed. Wait for remaining data to be
 812  * sent. Disable port and free resources.
 813  */
 814 static void close(struct tty_struct *tty, struct file *filp)
 815 {
 816         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 817
 818         if (sanity_check(info, tty->name, "close"))
 819                 return;
 820
 821         if (debug_level >= DEBUG_LEVEL_INFO)
 822                 printk("%s(%d):%s close() entry, count=%d\n",
 823                          __FILE__,__LINE__, info->device_name, info->count);
 824
 825         if (!info->count)
 826                 return;
 827
 828         if (tty_hung_up_p(filp))
 829                 goto cleanup;
 830
 831         if ((tty->count == 1) && (info->count != 1)) {
 832                 /*
 833                  * tty->count is 1 and the tty structure will be freed.
 834                  * info->count should be one in this case.
 835                  * if it's not, correct it so that the port is shutdown.
 836                  */
 837                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 838                        "info->count is %d\n",
 839                          __FILE__,__LINE__, info->device_name, info->count);
 840                 info->count = 1;
 841         }
 842
 843         info->count--;
 844
 845         /* if at least one open remaining, leave hardware active */
 846         if (info->count)
 847                 goto cleanup;
 848
 849         info->flags |= ASYNC_CLOSING;
 850
 851         /* set tty->closing to notify line discipline to
 852          * only process XON/XOFF characters. Only the N_TTY
 853          * discipline appears to use this (ppp does not).
 854          */
 855         tty->closing = 1;
 856
 857         /* wait for transmit data to clear all layers */
 858
 859         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 860                 if (debug_level >= DEBUG_LEVEL_INFO)
 861                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 862                                  __FILE__,__LINE__, info->device_name );
 863                 tty_wait_until_sent(tty, info->closing_wait);
 864         }
 865
 866         if (info->flags & ASYNC_INITIALIZED)
 867                 wait_until_sent(tty, info->timeout);
 868
 869         if (tty->driver->flush_buffer)
 870                 tty->driver->flush_buffer(tty);
 871
 872         tty_ldisc_flush(tty);
 873
 874         shutdown(info);
 875
 876         tty->closing = 0;
 877         info->tty = NULL;
 878
 879         if (info->blocked_open) {
 880                 if (info->close_delay) {
 881                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 882                 }
 883                 wake_up_interruptible(&info->open_wait);
 884         }
 885
 886         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 887
 888         wake_up_interruptible(&info->close_wait);
 889
 890 cleanup:
 891         if (debug_level >= DEBUG_LEVEL_INFO)
 892                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 893                         tty->driver->name, info->count);
 894 }
 895
 896 /* Called by tty_hangup() when a hangup is signaled.
 897  * This is the same as closing all open descriptors for the port.
 898  */
 899 static void hangup(struct tty_struct *tty)
 900 {
 901         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 902
 903         if (debug_level >= DEBUG_LEVEL_INFO)
 904                 printk("%s(%d):%s hangup()\n",
 905                          __FILE__,__LINE__, info->device_name );
 906
 907         if (sanity_check(info, tty->name, "hangup"))
 908                 return;
 909
 910         flush_buffer(tty);
 911         shutdown(info);
 912
 913         info->count = 0;
 914         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 915         info->tty = NULL;
 916
 917         wake_up_interruptible(&info->open_wait);
 918 }
 919
 920 /* Set new termios settings
 921  */
 922 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 923 {
 924         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 925         unsigned long flags;
 926
 927         if (debug_level >= DEBUG_LEVEL_INFO)
 928                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 929                         tty->driver->name );
 930
 931         /* just return if nothing has changed */
 932         if ((tty->termios->c_cflag == old_termios->c_cflag)
 933             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 934                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 935           return;
 936
 937         change_params(info);
 938
 939         /* Handle transition to B0 status */
 940         if (old_termios->c_cflag & CBAUD &&
 941             !(tty->termios->c_cflag & CBAUD)) {
 942                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 943                 spin_lock_irqsave(&info->lock,flags);
 944                 set_signals(info);
 945                 spin_unlock_irqrestore(&info->lock,flags);
 946         }
 947
 948         /* Handle transition away from B0 status */
 949         if (!(old_termios->c_cflag & CBAUD) &&
 950             tty->termios->c_cflag & CBAUD) {
 951                 info->serial_signals |= SerialSignal_DTR;
 952                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 953                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 954                         info->serial_signals |= SerialSignal_RTS;
 955                 }
 956                 spin_lock_irqsave(&info->lock,flags);
 957                 set_signals(info);
 958                 spin_unlock_irqrestore(&info->lock,flags);
 959         }
 960
 961         /* Handle turning off CRTSCTS */
 962         if (old_termios->c_cflag & CRTSCTS &&
 963             !(tty->termios->c_cflag & CRTSCTS)) {
 964                 tty->hw_stopped = 0;
 965                 tx_release(tty);
 966         }
 967 }
 968
 969 /* Send a block of data
 970  *
 971  * Arguments:
 972  *
 973  *      tty             pointer to tty information structure
 974  *      buf             pointer to buffer containing send data
 975  *      count           size of send data in bytes
 976  *
 977  * Return Value:        number of characters written
 978  */
 979 static int write(struct tty_struct *tty,
 980                  const unsigned char *buf, int count)
 981 {
 982         int     c, ret = 0;
 983         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 984         unsigned long flags;
 985
 986         if (debug_level >= DEBUG_LEVEL_INFO)
 987                 printk("%s(%d):%s write() count=%d\n",
 988                        __FILE__,__LINE__,info->device_name,count);
 989
 990         if (sanity_check(info, tty->name, "write"))
 991                 goto cleanup;
 992
 993         if (!tty || !info->tx_buf)
 994                 goto cleanup;
 995
 996         if (info->params.mode == MGSL_MODE_HDLC) {
 997                 if (count > info->max_frame_size) {
 998                         ret = -EIO;
 999                         goto cleanup;
1000                 }
1001                 if (info->tx_active)
1002                         goto cleanup;
1003                 if (info->tx_count) {
1004                         /* send accumulated data from send_char() calls */
1005                         /* as frame and wait before accepting more data. */
1006                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1007                         goto start;
1008                 }
1009                 ret = info->tx_count = count;
1010                 tx_load_dma_buffer(info, buf, count);
1011                 goto start;
1012         }
1013
1014         for (;;) {
1015                 c = min_t(int, count,
1016                         min(info->max_frame_size - info->tx_count - 1,
1017                             info->max_frame_size - info->tx_put));
1018                 if (c <= 0)
1019                         break;
1020
1021                 memcpy(info->tx_buf + info->tx_put, buf, c);
1022
1023                 spin_lock_irqsave(&info->lock,flags);
1024                 info->tx_put += c;
1025                 if (info->tx_put >= info->max_frame_size)
1026                         info->tx_put -= info->max_frame_size;
1027                 info->tx_count += c;
1028                 spin_unlock_irqrestore(&info->lock,flags);
1029
1030                 buf += c;
1031                 count -= c;
1032                 ret += c;
1033         }
1034
1035         if (info->params.mode == MGSL_MODE_HDLC) {
1036                 if (count) {
1037                         ret = info->tx_count = 0;
1038                         goto cleanup;
1039                 }
1040                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1041         }
1042 start:
1043         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1044                 spin_lock_irqsave(&info->lock,flags);
1045                 if (!info->tx_active)
1046                         tx_start(info);
1047                 spin_unlock_irqrestore(&info->lock,flags);
1048         }
1049
1050 cleanup:
1051         if (debug_level >= DEBUG_LEVEL_INFO)
1052                 printk( "%s(%d):%s write() returning=%d\n",
1053                         __FILE__,__LINE__,info->device_name,ret);
1054         return ret;
1055 }
1056
1057 /* Add a character to the transmit buffer.
1058  */
1059 static void put_char(struct tty_struct *tty, unsigned char ch)
1060 {
1061         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1062         unsigned long flags;
1063
1064         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1065                 printk( "%s(%d):%s put_char(%d)\n",
1066                         __FILE__,__LINE__,info->device_name,ch);
1067         }
1068
1069         if (sanity_check(info, tty->name, "put_char"))
1070                 return;
1071
1072         if (!tty || !info->tx_buf)
1073                 return;
1074
1075         spin_lock_irqsave(&info->lock,flags);
1076
1077         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1078              !info->tx_active ) {
1079
1080                 if (info->tx_count < info->max_frame_size - 1) {
1081                         info->tx_buf[info->tx_put++] = ch;
1082                         if (info->tx_put >= info->max_frame_size)
1083                                 info->tx_put -= info->max_frame_size;
1084                         info->tx_count++;
1085                 }
1086         }
1087
1088         spin_unlock_irqrestore(&info->lock,flags);
1089 }
1090
1091 /* Send a high-priority XON/XOFF character
1092  */
1093 static void send_xchar(struct tty_struct *tty, char ch)
1094 {
1095         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1096         unsigned long flags;
1097
1098         if (debug_level >= DEBUG_LEVEL_INFO)
1099                 printk("%s(%d):%s send_xchar(%d)\n",
1100                          __FILE__,__LINE__, info->device_name, ch );
1101
1102         if (sanity_check(info, tty->name, "send_xchar"))
1103                 return;
1104
1105         info->x_char = ch;
1106         if (ch) {
1107                 /* Make sure transmit interrupts are on */
1108                 spin_lock_irqsave(&info->lock,flags);
1109                 if (!info->tx_enabled)
1110                         tx_start(info);
1111                 spin_unlock_irqrestore(&info->lock,flags);
1112         }
1113 }
1114
1115 /* Wait until the transmitter is empty.
1116  */
1117 static void wait_until_sent(struct tty_struct *tty, int timeout)
1118 {
1119         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1120         unsigned long orig_jiffies, char_time;
1121
1122         if (!info )
1123                 return;
1124
1125         if (debug_level >= DEBUG_LEVEL_INFO)
1126                 printk("%s(%d):%s wait_until_sent() entry\n",
1127                          __FILE__,__LINE__, info->device_name );
1128
1129         if (sanity_check(info, tty->name, "wait_until_sent"))
1130                 return;
1131
1132         if (!(info->flags & ASYNC_INITIALIZED))
1133                 goto exit;
1134
1135         orig_jiffies = jiffies;
1136
1137         /* Set check interval to 1/5 of estimated time to
1138          * send a character, and make it at least 1. The check
1139          * interval should also be less than the timeout.
1140          * Note: use tight timings here to satisfy the NIST-PCTS.
1141          */
1142
1143         if ( info->params.data_rate ) {
1144                 char_time = info->timeout/(32 * 5);
1145                 if (!char_time)
1146                         char_time++;
1147         } else
1148                 char_time = 1;
1149
1150         if (timeout)
1151                 char_time = min_t(unsigned long, char_time, timeout);
1152
1153         if ( info->params.mode == MGSL_MODE_HDLC ) {
1154                 while (info->tx_active) {
1155                         msleep_interruptible(jiffies_to_msecs(char_time));
1156                         if (signal_pending(current))
1157                                 break;
1158                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1159                                 break;
1160                 }
1161         } else {
1162                 //TODO: determine if there is something similar to USC16C32
1163                 //      TXSTATUS_ALL_SENT status
1164                 while ( info->tx_active && info->tx_enabled) {
1165                         msleep_interruptible(jiffies_to_msecs(char_time));
1166                         if (signal_pending(current))
1167                                 break;
1168                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1169                                 break;
1170                 }
1171         }
1172
1173 exit:
1174         if (debug_level >= DEBUG_LEVEL_INFO)
1175                 printk("%s(%d):%s wait_until_sent() exit\n",
1176                          __FILE__,__LINE__, info->device_name );
1177 }
1178
1179 /* Return the count of free bytes in transmit buffer
1180  */
1181 static int write_room(struct tty_struct *tty)
1182 {
1183         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1184         int ret;
1185
1186         if (sanity_check(info, tty->name, "write_room"))
1187                 return 0;
1188
1189         if (info->params.mode == MGSL_MODE_HDLC) {
1190                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1191         } else {
1192                 ret = info->max_frame_size - info->tx_count - 1;
1193                 if (ret < 0)
1194                         ret = 0;
1195         }
1196
1197         if (debug_level >= DEBUG_LEVEL_INFO)
1198                 printk("%s(%d):%s write_room()=%d\n",
1199                        __FILE__, __LINE__, info->device_name, ret);
1200
1201         return ret;
1202 }
1203
1204 /* enable transmitter and send remaining buffered characters
1205  */
1206 static void flush_chars(struct tty_struct *tty)
1207 {
1208         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1209         unsigned long flags;
1210
1211         if ( debug_level >= DEBUG_LEVEL_INFO )
1212                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1213                         __FILE__,__LINE__,info->device_name,info->tx_count);
1214
1215         if (sanity_check(info, tty->name, "flush_chars"))
1216                 return;
1217
1218         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1219             !info->tx_buf)
1220                 return;
1221
1222         if ( debug_level >= DEBUG_LEVEL_INFO )
1223                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1224                         __FILE__,__LINE__,info->device_name );
1225
1226         spin_lock_irqsave(&info->lock,flags);
1227
1228         if (!info->tx_active) {
1229                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1230                         info->tx_count ) {
1231                         /* operating in synchronous (frame oriented) mode */
1232                         /* copy data from circular tx_buf to */
1233                         /* transmit DMA buffer. */
1234                         tx_load_dma_buffer(info,
1235                                  info->tx_buf,info->tx_count);
1236                 }
1237                 tx_start(info);
1238         }
1239
1240         spin_unlock_irqrestore(&info->lock,flags);
1241 }
1242
1243 /* Discard all data in the send buffer
1244  */
1245 static void flush_buffer(struct tty_struct *tty)
1246 {
1247         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1248         unsigned long flags;
1249
1250         if (debug_level >= DEBUG_LEVEL_INFO)
1251                 printk("%s(%d):%s flush_buffer() entry\n",
1252                          __FILE__,__LINE__, info->device_name );
1253
1254         if (sanity_check(info, tty->name, "flush_buffer"))
1255                 return;
1256
1257         spin_lock_irqsave(&info->lock,flags);
1258         info->tx_count = info->tx_put = info->tx_get = 0;
1259         del_timer(&info->tx_timer);
1260         spin_unlock_irqrestore(&info->lock,flags);
1261
1262         wake_up_interruptible(&tty->write_wait);
1263         tty_wakeup(tty);
1264 }
1265
1266 /* throttle (stop) transmitter
1267  */
1268 static void tx_hold(struct tty_struct *tty)
1269 {
1270         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1271         unsigned long flags;
1272
1273         if (sanity_check(info, tty->name, "tx_hold"))
1274                 return;
1275
1276         if ( debug_level >= DEBUG_LEVEL_INFO )
1277                 printk("%s(%d):%s tx_hold()\n",
1278                         __FILE__,__LINE__,info->device_name);
1279
1280         spin_lock_irqsave(&info->lock,flags);
1281         if (info->tx_enabled)
1282                 tx_stop(info);
1283         spin_unlock_irqrestore(&info->lock,flags);
1284 }
1285
1286 /* release (start) transmitter
1287  */
1288 static void tx_release(struct tty_struct *tty)
1289 {
1290         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1291         unsigned long flags;
1292
1293         if (sanity_check(info, tty->name, "tx_release"))
1294                 return;
1295
1296         if ( debug_level >= DEBUG_LEVEL_INFO )
1297                 printk("%s(%d):%s tx_release()\n",
1298                         __FILE__,__LINE__,info->device_name);
1299
1300         spin_lock_irqsave(&info->lock,flags);
1301         if (!info->tx_enabled)
1302                 tx_start(info);
1303         spin_unlock_irqrestore(&info->lock,flags);
1304 }
1305
1306 /* Service an IOCTL request
1307  *
1308  * Arguments:
1309  *
1310  *      tty     pointer to tty instance data
1311  *      file    pointer to associated file object for device
1312  *      cmd     IOCTL command code
1313  *      arg     command argument/context
1314  *
1315  * Return Value:        0 if success, otherwise error code
1316  */
1317 static int ioctl(struct tty_struct *tty, struct file *file,
1318                  unsigned int cmd, unsigned long arg)
1319 {
1320         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1321         int error;
1322         struct mgsl_icount cnow;        /* kernel counter temps */
1323         struct serial_icounter_struct __user *p_cuser;  /* user space */
1324         unsigned long flags;
1325         void __user *argp = (void __user *)arg;
1326
1327         if (debug_level >= DEBUG_LEVEL_INFO)
1328                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1329                         info->device_name, cmd );
1330
1331         if (sanity_check(info, tty->name, "ioctl"))
1332                 return -ENODEV;
1333
1334         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1335             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1336                 if (tty->flags & (1 << TTY_IO_ERROR))
1337                     return -EIO;
1338         }
1339
1340         switch (cmd) {
1341         case MGSL_IOCGPARAMS:
1342                 return get_params(info, argp);
1343         case MGSL_IOCSPARAMS:
1344                 return set_params(info, argp);
1345         case MGSL_IOCGTXIDLE:
1346                 return get_txidle(info, argp);
1347         case MGSL_IOCSTXIDLE:
1348                 return set_txidle(info, (int)arg);
1349         case MGSL_IOCTXENABLE:
1350                 return tx_enable(info, (int)arg);
1351         case MGSL_IOCRXENABLE:
1352                 return rx_enable(info, (int)arg);
1353         case MGSL_IOCTXABORT:
1354                 return tx_abort(info);
1355         case MGSL_IOCGSTATS:
1356                 return get_stats(info, argp);
1357         case MGSL_IOCWAITEVENT:
1358                 return wait_mgsl_event(info, argp);
1359         case MGSL_IOCLOOPTXDONE:
1360                 return 0; // TODO: Not supported, need to document
1361                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1362                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1363                  */
1364         case TIOCMIWAIT:
1365                 return modem_input_wait(info,(int)arg);
1366
1367                 /*
1368                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1369                  * Return: write counters to the user passed counter struct
1370                  * NB: both 1->0 and 0->1 transitions are counted except for
1371                  *     RI where only 0->1 is counted.
1372                  */
1373         case TIOCGICOUNT:
1374                 spin_lock_irqsave(&info->lock,flags);
1375                 cnow = info->icount;
1376                 spin_unlock_irqrestore(&info->lock,flags);
1377                 p_cuser = argp;
1378                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1379                 if (error) return error;
1380                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1381                 if (error) return error;
1382                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1383                 if (error) return error;
1384                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1385                 if (error) return error;
1386                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1387                 if (error) return error;
1388                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1389                 if (error) return error;
1390                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1391                 if (error) return error;
1392                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1393                 if (error) return error;
1394                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1395                 if (error) return error;
1396                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1397                 if (error) return error;
1398                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1399                 if (error) return error;
1400                 return 0;
1401         default:
1402                 return -ENOIOCTLCMD;
1403         }
1404         return 0;
1405 }
1406
1407 /*
1408  * /proc fs routines....
1409  */
1410
1411 static inline int line_info(char *buf, SLMP_INFO *info)
1412 {
1413         char    stat_buf[30];
1414         int     ret;
1415         unsigned long flags;
1416
1417         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1418                        "\tIRQ=%d MaxFrameSize=%u\n",
1419                 info->device_name,
1420                 info->phys_sca_base,
1421                 info->phys_memory_base,
1422                 info->phys_statctrl_base,
1423                 info->phys_lcr_base,
1424                 info->irq_level,
1425                 info->max_frame_size );
1426
1427         /* output current serial signal states */
1428         spin_lock_irqsave(&info->lock,flags);
1429         get_signals(info);
1430         spin_unlock_irqrestore(&info->lock,flags);
1431
1432         stat_buf[0] = 0;
1433         stat_buf[1] = 0;
1434         if (info->serial_signals & SerialSignal_RTS)
1435                 strcat(stat_buf, "|RTS");
1436         if (info->serial_signals & SerialSignal_CTS)
1437                 strcat(stat_buf, "|CTS");
1438         if (info->serial_signals & SerialSignal_DTR)
1439                 strcat(stat_buf, "|DTR");
1440         if (info->serial_signals & SerialSignal_DSR)
1441                 strcat(stat_buf, "|DSR");
1442         if (info->serial_signals & SerialSignal_DCD)
1443                 strcat(stat_buf, "|CD");
1444         if (info->serial_signals & SerialSignal_RI)
1445                 strcat(stat_buf, "|RI");
1446
1447         if (info->params.mode == MGSL_MODE_HDLC) {
1448                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1449                               info->icount.txok, info->icount.rxok);
1450                 if (info->icount.txunder)
1451                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1452                 if (info->icount.txabort)
1453                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1454                 if (info->icount.rxshort)
1455                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1456                 if (info->icount.rxlong)
1457                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1458                 if (info->icount.rxover)
1459                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1460                 if (info->icount.rxcrc)
1461                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1462         } else {
1463                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1464                               info->icount.tx, info->icount.rx);
1465                 if (info->icount.frame)
1466                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1467                 if (info->icount.parity)
1468                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1469                 if (info->icount.brk)
1470                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1471                 if (info->icount.overrun)
1472                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1473         }
1474
1475         /* Append serial signal status to end */
1476         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1477
1478         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1479          info->tx_active,info->bh_requested,info->bh_running,
1480          info->pending_bh);
1481
1482         return ret;
1483 }
1484
1485 /* Called to print information about devices
1486  */
1487 int read_proc(char *page, char **start, off_t off, int count,
1488               int *eof, void *data)
1489 {
1490         int len = 0, l;
1491         off_t   begin = 0;
1492         SLMP_INFO *info;
1493
1494         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1495
1496         info = synclinkmp_device_list;
1497         while( info ) {
1498                 l = line_info(page + len, info);
1499                 len += l;
1500                 if (len+begin > off+count)
1501                         goto done;
1502                 if (len+begin < off) {
1503                         begin += len;
1504                         len = 0;
1505                 }
1506                 info = info->next_device;
1507         }
1508
1509         *eof = 1;
1510 done:
1511         if (off >= len+begin)
1512                 return 0;
1513         *start = page + (off-begin);
1514         return ((count < begin+len-off) ? count : begin+len-off);
1515 }
1516
1517 /* Return the count of bytes in transmit buffer
1518  */
1519 static int chars_in_buffer(struct tty_struct *tty)
1520 {
1521         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1522
1523         if (sanity_check(info, tty->name, "chars_in_buffer"))
1524                 return 0;
1525
1526         if (debug_level >= DEBUG_LEVEL_INFO)
1527                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1528                        __FILE__, __LINE__, info->device_name, info->tx_count);
1529
1530         return info->tx_count;
1531 }
1532
1533 /* Signal remote device to throttle send data (our receive data)
1534  */
1535 static void throttle(struct tty_struct * tty)
1536 {
1537         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1538         unsigned long flags;
1539
1540         if (debug_level >= DEBUG_LEVEL_INFO)
1541                 printk("%s(%d):%s throttle() entry\n",
1542                          __FILE__,__LINE__, info->device_name );
1543
1544         if (sanity_check(info, tty->name, "throttle"))
1545                 return;
1546
1547         if (I_IXOFF(tty))
1548                 send_xchar(tty, STOP_CHAR(tty));
1549
1550         if (tty->termios->c_cflag & CRTSCTS) {
1551                 spin_lock_irqsave(&info->lock,flags);
1552                 info->serial_signals &= ~SerialSignal_RTS;
1553                 set_signals(info);
1554                 spin_unlock_irqrestore(&info->lock,flags);
1555         }
1556 }
1557
1558 /* Signal remote device to stop throttling send data (our receive data)
1559  */
1560 static void unthrottle(struct tty_struct * tty)
1561 {
1562         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1563         unsigned long flags;
1564
1565         if (debug_level >= DEBUG_LEVEL_INFO)
1566                 printk("%s(%d):%s unthrottle() entry\n",
1567                          __FILE__,__LINE__, info->device_name );
1568
1569         if (sanity_check(info, tty->name, "unthrottle"))
1570                 return;
1571
1572         if (I_IXOFF(tty)) {
1573                 if (info->x_char)
1574                         info->x_char = 0;
1575                 else
1576                         send_xchar(tty, START_CHAR(tty));
1577         }
1578
1579         if (tty->termios->c_cflag & CRTSCTS) {
1580                 spin_lock_irqsave(&info->lock,flags);
1581                 info->serial_signals |= SerialSignal_RTS;
1582                 set_signals(info);
1583                 spin_unlock_irqrestore(&info->lock,flags);
1584         }
1585 }
1586
1587 /* set or clear transmit break condition
1588  * break_state  -1=set break condition, 0=clear
1589  */
1590 static void set_break(struct tty_struct *tty, int break_state)
1591 {
1592         unsigned char RegValue;
1593         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1594         unsigned long flags;
1595
1596         if (debug_level >= DEBUG_LEVEL_INFO)
1597                 printk("%s(%d):%s set_break(%d)\n",
1598                          __FILE__,__LINE__, info->device_name, break_state);
1599
1600         if (sanity_check(info, tty->name, "set_break"))
1601                 return;
1602
1603         spin_lock_irqsave(&info->lock,flags);
1604         RegValue = read_reg(info, CTL);
1605         if (break_state == -1)
1606                 RegValue |= BIT3;
1607         else
1608                 RegValue &= ~BIT3;
1609         write_reg(info, CTL, RegValue);
1610         spin_unlock_irqrestore(&info->lock,flags);
1611 }
1612
1613 #ifdef CONFIG_HDLC
1614
1615 /**
1616  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1617  * set encoding and frame check sequence (FCS) options
1618  *
1619  * dev       pointer to network device structure
1620  * encoding  serial encoding setting
1621  * parity    FCS setting
1622  *
1623  * returns 0 if success, otherwise error code
1624  */
1625 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1626                           unsigned short parity)
1627 {
1628         SLMP_INFO *info = dev_to_port(dev);
1629         unsigned char  new_encoding;
1630         unsigned short new_crctype;
1631
1632         /* return error if TTY interface open */
1633         if (info->count)
1634                 return -EBUSY;
1635
1636         switch (encoding)
1637         {
1638         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1639         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1640         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1641         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1642         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1643         default: return -EINVAL;
1644         }
1645
1646         switch (parity)
1647         {
1648         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1649         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1650         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1651         default: return -EINVAL;
1652         }
1653
1654         info->params.encoding = new_encoding;
1655         info->params.crc_type = new_crctype;;
1656
1657         /* if network interface up, reprogram hardware */
1658         if (info->netcount)
1659                 program_hw(info);
1660
1661         return 0;
1662 }
1663
1664 /**
1665  * called by generic HDLC layer to send frame
1666  *
1667  * skb  socket buffer containing HDLC frame
1668  * dev  pointer to network device structure
1669  *
1670  * returns 0 if success, otherwise error code
1671  */
1672 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1673 {
1674         SLMP_INFO *info = dev_to_port(dev);
1675         struct net_device_stats *stats = hdlc_stats(dev);
1676         unsigned long flags;
1677
1678         if (debug_level >= DEBUG_LEVEL_INFO)
1679                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1680
1681         /* stop sending until this frame completes */
1682         netif_stop_queue(dev);
1683
1684         /* copy data to device buffers */
1685         info->tx_count = skb->len;
1686         tx_load_dma_buffer(info, skb->data, skb->len);
1687
1688         /* update network statistics */
1689         stats->tx_packets++;
1690         stats->tx_bytes += skb->len;
1691
1692         /* done with socket buffer, so free it */
1693         dev_kfree_skb(skb);
1694
1695         /* save start time for transmit timeout detection */
1696         dev->trans_start = jiffies;
1697
1698         /* start hardware transmitter if necessary */
1699         spin_lock_irqsave(&info->lock,flags);
1700         if (!info->tx_active)
1701                 tx_start(info);
1702         spin_unlock_irqrestore(&info->lock,flags);
1703
1704         return 0;
1705 }
1706
1707 /**
1708  * called by network layer when interface enabled
1709  * claim resources and initialize hardware
1710  *
1711  * dev  pointer to network device structure
1712  *
1713  * returns 0 if success, otherwise error code
1714  */
1715 static int hdlcdev_open(struct net_device *dev)
1716 {
1717         SLMP_INFO *info = dev_to_port(dev);
1718         int rc;
1719         unsigned long flags;
1720
1721         if (debug_level >= DEBUG_LEVEL_INFO)
1722                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1723
1724         /* generic HDLC layer open processing */
1725         if ((rc = hdlc_open(dev)))
1726                 return rc;
1727
1728         /* arbitrate between network and tty opens */
1729         spin_lock_irqsave(&info->netlock, flags);
1730         if (info->count != 0 || info->netcount != 0) {
1731                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1732                 spin_unlock_irqrestore(&info->netlock, flags);
1733                 return -EBUSY;
1734         }
1735         info->netcount=1;
1736         spin_unlock_irqrestore(&info->netlock, flags);
1737
1738         /* claim resources and init adapter */
1739         if ((rc = startup(info)) != 0) {
1740                 spin_lock_irqsave(&info->netlock, flags);
1741                 info->netcount=0;
1742                 spin_unlock_irqrestore(&info->netlock, flags);
1743                 return rc;
1744         }
1745
1746         /* assert DTR and RTS, apply hardware settings */
1747         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1748         program_hw(info);
1749
1750         /* enable network layer transmit */
1751         dev->trans_start = jiffies;
1752         netif_start_queue(dev);
1753
1754         /* inform generic HDLC layer of current DCD status */
1755         spin_lock_irqsave(&info->lock, flags);
1756         get_signals(info);
1757         spin_unlock_irqrestore(&info->lock, flags);
1758         hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
1759
1760         return 0;
1761 }
1762
1763 /**
1764  * called by network layer when interface is disabled
1765  * shutdown hardware and release resources
1766  *
1767  * dev  pointer to network device structure
1768  *
1769  * returns 0 if success, otherwise error code
1770  */
1771 static int hdlcdev_close(struct net_device *dev)
1772 {
1773         SLMP_INFO *info = dev_to_port(dev);
1774         unsigned long flags;
1775
1776         if (debug_level >= DEBUG_LEVEL_INFO)
1777                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1778
1779         netif_stop_queue(dev);
1780
1781         /* shutdown adapter and release resources */
1782         shutdown(info);
1783
1784         hdlc_close(dev);
1785
1786         spin_lock_irqsave(&info->netlock, flags);
1787         info->netcount=0;
1788         spin_unlock_irqrestore(&info->netlock, flags);
1789
1790         return 0;
1791 }
1792
1793 /**
1794  * called by network layer to process IOCTL call to network device
1795  *
1796  * dev  pointer to network device structure
1797  * ifr  pointer to network interface request structure
1798  * cmd  IOCTL command code
1799  *
1800  * returns 0 if success, otherwise error code
1801  */
1802 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1803 {
1804         const size_t size = sizeof(sync_serial_settings);
1805         sync_serial_settings new_line;
1806         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1807         SLMP_INFO *info = dev_to_port(dev);
1808         unsigned int flags;
1809
1810         if (debug_level >= DEBUG_LEVEL_INFO)
1811                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1812
1813         /* return error if TTY interface open */
1814         if (info->count)
1815                 return -EBUSY;
1816
1817         if (cmd != SIOCWANDEV)
1818                 return hdlc_ioctl(dev, ifr, cmd);
1819
1820         switch(ifr->ifr_settings.type) {
1821         case IF_GET_IFACE: /* return current sync_serial_settings */
1822
1823                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1824                 if (ifr->ifr_settings.size < size) {
1825                         ifr->ifr_settings.size = size; /* data size wanted */
1826                         return -ENOBUFS;
1827                 }
1828
1829                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1830                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1831                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1832                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1833
1834                 switch (flags){
1835                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1836                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1837                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1838                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1839                 default: new_line.clock_type = CLOCK_DEFAULT;
1840                 }
1841
1842                 new_line.clock_rate = info->params.clock_speed;
1843                 new_line.loopback   = info->params.loopback ? 1:0;
1844
1845                 if (copy_to_user(line, &new_line, size))
1846                         return -EFAULT;
1847                 return 0;
1848
1849         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1850
1851                 if(!capable(CAP_NET_ADMIN))
1852                         return -EPERM;
1853                 if (copy_from_user(&new_line, line, size))
1854                         return -EFAULT;
1855
1856                 switch (new_line.clock_type)
1857                 {
1858                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1859                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1860                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1861                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1862                 case CLOCK_DEFAULT:  flags = info->params.flags &
1863                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1864                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1865                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1866                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1867                 default: return -EINVAL;
1868                 }
1869
1870                 if (new_line.loopback != 0 && new_line.loopback != 1)
1871                         return -EINVAL;
1872
1873                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1874                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1875                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1876                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1877                 info->params.flags |= flags;
1878
1879                 info->params.loopback = new_line.loopback;
1880
1881                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1882                         info->params.clock_speed = new_line.clock_rate;
1883                 else
1884                         info->params.clock_speed = 0;
1885
1886                 /* if network interface up, reprogram hardware */
1887                 if (info->netcount)
1888                         program_hw(info);
1889                 return 0;
1890
1891         default:
1892                 return hdlc_ioctl(dev, ifr, cmd);
1893         }
1894 }
1895
1896 /**
1897  * called by network layer when transmit timeout is detected
1898  *
1899  * dev  pointer to network device structure
1900  */
1901 static void hdlcdev_tx_timeout(struct net_device *dev)
1902 {
1903         SLMP_INFO *info = dev_to_port(dev);
1904         struct net_device_stats *stats = hdlc_stats(dev);
1905         unsigned long flags;
1906
1907         if (debug_level >= DEBUG_LEVEL_INFO)
1908                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1909
1910         stats->tx_errors++;
1911         stats->tx_aborted_errors++;
1912
1913         spin_lock_irqsave(&info->lock,flags);
1914         tx_stop(info);
1915         spin_unlock_irqrestore(&info->lock,flags);
1916
1917         netif_wake_queue(dev);
1918 }
1919
1920 /**
1921  * called by device driver when transmit completes
1922  * reenable network layer transmit if stopped
1923  *
1924  * info  pointer to device instance information
1925  */
1926 static void hdlcdev_tx_done(SLMP_INFO *info)
1927 {
1928         if (netif_queue_stopped(info->netdev))
1929                 netif_wake_queue(info->netdev);
1930 }
1931
1932 /**
1933  * called by device driver when frame received
1934  * pass frame to network layer
1935  *
1936  * info  pointer to device instance information
1937  * buf   pointer to buffer contianing frame data
1938  * size  count of data bytes in buf
1939  */
1940 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1941 {
1942         struct sk_buff *skb = dev_alloc_skb(size);
1943         struct net_device *dev = info->netdev;
1944         struct net_device_stats *stats = hdlc_stats(dev);
1945
1946         if (debug_level >= DEBUG_LEVEL_INFO)
1947                 printk("hdlcdev_rx(%s)\n",dev->name);
1948
1949         if (skb == NULL) {
1950                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1951                 stats->rx_dropped++;
1952                 return;
1953         }
1954
1955         memcpy(skb_put(skb, size),buf,size);
1956
1957         skb->protocol = hdlc_type_trans(skb, info->netdev);
1958
1959         stats->rx_packets++;
1960         stats->rx_bytes += size;
1961
1962         netif_rx(skb);
1963
1964         info->netdev->last_rx = jiffies;
1965 }
1966
1967 /**
1968  * called by device driver when adding device instance
1969  * do generic HDLC initialization
1970  *
1971  * info  pointer to device instance information
1972  *
1973  * returns 0 if success, otherwise error code
1974  */
1975 static int hdlcdev_init(SLMP_INFO *info)
1976 {
1977         int rc;
1978         struct net_device *dev;
1979         hdlc_device *hdlc;
1980
1981         /* allocate and initialize network and HDLC layer objects */
1982
1983         if (!(dev = alloc_hdlcdev(info))) {
1984                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1985                 return -ENOMEM;
1986         }
1987
1988         /* for network layer reporting purposes only */
1989         dev->mem_start = info->phys_sca_base;
1990         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1991         dev->irq       = info->irq_level;
1992
1993         /* network layer callbacks and settings */
1994         dev->do_ioctl       = hdlcdev_ioctl;
1995         dev->open           = hdlcdev_open;
1996         dev->stop           = hdlcdev_close;
1997         dev->tx_timeout     = hdlcdev_tx_timeout;
1998         dev->watchdog_timeo = 10*HZ;
1999         dev->tx_queue_len   = 50;
2000
2001         /* generic HDLC layer callbacks and settings */
2002         hdlc         = dev_to_hdlc(dev);
2003         hdlc->attach = hdlcdev_attach;
2004         hdlc->xmit   = hdlcdev_xmit;
2005
2006         /* register objects with HDLC layer */
2007         if ((rc = register_hdlc_device(dev))) {
2008                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2009                 free_netdev(dev);
2010                 return rc;
2011         }
2012
2013         info->netdev = dev;
2014         return 0;
2015 }
2016
2017 /**
2018  * called by device driver when removing device instance
2019  * do generic HDLC cleanup
2020  *
2021  * info  pointer to device instance information
2022  */
2023 static void hdlcdev_exit(SLMP_INFO *info)
2024 {
2025         unregister_hdlc_device(info->netdev);
2026         free_netdev(info->netdev);
2027         info->netdev = NULL;
2028 }
2029
2030 #endif /* CONFIG_HDLC */
2031
2032
2033 /* Return next bottom half action to perform.
2034  * Return Value:        BH action code or 0 if nothing to do.
2035  */
2036 int bh_action(SLMP_INFO *info)
2037 {
2038         unsigned long flags;
2039         int rc = 0;
2040
2041         spin_lock_irqsave(&info->lock,flags);
2042
2043         if (info->pending_bh & BH_RECEIVE) {
2044                 info->pending_bh &= ~BH_RECEIVE;
2045                 rc = BH_RECEIVE;
2046         } else if (info->pending_bh & BH_TRANSMIT) {
2047                 info->pending_bh &= ~BH_TRANSMIT;
2048                 rc = BH_TRANSMIT;
2049         } else if (info->pending_bh & BH_STATUS) {
2050                 info->pending_bh &= ~BH_STATUS;
2051                 rc = BH_STATUS;
2052         }
2053
2054         if (!rc) {
2055                 /* Mark BH routine as complete */
2056                 info->bh_running   = 0;
2057                 info->bh_requested = 0;
2058         }
2059
2060         spin_unlock_irqrestore(&info->lock,flags);
2061
2062         return rc;
2063 }
2064
2065 /* Perform bottom half processing of work items queued by ISR.
2066  */
2067 void bh_handler(void* Context)
2068 {
2069         SLMP_INFO *info = (SLMP_INFO*)Context;
2070         int action;
2071
2072         if (!info)
2073                 return;
2074
2075         if ( debug_level >= DEBUG_LEVEL_BH )
2076                 printk( "%s(%d):%s bh_handler() entry\n",
2077                         __FILE__,__LINE__,info->device_name);
2078
2079         info->bh_running = 1;
2080
2081         while((action = bh_action(info)) != 0) {
2082
2083                 /* Process work item */
2084                 if ( debug_level >= DEBUG_LEVEL_BH )
2085                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2086                                 __FILE__,__LINE__,info->device_name, action);
2087
2088                 switch (action) {
2089
2090                 case BH_RECEIVE:
2091                         bh_receive(info);
2092                         break;
2093                 case BH_TRANSMIT:
2094                         bh_transmit(info);
2095                         break;
2096                 case BH_STATUS:
2097                         bh_status(info);
2098                         break;
2099                 default:
2100                         /* unknown work item ID */
2101                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2102                                 __FILE__,__LINE__,info->device_name,action);
2103                         break;
2104                 }
2105         }
2106
2107         if ( debug_level >= DEBUG_LEVEL_BH )
2108                 printk( "%s(%d):%s bh_handler() exit\n",
2109                         __FILE__,__LINE__,info->device_name);
2110 }
2111
2112 void bh_receive(SLMP_INFO *info)
2113 {
2114         if ( debug_level >= DEBUG_LEVEL_BH )
2115                 printk( "%s(%d):%s bh_receive()\n",
2116                         __FILE__,__LINE__,info->device_name);
2117
2118         while( rx_get_frame(info) );
2119 }
2120
2121 void bh_transmit(SLMP_INFO *info)
2122 {
2123         struct tty_struct *tty = info->tty;
2124
2125         if ( debug_level >= DEBUG_LEVEL_BH )
2126                 printk( "%s(%d):%s bh_transmit() entry\n",
2127                         __FILE__,__LINE__,info->device_name);
2128
2129         if (tty) {
2130                 tty_wakeup(tty);
2131                 wake_up_interruptible(&tty->write_wait);
2132         }
2133 }
2134
2135 void bh_status(SLMP_INFO *info)
2136 {
2137         if ( debug_level >= DEBUG_LEVEL_BH )
2138                 printk( "%s(%d):%s bh_status() entry\n",
2139                         __FILE__,__LINE__,info->device_name);
2140
2141         info->ri_chkcount = 0;
2142         info->dsr_chkcount = 0;
2143         info->dcd_chkcount = 0;
2144         info->cts_chkcount = 0;
2145 }
2146
2147 void isr_timer(SLMP_INFO * info)
2148 {
2149         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2150
2151         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2152         write_reg(info, IER2, 0);
2153
2154         /* TMCS, Timer Control/Status Register
2155          *
2156          * 07      CMF, Compare match flag (read only) 1=match
2157          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2158          * 05      Reserved, must be 0
2159          * 04      TME, Timer Enable
2160          * 03..00  Reserved, must be 0
2161          *
2162          * 0000 0000
2163          */
2164         write_reg(info, (unsigned char)(timer + TMCS), 0);
2165
2166         info->irq_occurred = TRUE;
2167
2168         if ( debug_level >= DEBUG_LEVEL_ISR )
2169                 printk("%s(%d):%s isr_timer()\n",
2170                         __FILE__,__LINE__,info->device_name);
2171 }
2172
2173 void isr_rxint(SLMP_INFO * info)
2174 {
2175         struct tty_struct *tty = info->tty;
2176         struct  mgsl_icount *icount = &info->icount;
2177         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2178         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2179
2180         /* clear status bits */
2181         if (status)
2182                 write_reg(info, SR1, status);
2183
2184         if (status2)
2185                 write_reg(info, SR2, status2);
2186
2187         if ( debug_level >= DEBUG_LEVEL_ISR )
2188                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2189                         __FILE__,__LINE__,info->device_name,status,status2);
2190
2191         if (info->params.mode == MGSL_MODE_ASYNC) {
2192                 if (status & BRKD) {
2193                         icount->brk++;
2194
2195                         /* process break detection if tty control
2196                          * is not set to ignore it
2197                          */
2198                         if ( tty ) {
2199                                 if (!(status & info->ignore_status_mask1)) {
2200                                         if (info->read_status_mask1 & BRKD) {
2201                                                 *tty->flip.flag_buf_ptr = TTY_BREAK;
2202                                                 if (info->flags & ASYNC_SAK)
2203                                                         do_SAK(tty);
2204                                         }
2205                                 }
2206                         }
2207                 }
2208         }
2209         else {
2210                 if (status & (FLGD|IDLD)) {
2211                         if (status & FLGD)
2212                                 info->icount.exithunt++;
2213                         else if (status & IDLD)
2214                                 info->icount.rxidle++;
2215                         wake_up_interruptible(&info->event_wait_q);
2216                 }
2217         }
2218
2219         if (status & CDCD) {
2220                 /* simulate a common modem status change interrupt
2221                  * for our handler
2222                  */
2223                 get_signals( info );
2224                 isr_io_pin(info,
2225                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2226         }
2227 }
2228
2229 /*
2230  * handle async rx data interrupts
2231  */
2232 void isr_rxrdy(SLMP_INFO * info)
2233 {
2234         u16 status;
2235         unsigned char DataByte;
2236         struct tty_struct *tty = info->tty;
2237         struct  mgsl_icount *icount = &info->icount;
2238
2239         if ( debug_level >= DEBUG_LEVEL_ISR )
2240                 printk("%s(%d):%s isr_rxrdy\n",
2241                         __FILE__,__LINE__,info->device_name);
2242
2243         while((status = read_reg(info,CST0)) & BIT0)
2244         {
2245                 DataByte = read_reg(info,TRB);
2246
2247                 if ( tty ) {
2248                         if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2249                                 continue;
2250
2251                         *tty->flip.char_buf_ptr = DataByte;
2252                         *tty->flip.flag_buf_ptr = 0;
2253                 }
2254
2255                 icount->rx++;
2256
2257                 if ( status & (PE + FRME + OVRN) ) {
2258                         printk("%s(%d):%s rxerr=%04X\n",
2259                                 __FILE__,__LINE__,info->device_name,status);
2260
2261                         /* update error statistics */
2262                         if (status & PE)
2263                                 icount->parity++;
2264                         else if (status & FRME)
2265                                 icount->frame++;
2266                         else if (status & OVRN)
2267                                 icount->overrun++;
2268
2269                         /* discard char if tty control flags say so */
2270                         if (status & info->ignore_status_mask2)
2271                                 continue;
2272
2273                         status &= info->read_status_mask2;
2274
2275                         if ( tty ) {
2276                                 if (status & PE)
2277                                         *tty->flip.flag_buf_ptr = TTY_PARITY;
2278                                 else if (status & FRME)
2279                                         *tty->flip.flag_buf_ptr = TTY_FRAME;
2280                                 if (status & OVRN) {
2281                                         /* Overrun is special, since it's
2282                                          * reported immediately, and doesn't
2283                                          * affect the current character
2284                                          */
2285                                         if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2286                                                 tty->flip.count++;
2287                                                 tty->flip.flag_buf_ptr++;
2288                                                 tty->flip.char_buf_ptr++;
2289                                                 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2290                                         }
2291                                 }
2292                         }
2293                 }       /* end of if (error) */
2294
2295                 if ( tty ) {
2296                         tty->flip.flag_buf_ptr++;
2297                         tty->flip.char_buf_ptr++;
2298                         tty->flip.count++;
2299                 }
2300         }
2301
2302         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2303                 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2304                         __FILE__,__LINE__,info->device_name,
2305                         tty ? tty->flip.count : 0);
2306                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2307                         __FILE__,__LINE__,info->device_name,
2308                         icount->rx,icount->brk,icount->parity,
2309                         icount->frame,icount->overrun);
2310         }
2311
2312         if ( tty && tty->flip.count )
2313                 tty_flip_buffer_push(tty);
2314 }
2315
2316 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2317 {
2318         if ( debug_level >= DEBUG_LEVEL_ISR )
2319                 printk("%s(%d):%s isr_txeom status=%02x\n",
2320                         __FILE__,__LINE__,info->device_name,status);
2321
2322         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2323         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2324         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2325
2326         if (status & UDRN) {
2327                 write_reg(info, CMD, TXRESET);
2328                 write_reg(info, CMD, TXENABLE);
2329         } else
2330                 write_reg(info, CMD, TXBUFCLR);
2331
2332         /* disable and clear tx interrupts */
2333         info->ie0_value &= ~TXRDYE;
2334         info->ie1_value &= ~(IDLE + UDRN);
2335         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2336         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2337
2338         if ( info->tx_active ) {
2339                 if (info->params.mode != MGSL_MODE_ASYNC) {
2340                         if (status & UDRN)
2341                                 info->icount.txunder++;
2342                         else if (status & IDLE)
2343                                 info->icount.txok++;
2344                 }
2345
2346                 info->tx_active = 0;
2347                 info->tx_count = info->tx_put = info->tx_get = 0;
2348
2349                 del_timer(&info->tx_timer);
2350
2351                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2352                         info->serial_signals &= ~SerialSignal_RTS;
2353                         info->drop_rts_on_tx_done = 0;
2354                         set_signals(info);
2355                 }
2356
2357 #ifdef CONFIG_HDLC
2358                 if (info->netcount)
2359                         hdlcdev_tx_done(info);
2360                 else
2361 #endif
2362                 {
2363                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2364                                 tx_stop(info);
2365                                 return;
2366                         }
2367                         info->pending_bh |= BH_TRANSMIT;
2368                 }
2369         }
2370 }
2371
2372
2373 /*
2374  * handle tx status interrupts
2375  */
2376 void isr_txint(SLMP_INFO * info)
2377 {
2378         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2379
2380         /* clear status bits */
2381         write_reg(info, SR1, status);
2382
2383         if ( debug_level >= DEBUG_LEVEL_ISR )
2384                 printk("%s(%d):%s isr_txint status=%02x\n",
2385                         __FILE__,__LINE__,info->device_name,status);
2386
2387         if (status & (UDRN + IDLE))
2388                 isr_txeom(info, status);
2389
2390         if (status & CCTS) {
2391                 /* simulate a common modem status change interrupt
2392                  * for our handler
2393                  */
2394                 get_signals( info );
2395                 isr_io_pin(info,
2396                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2397
2398         }
2399 }
2400
2401 /*
2402  * handle async tx data interrupts
2403  */
2404 void isr_txrdy(SLMP_INFO * info)
2405 {
2406         if ( debug_level >= DEBUG_LEVEL_ISR )
2407                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2408                         __FILE__,__LINE__,info->device_name,info->tx_count);
2409
2410         if (info->params.mode != MGSL_MODE_ASYNC) {
2411                 /* disable TXRDY IRQ, enable IDLE IRQ */
2412                 info->ie0_value &= ~TXRDYE;
2413                 info->ie1_value |= IDLE;
2414                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2415                 return;
2416         }
2417
2418         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2419                 tx_stop(info);
2420                 return;
2421         }
2422
2423         if ( info->tx_count )
2424                 tx_load_fifo( info );
2425         else {
2426                 info->tx_active = 0;
2427                 info->ie0_value &= ~TXRDYE;
2428                 write_reg(info, IE0, info->ie0_value);
2429         }
2430
2431         if (info->tx_count < WAKEUP_CHARS)
2432                 info->pending_bh |= BH_TRANSMIT;
2433 }
2434
2435 void isr_rxdmaok(SLMP_INFO * info)
2436 {
2437         /* BIT7 = EOT (end of transfer)
2438          * BIT6 = EOM (end of message/frame)
2439          */
2440         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2441
2442         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2443         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2444
2445         if ( debug_level >= DEBUG_LEVEL_ISR )
2446                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2447                         __FILE__,__LINE__,info->device_name,status);
2448
2449         info->pending_bh |= BH_RECEIVE;
2450 }
2451
2452 void isr_rxdmaerror(SLMP_INFO * info)
2453 {
2454         /* BIT5 = BOF (buffer overflow)
2455          * BIT4 = COF (counter overflow)
2456          */
2457         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2458
2459         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2460         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2461
2462         if ( debug_level >= DEBUG_LEVEL_ISR )
2463                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2464                         __FILE__,__LINE__,info->device_name,status);
2465
2466         info->rx_overflow = TRUE;
2467         info->pending_bh |= BH_RECEIVE;
2468 }
2469
2470 void isr_txdmaok(SLMP_INFO * info)
2471 {
2472         unsigned char status_reg1 = read_reg(info, SR1);
2473
2474         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2475         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2476         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2477
2478         if ( debug_level >= DEBUG_LEVEL_ISR )
2479                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2480                         __FILE__,__LINE__,info->device_name,status_reg1);
2481
2482         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2483         write_reg16(info, TRC0, 0);
2484         info->ie0_value |= TXRDYE;
2485         write_reg(info, IE0, info->ie0_value);
2486 }
2487
2488 void isr_txdmaerror(SLMP_INFO * info)
2489 {
2490         /* BIT5 = BOF (buffer overflow)
2491          * BIT4 = COF (counter overflow)
2492          */
2493         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2494
2495         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2496         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2497
2498         if ( debug_level >= DEBUG_LEVEL_ISR )
2499                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2500                         __FILE__,__LINE__,info->device_name,status);
2501 }
2502
2503 /* handle input serial signal changes
2504  */
2505 void isr_io_pin( SLMP_INFO *info, u16 status )
2506 {
2507         struct  mgsl_icount *icount;
2508
2509         if ( debug_level >= DEBUG_LEVEL_ISR )
2510                 printk("%s(%d):isr_io_pin status=%04X\n",
2511                         __FILE__,__LINE__,status);
2512
2513         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2514                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2515                 icount = &info->icount;
2516                 /* update input line counters */
2517                 if (status & MISCSTATUS_RI_LATCHED) {
2518                         icount->rng++;
2519                         if ( status & SerialSignal_RI )
2520                                 info->input_signal_events.ri_up++;
2521                         else
2522                                 info->input_signal_events.ri_down++;
2523                 }
2524                 if (status & MISCSTATUS_DSR_LATCHED) {
2525                         icount->dsr++;
2526                         if ( status & SerialSignal_DSR )
2527                                 info->input_signal_events.dsr_up++;
2528                         else
2529                                 info->input_signal_events.dsr_down++;
2530                 }
2531                 if (status & MISCSTATUS_DCD_LATCHED) {
2532                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2533                                 info->ie1_value &= ~CDCD;
2534                                 write_reg(info, IE1, info->ie1_value);
2535                         }
2536                         icount->dcd++;
2537                         if (status & SerialSignal_DCD) {
2538                                 info->input_signal_events.dcd_up++;
2539                         } else
2540                                 info->input_signal_events.dcd_down++;
2541 #ifdef CONFIG_HDLC
2542                         if (info->netcount)
2543                                 hdlc_set_carrier(status & SerialSignal_DCD, info->netdev);
2544 #endif
2545                 }
2546                 if (status & MISCSTATUS_CTS_LATCHED)
2547                 {
2548                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2549                                 info->ie1_value &= ~CCTS;
2550                                 write_reg(info, IE1, info->ie1_value);
2551                         }
2552                         icount->cts++;
2553                         if ( status & SerialSignal_CTS )
2554                                 info->input_signal_events.cts_up++;
2555                         else
2556                                 info->input_signal_events.cts_down++;
2557                 }
2558                 wake_up_interruptible(&info->status_event_wait_q);
2559                 wake_up_interruptible(&info->event_wait_q);
2560
2561                 if ( (info->flags & ASYNC_CHECK_CD) &&
2562                      (status & MISCSTATUS_DCD_LATCHED) ) {
2563                         if ( debug_level >= DEBUG_LEVEL_ISR )
2564                                 printk("%s CD now %s...", info->device_name,
2565                                        (status & SerialSignal_DCD) ? "on" : "off");
2566                         if (status & SerialSignal_DCD)
2567                                 wake_up_interruptible(&info->open_wait);
2568                         else {
2569                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2570                                         printk("doing serial hangup...");
2571                                 if (info->tty)
2572                                         tty_hangup(info->tty);
2573                         }
2574                 }
2575
2576                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2577                      (status & MISCSTATUS_CTS_LATCHED) ) {
2578                         if ( info->tty ) {
2579                                 if (info->tty->hw_stopped) {
2580                                         if (status & SerialSignal_CTS) {
2581                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2582                                                         printk("CTS tx start...");
2583                                                 info->tty->hw_stopped = 0;
2584                                                 tx_start(info);
2585                                                 info->pending_bh |= BH_TRANSMIT;
2586                                                 return;
2587                                         }
2588                                 } else {
2589                                         if (!(status & SerialSignal_CTS)) {
2590                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2591                                                         printk("CTS tx stop...");
2592                                                 info->tty->hw_stopped = 1;
2593                                                 tx_stop(info);
2594                                         }
2595                                 }
2596                         }
2597                 }
2598         }
2599
2600         info->pending_bh |= BH_STATUS;
2601 }
2602
2603 /* Interrupt service routine entry point.
2604  *
2605  * Arguments:
2606  *      irq             interrupt number that caused interrupt
2607  *      dev_id          device ID supplied during interrupt registration
2608  *      regs            interrupted processor context
2609  */
2610 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2611                                         struct pt_regs *regs)
2612 {
2613         SLMP_INFO * info;
2614         unsigned char status, status0, status1=0;
2615         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2616         unsigned char timerstatus0, timerstatus1=0;
2617         unsigned char shift;
2618         unsigned int i;
2619         unsigned short tmp;
2620
2621         if ( debug_level >= DEBUG_LEVEL_ISR )
2622                 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2623                         __FILE__,__LINE__,irq);
2624
2625         info = (SLMP_INFO *)dev_id;
2626         if (!info)
2627                 return IRQ_NONE;
2628
2629         spin_lock(&info->lock);
2630
2631         for(;;) {
2632
2633                 /* get status for SCA0 (ports 0-1) */
2634                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2635                 status0 = (unsigned char)tmp;
2636                 dmastatus0 = (unsigned char)(tmp>>8);
2637                 timerstatus0 = read_reg(info, ISR2);
2638
2639                 if ( debug_level >= DEBUG_LEVEL_ISR )
2640                         printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2641                                 __FILE__,__LINE__,info->device_name,
2642                                 status0,dmastatus0,timerstatus0);
2643
2644                 if (info->port_count == 4) {
2645                         /* get status for SCA1 (ports 2-3) */
2646                         tmp = read_reg16(info->port_array[2], ISR0);
2647                         status1 = (unsigned char)tmp;
2648                         dmastatus1 = (unsigned char)(tmp>>8);
2649                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2650
2651                         if ( debug_level >= DEBUG_LEVEL_ISR )
2652                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2653                                         __FILE__,__LINE__,info->device_name,
2654                                         status1,dmastatus1,timerstatus1);
2655                 }
2656
2657                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2658                          !status1 && !dmastatus1 && !timerstatus1)
2659                         break;
2660
2661                 for(i=0; i < info->port_count ; i++) {
2662                         if (info->port_array[i] == NULL)
2663                                 continue;
2664                         if (i < 2) {
2665                                 status = status0;
2666                                 dmastatus = dmastatus0;
2667                         } else {
2668                                 status = status1;
2669                                 dmastatus = dmastatus1;
2670                         }
2671
2672                         shift = i & 1 ? 4 :0;
2673
2674                         if (status & BIT0 << shift)
2675                                 isr_rxrdy(info->port_array[i]);
2676                         if (status & BIT1 << shift)
2677                                 isr_txrdy(info->port_array[i]);
2678                         if (status & BIT2 << shift)
2679                                 isr_rxint(info->port_array[i]);
2680                         if (status & BIT3 << shift)
2681                                 isr_txint(info->port_array[i]);
2682
2683                         if (dmastatus & BIT0 << shift)
2684                                 isr_rxdmaerror(info->port_array[i]);
2685                         if (dmastatus & BIT1 << shift)
2686                                 isr_rxdmaok(info->port_array[i]);
2687                         if (dmastatus & BIT2 << shift)
2688                                 isr_txdmaerror(info->port_array[i]);
2689                         if (dmastatus & BIT3 << shift)
2690                                 isr_txdmaok(info->port_array[i]);
2691                 }
2692
2693                 if (timerstatus0 & (BIT5 | BIT4))
2694                         isr_timer(info->port_array[0]);
2695                 if (timerstatus0 & (BIT7 | BIT6))
2696                         isr_timer(info->port_array[1]);
2697                 if (timerstatus1 & (BIT5 | BIT4))
2698                         isr_timer(info->port_array[2]);
2699                 if (timerstatus1 & (BIT7 | BIT6))
2700                         isr_timer(info->port_array[3]);
2701         }
2702
2703         for(i=0; i < info->port_count ; i++) {
2704                 SLMP_INFO * port = info->port_array[i];
2705
2706                 /* Request bottom half processing if there's something
2707                  * for it to do and the bh is not already running.
2708                  *
2709                  * Note: startup adapter diags require interrupts.
2710                  * do not request bottom half processing if the
2711                  * device is not open in a normal mode.
2712                  */
2713                 if ( port && (port->count || port->netcount) &&
2714                      port->pending_bh && !port->bh_running &&
2715                      !port->bh_requested ) {
2716                         if ( debug_level >= DEBUG_LEVEL_ISR )
2717                                 printk("%s(%d):%s queueing bh task.\n",
2718                                         __FILE__,__LINE__,port->device_name);
2719                         schedule_work(&port->task);
2720                         port->bh_requested = 1;
2721                 }
2722         }
2723
2724         spin_unlock(&info->lock);
2725
2726         if ( debug_level >= DEBUG_LEVEL_ISR )
2727                 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2728                         __FILE__,__LINE__,irq);
2729         return IRQ_HANDLED;
2730 }
2731
2732 /* Initialize and start device.
2733  */
2734 static int startup(SLMP_INFO * info)
2735 {
2736         if ( debug_level >= DEBUG_LEVEL_INFO )
2737                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2738
2739         if (info->flags & ASYNC_INITIALIZED)
2740                 return 0;
2741
2742         if (!info->tx_buf) {
2743                 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2744                 if (!info->tx_buf) {
2745                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2746                                 __FILE__,__LINE__,info->device_name);
2747                         return -ENOMEM;
2748                 }
2749         }
2750
2751         info->pending_bh = 0;
2752
2753         /* program hardware for current parameters */
2754         reset_port(info);
2755
2756         change_params(info);
2757
2758         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
2759         add_timer(&info->status_timer);
2760
2761         if (info->tty)
2762                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2763
2764         info->flags |= ASYNC_INITIALIZED;
2765
2766         return 0;
2767 }
2768
2769 /* Called by close() and hangup() to shutdown hardware
2770  */
2771 static void shutdown(SLMP_INFO * info)
2772 {
2773         unsigned long flags;
2774
2775         if (!(info->flags & ASYNC_INITIALIZED))
2776                 return;
2777
2778         if (debug_level >= DEBUG_LEVEL_INFO)
2779                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2780                          __FILE__,__LINE__, info->device_name );
2781
2782         /* clear status wait queue because status changes */
2783         /* can't happen after shutting down the hardware */
2784         wake_up_interruptible(&info->status_event_wait_q);
2785         wake_up_interruptible(&info->event_wait_q);
2786
2787         del_timer(&info->tx_timer);
2788         del_timer(&info->status_timer);
2789
2790         if (info->tx_buf) {
2791                 kfree(info->tx_buf);
2792                 info->tx_buf = NULL;
2793         }
2794
2795         spin_lock_irqsave(&info->lock,flags);
2796
2797         reset_port(info);
2798
2799         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2800                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2801                 set_signals(info);
2802         }
2803
2804         spin_unlock_irqrestore(&info->lock,flags);
2805
2806         if (info->tty)
2807                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2808
2809         info->flags &= ~ASYNC_INITIALIZED;
2810 }
2811
2812 static void program_hw(SLMP_INFO *info)
2813 {
2814         unsigned long flags;
2815
2816         spin_lock_irqsave(&info->lock,flags);
2817
2818         rx_stop(info);
2819         tx_stop(info);
2820
2821         info->tx_count = info->tx_put = info->tx_get = 0;
2822
2823         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2824                 hdlc_mode(info);
2825         else
2826                 async_mode(info);
2827
2828         set_signals(info);
2829
2830         info->dcd_chkcount = 0;
2831         info->cts_chkcount = 0;
2832         info->ri_chkcount = 0;
2833         info->dsr_chkcount = 0;
2834
2835         info->ie1_value |= (CDCD|CCTS);
2836         write_reg(info, IE1, info->ie1_value);
2837
2838         get_signals(info);
2839
2840         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2841                 rx_start(info);
2842
2843         spin_unlock_irqrestore(&info->lock,flags);
2844 }
2845
2846 /* Reconfigure adapter based on new parameters
2847  */
2848 static void change_params(SLMP_INFO *info)
2849 {
2850         unsigned cflag;
2851         int bits_per_char;
2852
2853         if (!info->tty || !info->tty->termios)
2854                 return;
2855
2856         if (debug_level >= DEBUG_LEVEL_INFO)
2857                 printk("%s(%d):%s change_params()\n",
2858                          __FILE__,__LINE__, info->device_name );
2859
2860         cflag = info->tty->termios->c_cflag;
2861
2862         /* if B0 rate (hangup) specified then negate DTR and RTS */
2863         /* otherwise assert DTR and RTS */
2864         if (cflag & CBAUD)
2865                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2866         else
2867                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2868
2869         /* byte size and parity */
2870
2871         switch (cflag & CSIZE) {
2872               case CS5: info->params.data_bits = 5; break;
2873               case CS6: info->params.data_bits = 6; break;
2874               case CS7: info->params.data_bits = 7; break;
2875               case CS8: info->params.data_bits = 8; break;
2876               /* Never happens, but GCC is too dumb to figure it out */
2877               default:  info->params.data_bits = 7; break;
2878               }
2879
2880         if (cflag & CSTOPB)
2881                 info->params.stop_bits = 2;
2882         else
2883                 info->params.stop_bits = 1;
2884
2885         info->params.parity = ASYNC_PARITY_NONE;
2886         if (cflag & PARENB) {
2887                 if (cflag & PARODD)
2888                         info->params.parity = ASYNC_PARITY_ODD;
2889                 else
2890                         info->params.parity = ASYNC_PARITY_EVEN;
2891 #ifdef CMSPAR
2892                 if (cflag & CMSPAR)
2893                         info->params.parity = ASYNC_PARITY_SPACE;
2894 #endif
2895         }
2896
2897         /* calculate number of jiffies to transmit a full
2898          * FIFO (32 bytes) at specified data rate
2899          */
2900         bits_per_char = info->params.data_bits +
2901                         info->params.stop_bits + 1;
2902
2903         /* if port data rate is set to 460800 or less then
2904          * allow tty settings to override, otherwise keep the
2905          * current data rate.
2906          */
2907         if (info->params.data_rate <= 460800) {
2908                 info->params.data_rate = tty_get_baud_rate(info->tty);
2909         }
2910
2911         if ( info->params.data_rate ) {
2912                 info->timeout = (32*HZ*bits_per_char) /
2913                                 info->params.data_rate;
2914         }
2915         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2916
2917         if (cflag & CRTSCTS)
2918                 info->flags |= ASYNC_CTS_FLOW;
2919         else
2920                 info->flags &= ~ASYNC_CTS_FLOW;
2921
2922         if (cflag & CLOCAL)
2923                 info->flags &= ~ASYNC_CHECK_CD;
2924         else
2925                 info->flags |= ASYNC_CHECK_CD;
2926
2927         /* process tty input control flags */
2928
2929         info->read_status_mask2 = OVRN;
2930         if (I_INPCK(info->tty))
2931                 info->read_status_mask2 |= PE | FRME;
2932         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2933                 info->read_status_mask1 |= BRKD;
2934         if (I_IGNPAR(info->tty))
2935                 info->ignore_status_mask2 |= PE | FRME;
2936         if (I_IGNBRK(info->tty)) {
2937                 info->ignore_status_mask1 |= BRKD;
2938                 /* If ignoring parity and break indicators, ignore
2939                  * overruns too.  (For real raw support).
2940                  */
2941                 if (I_IGNPAR(info->tty))
2942                         info->ignore_status_mask2 |= OVRN;
2943         }
2944
2945         program_hw(info);
2946 }
2947
2948 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2949 {
2950         int err;
2951
2952         if (debug_level >= DEBUG_LEVEL_INFO)
2953                 printk("%s(%d):%s get_params()\n",
2954                          __FILE__,__LINE__, info->device_name);
2955
2956         COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2957         if (err) {
2958                 if ( debug_level >= DEBUG_LEVEL_INFO )
2959                         printk( "%s(%d):%s get_stats() user buffer copy failed\n",
2960                                 __FILE__,__LINE__,info->device_name);
2961                 return -EFAULT;
2962         }
2963
2964         return 0;
2965 }
2966
2967 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2968 {
2969         int err;
2970         if (debug_level >= DEBUG_LEVEL_INFO)
2971                 printk("%s(%d):%s get_params()\n",
2972                          __FILE__,__LINE__, info->device_name);
2973
2974         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2975         if (err) {
2976                 if ( debug_level >= DEBUG_LEVEL_INFO )
2977                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2978                                 __FILE__,__LINE__,info->device_name);
2979                 return -EFAULT;
2980         }
2981
2982         return 0;
2983 }
2984
2985 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2986 {
2987         unsigned long flags;
2988         MGSL_PARAMS tmp_params;
2989         int err;
2990
2991         if (debug_level >= DEBUG_LEVEL_INFO)
2992                 printk("%s(%d):%s set_params\n",
2993                         __FILE__,__LINE__,info->device_name );
2994         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2995         if (err) {
2996                 if ( debug_level >= DEBUG_LEVEL_INFO )
2997                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2998                                 __FILE__,__LINE__,info->device_name);
2999                 return -EFAULT;
3000         }
3001
3002         spin_lock_irqsave(&info->lock,flags);
3003         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
3004         spin_unlock_irqrestore(&info->lock,flags);
3005
3006         change_params(info);
3007
3008         return 0;
3009 }
3010
3011 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
3012 {
3013         int err;
3014
3015         if (debug_level >= DEBUG_LEVEL_INFO)
3016                 printk("%s(%d):%s get_txidle()=%d\n",
3017                          __FILE__,__LINE__, info->device_name, info->idle_mode);
3018
3019         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3020         if (err) {
3021                 if ( debug_level >= DEBUG_LEVEL_INFO )
3022                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3023                                 __FILE__,__LINE__,info->device_name);
3024                 return -EFAULT;
3025         }
3026
3027         return 0;
3028 }
3029
3030 static int set_txidle(SLMP_INFO * info, int idle_mode)
3031 {
3032         unsigned long flags;
3033
3034         if (debug_level >= DEBUG_LEVEL_INFO)
3035                 printk("%s(%d):%s set_txidle(%d)\n",
3036                         __FILE__,__LINE__,info->device_name, idle_mode );
3037
3038         spin_lock_irqsave(&info->lock,flags);
3039         info->idle_mode = idle_mode;
3040         tx_set_idle( info );
3041         spin_unlock_irqrestore(&info->lock,flags);
3042         return 0;
3043 }
3044
3045 static int tx_enable(SLMP_INFO * info, int enable)
3046 {
3047         unsigned long flags;
3048
3049         if (debug_level >= DEBUG_LEVEL_INFO)
3050                 printk("%s(%d):%s tx_enable(%d)\n",
3051                         __FILE__,__LINE__,info->device_name, enable);
3052
3053         spin_lock_irqsave(&info->lock,flags);
3054         if ( enable ) {
3055                 if ( !info->tx_enabled ) {
3056                         tx_start(info);
3057                 }
3058         } else {
3059                 if ( info->tx_enabled )
3060                         tx_stop(info);
3061         }
3062         spin_unlock_irqrestore(&info->lock,flags);
3063         return 0;
3064 }
3065
3066 /* abort send HDLC frame
3067  */
3068 static int tx_abort(SLMP_INFO * info)
3069 {
3070         unsigned long flags;
3071
3072         if (debug_level >= DEBUG_LEVEL_INFO)
3073                 printk("%s(%d):%s tx_abort()\n",
3074                         __FILE__,__LINE__,info->device_name);
3075
3076         spin_lock_irqsave(&info->lock,flags);
3077         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3078                 info->ie1_value &= ~UDRN;
3079                 info->ie1_value |= IDLE;
3080                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3081                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3082
3083                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3084                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3085
3086                 write_reg(info, CMD, TXABORT);
3087         }
3088         spin_unlock_irqrestore(&info->lock,flags);
3089         return 0;
3090 }
3091
3092 static int rx_enable(SLMP_INFO * info, int enable)
3093 {
3094         unsigned long flags;
3095
3096         if (debug_level >= DEBUG_LEVEL_INFO)
3097                 printk("%s(%d):%s rx_enable(%d)\n",
3098                         __FILE__,__LINE__,info->device_name,enable);
3099
3100         spin_lock_irqsave(&info->lock,flags);
3101         if ( enable ) {
3102                 if ( !info->rx_enabled )
3103                         rx_start(info);
3104         } else {
3105                 if ( info->rx_enabled )
3106                         rx_stop(info);
3107         }
3108         spin_unlock_irqrestore(&info->lock,flags);
3109         return 0;
3110 }
3111
3112 static int map_status(int signals)
3113 {
3114         /* Map status bits to API event bits */
3115
3116         return ((signals & SerialSignal_DSR) ? MgslEvent_DsrActive : MgslEvent_DsrInactive) +
3117                ((signals & SerialSignal_CTS) ? MgslEvent_CtsActive : MgslEvent_CtsInactive) +
3118                ((signals & SerialSignal_DCD) ? MgslEvent_DcdActive : MgslEvent_DcdInactive) +
3119                ((signals & SerialSignal_RI)  ? MgslEvent_RiActive : MgslEvent_RiInactive);
3120 }
3121
3122 /* wait for specified event to occur
3123  */
3124 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3125 {
3126         unsigned long flags;
3127         int s;
3128         int rc=0;
3129         struct mgsl_icount cprev, cnow;
3130         int events;
3131         int mask;
3132         struct  _input_signal_events oldsigs, newsigs;
3133         DECLARE_WAITQUEUE(wait, current);
3134
3135         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3136         if (rc) {
3137                 return  -EFAULT;
3138         }
3139
3140         if (debug_level >= DEBUG_LEVEL_INFO)
3141                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3142                         __FILE__,__LINE__,info->device_name,mask);
3143
3144         spin_lock_irqsave(&info->lock,flags);
3145
3146         /* return immediately if state matches requested events */
3147         get_signals(info);
3148         s = map_status(info->serial_signals);
3149
3150         events = mask &
3151                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3152                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3153                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3154                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3155         if (events) {
3156                 spin_unlock_irqrestore(&info->lock,flags);
3157                 goto exit;
3158         }
3159
3160         /* save current irq counts */
3161         cprev = info->icount;
3162         oldsigs = info->input_signal_events;
3163
3164         /* enable hunt and idle irqs if needed */
3165         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3166                 unsigned char oldval = info->ie1_value;
3167                 unsigned char newval = oldval +
3168                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3169                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3170                 if ( oldval != newval ) {
3171                         info->ie1_value = newval;
3172                         write_reg(info, IE1, info->ie1_value);
3173                 }
3174         }
3175
3176         set_current_state(TASK_INTERRUPTIBLE);
3177         add_wait_queue(&info->event_wait_q, &wait);
3178
3179         spin_unlock_irqrestore(&info->lock,flags);
3180
3181         for(;;) {
3182                 schedule();
3183                 if (signal_pending(current)) {
3184                         rc = -ERESTARTSYS;
3185                         break;
3186                 }
3187
3188                 /* get current irq counts */
3189                 spin_lock_irqsave(&info->lock,flags);
3190                 cnow = info->icount;
3191                 newsigs = info->input_signal_events;
3192                 set_current_state(TASK_INTERRUPTIBLE);
3193                 spin_unlock_irqrestore(&info->lock,flags);
3194
3195                 /* if no change, wait aborted for some reason */
3196                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3197                     newsigs.dsr_down == oldsigs.dsr_down &&
3198                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3199                     newsigs.dcd_down == oldsigs.dcd_down &&
3200                     newsigs.cts_up   == oldsigs.cts_up   &&
3201                     newsigs.cts_down == oldsigs.cts_down &&
3202                     newsigs.ri_up    == oldsigs.ri_up    &&
3203                     newsigs.ri_down  == oldsigs.ri_down  &&
3204                     cnow.exithunt    == cprev.exithunt   &&
3205                     cnow.rxidle      == cprev.rxidle) {
3206                         rc = -EIO;
3207                         break;
3208                 }
3209
3210                 events = mask &
3211                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3212                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3213                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3214                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3215                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3216                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3217                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3218                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3219                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3220                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3221                 if (events)
3222                         break;
3223
3224                 cprev = cnow;
3225                 oldsigs = newsigs;
3226         }
3227
3228         remove_wait_queue(&info->event_wait_q, &wait);
3229         set_current_state(TASK_RUNNING);
3230
3231
3232         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3233                 spin_lock_irqsave(&info->lock,flags);
3234                 if (!waitqueue_active(&info->event_wait_q)) {
3235                         /* disable enable exit hunt mode/idle rcvd IRQs */
3236                         info->ie1_value &= ~(FLGD|IDLD);
3237                         write_reg(info, IE1, info->ie1_value);
3238                 }
3239                 spin_unlock_irqrestore(&info->lock,flags);
3240         }
3241 exit:
3242         if ( rc == 0 )
3243                 PUT_USER(rc, events, mask_ptr);
3244
3245         return rc;
3246 }
3247
3248 static int modem_input_wait(SLMP_INFO *info,int arg)
3249 {
3250         unsigned long flags;
3251         int rc;
3252         struct mgsl_icount cprev, cnow;
3253         DECLARE_WAITQUEUE(wait, current);
3254
3255         /* save current irq counts */
3256         spin_lock_irqsave(&info->lock,flags);
3257         cprev = info->icount;
3258         add_wait_queue(&info->status_event_wait_q, &wait);
3259         set_current_state(TASK_INTERRUPTIBLE);
3260         spin_unlock_irqrestore(&info->lock,flags);
3261
3262         for(;;) {
3263                 schedule();
3264                 if (signal_pending(current)) {
3265                         rc = -ERESTARTSYS;
3266                         break;
3267                 }
3268
3269                 /* get new irq counts */
3270                 spin_lock_irqsave(&info->lock,flags);
3271                 cnow = info->icount;
3272                 set_current_state(TASK_INTERRUPTIBLE);
3273                 spin_unlock_irqrestore(&info->lock,flags);
3274
3275                 /* if no change, wait aborted for some reason */
3276                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3277                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3278                         rc = -EIO;
3279                         break;
3280                 }
3281
3282                 /* check for change in caller specified modem input */
3283                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3284                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3285                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3286                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3287                         rc = 0;
3288                         break;
3289                 }
3290
3291                 cprev = cnow;
3292         }
3293         remove_wait_queue(&info->status_event_wait_q, &wait);
3294         set_current_state(TASK_RUNNING);
3295         return rc;
3296 }
3297
3298 /* return the state of the serial control and status signals
3299  */
3300 static int tiocmget(struct tty_struct *tty, struct file *file)
3301 {
3302         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3303         unsigned int result;
3304         unsigned long flags;
3305
3306         spin_lock_irqsave(&info->lock,flags);
3307         get_signals(info);
3308         spin_unlock_irqrestore(&info->lock,flags);
3309
3310         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3311                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3312                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3313                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3314                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3315                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3316
3317         if (debug_level >= DEBUG_LEVEL_INFO)
3318                 printk("%s(%d):%s tiocmget() value=%08X\n",
3319                          __FILE__,__LINE__, info->device_name, result );
3320         return result;
3321 }
3322
3323 /* set modem control signals (DTR/RTS)
3324  */
3325 static int tiocmset(struct tty_struct *tty, struct file *file,
3326                     unsigned int set, unsigned int clear)
3327 {
3328         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3329         unsigned long flags;
3330
3331         if (debug_level >= DEBUG_LEVEL_INFO)
3332                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3333                         __FILE__,__LINE__,info->device_name, set, clear);
3334
3335         if (set & TIOCM_RTS)
3336                 info->serial_signals |= SerialSignal_RTS;
3337         if (set & TIOCM_DTR)
3338                 info->serial_signals |= SerialSignal_DTR;
3339         if (clear & TIOCM_RTS)
3340                 info->serial_signals &= ~SerialSignal_RTS;
3341         if (clear & TIOCM_DTR)
3342                 info->serial_signals &= ~SerialSignal_DTR;
3343
3344         spin_lock_irqsave(&info->lock,flags);
3345         set_signals(info);
3346         spin_unlock_irqrestore(&info->lock,flags);
3347
3348         return 0;
3349 }
3350
3351
3352
3353 /* Block the current process until the specified port is ready to open.
3354  */
3355 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3356                            SLMP_INFO *info)
3357 {
3358         DECLARE_WAITQUEUE(wait, current);
3359         int             retval;
3360         int             do_clocal = 0, extra_count = 0;
3361         unsigned long   flags;
3362
3363         if (debug_level >= DEBUG_LEVEL_INFO)
3364                 printk("%s(%d):%s block_til_ready()\n",
3365                          __FILE__,__LINE__, tty->driver->name );
3366
3367         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3368                 /* nonblock mode is set or port is not enabled */
3369                 /* just verify that callout device is not active */
3370                 info->flags |= ASYNC_NORMAL_ACTIVE;
3371                 return 0;
3372         }
3373
3374         if (tty->termios->c_cflag & CLOCAL)
3375                 do_clocal = 1;
3376
3377         /* Wait for carrier detect and the line to become
3378          * free (i.e., not in use by the callout).  While we are in
3379          * this loop, info->count is dropped by one, so that
3380          * close() knows when to free things.  We restore it upon
3381          * exit, either normal or abnormal.
3382          */
3383
3384         retval = 0;
3385         add_wait_queue(&info->open_wait, &wait);
3386
3387         if (debug_level >= DEBUG_LEVEL_INFO)
3388                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3389                          __FILE__,__LINE__, tty->driver->name, info->count );
3390
3391         spin_lock_irqsave(&info->lock, flags);
3392         if (!tty_hung_up_p(filp)) {
3393                 extra_count = 1;
3394                 info->count--;
3395         }
3396         spin_unlock_irqrestore(&info->lock, flags);
3397         info->blocked_open++;
3398
3399         while (1) {
3400                 if ((tty->termios->c_cflag & CBAUD)) {
3401                         spin_lock_irqsave(&info->lock,flags);
3402                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3403                         set_signals(info);
3404                         spin_unlock_irqrestore(&info->lock,flags);
3405                 }
3406
3407                 set_current_state(TASK_INTERRUPTIBLE);
3408
3409                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3410                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3411                                         -EAGAIN : -ERESTARTSYS;
3412                         break;
3413                 }
3414
3415                 spin_lock_irqsave(&info->lock,flags);
3416                 get_signals(info);
3417                 spin_unlock_irqrestore(&info->lock,flags);
3418
3419                 if (!(info->flags & ASYNC_CLOSING) &&
3420                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3421                         break;
3422                 }
3423
3424                 if (signal_pending(current)) {
3425                         retval = -ERESTARTSYS;
3426                         break;
3427                 }
3428
3429                 if (debug_level >= DEBUG_LEVEL_INFO)
3430                         printk("%s(%d):%s block_til_ready() count=%d\n",
3431                                  __FILE__,__LINE__, tty->driver->name, info->count );
3432
3433                 schedule();
3434         }
3435
3436         set_current_state(TASK_RUNNING);
3437         remove_wait_queue(&info->open_wait, &wait);
3438
3439         if (extra_count)
3440                 info->count++;
3441         info->blocked_open--;
3442
3443         if (debug_level >= DEBUG_LEVEL_INFO)
3444                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3445                          __FILE__,__LINE__, tty->driver->name, info->count );
3446
3447         if (!retval)
3448                 info->flags |= ASYNC_NORMAL_ACTIVE;
3449
3450         return retval;
3451 }
3452
3453 int alloc_dma_bufs(SLMP_INFO *info)
3454 {
3455         unsigned short BuffersPerFrame;
3456         unsigned short BufferCount;
3457
3458         // Force allocation to start at 64K boundary for each port.
3459         // This is necessary because *all* buffer descriptors for a port
3460         // *must* be in the same 64K block. All descriptors on a port
3461         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3462         // into the CBP register.
3463         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3464
3465         /* Calculate the number of DMA buffers necessary to hold the */
3466         /* largest allowable frame size. Note: If the max frame size is */
3467         /* not an even multiple of the DMA buffer size then we need to */
3468         /* round the buffer count per frame up one. */
3469
3470         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3471         if ( info->max_frame_size % SCABUFSIZE )
3472                 BuffersPerFrame++;
3473
3474         /* calculate total number of data buffers (SCABUFSIZE) possible
3475          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3476          * for the descriptor list (BUFFERLISTSIZE).
3477          */
3478         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3479
3480         /* limit number of buffers to maximum amount of descriptors */
3481         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3482                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3483
3484         /* use enough buffers to transmit one max size frame */
3485         info->tx_buf_count = BuffersPerFrame + 1;
3486
3487         /* never use more than half the available buffers for transmit */
3488         if (info->tx_buf_count > (BufferCount/2))
3489                 info->tx_buf_count = BufferCount/2;
3490
3491         if (info->tx_buf_count > SCAMAXDESC)
3492                 info->tx_buf_count = SCAMAXDESC;
3493
3494         /* use remaining buffers for receive */
3495         info->rx_buf_count = BufferCount - info->tx_buf_count;
3496
3497         if (info->rx_buf_count > SCAMAXDESC)
3498                 info->rx_buf_count = SCAMAXDESC;
3499
3500         if ( debug_level >= DEBUG_LEVEL_INFO )
3501                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3502                         __FILE__,__LINE__, info->device_name,
3503                         info->tx_buf_count,info->rx_buf_count);
3504
3505         if ( alloc_buf_list( info ) < 0 ||
3506                 alloc_frame_bufs(info,
3507                                         info->rx_buf_list,
3508                                         info->rx_buf_list_ex,
3509                                         info->rx_buf_count) < 0 ||
3510                 alloc_frame_bufs(info,
3511                                         info->tx_buf_list,
3512                                         info->tx_buf_list_ex,
3513                                         info->tx_buf_count) < 0 ||
3514                 alloc_tmp_rx_buf(info) < 0 ) {
3515                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3516                         __FILE__,__LINE__, info->device_name);
3517                 return -ENOMEM;
3518         }
3519
3520         rx_reset_buffers( info );
3521
3522         return 0;
3523 }
3524
3525 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3526  */
3527 int alloc_buf_list(SLMP_INFO *info)
3528 {
3529         unsigned int i;
3530
3531         /* build list in adapter shared memory */
3532         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3533         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3534         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3535
3536         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3537
3538         /* Save virtual address pointers to the receive and */
3539         /* transmit buffer lists. (Receive 1st). These pointers will */
3540         /* be used by the processor to access the lists. */
3541         info->rx_buf_list = (SCADESC *)info->buffer_list;
3542
3543         info->tx_buf_list = (SCADESC *)info->buffer_list;
3544         info->tx_buf_list += info->rx_buf_count;
3545
3546         /* Build links for circular buffer entry lists (tx and rx)
3547          *
3548          * Note: links are physical addresses read by the SCA device
3549          * to determine the next buffer entry to use.
3550          */
3551
3552         for ( i = 0; i < info->rx_buf_count; i++ ) {
3553                 /* calculate and store physical address of this buffer entry */
3554                 info->rx_buf_list_ex[i].phys_entry =
3555                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3556
3557                 /* calculate and store physical address of */
3558                 /* next entry in cirular list of entries */
3559                 info->rx_buf_list[i].next = info->buffer_list_phys;
3560                 if ( i < info->rx_buf_count - 1 )
3561                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3562
3563                 info->rx_buf_list[i].length = SCABUFSIZE;
3564         }
3565
3566         for ( i = 0; i < info->tx_buf_count; i++ ) {
3567                 /* calculate and store physical address of this buffer entry */
3568                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3569                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3570
3571                 /* calculate and store physical address of */
3572                 /* next entry in cirular list of entries */
3573
3574                 info->tx_buf_list[i].next = info->buffer_list_phys +
3575                         info->rx_buf_count * sizeof(SCADESC);
3576
3577                 if ( i < info->tx_buf_count - 1 )
3578                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3579         }
3580
3581         return 0;
3582 }
3583
3584 /* Allocate the frame DMA buffers used by the specified buffer list.
3585  */
3586 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3587 {
3588         int i;
3589         unsigned long phys_addr;
3590
3591         for ( i = 0; i < count; i++ ) {
3592                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3593                 phys_addr = info->port_array[0]->last_mem_alloc;
3594                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3595
3596                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3597                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3598         }
3599
3600         return 0;
3601 }
3602
3603 void free_dma_bufs(SLMP_INFO *info)
3604 {
3605         info->buffer_list = NULL;
3606         info->rx_buf_list = NULL;
3607         info->tx_buf_list = NULL;
3608 }
3609
3610 /* allocate buffer large enough to hold max_frame_size.
3611  * This buffer is used to pass an assembled frame to the line discipline.
3612  */
3613 int alloc_tmp_rx_buf(SLMP_INFO *info)
3614 {
3615         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3616         if (info->tmp_rx_buf == NULL)
3617                 return -ENOMEM;
3618         return 0;
3619 }
3620
3621 void free_tmp_rx_buf(SLMP_INFO *info)
3622 {
3623         if (info->tmp_rx_buf)
3624                 kfree(info->tmp_rx_buf);
3625         info->tmp_rx_buf = NULL;
3626 }
3627
3628 int claim_resources(SLMP_INFO *info)
3629 {
3630         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3631                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3632                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3633                 info->init_error = DiagStatus_AddressConflict;
3634                 goto errout;
3635         }
3636         else
3637                 info->shared_mem_requested = 1;
3638
3639         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3640                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3641                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3642                 info->init_error = DiagStatus_AddressConflict;
3643                 goto errout;
3644         }
3645         else
3646                 info->lcr_mem_requested = 1;
3647
3648         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3649                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3650                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3651                 info->init_error = DiagStatus_AddressConflict;
3652                 goto errout;
3653         }
3654         else
3655                 info->sca_base_requested = 1;
3656
3657         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3658                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3659                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3660                 info->init_error = DiagStatus_AddressConflict;
3661                 goto errout;
3662         }
3663         else
3664                 info->sca_statctrl_requested = 1;
3665
3666         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3667         if (!info->memory_base) {
3668                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3669                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3670                 info->init_error = DiagStatus_CantAssignPciResources;
3671                 goto errout;
3672         }
3673
3674         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3675         if (!info->lcr_base) {
3676                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3677                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3678                 info->init_error = DiagStatus_CantAssignPciResources;
3679                 goto errout;
3680         }
3681         info->lcr_base += info->lcr_offset;
3682
3683         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3684         if (!info->sca_base) {
3685                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3686                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3687                 info->init_error = DiagStatus_CantAssignPciResources;
3688                 goto errout;
3689         }
3690         info->sca_base += info->sca_offset;
3691
3692         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3693         if (!info->statctrl_base) {
3694                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3695                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3696                 info->init_error = DiagStatus_CantAssignPciResources;
3697                 goto errout;
3698         }
3699         info->statctrl_base += info->statctrl_offset;
3700
3701         if ( !memory_test(info) ) {
3702                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3703                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3704                 info->init_error = DiagStatus_MemoryError;
3705                 goto errout;
3706         }
3707
3708         return 0;
3709
3710 errout:
3711         release_resources( info );
3712         return -ENODEV;
3713 }
3714
3715 void release_resources(SLMP_INFO *info)
3716 {
3717         if ( debug_level >= DEBUG_LEVEL_INFO )
3718                 printk( "%s(%d):%s release_resources() entry\n",
3719                         __FILE__,__LINE__,info->device_name );
3720
3721         if ( info->irq_requested ) {
3722                 free_irq(info->irq_level, info);
3723                 info->irq_requested = 0;
3724         }
3725
3726         if ( info->shared_mem_requested ) {
3727                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3728                 info->shared_mem_requested = 0;
3729         }
3730         if ( info->lcr_mem_requested ) {
3731                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3732                 info->lcr_mem_requested = 0;
3733         }
3734         if ( info->sca_base_requested ) {
3735                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3736                 info->sca_base_requested = 0;
3737         }
3738         if ( info->sca_statctrl_requested ) {
3739                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3740                 info->sca_statctrl_requested = 0;
3741         }
3742
3743         if (info->memory_base){
3744                 iounmap(info->memory_base);
3745                 info->memory_base = NULL;
3746         }
3747
3748         if (info->sca_base) {
3749                 iounmap(info->sca_base - info->sca_offset);
3750                 info->sca_base=NULL;
3751         }
3752
3753         if (info->statctrl_base) {
3754                 iounmap(info->statctrl_base - info->statctrl_offset);
3755                 info->statctrl_base=NULL;
3756         }
3757
3758         if (info->lcr_base){
3759                 iounmap(info->lcr_base - info->lcr_offset);
3760                 info->lcr_base = NULL;
3761         }
3762
3763         if ( debug_level >= DEBUG_LEVEL_INFO )
3764                 printk( "%s(%d):%s release_resources() exit\n",
3765                         __FILE__,__LINE__,info->device_name );
3766 }
3767
3768 /* Add the specified device instance data structure to the
3769  * global linked list of devices and increment the device count.
3770  */
3771 void add_device(SLMP_INFO *info)
3772 {
3773         info->next_device = NULL;
3774         info->line = synclinkmp_device_count;
3775         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3776
3777         if (info->line < MAX_DEVICES) {
3778                 if (maxframe[info->line])
3779                         info->max_frame_size = maxframe[info->line];
3780                 info->dosyncppp = dosyncppp[info->line];
3781         }
3782
3783         synclinkmp_device_count++;
3784
3785         if ( !synclinkmp_device_list )
3786                 synclinkmp_device_list = info;
3787         else {
3788                 SLMP_INFO *current_dev = synclinkmp_device_list;
3789                 while( current_dev->next_device )
3790                         current_dev = current_dev->next_device;
3791                 current_dev->next_device = info;
3792         }
3793
3794         if ( info->max_frame_size < 4096 )
3795                 info->max_frame_size = 4096;
3796         else if ( info->max_frame_size > 65535 )
3797                 info->max_frame_size = 65535;
3798
3799         printk( "SyncLink MultiPort %s: "
3800                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3801                 info->device_name,
3802                 info->phys_sca_base,
3803                 info->phys_memory_base,
3804                 info->phys_statctrl_base,
3805                 info->phys_lcr_base,
3806                 info->irq_level,
3807                 info->max_frame_size );
3808
3809 #ifdef CONFIG_HDLC
3810         hdlcdev_init(info);
3811 #endif
3812 }
3813
3814 /* Allocate and initialize a device instance structure
3815  *
3816  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3817  */
3818 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3819 {
3820         SLMP_INFO *info;
3821
3822         info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3823                  GFP_KERNEL);
3824
3825         if (!info) {
3826                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3827                         __FILE__,__LINE__, adapter_num, port_num);
3828         } else {
3829                 memset(info, 0, sizeof(SLMP_INFO));
3830                 info->magic = MGSL_MAGIC;
3831                 INIT_WORK(&info->task, bh_handler, info);
3832                 info->max_frame_size = 4096;
3833                 info->close_delay = 5*HZ/10;
3834                 info->closing_wait = 30*HZ;
3835                 init_waitqueue_head(&info->open_wait);
3836                 init_waitqueue_head(&info->close_wait);
3837                 init_waitqueue_head(&info->status_event_wait_q);
3838                 init_waitqueue_head(&info->event_wait_q);
3839                 spin_lock_init(&info->netlock);
3840                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3841                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3842                 info->adapter_num = adapter_num;
3843                 info->port_num = port_num;
3844
3845                 /* Copy configuration info to device instance data */
3846                 info->irq_level = pdev->irq;
3847                 info->phys_lcr_base = pci_resource_start(pdev,0);
3848                 info->phys_sca_base = pci_resource_start(pdev,2);
3849                 info->phys_memory_base = pci_resource_start(pdev,3);
3850                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3851
3852                 /* Because veremap only works on page boundaries we must map
3853                  * a larger area than is actually implemented for the LCR
3854                  * memory range. We map a full page starting at the page boundary.
3855                  */
3856                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3857                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3858
3859                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3860                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3861
3862                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3863                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3864
3865                 info->bus_type = MGSL_BUS_TYPE_PCI;
3866                 info->irq_flags = SA_SHIRQ;
3867
3868                 init_timer(&info->tx_timer);
3869                 info->tx_timer.data = (unsigned long)info;
3870                 info->tx_timer.function = tx_timeout;
3871
3872                 init_timer(&info->status_timer);
3873                 info->status_timer.data = (unsigned long)info;
3874                 info->status_timer.function = status_timeout;
3875
3876                 /* Store the PCI9050 misc control register value because a flaw
3877                  * in the PCI9050 prevents LCR registers from being read if
3878                  * BIOS assigns an LCR base address with bit 7 set.
3879                  *
3880                  * Only the misc control register is accessed for which only
3881                  * write access is needed, so set an initial value and change
3882                  * bits to the device instance data as we write the value
3883                  * to the actual misc control register.
3884                  */
3885                 info->misc_ctrl_value = 0x087e4546;
3886
3887                 /* initial port state is unknown - if startup errors
3888                  * occur, init_error will be set to indicate the
3889                  * problem. Once the port is fully initialized,
3890                  * this value will be set to 0 to indicate the
3891                  * port is available.
3892                  */
3893                 info->init_error = -1;
3894         }
3895
3896         return info;
3897 }
3898
3899 void device_init(int adapter_num, struct pci_dev *pdev)
3900 {
3901         SLMP_INFO *port_array[SCA_MAX_PORTS];
3902         int port;
3903
3904         /* allocate device instances for up to SCA_MAX_PORTS devices */
3905         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3906                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3907                 if( port_array[port] == NULL ) {
3908                         for ( --port; port >= 0; --port )
3909                                 kfree(port_array[port]);
3910                         return;
3911                 }
3912         }
3913
3914         /* give copy of port_array to all ports and add to device list  */
3915         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3916                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3917                 add_device( port_array[port] );
3918                 spin_lock_init(&port_array[port]->lock);
3919         }
3920
3921         /* Allocate and claim adapter resources */
3922         if ( !claim_resources(port_array[0]) ) {
3923
3924                 alloc_dma_bufs(port_array[0]);
3925
3926                 /* copy resource information from first port to others */
3927                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3928                         port_array[port]->lock  = port_array[0]->lock;
3929                         port_array[port]->irq_level     = port_array[0]->irq_level;
3930                         port_array[port]->memory_base   = port_array[0]->memory_base;
3931                         port_array[port]->sca_base      = port_array[0]->sca_base;
3932                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3933                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3934                         alloc_dma_bufs(port_array[port]);
3935                 }
3936
3937                 if ( request_irq(port_array[0]->irq_level,
3938                                         synclinkmp_interrupt,
3939                                         port_array[0]->irq_flags,
3940                                         port_array[0]->device_name,
3941                                         port_array[0]) < 0 ) {
3942                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3943                                 __FILE__,__LINE__,
3944                                 port_array[0]->device_name,
3945                                 port_array[0]->irq_level );
3946                 }
3947                 else {
3948                         port_array[0]->irq_requested = 1;
3949                         adapter_test(port_array[0]);
3950                 }
3951         }
3952 }
3953
3954 static struct tty_operations ops = {
3955         .open = open,
3956         .close = close,
3957         .write = write,
3958         .put_char = put_char,
3959         .flush_chars = flush_chars,
3960         .write_room = write_room,
3961         .chars_in_buffer = chars_in_buffer,
3962         .flush_buffer = flush_buffer,
3963         .ioctl = ioctl,
3964         .throttle = throttle,
3965         .unthrottle = unthrottle,
3966         .send_xchar = send_xchar,
3967         .break_ctl = set_break,
3968         .wait_until_sent = wait_until_sent,
3969         .read_proc = read_proc,
3970         .set_termios = set_termios,
3971         .stop = tx_hold,
3972         .start = tx_release,
3973         .hangup = hangup,
3974         .tiocmget = tiocmget,
3975         .tiocmset = tiocmset,
3976 };
3977
3978 static void synclinkmp_cleanup(void)
3979 {
3980         int rc;
3981         SLMP_INFO *info;
3982         SLMP_INFO *tmp;
3983
3984         printk("Unloading %s %s\n", driver_name, driver_version);
3985
3986         if (serial_driver) {
3987                 if ((rc = tty_unregister_driver(serial_driver)))
3988                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3989                                __FILE__,__LINE__,rc);
3990                 put_tty_driver(serial_driver);
3991         }
3992
3993         /* reset devices */
3994         info = synclinkmp_device_list;
3995         while(info) {
3996                 reset_port(info);
3997                 info = info->next_device;
3998         }
3999
4000         /* release devices */
4001         info = synclinkmp_device_list;
4002         while(info) {
4003 #ifdef CONFIG_HDLC
4004                 hdlcdev_exit(info);
4005 #endif
4006                 free_dma_bufs(info);
4007                 free_tmp_rx_buf(info);
4008                 if ( info->port_num == 0 ) {
4009                         if (info->sca_base)
4010                                 write_reg(info, LPR, 1); /* set low power mode */
4011                         release_resources(info);
4012                 }
4013                 tmp = info;
4014                 info = info->next_device;
4015                 kfree(tmp);
4016         }
4017
4018         pci_unregister_driver(&synclinkmp_pci_driver);
4019 }
4020
4021 /* Driver initialization entry point.
4022  */
4023
4024 static int __init synclinkmp_init(void)
4025 {
4026         int rc;
4027
4028         if (break_on_load) {
4029                 synclinkmp_get_text_ptr();
4030                 BREAKPOINT();
4031         }
4032
4033         printk("%s %s\n", driver_name, driver_version);
4034
4035         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4036                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4037                 return rc;
4038         }
4039
4040         serial_driver = alloc_tty_driver(128);
4041         if (!serial_driver) {
4042                 rc = -ENOMEM;
4043                 goto error;
4044         }
4045
4046         /* Initialize the tty_driver structure */
4047
4048         serial_driver->owner = THIS_MODULE;
4049         serial_driver->driver_name = "synclinkmp";
4050         serial_driver->name = "ttySLM";
4051         serial_driver->major = ttymajor;
4052         serial_driver->minor_start = 64;
4053         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4054         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4055         serial_driver->init_termios = tty_std_termios;
4056         serial_driver->init_termios.c_cflag =
4057                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4058         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4059         tty_set_operations(serial_driver, &ops);
4060         if ((rc = tty_register_driver(serial_driver)) < 0) {
4061                 printk("%s(%d):Couldn't register serial driver\n",
4062                         __FILE__,__LINE__);
4063                 put_tty_driver(serial_driver);
4064                 serial_driver = NULL;
4065                 goto error;
4066         }
4067
4068         printk("%s %s, tty major#%d\n",
4069                 driver_name, driver_version,
4070                 serial_driver->major);
4071
4072         return 0;
4073
4074 error:
4075         synclinkmp_cleanup();
4076         return rc;
4077 }
4078
4079 static void __exit synclinkmp_exit(void)
4080 {
4081         synclinkmp_cleanup();
4082 }
4083
4084 module_init(synclinkmp_init);
4085 module_exit(synclinkmp_exit);
4086
4087 /* Set the port for internal loopback mode.
4088  * The TxCLK and RxCLK signals are generated from the BRG and
4089  * the TxD is looped back to the RxD internally.
4090  */
4091 void enable_loopback(SLMP_INFO *info, int enable)
4092 {
4093         if (enable) {
4094                 /* MD2 (Mode Register 2)
4095                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4096                  */
4097                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4098
4099                 /* degate external TxC clock source */
4100                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4101                 write_control_reg(info);
4102
4103                 /* RXS/TXS (Rx/Tx clock source)
4104                  * 07      Reserved, must be 0
4105                  * 06..04  Clock Source, 100=BRG
4106                  * 03..00  Clock Divisor, 0000=1
4107                  */
4108                 write_reg(info, RXS, 0x40);
4109                 write_reg(info, TXS, 0x40);
4110
4111         } else {
4112                 /* MD2 (Mode Register 2)
4113                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4114                  */
4115                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4116
4117                 /* RXS/TXS (Rx/Tx clock source)
4118                  * 07      Reserved, must be 0
4119                  * 06..04  Clock Source, 000=RxC/TxC Pin
4120                  * 03..00  Clock Divisor, 0000=1
4121                  */
4122                 write_reg(info, RXS, 0x00);
4123                 write_reg(info, TXS, 0x00);
4124         }
4125
4126         /* set LinkSpeed if available, otherwise default to 2Mbps */
4127         if (info->params.clock_speed)
4128                 set_rate(info, info->params.clock_speed);
4129         else
4130                 set_rate(info, 3686400);
4131 }
4132
4133 /* Set the baud rate register to the desired speed
4134  *
4135  *      data_rate       data rate of clock in bits per second
4136  *                      A data rate of 0 disables the AUX clock.
4137  */
4138 void set_rate( SLMP_INFO *info, u32 data_rate )
4139 {
4140         u32 TMCValue;
4141         unsigned char BRValue;
4142         u32 Divisor=0;
4143
4144         /* fBRG = fCLK/(TMC * 2^BR)
4145          */
4146         if (data_rate != 0) {
4147                 Divisor = 14745600/data_rate;
4148                 if (!Divisor)
4149                         Divisor = 1;
4150
4151                 TMCValue = Divisor;
4152
4153                 BRValue = 0;
4154                 if (TMCValue != 1 && TMCValue != 2) {
4155                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4156                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4157                          * 50/50 duty cycle.
4158                          */
4159                         BRValue = 1;
4160                         TMCValue >>= 1;
4161                 }
4162
4163                 /* while TMCValue is too big for TMC register, divide
4164                  * by 2 and increment BR exponent.
4165                  */
4166                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4167                         TMCValue >>= 1;
4168
4169                 write_reg(info, TXS,
4170                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4171                 write_reg(info, RXS,
4172                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4173                 write_reg(info, TMC, (unsigned char)TMCValue);
4174         }
4175         else {
4176                 write_reg(info, TXS,0);
4177                 write_reg(info, RXS,0);
4178                 write_reg(info, TMC, 0);
4179         }
4180 }
4181
4182 /* Disable receiver
4183  */
4184 void rx_stop(SLMP_INFO *info)
4185 {
4186         if (debug_level >= DEBUG_LEVEL_ISR)
4187                 printk("%s(%d):%s rx_stop()\n",
4188                          __FILE__,__LINE__, info->device_name );
4189
4190         write_reg(info, CMD, RXRESET);
4191
4192         info->ie0_value &= ~RXRDYE;
4193         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4194
4195         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4196         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4197         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4198
4199         info->rx_enabled = 0;
4200         info->rx_overflow = 0;
4201 }
4202
4203 /* enable the receiver
4204  */
4205 void rx_start(SLMP_INFO *info)
4206 {
4207         int i;
4208
4209         if (debug_level >= DEBUG_LEVEL_ISR)
4210                 printk("%s(%d):%s rx_start()\n",
4211                          __FILE__,__LINE__, info->device_name );
4212
4213         write_reg(info, CMD, RXRESET);
4214
4215         if ( info->params.mode == MGSL_MODE_HDLC ) {
4216                 /* HDLC, disabe IRQ on rxdata */
4217                 info->ie0_value &= ~RXRDYE;
4218                 write_reg(info, IE0, info->ie0_value);
4219
4220                 /* Reset all Rx DMA buffers and program rx dma */
4221                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4222                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4223
4224                 for (i = 0; i < info->rx_buf_count; i++) {
4225                         info->rx_buf_list[i].status = 0xff;
4226
4227                         // throttle to 4 shared memory writes at a time to prevent
4228                         // hogging local bus (keep latency time for DMA requests low).
4229                         if (!(i % 4))
4230                                 read_status_reg(info);
4231                 }
4232                 info->current_rx_buf = 0;
4233
4234                 /* set current/1st descriptor address */
4235                 write_reg16(info, RXDMA + CDA,
4236                         info->rx_buf_list_ex[0].phys_entry);
4237
4238                 /* set new last rx descriptor address */
4239                 write_reg16(info, RXDMA + EDA,
4240                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4241
4242                 /* set buffer length (shared by all rx dma data buffers) */
4243                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4244
4245                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4246                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4247         } else {
4248                 /* async, enable IRQ on rxdata */
4249                 info->ie0_value |= RXRDYE;
4250                 write_reg(info, IE0, info->ie0_value);
4251         }
4252
4253         write_reg(info, CMD, RXENABLE);
4254
4255         info->rx_overflow = FALSE;
4256         info->rx_enabled = 1;
4257 }
4258
4259 /* Enable the transmitter and send a transmit frame if
4260  * one is loaded in the DMA buffers.
4261  */
4262 void tx_start(SLMP_INFO *info)
4263 {
4264         if (debug_level >= DEBUG_LEVEL_ISR)
4265                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4266                          __FILE__,__LINE__, info->device_name,info->tx_count );
4267
4268         if (!info->tx_enabled ) {
4269                 write_reg(info, CMD, TXRESET);
4270                 write_reg(info, CMD, TXENABLE);
4271                 info->tx_enabled = TRUE;
4272         }
4273
4274         if ( info->tx_count ) {
4275
4276                 /* If auto RTS enabled and RTS is inactive, then assert */
4277                 /* RTS and set a flag indicating that the driver should */
4278                 /* negate RTS when the transmission completes. */
4279
4280                 info->drop_rts_on_tx_done = 0;
4281
4282                 if (info->params.mode != MGSL_MODE_ASYNC) {
4283
4284                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4285                                 get_signals( info );
4286                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4287                                         info->serial_signals |= SerialSignal_RTS;
4288                                         set_signals( info );
4289                                         info->drop_rts_on_tx_done = 1;
4290                                 }
4291                         }
4292
4293                         write_reg16(info, TRC0,
4294                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4295
4296                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4297                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4298
4299                         /* set TX CDA (current descriptor address) */
4300                         write_reg16(info, TXDMA + CDA,
4301                                 info->tx_buf_list_ex[0].phys_entry);
4302
4303                         /* set TX EDA (last descriptor address) */
4304                         write_reg16(info, TXDMA + EDA,
4305                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4306
4307                         /* enable underrun IRQ */
4308                         info->ie1_value &= ~IDLE;
4309                         info->ie1_value |= UDRN;
4310                         write_reg(info, IE1, info->ie1_value);
4311                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4312
4313                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4314                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4315
4316                         info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
4317                         add_timer(&info->tx_timer);
4318                 }
4319                 else {
4320                         tx_load_fifo(info);
4321                         /* async, enable IRQ on txdata */
4322                         info->ie0_value |= TXRDYE;
4323                         write_reg(info, IE0, info->ie0_value);
4324                 }
4325
4326                 info->tx_active = 1;
4327         }
4328 }
4329
4330 /* stop the transmitter and DMA
4331  */
4332 void tx_stop( SLMP_INFO *info )
4333 {
4334         if (debug_level >= DEBUG_LEVEL_ISR)
4335                 printk("%s(%d):%s tx_stop()\n",
4336                          __FILE__,__LINE__, info->device_name );
4337
4338         del_timer(&info->tx_timer);
4339
4340         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4341         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4342
4343         write_reg(info, CMD, TXRESET);
4344
4345         info->ie1_value &= ~(UDRN + IDLE);
4346         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4347         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4348
4349         info->ie0_value &= ~TXRDYE;
4350         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4351
4352         info->tx_enabled = 0;
4353         info->tx_active  = 0;
4354 }
4355
4356 /* Fill the transmit FIFO until the FIFO is full or
4357  * there is no more data to load.
4358  */
4359 void tx_load_fifo(SLMP_INFO *info)
4360 {
4361         u8 TwoBytes[2];
4362
4363         /* do nothing is now tx data available and no XON/XOFF pending */
4364
4365         if ( !info->tx_count && !info->x_char )
4366                 return;
4367
4368         /* load the Transmit FIFO until FIFOs full or all data sent */
4369
4370         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4371
4372                 /* there is more space in the transmit FIFO and */
4373                 /* there is more data in transmit buffer */
4374
4375                 if ( (info->tx_count > 1) && !info->x_char ) {
4376                         /* write 16-bits */
4377                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4378                         if (info->tx_get >= info->max_frame_size)
4379                                 info->tx_get -= info->max_frame_size;
4380                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4381                         if (info->tx_get >= info->max_frame_size)
4382                                 info->tx_get -= info->max_frame_size;
4383
4384                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4385
4386                         info->tx_count -= 2;
4387                         info->icount.tx += 2;
4388                 } else {
4389                         /* only 1 byte left to transmit or 1 FIFO slot left */
4390
4391                         if (info->x_char) {
4392                                 /* transmit pending high priority char */
4393                                 write_reg(info, TRB, info->x_char);
4394                                 info->x_char = 0;
4395                         } else {
4396                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4397                                 if (info->tx_get >= info->max_frame_size)
4398                                         info->tx_get -= info->max_frame_size;
4399                                 info->tx_count--;
4400                         }
4401                         info->icount.tx++;
4402                 }
4403         }
4404 }
4405
4406 /* Reset a port to a known state
4407  */
4408 void reset_port(SLMP_INFO *info)
4409 {
4410         if (info->sca_base) {
4411
4412                 tx_stop(info);
4413                 rx_stop(info);
4414
4415                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4416                 set_signals(info);
4417
4418                 /* disable all port interrupts */
4419                 info->ie0_value = 0;
4420                 info->ie1_value = 0;
4421                 info->ie2_value = 0;
4422                 write_reg(info, IE0, info->ie0_value);
4423                 write_reg(info, IE1, info->ie1_value);
4424                 write_reg(info, IE2, info->ie2_value);
4425
4426                 write_reg(info, CMD, CHRESET);
4427         }
4428 }
4429
4430 /* Reset all the ports to a known state.
4431  */
4432 void reset_adapter(SLMP_INFO *info)
4433 {
4434         int i;
4435
4436         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4437                 if (info->port_array[i])
4438                         reset_port(info->port_array[i]);
4439         }
4440 }
4441
4442 /* Program port for asynchronous communications.
4443  */
4444 void async_mode(SLMP_INFO *info)
4445 {
4446
4447         unsigned char RegValue;
4448
4449         tx_stop(info);
4450         rx_stop(info);
4451
4452         /* MD0, Mode Register 0
4453          *
4454          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4455          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4456          * 03      Reserved, must be 0
4457          * 02      CRCCC, CRC Calculation, 0=disabled
4458          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4459          *
4460          * 0000 0000
4461          */
4462         RegValue = 0x00;
4463         if (info->params.stop_bits != 1)
4464                 RegValue |= BIT1;
4465         write_reg(info, MD0, RegValue);
4466
4467         /* MD1, Mode Register 1
4468          *
4469          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4470          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4471          * 03..02  RXCHR<1..0>, rx char size
4472          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4473          *
4474          * 0100 0000
4475          */
4476         RegValue = 0x40;
4477         switch (info->params.data_bits) {
4478         case 7: RegValue |= BIT4 + BIT2; break;
4479         case 6: RegValue |= BIT5 + BIT3; break;
4480         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4481         }
4482         if (info->params.parity != ASYNC_PARITY_NONE) {
4483                 RegValue |= BIT1;
4484                 if (info->params.parity == ASYNC_PARITY_ODD)
4485                         RegValue |= BIT0;
4486         }
4487         write_reg(info, MD1, RegValue);
4488
4489         /* MD2, Mode Register 2
4490          *
4491          * 07..02  Reserved, must be 0
4492          * 01..00  CNCT<1..0> Channel connection, 0=normal
4493          *
4494          * 0000 0000
4495          */
4496         RegValue = 0x00;
4497         write_reg(info, MD2, RegValue);
4498
4499         /* RXS, Receive clock source
4500          *
4501          * 07      Reserved, must be 0
4502          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4503          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4504          */
4505         RegValue=BIT6;
4506         write_reg(info, RXS, RegValue);
4507
4508         /* TXS, Transmit clock source
4509          *
4510          * 07      Reserved, must be 0
4511          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4512          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4513          */
4514         RegValue=BIT6;
4515         write_reg(info, TXS, RegValue);
4516
4517         /* Control Register
4518          *
4519          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4520          */
4521         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4522         write_control_reg(info);
4523
4524         tx_set_idle(info);
4525
4526         /* RRC Receive Ready Control 0
4527          *
4528          * 07..05  Reserved, must be 0
4529          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4530          */
4531         write_reg(info, RRC, 0x00);
4532
4533         /* TRC0 Transmit Ready Control 0
4534          *
4535          * 07..05  Reserved, must be 0
4536          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4537          */
4538         write_reg(info, TRC0, 0x10);
4539
4540         /* TRC1 Transmit Ready Control 1
4541          *
4542          * 07..05  Reserved, must be 0
4543          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4544          */
4545         write_reg(info, TRC1, 0x1e);
4546
4547         /* CTL, MSCI control register
4548          *
4549          * 07..06  Reserved, set to 0
4550          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4551          * 04      IDLC, idle control, 0=mark 1=idle register
4552          * 03      BRK, break, 0=off 1 =on (async)
4553          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4554          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4555          * 00      RTS, RTS output control, 0=active 1=inactive
4556          *
4557          * 0001 0001
4558          */
4559         RegValue = 0x10;
4560         if (!(info->serial_signals & SerialSignal_RTS))
4561                 RegValue |= 0x01;
4562         write_reg(info, CTL, RegValue);
4563
4564         /* enable status interrupts */
4565         info->ie0_value |= TXINTE + RXINTE;
4566         write_reg(info, IE0, info->ie0_value);
4567
4568         /* enable break detect interrupt */
4569         info->ie1_value = BRKD;
4570         write_reg(info, IE1, info->ie1_value);
4571
4572         /* enable rx overrun interrupt */
4573         info->ie2_value = OVRN;
4574         write_reg(info, IE2, info->ie2_value);
4575
4576         set_rate( info, info->params.data_rate * 16 );
4577
4578         if (info->params.loopback)
4579                 enable_loopback(info,1);
4580 }
4581
4582 /* Program the SCA for HDLC communications.
4583  */
4584 void hdlc_mode(SLMP_INFO *info)
4585 {
4586         unsigned char RegValue;
4587         u32 DpllDivisor;
4588
4589         // Can't use DPLL because SCA outputs recovered clock on RxC when
4590         // DPLL mode selected. This causes output contention with RxC receiver.
4591         // Use of DPLL would require external hardware to disable RxC receiver
4592         // when DPLL mode selected.
4593         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4594
4595         /* disable DMA interrupts */
4596         write_reg(info, TXDMA + DIR, 0);
4597         write_reg(info, RXDMA + DIR, 0);
4598
4599         /* MD0, Mode Register 0
4600          *
4601          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4602          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4603          * 03      Reserved, must be 0
4604          * 02      CRCCC, CRC Calculation, 1=enabled
4605          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4606          * 00      CRC0, CRC initial value, 1 = all 1s
4607          *
4608          * 1000 0001
4609          */
4610         RegValue = 0x81;
4611         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4612                 RegValue |= BIT4;
4613         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4614                 RegValue |= BIT4;
4615         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4616                 RegValue |= BIT2 + BIT1;
4617         write_reg(info, MD0, RegValue);
4618
4619         /* MD1, Mode Register 1
4620          *
4621          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4622          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4623          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4624          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4625          *
4626          * 0000 0000
4627          */
4628         RegValue = 0x00;
4629         write_reg(info, MD1, RegValue);
4630
4631         /* MD2, Mode Register 2
4632          *
4633          * 07      NRZFM, 0=NRZ, 1=FM
4634          * 06..05  CODE<1..0> Encoding, 00=NRZ
4635          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4636          * 02      Reserved, must be 0
4637          * 01..00  CNCT<1..0> Channel connection, 0=normal
4638          *
4639          * 0000 0000
4640          */
4641         RegValue = 0x00;
4642         switch(info->params.encoding) {
4643         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4644         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4645         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4646         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4647 #if 0
4648         case HDLC_ENCODING_NRZB:                                        /* not supported */
4649         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4650         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4651 #endif
4652         }
4653         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4654                 DpllDivisor = 16;
4655                 RegValue |= BIT3;
4656         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4657                 DpllDivisor = 8;
4658         } else {
4659                 DpllDivisor = 32;
4660                 RegValue |= BIT4;
4661         }
4662         write_reg(info, MD2, RegValue);
4663
4664
4665         /* RXS, Receive clock source
4666          *
4667          * 07      Reserved, must be 0
4668          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4669          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4670          */
4671         RegValue=0;
4672         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4673                 RegValue |= BIT6;
4674         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4675                 RegValue |= BIT6 + BIT5;
4676         write_reg(info, RXS, RegValue);
4677
4678         /* TXS, Transmit clock source
4679          *
4680          * 07      Reserved, must be 0
4681          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4682          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4683          */
4684         RegValue=0;
4685         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4686                 RegValue |= BIT6;
4687         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4688                 RegValue |= BIT6 + BIT5;
4689         write_reg(info, TXS, RegValue);
4690
4691         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4692                 set_rate(info, info->params.clock_speed * DpllDivisor);
4693         else
4694                 set_rate(info, info->params.clock_speed);
4695
4696         /* GPDATA (General Purpose I/O Data Register)
4697          *
4698          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4699          */
4700         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4701                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4702         else
4703                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4704         write_control_reg(info);
4705
4706         /* RRC Receive Ready Control 0
4707          *
4708          * 07..05  Reserved, must be 0
4709          * 04..00  RRC<4..0> Rx FIFO trigger active
4710          */
4711         write_reg(info, RRC, rx_active_fifo_level);
4712
4713         /* TRC0 Transmit Ready Control 0
4714          *
4715          * 07..05  Reserved, must be 0
4716          * 04..00  TRC<4..0> Tx FIFO trigger active
4717          */
4718         write_reg(info, TRC0, tx_active_fifo_level);
4719
4720         /* TRC1 Transmit Ready Control 1
4721          *
4722          * 07..05  Reserved, must be 0
4723          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4724          */
4725         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4726
4727         /* DMR, DMA Mode Register
4728          *
4729          * 07..05  Reserved, must be 0
4730          * 04      TMOD, Transfer Mode: 1=chained-block
4731          * 03      Reserved, must be 0
4732          * 02      NF, Number of Frames: 1=multi-frame
4733          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4734          * 00      Reserved, must be 0
4735          *
4736          * 0001 0100
4737          */
4738         write_reg(info, TXDMA + DMR, 0x14);
4739         write_reg(info, RXDMA + DMR, 0x14);
4740
4741         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4742         write_reg(info, RXDMA + CPB,
4743                 (unsigned char)(info->buffer_list_phys >> 16));
4744
4745         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4746         write_reg(info, TXDMA + CPB,
4747                 (unsigned char)(info->buffer_list_phys >> 16));
4748
4749         /* enable status interrupts. other code enables/disables
4750          * the individual sources for these two interrupt classes.
4751          */
4752         info->ie0_value |= TXINTE + RXINTE;
4753         write_reg(info, IE0, info->ie0_value);
4754
4755         /* CTL, MSCI control register
4756          *
4757          * 07..06  Reserved, set to 0
4758          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4759          * 04      IDLC, idle control, 0=mark 1=idle register
4760          * 03      BRK, break, 0=off 1 =on (async)
4761          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4762          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4763          * 00      RTS, RTS output control, 0=active 1=inactive
4764          *
4765          * 0001 0001
4766          */
4767         RegValue = 0x10;
4768         if (!(info->serial_signals & SerialSignal_RTS))
4769                 RegValue |= 0x01;
4770         write_reg(info, CTL, RegValue);
4771
4772         /* preamble not supported ! */
4773
4774         tx_set_idle(info);
4775         tx_stop(info);
4776         rx_stop(info);
4777
4778         set_rate(info, info->params.clock_speed);
4779
4780         if (info->params.loopback)
4781                 enable_loopback(info,1);
4782 }
4783
4784 /* Set the transmit HDLC idle mode
4785  */
4786 void tx_set_idle(SLMP_INFO *info)
4787 {
4788         unsigned char RegValue = 0xff;
4789
4790         /* Map API idle mode to SCA register bits */
4791         switch(info->idle_mode) {
4792         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4793         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4794         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4795         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4796         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4797         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4798         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4799         }
4800
4801         write_reg(info, IDL, RegValue);
4802 }
4803
4804 /* Query the adapter for the state of the V24 status (input) signals.
4805  */
4806 void get_signals(SLMP_INFO *info)
4807 {
4808         u16 status = read_reg(info, SR3);
4809         u16 gpstatus = read_status_reg(info);
4810         u16 testbit;
4811
4812         /* clear all serial signals except DTR and RTS */
4813         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4814
4815         /* set serial signal bits to reflect MISR */
4816
4817         if (!(status & BIT3))
4818                 info->serial_signals |= SerialSignal_CTS;
4819
4820         if ( !(status & BIT2))
4821                 info->serial_signals |= SerialSignal_DCD;
4822
4823         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4824         if (!(gpstatus & testbit))
4825                 info->serial_signals |= SerialSignal_RI;
4826
4827         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4828         if (!(gpstatus & testbit))
4829                 info->serial_signals |= SerialSignal_DSR;
4830 }
4831
4832 /* Set the state of DTR and RTS based on contents of
4833  * serial_signals member of device context.
4834  */
4835 void set_signals(SLMP_INFO *info)
4836 {
4837         unsigned char RegValue;
4838         u16 EnableBit;
4839
4840         RegValue = read_reg(info, CTL);
4841         if (info->serial_signals & SerialSignal_RTS)
4842                 RegValue &= ~BIT0;
4843         else
4844                 RegValue |= BIT0;
4845         write_reg(info, CTL, RegValue);
4846
4847         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4848         EnableBit = BIT1 << (info->port_num*2);
4849         if (info->serial_signals & SerialSignal_DTR)
4850                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4851         else
4852                 info->port_array[0]->ctrlreg_value |= EnableBit;
4853         write_control_reg(info);
4854 }
4855
4856 /*******************/
4857 /* DMA Buffer Code */
4858 /*******************/
4859
4860 /* Set the count for all receive buffers to SCABUFSIZE
4861  * and set the current buffer to the first buffer. This effectively
4862  * makes all buffers free and discards any data in buffers.
4863  */
4864 void rx_reset_buffers(SLMP_INFO *info)
4865 {
4866         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4867 }
4868
4869 /* Free the buffers used by a received frame
4870  *
4871  * info   pointer to device instance data
4872  * first  index of 1st receive buffer of frame
4873  * last   index of last receive buffer of frame
4874  */
4875 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4876 {
4877         int done = 0;
4878
4879         while(!done) {
4880                 /* reset current buffer for reuse */
4881                 info->rx_buf_list[first].status = 0xff;
4882
4883                 if (first == last) {
4884                         done = 1;
4885                         /* set new last rx descriptor address */
4886                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4887                 }
4888
4889                 first++;
4890                 if (first == info->rx_buf_count)
4891                         first = 0;
4892         }
4893
4894         /* set current buffer to next buffer after last buffer of frame */
4895         info->current_rx_buf = first;
4896 }
4897
4898 /* Return a received frame from the receive DMA buffers.
4899  * Only frames received without errors are returned.
4900  *
4901  * Return Value:        1 if frame returned, otherwise 0
4902  */
4903 int rx_get_frame(SLMP_INFO *info)
4904 {
4905         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4906         unsigned short status;
4907         unsigned int framesize = 0;
4908         int ReturnCode = 0;
4909         unsigned long flags;
4910         struct tty_struct *tty = info->tty;
4911         unsigned char addr_field = 0xff;
4912         SCADESC *desc;
4913         SCADESC_EX *desc_ex;
4914
4915 CheckAgain:
4916         /* assume no frame returned, set zero length */
4917         framesize = 0;
4918         addr_field = 0xff;
4919
4920         /*
4921          * current_rx_buf points to the 1st buffer of the next available
4922          * receive frame. To find the last buffer of the frame look for
4923          * a non-zero status field in the buffer entries. (The status
4924          * field is set by the 16C32 after completing a receive frame.
4925          */
4926         StartIndex = EndIndex = info->current_rx_buf;
4927
4928         for ( ;; ) {
4929                 desc = &info->rx_buf_list[EndIndex];
4930                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4931
4932                 if (desc->status == 0xff)
4933                         goto Cleanup;   /* current desc still in use, no frames available */
4934
4935                 if (framesize == 0 && info->params.addr_filter != 0xff)
4936                         addr_field = desc_ex->virt_addr[0];
4937
4938                 framesize += desc->length;
4939
4940                 /* Status != 0 means last buffer of frame */
4941                 if (desc->status)
4942                         break;
4943
4944                 EndIndex++;
4945                 if (EndIndex == info->rx_buf_count)
4946                         EndIndex = 0;
4947
4948                 if (EndIndex == info->current_rx_buf) {
4949                         /* all buffers have been 'used' but none mark      */
4950                         /* the end of a frame. Reset buffers and receiver. */
4951                         if ( info->rx_enabled ){
4952                                 spin_lock_irqsave(&info->lock,flags);
4953                                 rx_start(info);
4954                                 spin_unlock_irqrestore(&info->lock,flags);
4955                         }
4956                         goto Cleanup;
4957                 }
4958
4959         }
4960
4961         /* check status of receive frame */
4962
4963         /* frame status is byte stored after frame data
4964          *
4965          * 7 EOM (end of msg), 1 = last buffer of frame
4966          * 6 Short Frame, 1 = short frame
4967          * 5 Abort, 1 = frame aborted
4968          * 4 Residue, 1 = last byte is partial
4969          * 3 Overrun, 1 = overrun occurred during frame reception
4970          * 2 CRC,     1 = CRC error detected
4971          *
4972          */
4973         status = desc->status;
4974
4975         /* ignore CRC bit if not using CRC (bit is undefined) */
4976         /* Note:CRC is not save to data buffer */
4977         if (info->params.crc_type == HDLC_CRC_NONE)
4978                 status &= ~BIT2;
4979
4980         if (framesize == 0 ||
4981                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4982                 /* discard 0 byte frames, this seems to occur sometime
4983                  * when remote is idling flags.
4984                  */
4985                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4986                 goto CheckAgain;
4987         }
4988
4989         if (framesize < 2)
4990                 status |= BIT6;
4991
4992         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4993                 /* received frame has errors,
4994                  * update counts and mark frame size as 0
4995                  */
4996                 if (status & BIT6)
4997                         info->icount.rxshort++;
4998                 else if (status & BIT5)
4999                         info->icount.rxabort++;
5000                 else if (status & BIT3)
5001                         info->icount.rxover++;
5002                 else
5003                         info->icount.rxcrc++;
5004
5005                 framesize = 0;
5006 #ifdef CONFIG_HDLC
5007                 {
5008                         struct net_device_stats *stats = hdlc_stats(info->netdev);
5009                         stats->rx_errors++;
5010                         stats->rx_frame_errors++;
5011                 }
5012 #endif
5013         }
5014
5015         if ( debug_level >= DEBUG_LEVEL_BH )
5016                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
5017                         __FILE__,__LINE__,info->device_name,status,framesize);
5018
5019         if ( debug_level >= DEBUG_LEVEL_DATA )
5020                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
5021                         min_t(int, framesize,SCABUFSIZE),0);
5022
5023         if (framesize) {
5024                 if (framesize > info->max_frame_size)
5025                         info->icount.rxlong++;
5026                 else {
5027                         /* copy dma buffer(s) to contiguous intermediate buffer */
5028                         int copy_count = framesize;
5029                         int index = StartIndex;
5030                         unsigned char *ptmp = info->tmp_rx_buf;
5031                         info->tmp_rx_buf_count = framesize;
5032
5033                         info->icount.rxok++;
5034
5035                         while(copy_count) {
5036                                 int partial_count = min(copy_count,SCABUFSIZE);
5037                                 memcpy( ptmp,
5038                                         info->rx_buf_list_ex[index].virt_addr,
5039                                         partial_count );
5040                                 ptmp += partial_count;
5041                                 copy_count -= partial_count;
5042
5043                                 if ( ++index == info->rx_buf_count )
5044                                         index = 0;
5045                         }
5046
5047 #ifdef CONFIG_HDLC
5048                         if (info->netcount)
5049                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5050                         else
5051 #endif
5052                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5053                                                   info->flag_buf, framesize);
5054                 }
5055         }
5056         /* Free the buffers used by this frame. */
5057         rx_free_frame_buffers( info, StartIndex, EndIndex );
5058
5059         ReturnCode = 1;
5060
5061 Cleanup:
5062         if ( info->rx_enabled && info->rx_overflow ) {
5063                 /* Receiver is enabled, but needs to restarted due to
5064                  * rx buffer overflow. If buffers are empty, restart receiver.
5065                  */
5066                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5067                         spin_lock_irqsave(&info->lock,flags);
5068                         rx_start(info);
5069                         spin_unlock_irqrestore(&info->lock,flags);
5070                 }
5071         }
5072
5073         return ReturnCode;
5074 }
5075
5076 /* load the transmit DMA buffer with data
5077  */
5078 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5079 {
5080         unsigned short copy_count;
5081         unsigned int i = 0;
5082         SCADESC *desc;
5083         SCADESC_EX *desc_ex;
5084
5085         if ( debug_level >= DEBUG_LEVEL_DATA )
5086                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5087
5088         /* Copy source buffer to one or more DMA buffers, starting with
5089          * the first transmit dma buffer.
5090          */
5091         for(i=0;;)
5092         {
5093                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5094
5095                 desc = &info->tx_buf_list[i];
5096                 desc_ex = &info->tx_buf_list_ex[i];
5097
5098                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5099
5100                 desc->length = copy_count;
5101                 desc->status = 0;
5102
5103                 buf += copy_count;
5104                 count -= copy_count;
5105
5106                 if (!count)
5107                         break;
5108
5109                 i++;
5110                 if (i >= info->tx_buf_count)
5111                         i = 0;
5112         }
5113
5114         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5115         info->last_tx_buf = ++i;
5116 }
5117
5118 int register_test(SLMP_INFO *info)
5119 {
5120         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5121         static unsigned int count = sizeof(testval)/sizeof(unsigned char);
5122         unsigned int i;
5123         int rc = TRUE;
5124         unsigned long flags;
5125
5126         spin_lock_irqsave(&info->lock,flags);
5127         reset_port(info);
5128
5129         /* assume failure */
5130         info->init_error = DiagStatus_AddressFailure;
5131
5132         /* Write bit patterns to various registers but do it out of */
5133         /* sync, then read back and verify values. */
5134
5135         for (i = 0 ; i < count ; i++) {
5136                 write_reg(info, TMC, testval[i]);
5137                 write_reg(info, IDL, testval[(i+1)%count]);
5138                 write_reg(info, SA0, testval[(i+2)%count]);
5139                 write_reg(info, SA1, testval[(i+3)%count]);
5140
5141                 if ( (read_reg(info, TMC) != testval[i]) ||
5142                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5143                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5144                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5145                 {
5146                         rc = FALSE;
5147                         break;
5148                 }
5149         }
5150
5151         reset_port(info);
5152         spin_unlock_irqrestore(&info->lock,flags);
5153
5154         return rc;
5155 }
5156
5157 int irq_test(SLMP_INFO *info)
5158 {
5159         unsigned long timeout;
5160         unsigned long flags;
5161
5162         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5163
5164         spin_lock_irqsave(&info->lock,flags);
5165         reset_port(info);
5166
5167         /* assume failure */
5168         info->init_error = DiagStatus_IrqFailure;
5169         info->irq_occurred = FALSE;
5170
5171         /* setup timer0 on SCA0 to interrupt */
5172
5173         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5174         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5175
5176         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5177         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5178
5179
5180         /* TMCS, Timer Control/Status Register
5181          *
5182          * 07      CMF, Compare match flag (read only) 1=match
5183          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5184          * 05      Reserved, must be 0
5185          * 04      TME, Timer Enable
5186          * 03..00  Reserved, must be 0
5187          *
5188          * 0101 0000
5189          */
5190         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5191
5192         spin_unlock_irqrestore(&info->lock,flags);
5193
5194         timeout=100;
5195         while( timeout-- && !info->irq_occurred ) {
5196                 msleep_interruptible(10);
5197         }
5198
5199         spin_lock_irqsave(&info->lock,flags);
5200         reset_port(info);
5201         spin_unlock_irqrestore(&info->lock,flags);
5202
5203         return info->irq_occurred;
5204 }
5205
5206 /* initialize individual SCA device (2 ports)
5207  */
5208 static int sca_init(SLMP_INFO *info)
5209 {
5210         /* set wait controller to single mem partition (low), no wait states */
5211         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5212         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5213         write_reg(info, WCRL, 0);       /* wait controller low range */
5214         write_reg(info, WCRM, 0);       /* wait controller mid range */
5215         write_reg(info, WCRH, 0);       /* wait controller high range */
5216
5217         /* DPCR, DMA Priority Control
5218          *
5219          * 07..05  Not used, must be 0
5220          * 04      BRC, bus release condition: 0=all transfers complete
5221          * 03      CCC, channel change condition: 0=every cycle
5222          * 02..00  PR<2..0>, priority 100=round robin
5223          *
5224          * 00000100 = 0x04
5225          */
5226         write_reg(info, DPCR, dma_priority);
5227
5228         /* DMA Master Enable, BIT7: 1=enable all channels */
5229         write_reg(info, DMER, 0x80);
5230
5231         /* enable all interrupt classes */
5232         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5233         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5234         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5235
5236         /* ITCR, interrupt control register
5237          * 07      IPC, interrupt priority, 0=MSCI->DMA
5238          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5239          * 04      VOS, Vector Output, 0=unmodified vector
5240          * 03..00  Reserved, must be 0
5241          */
5242         write_reg(info, ITCR, 0);
5243
5244         return TRUE;
5245 }
5246
5247 /* initialize adapter hardware
5248  */
5249 int init_adapter(SLMP_INFO *info)
5250 {
5251         int i;
5252
5253         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5254         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5255         u32 readval;
5256
5257         info->misc_ctrl_value |= BIT30;
5258         *MiscCtrl = info->misc_ctrl_value;
5259
5260         /*
5261          * Force at least 170ns delay before clearing
5262          * reset bit. Each read from LCR takes at least
5263          * 30ns so 10 times for 300ns to be safe.
5264          */
5265         for(i=0;i<10;i++)
5266                 readval = *MiscCtrl;
5267
5268         info->misc_ctrl_value &= ~BIT30;
5269         *MiscCtrl = info->misc_ctrl_value;
5270
5271         /* init control reg (all DTRs off, all clksel=input) */
5272         info->ctrlreg_value = 0xaa;
5273         write_control_reg(info);
5274
5275         {
5276                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5277                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5278
5279                 switch(read_ahead_count)
5280                 {
5281                 case 16:
5282                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5283                         break;
5284                 case 8:
5285                         lcr1_brdr_value |= BIT5 + BIT4;
5286                         break;
5287                 case 4:
5288                         lcr1_brdr_value |= BIT5 + BIT3;
5289                         break;
5290                 case 0:
5291                         lcr1_brdr_value |= BIT5;
5292                         break;
5293                 }
5294
5295                 *LCR1BRDR = lcr1_brdr_value;
5296                 *MiscCtrl = misc_ctrl_value;
5297         }
5298
5299         sca_init(info->port_array[0]);
5300         sca_init(info->port_array[2]);
5301
5302         return TRUE;
5303 }
5304
5305 /* Loopback an HDLC frame to test the hardware
5306  * interrupt and DMA functions.
5307  */
5308 int loopback_test(SLMP_INFO *info)
5309 {
5310 #define TESTFRAMESIZE 20
5311
5312         unsigned long timeout;
5313         u16 count = TESTFRAMESIZE;
5314         unsigned char buf[TESTFRAMESIZE];
5315         int rc = FALSE;
5316         unsigned long flags;
5317
5318         struct tty_struct *oldtty = info->tty;
5319         u32 speed = info->params.clock_speed;
5320
5321         info->params.clock_speed = 3686400;
5322         info->tty = NULL;
5323
5324         /* assume failure */
5325         info->init_error = DiagStatus_DmaFailure;
5326
5327         /* build and send transmit frame */
5328         for (count = 0; count < TESTFRAMESIZE;++count)
5329                 buf[count] = (unsigned char)count;
5330
5331         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5332
5333         /* program hardware for HDLC and enabled receiver */
5334         spin_lock_irqsave(&info->lock,flags);
5335         hdlc_mode(info);
5336         enable_loopback(info,1);
5337         rx_start(info);
5338         info->tx_count = count;
5339         tx_load_dma_buffer(info,buf,count);
5340         tx_start(info);
5341         spin_unlock_irqrestore(&info->lock,flags);
5342
5343         /* wait for receive complete */
5344         /* Set a timeout for waiting for interrupt. */
5345         for ( timeout = 100; timeout; --timeout ) {
5346                 msleep_interruptible(10);
5347
5348                 if (rx_get_frame(info)) {
5349                         rc = TRUE;
5350                         break;
5351                 }
5352         }
5353
5354         /* verify received frame length and contents */
5355         if (rc == TRUE &&
5356                 ( info->tmp_rx_buf_count != count ||
5357                   memcmp(buf, info->tmp_rx_buf,count))) {
5358                 rc = FALSE;
5359         }
5360
5361         spin_lock_irqsave(&info->lock,flags);
5362         reset_adapter(info);
5363         spin_unlock_irqrestore(&info->lock,flags);
5364
5365         info->params.clock_speed = speed;
5366         info->tty = oldtty;
5367
5368         return rc;
5369 }
5370
5371 /* Perform diagnostics on hardware
5372  */
5373 int adapter_test( SLMP_INFO *info )
5374 {
5375         unsigned long flags;
5376         if ( debug_level >= DEBUG_LEVEL_INFO )
5377                 printk( "%s(%d):Testing device %s\n",
5378                         __FILE__,__LINE__,info->device_name );
5379
5380         spin_lock_irqsave(&info->lock,flags);
5381         init_adapter(info);
5382         spin_unlock_irqrestore(&info->lock,flags);
5383
5384         info->port_array[0]->port_count = 0;
5385
5386         if ( register_test(info->port_array[0]) &&
5387                 register_test(info->port_array[1])) {
5388
5389                 info->port_array[0]->port_count = 2;
5390
5391                 if ( register_test(info->port_array[2]) &&
5392                         register_test(info->port_array[3]) )
5393                         info->port_array[0]->port_count += 2;
5394         }
5395         else {
5396                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5397                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5398                 return -ENODEV;
5399         }
5400
5401         if ( !irq_test(info->port_array[0]) ||
5402                 !irq_test(info->port_array[1]) ||
5403                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5404                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5405                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5406                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5407                 return -ENODEV;
5408         }
5409
5410         if (!loopback_test(info->port_array[0]) ||
5411                 !loopback_test(info->port_array[1]) ||
5412                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5413                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5414                 printk( "%s(%d):DMA test failure for device %s\n",
5415                         __FILE__,__LINE__,info->device_name);
5416                 return -ENODEV;
5417         }
5418
5419         if ( debug_level >= DEBUG_LEVEL_INFO )
5420                 printk( "%s(%d):device %s passed diagnostics\n",
5421                         __FILE__,__LINE__,info->device_name );
5422
5423         info->port_array[0]->init_error = 0;
5424         info->port_array[1]->init_error = 0;
5425         if ( info->port_count > 2 ) {
5426                 info->port_array[2]->init_error = 0;
5427                 info->port_array[3]->init_error = 0;
5428         }
5429
5430         return 0;
5431 }
5432
5433 /* Test the shared memory on a PCI adapter.
5434  */
5435 int memory_test(SLMP_INFO *info)
5436 {
5437         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5438                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5439         unsigned long count = sizeof(testval)/sizeof(unsigned long);
5440         unsigned long i;
5441         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5442         unsigned long * addr = (unsigned long *)info->memory_base;
5443
5444         /* Test data lines with test pattern at one location. */
5445
5446         for ( i = 0 ; i < count ; i++ ) {
5447                 *addr = testval[i];
5448                 if ( *addr != testval[i] )
5449                         return FALSE;
5450         }
5451
5452         /* Test address lines with incrementing pattern over */
5453         /* entire address range. */
5454
5455         for ( i = 0 ; i < limit ; i++ ) {
5456                 *addr = i * 4;
5457                 addr++;
5458         }
5459
5460         addr = (unsigned long *)info->memory_base;
5461
5462         for ( i = 0 ; i < limit ; i++ ) {
5463                 if ( *addr != i * 4 )
5464                         return FALSE;
5465                 addr++;
5466         }
5467
5468         memset( info->memory_base, 0, SCA_MEM_SIZE );
5469         return TRUE;
5470 }
5471
5472 /* Load data into PCI adapter shared memory.
5473  *
5474  * The PCI9050 releases control of the local bus
5475  * after completing the current read or write operation.
5476  *
5477  * While the PCI9050 write FIFO not empty, the
5478  * PCI9050 treats all of the writes as a single transaction
5479  * and does not release the bus. This causes DMA latency problems
5480  * at high speeds when copying large data blocks to the shared memory.
5481  *
5482  * This function breaks a write into multiple transations by
5483  * interleaving a read which flushes the write FIFO and 'completes'
5484  * the write transation. This allows any pending DMA request to gain control
5485  * of the local bus in a timely fasion.
5486  */
5487 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5488 {
5489         /* A load interval of 16 allows for 4 32-bit writes at */
5490         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5491
5492         unsigned short interval = count / sca_pci_load_interval;
5493         unsigned short i;
5494
5495         for ( i = 0 ; i < interval ; i++ )
5496         {
5497                 memcpy(dest, src, sca_pci_load_interval);
5498                 read_status_reg(info);
5499                 dest += sca_pci_load_interval;
5500                 src += sca_pci_load_interval;
5501         }
5502
5503         memcpy(dest, src, count % sca_pci_load_interval);
5504 }
5505
5506 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5507 {
5508         int i;
5509         int linecount;
5510         if (xmit)
5511                 printk("%s tx data:\n",info->device_name);
5512         else
5513                 printk("%s rx data:\n",info->device_name);
5514
5515         while(count) {
5516                 if (count > 16)
5517                         linecount = 16;
5518                 else
5519                         linecount = count;
5520
5521                 for(i=0;i<linecount;i++)
5522                         printk("%02X ",(unsigned char)data[i]);
5523                 for(;i<17;i++)
5524                         printk("   ");
5525                 for(i=0;i<linecount;i++) {
5526                         if (data[i]>=040 && data[i]<=0176)
5527                                 printk("%c",data[i]);
5528                         else
5529                                 printk(".");
5530                 }
5531                 printk("\n");
5532
5533                 data  += linecount;
5534                 count -= linecount;
5535         }
5536 }       /* end of trace_block() */
5537
5538 /* called when HDLC frame times out
5539  * update stats and do tx completion processing
5540  */
5541 void tx_timeout(unsigned long context)
5542 {
5543         SLMP_INFO *info = (SLMP_INFO*)context;
5544         unsigned long flags;
5545
5546         if ( debug_level >= DEBUG_LEVEL_INFO )
5547                 printk( "%s(%d):%s tx_timeout()\n",
5548                         __FILE__,__LINE__,info->device_name);
5549         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5550                 info->icount.txtimeout++;
5551         }
5552         spin_lock_irqsave(&info->lock,flags);
5553         info->tx_active = 0;
5554         info->tx_count = info->tx_put = info->tx_get = 0;
5555
5556         spin_unlock_irqrestore(&info->lock,flags);
5557
5558 #ifdef CONFIG_HDLC
5559         if (info->netcount)
5560                 hdlcdev_tx_done(info);
5561         else
5562 #endif
5563                 bh_transmit(info);
5564 }
5565
5566 /* called to periodically check the DSR/RI modem signal input status
5567  */
5568 void status_timeout(unsigned long context)
5569 {
5570         u16 status = 0;
5571         SLMP_INFO *info = (SLMP_INFO*)context;
5572         unsigned long flags;
5573         unsigned char delta;
5574
5575
5576         spin_lock_irqsave(&info->lock,flags);
5577         get_signals(info);
5578         spin_unlock_irqrestore(&info->lock,flags);
5579
5580         /* check for DSR/RI state change */
5581
5582         delta = info->old_signals ^ info->serial_signals;
5583         info->old_signals = info->serial_signals;
5584
5585         if (delta & SerialSignal_DSR)
5586                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5587
5588         if (delta & SerialSignal_RI)
5589                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5590
5591         if (delta & SerialSignal_DCD)
5592                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5593
5594         if (delta & SerialSignal_CTS)
5595                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5596
5597         if (status)
5598                 isr_io_pin(info,status);
5599
5600         info->status_timer.data = (unsigned long)info;
5601         info->status_timer.function = status_timeout;
5602         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
5603         add_timer(&info->status_timer);
5604 }
5605
5606
5607 /* Register Access Routines -
5608  * All registers are memory mapped
5609  */
5610 #define CALC_REGADDR() \
5611         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5612         if (info->port_num > 1) \
5613                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5614         if ( info->port_num & 1) { \
5615                 if (Addr > 0x7f) \
5616                         RegAddr += 0x40;        /* DMA access */ \
5617                 else if (Addr > 0x1f && Addr < 0x60) \
5618                         RegAddr += 0x20;        /* MSCI access */ \
5619         }
5620
5621
5622 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5623 {
5624         CALC_REGADDR();
5625         return *RegAddr;
5626 }
5627 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5628 {
5629         CALC_REGADDR();
5630         *RegAddr = Value;
5631 }
5632
5633 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5634 {
5635         CALC_REGADDR();
5636         return *((u16 *)RegAddr);
5637 }
5638
5639 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5640 {
5641         CALC_REGADDR();
5642         *((u16 *)RegAddr) = Value;
5643 }
5644
5645 unsigned char read_status_reg(SLMP_INFO * info)
5646 {
5647         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5648         return *RegAddr;
5649 }
5650
5651 void write_control_reg(SLMP_INFO * info)
5652 {
5653         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5654         *RegAddr = info->port_array[0]->ctrlreg_value;
5655 }
5656
5657
5658 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5659                                           const struct pci_device_id *ent)
5660 {
5661         if (pci_enable_device(dev)) {
5662                 printk("error enabling pci device %p\n", dev);
5663                 return -EIO;
5664         }
5665         device_init( ++synclinkmp_adapter_count, dev );
5666         return 0;
5667 }
5668
5669 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5670 {
5671 }