1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <asm/bitops.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
45 #include <net/checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/prefetch.h>
51 #include <linux/cache.h>
52 #include <linux/zlib.h>
57 #define DRV_MODULE_NAME "bnx2"
58 #define PFX DRV_MODULE_NAME ": "
59 #define DRV_MODULE_VERSION "1.4.45"
60 #define DRV_MODULE_RELDATE "September 29, 2006"
62 #define RUN_AT(x) (jiffies + (x))
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (5*HZ)
67 static const char version[] __devinitdata =
68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
72 MODULE_LICENSE("GPL");
73 MODULE_VERSION(DRV_MODULE_VERSION);
75 static int disable_msi = 0;
77 module_param(disable_msi, int, 0);
78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
90 /* indexed by board_t, above */
93 } board_info[] __devinitdata = {
94 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
95 { "HP NC370T Multifunction Gigabit Server Adapter" },
96 { "HP NC370i Multifunction Gigabit Server Adapter" },
97 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
98 { "HP NC370F Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
100 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
103 static struct pci_device_id bnx2_pci_tbl[] = {
104 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
105 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
106 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
107 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
113 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
121 static struct flash_spec flash_table[] =
124 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
125 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
126 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
128 /* Expansion entry 0001 */
129 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
130 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
131 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
133 /* Saifun SA25F010 (non-buffered flash) */
134 /* strap, cfg1, & write1 need updates */
135 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
136 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
137 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
138 "Non-buffered flash (128kB)"},
139 /* Saifun SA25F020 (non-buffered flash) */
140 /* strap, cfg1, & write1 need updates */
141 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
142 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
143 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
144 "Non-buffered flash (256kB)"},
145 /* Expansion entry 0100 */
146 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
147 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
148 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
150 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
151 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
152 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
153 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
154 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
155 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
156 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
157 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
158 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
159 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
160 /* Saifun SA25F005 (non-buffered flash) */
161 /* strap, cfg1, & write1 need updates */
162 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
163 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
164 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
165 "Non-buffered flash (64kB)"},
167 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
168 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
169 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
171 /* Expansion entry 1001 */
172 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
173 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
176 /* Expansion entry 1010 */
177 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
178 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
179 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
181 /* ATMEL AT45DB011B (buffered flash) */
182 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
183 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
184 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
185 "Buffered flash (128kB)"},
186 /* Expansion entry 1100 */
187 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
188 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
191 /* Expansion entry 1101 */
192 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
193 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
196 /* Ateml Expansion entry 1110 */
197 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
198 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
199 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1110 (Atmel)"},
201 /* ATMEL AT45DB021B (buffered flash) */
202 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
203 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
204 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
205 "Buffered flash (256kB)"},
208 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
210 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
215 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
216 if (diff > MAX_TX_DESC_CNT)
217 diff = (diff & MAX_TX_DESC_CNT) - 1;
218 return (bp->tx_ring_size - diff);
222 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
224 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
225 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
229 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
231 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
232 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
236 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
239 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
240 REG_WR(bp, BNX2_CTX_DATA, val);
244 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
249 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
250 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
251 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
253 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
254 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
259 val1 = (bp->phy_addr << 21) | (reg << 16) |
260 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
261 BNX2_EMAC_MDIO_COMM_START_BUSY;
262 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
264 for (i = 0; i < 50; i++) {
267 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
268 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
271 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
272 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
278 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
287 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
288 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
289 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
291 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
292 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
301 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
306 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
307 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
308 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
310 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
311 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
316 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
317 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
318 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
319 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
321 for (i = 0; i < 50; i++) {
324 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
325 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
331 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
336 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
337 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
338 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
340 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
341 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
350 bnx2_disable_int(struct bnx2 *bp)
352 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
353 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
354 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
358 bnx2_enable_int(struct bnx2 *bp)
360 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
361 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
362 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
364 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
365 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
367 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
371 bnx2_disable_int_sync(struct bnx2 *bp)
373 atomic_inc(&bp->intr_sem);
374 bnx2_disable_int(bp);
375 synchronize_irq(bp->pdev->irq);
379 bnx2_netif_stop(struct bnx2 *bp)
381 bnx2_disable_int_sync(bp);
382 if (netif_running(bp->dev)) {
383 netif_poll_disable(bp->dev);
384 netif_tx_disable(bp->dev);
385 bp->dev->trans_start = jiffies; /* prevent tx timeout */
390 bnx2_netif_start(struct bnx2 *bp)
392 if (atomic_dec_and_test(&bp->intr_sem)) {
393 if (netif_running(bp->dev)) {
394 netif_wake_queue(bp->dev);
395 netif_poll_enable(bp->dev);
402 bnx2_free_mem(struct bnx2 *bp)
406 if (bp->status_blk) {
407 pci_free_consistent(bp->pdev, bp->status_stats_size,
408 bp->status_blk, bp->status_blk_mapping);
409 bp->status_blk = NULL;
410 bp->stats_blk = NULL;
412 if (bp->tx_desc_ring) {
413 pci_free_consistent(bp->pdev,
414 sizeof(struct tx_bd) * TX_DESC_CNT,
415 bp->tx_desc_ring, bp->tx_desc_mapping);
416 bp->tx_desc_ring = NULL;
418 kfree(bp->tx_buf_ring);
419 bp->tx_buf_ring = NULL;
420 for (i = 0; i < bp->rx_max_ring; i++) {
421 if (bp->rx_desc_ring[i])
422 pci_free_consistent(bp->pdev,
423 sizeof(struct rx_bd) * RX_DESC_CNT,
425 bp->rx_desc_mapping[i]);
426 bp->rx_desc_ring[i] = NULL;
428 vfree(bp->rx_buf_ring);
429 bp->rx_buf_ring = NULL;
433 bnx2_alloc_mem(struct bnx2 *bp)
435 int i, status_blk_size;
437 bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
439 if (bp->tx_buf_ring == NULL)
442 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
443 sizeof(struct tx_bd) *
445 &bp->tx_desc_mapping);
446 if (bp->tx_desc_ring == NULL)
449 bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
451 if (bp->rx_buf_ring == NULL)
454 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
457 for (i = 0; i < bp->rx_max_ring; i++) {
458 bp->rx_desc_ring[i] =
459 pci_alloc_consistent(bp->pdev,
460 sizeof(struct rx_bd) * RX_DESC_CNT,
461 &bp->rx_desc_mapping[i]);
462 if (bp->rx_desc_ring[i] == NULL)
467 /* Combine status and statistics blocks into one allocation. */
468 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
469 bp->status_stats_size = status_blk_size +
470 sizeof(struct statistics_block);
472 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
473 &bp->status_blk_mapping);
474 if (bp->status_blk == NULL)
477 memset(bp->status_blk, 0, bp->status_stats_size);
479 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
482 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
492 bnx2_report_fw_link(struct bnx2 *bp)
494 u32 fw_link_status = 0;
499 switch (bp->line_speed) {
501 if (bp->duplex == DUPLEX_HALF)
502 fw_link_status = BNX2_LINK_STATUS_10HALF;
504 fw_link_status = BNX2_LINK_STATUS_10FULL;
507 if (bp->duplex == DUPLEX_HALF)
508 fw_link_status = BNX2_LINK_STATUS_100HALF;
510 fw_link_status = BNX2_LINK_STATUS_100FULL;
513 if (bp->duplex == DUPLEX_HALF)
514 fw_link_status = BNX2_LINK_STATUS_1000HALF;
516 fw_link_status = BNX2_LINK_STATUS_1000FULL;
519 if (bp->duplex == DUPLEX_HALF)
520 fw_link_status = BNX2_LINK_STATUS_2500HALF;
522 fw_link_status = BNX2_LINK_STATUS_2500FULL;
526 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
529 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
531 bnx2_read_phy(bp, MII_BMSR, &bmsr);
532 bnx2_read_phy(bp, MII_BMSR, &bmsr);
534 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
535 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
536 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
538 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
542 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
544 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
548 bnx2_report_link(struct bnx2 *bp)
551 netif_carrier_on(bp->dev);
552 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
554 printk("%d Mbps ", bp->line_speed);
556 if (bp->duplex == DUPLEX_FULL)
557 printk("full duplex");
559 printk("half duplex");
562 if (bp->flow_ctrl & FLOW_CTRL_RX) {
563 printk(", receive ");
564 if (bp->flow_ctrl & FLOW_CTRL_TX)
565 printk("& transmit ");
568 printk(", transmit ");
570 printk("flow control ON");
575 netif_carrier_off(bp->dev);
576 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
579 bnx2_report_fw_link(bp);
583 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
585 u32 local_adv, remote_adv;
588 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
589 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
591 if (bp->duplex == DUPLEX_FULL) {
592 bp->flow_ctrl = bp->req_flow_ctrl;
597 if (bp->duplex != DUPLEX_FULL) {
601 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
602 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
605 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
606 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
607 bp->flow_ctrl |= FLOW_CTRL_TX;
608 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
609 bp->flow_ctrl |= FLOW_CTRL_RX;
613 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
614 bnx2_read_phy(bp, MII_LPA, &remote_adv);
616 if (bp->phy_flags & PHY_SERDES_FLAG) {
617 u32 new_local_adv = 0;
618 u32 new_remote_adv = 0;
620 if (local_adv & ADVERTISE_1000XPAUSE)
621 new_local_adv |= ADVERTISE_PAUSE_CAP;
622 if (local_adv & ADVERTISE_1000XPSE_ASYM)
623 new_local_adv |= ADVERTISE_PAUSE_ASYM;
624 if (remote_adv & ADVERTISE_1000XPAUSE)
625 new_remote_adv |= ADVERTISE_PAUSE_CAP;
626 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
627 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
629 local_adv = new_local_adv;
630 remote_adv = new_remote_adv;
633 /* See Table 28B-3 of 802.3ab-1999 spec. */
634 if (local_adv & ADVERTISE_PAUSE_CAP) {
635 if(local_adv & ADVERTISE_PAUSE_ASYM) {
636 if (remote_adv & ADVERTISE_PAUSE_CAP) {
637 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
639 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
640 bp->flow_ctrl = FLOW_CTRL_RX;
644 if (remote_adv & ADVERTISE_PAUSE_CAP) {
645 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
649 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
650 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
651 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
653 bp->flow_ctrl = FLOW_CTRL_TX;
659 bnx2_5708s_linkup(struct bnx2 *bp)
664 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
665 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
666 case BCM5708S_1000X_STAT1_SPEED_10:
667 bp->line_speed = SPEED_10;
669 case BCM5708S_1000X_STAT1_SPEED_100:
670 bp->line_speed = SPEED_100;
672 case BCM5708S_1000X_STAT1_SPEED_1G:
673 bp->line_speed = SPEED_1000;
675 case BCM5708S_1000X_STAT1_SPEED_2G5:
676 bp->line_speed = SPEED_2500;
679 if (val & BCM5708S_1000X_STAT1_FD)
680 bp->duplex = DUPLEX_FULL;
682 bp->duplex = DUPLEX_HALF;
688 bnx2_5706s_linkup(struct bnx2 *bp)
690 u32 bmcr, local_adv, remote_adv, common;
693 bp->line_speed = SPEED_1000;
695 bnx2_read_phy(bp, MII_BMCR, &bmcr);
696 if (bmcr & BMCR_FULLDPLX) {
697 bp->duplex = DUPLEX_FULL;
700 bp->duplex = DUPLEX_HALF;
703 if (!(bmcr & BMCR_ANENABLE)) {
707 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
708 bnx2_read_phy(bp, MII_LPA, &remote_adv);
710 common = local_adv & remote_adv;
711 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
713 if (common & ADVERTISE_1000XFULL) {
714 bp->duplex = DUPLEX_FULL;
717 bp->duplex = DUPLEX_HALF;
725 bnx2_copper_linkup(struct bnx2 *bp)
729 bnx2_read_phy(bp, MII_BMCR, &bmcr);
730 if (bmcr & BMCR_ANENABLE) {
731 u32 local_adv, remote_adv, common;
733 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
734 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
736 common = local_adv & (remote_adv >> 2);
737 if (common & ADVERTISE_1000FULL) {
738 bp->line_speed = SPEED_1000;
739 bp->duplex = DUPLEX_FULL;
741 else if (common & ADVERTISE_1000HALF) {
742 bp->line_speed = SPEED_1000;
743 bp->duplex = DUPLEX_HALF;
746 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
747 bnx2_read_phy(bp, MII_LPA, &remote_adv);
749 common = local_adv & remote_adv;
750 if (common & ADVERTISE_100FULL) {
751 bp->line_speed = SPEED_100;
752 bp->duplex = DUPLEX_FULL;
754 else if (common & ADVERTISE_100HALF) {
755 bp->line_speed = SPEED_100;
756 bp->duplex = DUPLEX_HALF;
758 else if (common & ADVERTISE_10FULL) {
759 bp->line_speed = SPEED_10;
760 bp->duplex = DUPLEX_FULL;
762 else if (common & ADVERTISE_10HALF) {
763 bp->line_speed = SPEED_10;
764 bp->duplex = DUPLEX_HALF;
773 if (bmcr & BMCR_SPEED100) {
774 bp->line_speed = SPEED_100;
777 bp->line_speed = SPEED_10;
779 if (bmcr & BMCR_FULLDPLX) {
780 bp->duplex = DUPLEX_FULL;
783 bp->duplex = DUPLEX_HALF;
791 bnx2_set_mac_link(struct bnx2 *bp)
795 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
796 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
797 (bp->duplex == DUPLEX_HALF)) {
798 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
801 /* Configure the EMAC mode register. */
802 val = REG_RD(bp, BNX2_EMAC_MODE);
804 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
805 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
809 switch (bp->line_speed) {
811 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
812 val |= BNX2_EMAC_MODE_PORT_MII_10;
817 val |= BNX2_EMAC_MODE_PORT_MII;
820 val |= BNX2_EMAC_MODE_25G;
823 val |= BNX2_EMAC_MODE_PORT_GMII;
828 val |= BNX2_EMAC_MODE_PORT_GMII;
831 /* Set the MAC to operate in the appropriate duplex mode. */
832 if (bp->duplex == DUPLEX_HALF)
833 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
834 REG_WR(bp, BNX2_EMAC_MODE, val);
836 /* Enable/disable rx PAUSE. */
837 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
839 if (bp->flow_ctrl & FLOW_CTRL_RX)
840 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
841 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
843 /* Enable/disable tx PAUSE. */
844 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
845 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
847 if (bp->flow_ctrl & FLOW_CTRL_TX)
848 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
849 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
851 /* Acknowledge the interrupt. */
852 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
858 bnx2_set_link(struct bnx2 *bp)
863 if (bp->loopback == MAC_LOOPBACK) {
868 link_up = bp->link_up;
870 bnx2_read_phy(bp, MII_BMSR, &bmsr);
871 bnx2_read_phy(bp, MII_BMSR, &bmsr);
873 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
874 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
877 val = REG_RD(bp, BNX2_EMAC_STATUS);
878 if (val & BNX2_EMAC_STATUS_LINK)
879 bmsr |= BMSR_LSTATUS;
881 bmsr &= ~BMSR_LSTATUS;
884 if (bmsr & BMSR_LSTATUS) {
887 if (bp->phy_flags & PHY_SERDES_FLAG) {
888 if (CHIP_NUM(bp) == CHIP_NUM_5706)
889 bnx2_5706s_linkup(bp);
890 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
891 bnx2_5708s_linkup(bp);
894 bnx2_copper_linkup(bp);
896 bnx2_resolve_flow_ctrl(bp);
899 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
900 (bp->autoneg & AUTONEG_SPEED)) {
904 bnx2_read_phy(bp, MII_BMCR, &bmcr);
905 if (!(bmcr & BMCR_ANENABLE)) {
906 bnx2_write_phy(bp, MII_BMCR, bmcr |
910 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
914 if (bp->link_up != link_up) {
915 bnx2_report_link(bp);
918 bnx2_set_mac_link(bp);
924 bnx2_reset_phy(struct bnx2 *bp)
929 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
931 #define PHY_RESET_MAX_WAIT 100
932 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
935 bnx2_read_phy(bp, MII_BMCR, ®);
936 if (!(reg & BMCR_RESET)) {
941 if (i == PHY_RESET_MAX_WAIT) {
948 bnx2_phy_get_pause_adv(struct bnx2 *bp)
952 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
953 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
955 if (bp->phy_flags & PHY_SERDES_FLAG) {
956 adv = ADVERTISE_1000XPAUSE;
959 adv = ADVERTISE_PAUSE_CAP;
962 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
963 if (bp->phy_flags & PHY_SERDES_FLAG) {
964 adv = ADVERTISE_1000XPSE_ASYM;
967 adv = ADVERTISE_PAUSE_ASYM;
970 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
971 if (bp->phy_flags & PHY_SERDES_FLAG) {
972 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
975 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
982 bnx2_setup_serdes_phy(struct bnx2 *bp)
987 if (!(bp->autoneg & AUTONEG_SPEED)) {
989 int force_link_down = 0;
991 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
992 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
993 if (up1 & BCM5708S_UP1_2G5) {
994 up1 &= ~BCM5708S_UP1_2G5;
995 bnx2_write_phy(bp, BCM5708S_UP1, up1);
1000 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
1001 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1003 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1004 new_bmcr = bmcr & ~BMCR_ANENABLE;
1005 new_bmcr |= BMCR_SPEED1000;
1006 if (bp->req_duplex == DUPLEX_FULL) {
1007 adv |= ADVERTISE_1000XFULL;
1008 new_bmcr |= BMCR_FULLDPLX;
1011 adv |= ADVERTISE_1000XHALF;
1012 new_bmcr &= ~BMCR_FULLDPLX;
1014 if ((new_bmcr != bmcr) || (force_link_down)) {
1015 /* Force a link down visible on the other side */
1017 bnx2_write_phy(bp, MII_ADVERTISE, adv &
1018 ~(ADVERTISE_1000XFULL |
1019 ADVERTISE_1000XHALF));
1020 bnx2_write_phy(bp, MII_BMCR, bmcr |
1021 BMCR_ANRESTART | BMCR_ANENABLE);
1024 netif_carrier_off(bp->dev);
1025 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1027 bnx2_write_phy(bp, MII_ADVERTISE, adv);
1028 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1033 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1034 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
1035 up1 |= BCM5708S_UP1_2G5;
1036 bnx2_write_phy(bp, BCM5708S_UP1, up1);
1039 if (bp->advertising & ADVERTISED_1000baseT_Full)
1040 new_adv |= ADVERTISE_1000XFULL;
1042 new_adv |= bnx2_phy_get_pause_adv(bp);
1044 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
1045 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1047 bp->serdes_an_pending = 0;
1048 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1049 /* Force a link down visible on the other side */
1053 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1054 for (i = 0; i < 110; i++) {
1059 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1060 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1062 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1063 /* Speed up link-up time when the link partner
1064 * does not autonegotiate which is very common
1065 * in blade servers. Some blade servers use
1066 * IPMI for kerboard input and it's important
1067 * to minimize link disruptions. Autoneg. involves
1068 * exchanging base pages plus 3 next pages and
1069 * normally completes in about 120 msec.
1071 bp->current_interval = SERDES_AN_TIMEOUT;
1072 bp->serdes_an_pending = 1;
1073 mod_timer(&bp->timer, jiffies + bp->current_interval);
1080 #define ETHTOOL_ALL_FIBRE_SPEED \
1081 (ADVERTISED_1000baseT_Full)
1083 #define ETHTOOL_ALL_COPPER_SPEED \
1084 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1085 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1086 ADVERTISED_1000baseT_Full)
1088 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1089 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1091 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1094 bnx2_setup_copper_phy(struct bnx2 *bp)
1099 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1101 if (bp->autoneg & AUTONEG_SPEED) {
1102 u32 adv_reg, adv1000_reg;
1103 u32 new_adv_reg = 0;
1104 u32 new_adv1000_reg = 0;
1106 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1107 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1108 ADVERTISE_PAUSE_ASYM);
1110 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1111 adv1000_reg &= PHY_ALL_1000_SPEED;
1113 if (bp->advertising & ADVERTISED_10baseT_Half)
1114 new_adv_reg |= ADVERTISE_10HALF;
1115 if (bp->advertising & ADVERTISED_10baseT_Full)
1116 new_adv_reg |= ADVERTISE_10FULL;
1117 if (bp->advertising & ADVERTISED_100baseT_Half)
1118 new_adv_reg |= ADVERTISE_100HALF;
1119 if (bp->advertising & ADVERTISED_100baseT_Full)
1120 new_adv_reg |= ADVERTISE_100FULL;
1121 if (bp->advertising & ADVERTISED_1000baseT_Full)
1122 new_adv1000_reg |= ADVERTISE_1000FULL;
1124 new_adv_reg |= ADVERTISE_CSMA;
1126 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1128 if ((adv1000_reg != new_adv1000_reg) ||
1129 (adv_reg != new_adv_reg) ||
1130 ((bmcr & BMCR_ANENABLE) == 0)) {
1132 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1133 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1134 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1137 else if (bp->link_up) {
1138 /* Flow ctrl may have changed from auto to forced */
1139 /* or vice-versa. */
1141 bnx2_resolve_flow_ctrl(bp);
1142 bnx2_set_mac_link(bp);
1148 if (bp->req_line_speed == SPEED_100) {
1149 new_bmcr |= BMCR_SPEED100;
1151 if (bp->req_duplex == DUPLEX_FULL) {
1152 new_bmcr |= BMCR_FULLDPLX;
1154 if (new_bmcr != bmcr) {
1158 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1159 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1161 if (bmsr & BMSR_LSTATUS) {
1162 /* Force link down */
1163 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1166 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1167 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1169 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1172 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1174 /* Normally, the new speed is setup after the link has
1175 * gone down and up again. In some cases, link will not go
1176 * down so we need to set up the new speed here.
1178 if (bmsr & BMSR_LSTATUS) {
1179 bp->line_speed = bp->req_line_speed;
1180 bp->duplex = bp->req_duplex;
1181 bnx2_resolve_flow_ctrl(bp);
1182 bnx2_set_mac_link(bp);
1189 bnx2_setup_phy(struct bnx2 *bp)
1191 if (bp->loopback == MAC_LOOPBACK)
1194 if (bp->phy_flags & PHY_SERDES_FLAG) {
1195 return (bnx2_setup_serdes_phy(bp));
1198 return (bnx2_setup_copper_phy(bp));
1203 bnx2_init_5708s_phy(struct bnx2 *bp)
1207 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1208 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1209 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1211 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1212 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1213 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1215 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1216 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1217 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1219 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1220 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1221 val |= BCM5708S_UP1_2G5;
1222 bnx2_write_phy(bp, BCM5708S_UP1, val);
1225 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1226 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1227 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1228 /* increase tx signal amplitude */
1229 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1230 BCM5708S_BLK_ADDR_TX_MISC);
1231 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1232 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1233 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1234 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1237 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1238 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1243 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1244 BNX2_SHARED_HW_CFG_CONFIG);
1245 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1246 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1247 BCM5708S_BLK_ADDR_TX_MISC);
1248 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1249 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1250 BCM5708S_BLK_ADDR_DIG);
1257 bnx2_init_5706s_phy(struct bnx2 *bp)
1259 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1261 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1262 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1265 if (bp->dev->mtu > 1500) {
1268 /* Set extended packet length bit */
1269 bnx2_write_phy(bp, 0x18, 0x7);
1270 bnx2_read_phy(bp, 0x18, &val);
1271 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1273 bnx2_write_phy(bp, 0x1c, 0x6c00);
1274 bnx2_read_phy(bp, 0x1c, &val);
1275 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1280 bnx2_write_phy(bp, 0x18, 0x7);
1281 bnx2_read_phy(bp, 0x18, &val);
1282 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1284 bnx2_write_phy(bp, 0x1c, 0x6c00);
1285 bnx2_read_phy(bp, 0x1c, &val);
1286 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1293 bnx2_init_copper_phy(struct bnx2 *bp)
1297 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1299 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1300 bnx2_write_phy(bp, 0x18, 0x0c00);
1301 bnx2_write_phy(bp, 0x17, 0x000a);
1302 bnx2_write_phy(bp, 0x15, 0x310b);
1303 bnx2_write_phy(bp, 0x17, 0x201f);
1304 bnx2_write_phy(bp, 0x15, 0x9506);
1305 bnx2_write_phy(bp, 0x17, 0x401f);
1306 bnx2_write_phy(bp, 0x15, 0x14e2);
1307 bnx2_write_phy(bp, 0x18, 0x0400);
1310 if (bp->dev->mtu > 1500) {
1311 /* Set extended packet length bit */
1312 bnx2_write_phy(bp, 0x18, 0x7);
1313 bnx2_read_phy(bp, 0x18, &val);
1314 bnx2_write_phy(bp, 0x18, val | 0x4000);
1316 bnx2_read_phy(bp, 0x10, &val);
1317 bnx2_write_phy(bp, 0x10, val | 0x1);
1320 bnx2_write_phy(bp, 0x18, 0x7);
1321 bnx2_read_phy(bp, 0x18, &val);
1322 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1324 bnx2_read_phy(bp, 0x10, &val);
1325 bnx2_write_phy(bp, 0x10, val & ~0x1);
1328 /* ethernet@wirespeed */
1329 bnx2_write_phy(bp, 0x18, 0x7007);
1330 bnx2_read_phy(bp, 0x18, &val);
1331 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1337 bnx2_init_phy(struct bnx2 *bp)
1342 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1343 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1345 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1349 bnx2_read_phy(bp, MII_PHYSID1, &val);
1350 bp->phy_id = val << 16;
1351 bnx2_read_phy(bp, MII_PHYSID2, &val);
1352 bp->phy_id |= val & 0xffff;
1354 if (bp->phy_flags & PHY_SERDES_FLAG) {
1355 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1356 rc = bnx2_init_5706s_phy(bp);
1357 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1358 rc = bnx2_init_5708s_phy(bp);
1361 rc = bnx2_init_copper_phy(bp);
1370 bnx2_set_mac_loopback(struct bnx2 *bp)
1374 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1375 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1376 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1377 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1382 static int bnx2_test_link(struct bnx2 *);
1385 bnx2_set_phy_loopback(struct bnx2 *bp)
1390 spin_lock_bh(&bp->phy_lock);
1391 rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
1393 spin_unlock_bh(&bp->phy_lock);
1397 for (i = 0; i < 10; i++) {
1398 if (bnx2_test_link(bp) == 0)
1403 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1404 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1405 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1406 BNX2_EMAC_MODE_25G);
1408 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
1409 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1415 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1421 msg_data |= bp->fw_wr_seq;
1423 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1425 /* wait for an acknowledgement. */
1426 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1429 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1431 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1434 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1437 /* If we timed out, inform the firmware that this is the case. */
1438 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1440 printk(KERN_ERR PFX "fw sync timeout, reset code = "
1443 msg_data &= ~BNX2_DRV_MSG_CODE;
1444 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1446 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1451 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1458 bnx2_init_context(struct bnx2 *bp)
1464 u32 vcid_addr, pcid_addr, offset;
1468 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1471 vcid_addr = GET_PCID_ADDR(vcid);
1473 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1478 pcid_addr = GET_PCID_ADDR(new_vcid);
1481 vcid_addr = GET_CID_ADDR(vcid);
1482 pcid_addr = vcid_addr;
1485 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1486 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1488 /* Zero out the context. */
1489 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1490 CTX_WR(bp, 0x00, offset, 0);
1493 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1494 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1499 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1505 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1506 if (good_mbuf == NULL) {
1507 printk(KERN_ERR PFX "Failed to allocate memory in "
1508 "bnx2_alloc_bad_rbuf\n");
1512 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1513 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1517 /* Allocate a bunch of mbufs and save the good ones in an array. */
1518 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1519 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1520 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1522 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1524 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1526 /* The addresses with Bit 9 set are bad memory blocks. */
1527 if (!(val & (1 << 9))) {
1528 good_mbuf[good_mbuf_cnt] = (u16) val;
1532 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1535 /* Free the good ones back to the mbuf pool thus discarding
1536 * all the bad ones. */
1537 while (good_mbuf_cnt) {
1540 val = good_mbuf[good_mbuf_cnt];
1541 val = (val << 9) | val | 1;
1543 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1550 bnx2_set_mac_addr(struct bnx2 *bp)
1553 u8 *mac_addr = bp->dev->dev_addr;
1555 val = (mac_addr[0] << 8) | mac_addr[1];
1557 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1559 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1560 (mac_addr[4] << 8) | mac_addr[5];
1562 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1566 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1568 struct sk_buff *skb;
1569 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1571 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
1572 unsigned long align;
1574 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1579 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1580 skb_reserve(skb, 8 - align);
1583 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1584 PCI_DMA_FROMDEVICE);
1587 pci_unmap_addr_set(rx_buf, mapping, mapping);
1589 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1590 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1592 bp->rx_prod_bseq += bp->rx_buf_use_size;
1598 bnx2_phy_int(struct bnx2 *bp)
1600 u32 new_link_state, old_link_state;
1602 new_link_state = bp->status_blk->status_attn_bits &
1603 STATUS_ATTN_BITS_LINK_STATE;
1604 old_link_state = bp->status_blk->status_attn_bits_ack &
1605 STATUS_ATTN_BITS_LINK_STATE;
1606 if (new_link_state != old_link_state) {
1607 if (new_link_state) {
1608 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1609 STATUS_ATTN_BITS_LINK_STATE);
1612 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1613 STATUS_ATTN_BITS_LINK_STATE);
1620 bnx2_tx_int(struct bnx2 *bp)
1622 struct status_block *sblk = bp->status_blk;
1623 u16 hw_cons, sw_cons, sw_ring_cons;
1626 hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
1627 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1630 sw_cons = bp->tx_cons;
1632 while (sw_cons != hw_cons) {
1633 struct sw_bd *tx_buf;
1634 struct sk_buff *skb;
1637 sw_ring_cons = TX_RING_IDX(sw_cons);
1639 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1642 /* partial BD completions possible with TSO packets */
1643 if (skb_is_gso(skb)) {
1644 u16 last_idx, last_ring_idx;
1646 last_idx = sw_cons +
1647 skb_shinfo(skb)->nr_frags + 1;
1648 last_ring_idx = sw_ring_cons +
1649 skb_shinfo(skb)->nr_frags + 1;
1650 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1653 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1658 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1659 skb_headlen(skb), PCI_DMA_TODEVICE);
1662 last = skb_shinfo(skb)->nr_frags;
1664 for (i = 0; i < last; i++) {
1665 sw_cons = NEXT_TX_BD(sw_cons);
1667 pci_unmap_page(bp->pdev,
1669 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1671 skb_shinfo(skb)->frags[i].size,
1675 sw_cons = NEXT_TX_BD(sw_cons);
1677 tx_free_bd += last + 1;
1681 hw_cons = bp->hw_tx_cons =
1682 sblk->status_tx_quick_consumer_index0;
1684 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1689 bp->tx_cons = sw_cons;
1690 /* Need to make the tx_cons update visible to bnx2_start_xmit()
1691 * before checking for netif_queue_stopped(). Without the
1692 * memory barrier, there is a small possibility that bnx2_start_xmit()
1693 * will miss it and cause the queue to be stopped forever.
1697 if (unlikely(netif_queue_stopped(bp->dev)) &&
1698 (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) {
1699 netif_tx_lock(bp->dev);
1700 if ((netif_queue_stopped(bp->dev)) &&
1701 (bnx2_tx_avail(bp) > bp->tx_wake_thresh))
1702 netif_wake_queue(bp->dev);
1703 netif_tx_unlock(bp->dev);
1708 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1711 struct sw_bd *cons_rx_buf, *prod_rx_buf;
1712 struct rx_bd *cons_bd, *prod_bd;
1714 cons_rx_buf = &bp->rx_buf_ring[cons];
1715 prod_rx_buf = &bp->rx_buf_ring[prod];
1717 pci_dma_sync_single_for_device(bp->pdev,
1718 pci_unmap_addr(cons_rx_buf, mapping),
1719 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1721 bp->rx_prod_bseq += bp->rx_buf_use_size;
1723 prod_rx_buf->skb = skb;
1728 pci_unmap_addr_set(prod_rx_buf, mapping,
1729 pci_unmap_addr(cons_rx_buf, mapping));
1731 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
1732 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1733 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
1734 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
1738 bnx2_rx_int(struct bnx2 *bp, int budget)
1740 struct status_block *sblk = bp->status_blk;
1741 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1742 struct l2_fhdr *rx_hdr;
1745 hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
1746 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1749 sw_cons = bp->rx_cons;
1750 sw_prod = bp->rx_prod;
1752 /* Memory barrier necessary as speculative reads of the rx
1753 * buffer can be ahead of the index in the status block
1756 while (sw_cons != hw_cons) {
1759 struct sw_bd *rx_buf;
1760 struct sk_buff *skb;
1761 dma_addr_t dma_addr;
1763 sw_ring_cons = RX_RING_IDX(sw_cons);
1764 sw_ring_prod = RX_RING_IDX(sw_prod);
1766 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1771 dma_addr = pci_unmap_addr(rx_buf, mapping);
1773 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
1774 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1776 rx_hdr = (struct l2_fhdr *) skb->data;
1777 len = rx_hdr->l2_fhdr_pkt_len - 4;
1779 if ((status = rx_hdr->l2_fhdr_status) &
1780 (L2_FHDR_ERRORS_BAD_CRC |
1781 L2_FHDR_ERRORS_PHY_DECODE |
1782 L2_FHDR_ERRORS_ALIGNMENT |
1783 L2_FHDR_ERRORS_TOO_SHORT |
1784 L2_FHDR_ERRORS_GIANT_FRAME)) {
1789 /* Since we don't have a jumbo ring, copy small packets
1792 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1793 struct sk_buff *new_skb;
1795 new_skb = netdev_alloc_skb(bp->dev, len + 2);
1796 if (new_skb == NULL)
1800 memcpy(new_skb->data,
1801 skb->data + bp->rx_offset - 2,
1804 skb_reserve(new_skb, 2);
1805 skb_put(new_skb, len);
1807 bnx2_reuse_rx_skb(bp, skb,
1808 sw_ring_cons, sw_ring_prod);
1812 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1813 pci_unmap_single(bp->pdev, dma_addr,
1814 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1816 skb_reserve(skb, bp->rx_offset);
1821 bnx2_reuse_rx_skb(bp, skb,
1822 sw_ring_cons, sw_ring_prod);
1826 skb->protocol = eth_type_trans(skb, bp->dev);
1828 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1829 (ntohs(skb->protocol) != 0x8100)) {
1836 skb->ip_summed = CHECKSUM_NONE;
1838 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1839 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1841 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
1842 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
1843 skb->ip_summed = CHECKSUM_UNNECESSARY;
1847 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1848 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1849 rx_hdr->l2_fhdr_vlan_tag);
1853 netif_receive_skb(skb);
1855 bp->dev->last_rx = jiffies;
1859 sw_cons = NEXT_RX_BD(sw_cons);
1860 sw_prod = NEXT_RX_BD(sw_prod);
1862 if ((rx_pkt == budget))
1865 /* Refresh hw_cons to see if there is new work */
1866 if (sw_cons == hw_cons) {
1867 hw_cons = bp->hw_rx_cons =
1868 sblk->status_rx_quick_consumer_index0;
1869 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1874 bp->rx_cons = sw_cons;
1875 bp->rx_prod = sw_prod;
1877 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1879 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1887 /* MSI ISR - The only difference between this and the INTx ISR
1888 * is that the MSI interrupt is always serviced.
1891 bnx2_msi(int irq, void *dev_instance)
1893 struct net_device *dev = dev_instance;
1894 struct bnx2 *bp = netdev_priv(dev);
1896 prefetch(bp->status_blk);
1897 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1898 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1899 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1901 /* Return here if interrupt is disabled. */
1902 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1905 netif_rx_schedule(dev);
1911 bnx2_interrupt(int irq, void *dev_instance)
1913 struct net_device *dev = dev_instance;
1914 struct bnx2 *bp = netdev_priv(dev);
1916 /* When using INTx, it is possible for the interrupt to arrive
1917 * at the CPU before the status block posted prior to the
1918 * interrupt. Reading a register will flush the status block.
1919 * When using MSI, the MSI message will always complete after
1920 * the status block write.
1922 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
1923 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1924 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1927 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1928 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1929 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1931 /* Return here if interrupt is shared and is disabled. */
1932 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1935 netif_rx_schedule(dev);
1941 bnx2_has_work(struct bnx2 *bp)
1943 struct status_block *sblk = bp->status_blk;
1945 if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1946 (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1949 if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1957 bnx2_poll(struct net_device *dev, int *budget)
1959 struct bnx2 *bp = netdev_priv(dev);
1961 if ((bp->status_blk->status_attn_bits &
1962 STATUS_ATTN_BITS_LINK_STATE) !=
1963 (bp->status_blk->status_attn_bits_ack &
1964 STATUS_ATTN_BITS_LINK_STATE)) {
1966 spin_lock(&bp->phy_lock);
1968 spin_unlock(&bp->phy_lock);
1970 /* This is needed to take care of transient status
1971 * during link changes.
1973 REG_WR(bp, BNX2_HC_COMMAND,
1974 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
1975 REG_RD(bp, BNX2_HC_COMMAND);
1978 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
1981 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
1982 int orig_budget = *budget;
1985 if (orig_budget > dev->quota)
1986 orig_budget = dev->quota;
1988 work_done = bnx2_rx_int(bp, orig_budget);
1989 *budget -= work_done;
1990 dev->quota -= work_done;
1993 bp->last_status_idx = bp->status_blk->status_idx;
1996 if (!bnx2_has_work(bp)) {
1997 netif_rx_complete(dev);
1998 if (likely(bp->flags & USING_MSI_FLAG)) {
1999 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2000 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2001 bp->last_status_idx);
2004 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2005 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2006 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2007 bp->last_status_idx);
2009 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2010 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2011 bp->last_status_idx);
2018 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2019 * from set_multicast.
2022 bnx2_set_rx_mode(struct net_device *dev)
2024 struct bnx2 *bp = netdev_priv(dev);
2025 u32 rx_mode, sort_mode;
2028 spin_lock_bh(&bp->phy_lock);
2030 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2031 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2032 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2034 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2035 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2037 if (!(bp->flags & ASF_ENABLE_FLAG))
2038 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2040 if (dev->flags & IFF_PROMISC) {
2041 /* Promiscuous mode. */
2042 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2043 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2044 BNX2_RPM_SORT_USER0_PROM_VLAN;
2046 else if (dev->flags & IFF_ALLMULTI) {
2047 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2048 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2051 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2054 /* Accept one or more multicast(s). */
2055 struct dev_mc_list *mclist;
2056 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2061 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2063 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2064 i++, mclist = mclist->next) {
2066 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2068 regidx = (bit & 0xe0) >> 5;
2070 mc_filter[regidx] |= (1 << bit);
2073 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2074 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2078 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2081 if (rx_mode != bp->rx_mode) {
2082 bp->rx_mode = rx_mode;
2083 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2086 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2087 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2088 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2090 spin_unlock_bh(&bp->phy_lock);
2093 #define FW_BUF_SIZE 0x8000
2096 bnx2_gunzip_init(struct bnx2 *bp)
2098 if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL)
2101 if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL)
2104 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
2105 if (bp->strm->workspace == NULL)
2115 vfree(bp->gunzip_buf);
2116 bp->gunzip_buf = NULL;
2119 printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for "
2120 "uncompression.\n", bp->dev->name);
2125 bnx2_gunzip_end(struct bnx2 *bp)
2127 kfree(bp->strm->workspace);
2132 if (bp->gunzip_buf) {
2133 vfree(bp->gunzip_buf);
2134 bp->gunzip_buf = NULL;
2139 bnx2_gunzip(struct bnx2 *bp, u8 *zbuf, int len, void **outbuf, int *outlen)
2143 /* check gzip header */
2144 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
2150 if (zbuf[3] & FNAME)
2151 while ((zbuf[n++] != 0) && (n < len));
2153 bp->strm->next_in = zbuf + n;
2154 bp->strm->avail_in = len - n;
2155 bp->strm->next_out = bp->gunzip_buf;
2156 bp->strm->avail_out = FW_BUF_SIZE;
2158 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
2162 rc = zlib_inflate(bp->strm, Z_FINISH);
2164 *outlen = FW_BUF_SIZE - bp->strm->avail_out;
2165 *outbuf = bp->gunzip_buf;
2167 if ((rc != Z_OK) && (rc != Z_STREAM_END))
2168 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
2169 bp->dev->name, bp->strm->msg);
2171 zlib_inflateEnd(bp->strm);
2173 if (rc == Z_STREAM_END)
2180 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2187 for (i = 0; i < rv2p_code_len; i += 8) {
2188 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2190 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2193 if (rv2p_proc == RV2P_PROC1) {
2194 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2195 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2198 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2199 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2203 /* Reset the processor, un-stall is done later. */
2204 if (rv2p_proc == RV2P_PROC1) {
2205 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2208 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2213 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2219 val = REG_RD_IND(bp, cpu_reg->mode);
2220 val |= cpu_reg->mode_value_halt;
2221 REG_WR_IND(bp, cpu_reg->mode, val);
2222 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2224 /* Load the Text area. */
2225 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2229 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2230 REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
2234 /* Load the Data area. */
2235 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2239 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2240 REG_WR_IND(bp, offset, fw->data[j]);
2244 /* Load the SBSS area. */
2245 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2249 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2250 REG_WR_IND(bp, offset, fw->sbss[j]);
2254 /* Load the BSS area. */
2255 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2259 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2260 REG_WR_IND(bp, offset, fw->bss[j]);
2264 /* Load the Read-Only area. */
2265 offset = cpu_reg->spad_base +
2266 (fw->rodata_addr - cpu_reg->mips_view_base);
2270 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2271 REG_WR_IND(bp, offset, fw->rodata[j]);
2275 /* Clear the pre-fetch instruction. */
2276 REG_WR_IND(bp, cpu_reg->inst, 0);
2277 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2279 /* Start the CPU. */
2280 val = REG_RD_IND(bp, cpu_reg->mode);
2281 val &= ~cpu_reg->mode_value_halt;
2282 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2283 REG_WR_IND(bp, cpu_reg->mode, val);
2287 bnx2_init_cpus(struct bnx2 *bp)
2289 struct cpu_reg cpu_reg;
2295 if ((rc = bnx2_gunzip_init(bp)) != 0)
2298 /* Initialize the RV2P processor. */
2299 rc = bnx2_gunzip(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), &text,
2304 load_rv2p_fw(bp, text, text_len, RV2P_PROC1);
2306 rc = bnx2_gunzip(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), &text,
2311 load_rv2p_fw(bp, text, text_len, RV2P_PROC2);
2313 /* Initialize the RX Processor. */
2314 cpu_reg.mode = BNX2_RXP_CPU_MODE;
2315 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2316 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2317 cpu_reg.state = BNX2_RXP_CPU_STATE;
2318 cpu_reg.state_value_clear = 0xffffff;
2319 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2320 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2321 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2322 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2323 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2324 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2325 cpu_reg.mips_view_base = 0x8000000;
2327 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2328 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2329 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2330 fw.start_addr = bnx2_RXP_b06FwStartAddr;
2332 fw.text_addr = bnx2_RXP_b06FwTextAddr;
2333 fw.text_len = bnx2_RXP_b06FwTextLen;
2336 rc = bnx2_gunzip(bp, bnx2_RXP_b06FwText, sizeof(bnx2_RXP_b06FwText),
2343 fw.data_addr = bnx2_RXP_b06FwDataAddr;
2344 fw.data_len = bnx2_RXP_b06FwDataLen;
2346 fw.data = bnx2_RXP_b06FwData;
2348 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2349 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2351 fw.sbss = bnx2_RXP_b06FwSbss;
2353 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2354 fw.bss_len = bnx2_RXP_b06FwBssLen;
2356 fw.bss = bnx2_RXP_b06FwBss;
2358 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2359 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2360 fw.rodata_index = 0;
2361 fw.rodata = bnx2_RXP_b06FwRodata;
2363 load_cpu_fw(bp, &cpu_reg, &fw);
2365 /* Initialize the TX Processor. */
2366 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2367 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2368 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2369 cpu_reg.state = BNX2_TXP_CPU_STATE;
2370 cpu_reg.state_value_clear = 0xffffff;
2371 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2372 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2373 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2374 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2375 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2376 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2377 cpu_reg.mips_view_base = 0x8000000;
2379 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2380 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2381 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2382 fw.start_addr = bnx2_TXP_b06FwStartAddr;
2384 fw.text_addr = bnx2_TXP_b06FwTextAddr;
2385 fw.text_len = bnx2_TXP_b06FwTextLen;
2388 rc = bnx2_gunzip(bp, bnx2_TXP_b06FwText, sizeof(bnx2_TXP_b06FwText),
2395 fw.data_addr = bnx2_TXP_b06FwDataAddr;
2396 fw.data_len = bnx2_TXP_b06FwDataLen;
2398 fw.data = bnx2_TXP_b06FwData;
2400 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2401 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2403 fw.sbss = bnx2_TXP_b06FwSbss;
2405 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2406 fw.bss_len = bnx2_TXP_b06FwBssLen;
2408 fw.bss = bnx2_TXP_b06FwBss;
2410 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2411 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2412 fw.rodata_index = 0;
2413 fw.rodata = bnx2_TXP_b06FwRodata;
2415 load_cpu_fw(bp, &cpu_reg, &fw);
2417 /* Initialize the TX Patch-up Processor. */
2418 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2419 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2420 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2421 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2422 cpu_reg.state_value_clear = 0xffffff;
2423 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2424 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2425 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2426 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2427 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2428 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2429 cpu_reg.mips_view_base = 0x8000000;
2431 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2432 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2433 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2434 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2436 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2437 fw.text_len = bnx2_TPAT_b06FwTextLen;
2440 rc = bnx2_gunzip(bp, bnx2_TPAT_b06FwText, sizeof(bnx2_TPAT_b06FwText),
2447 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2448 fw.data_len = bnx2_TPAT_b06FwDataLen;
2450 fw.data = bnx2_TPAT_b06FwData;
2452 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2453 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2455 fw.sbss = bnx2_TPAT_b06FwSbss;
2457 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2458 fw.bss_len = bnx2_TPAT_b06FwBssLen;
2460 fw.bss = bnx2_TPAT_b06FwBss;
2462 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2463 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2464 fw.rodata_index = 0;
2465 fw.rodata = bnx2_TPAT_b06FwRodata;
2467 load_cpu_fw(bp, &cpu_reg, &fw);
2469 /* Initialize the Completion Processor. */
2470 cpu_reg.mode = BNX2_COM_CPU_MODE;
2471 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2472 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2473 cpu_reg.state = BNX2_COM_CPU_STATE;
2474 cpu_reg.state_value_clear = 0xffffff;
2475 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2476 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2477 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2478 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2479 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2480 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2481 cpu_reg.mips_view_base = 0x8000000;
2483 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2484 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2485 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2486 fw.start_addr = bnx2_COM_b06FwStartAddr;
2488 fw.text_addr = bnx2_COM_b06FwTextAddr;
2489 fw.text_len = bnx2_COM_b06FwTextLen;
2492 rc = bnx2_gunzip(bp, bnx2_COM_b06FwText, sizeof(bnx2_COM_b06FwText),
2499 fw.data_addr = bnx2_COM_b06FwDataAddr;
2500 fw.data_len = bnx2_COM_b06FwDataLen;
2502 fw.data = bnx2_COM_b06FwData;
2504 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2505 fw.sbss_len = bnx2_COM_b06FwSbssLen;
2507 fw.sbss = bnx2_COM_b06FwSbss;
2509 fw.bss_addr = bnx2_COM_b06FwBssAddr;
2510 fw.bss_len = bnx2_COM_b06FwBssLen;
2512 fw.bss = bnx2_COM_b06FwBss;
2514 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2515 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2516 fw.rodata_index = 0;
2517 fw.rodata = bnx2_COM_b06FwRodata;
2519 load_cpu_fw(bp, &cpu_reg, &fw);
2522 bnx2_gunzip_end(bp);
2527 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2531 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2537 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2538 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2539 PCI_PM_CTRL_PME_STATUS);
2541 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2542 /* delay required during transition out of D3hot */
2545 val = REG_RD(bp, BNX2_EMAC_MODE);
2546 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2547 val &= ~BNX2_EMAC_MODE_MPKT;
2548 REG_WR(bp, BNX2_EMAC_MODE, val);
2550 val = REG_RD(bp, BNX2_RPM_CONFIG);
2551 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2552 REG_WR(bp, BNX2_RPM_CONFIG, val);
2563 autoneg = bp->autoneg;
2564 advertising = bp->advertising;
2566 bp->autoneg = AUTONEG_SPEED;
2567 bp->advertising = ADVERTISED_10baseT_Half |
2568 ADVERTISED_10baseT_Full |
2569 ADVERTISED_100baseT_Half |
2570 ADVERTISED_100baseT_Full |
2573 bnx2_setup_copper_phy(bp);
2575 bp->autoneg = autoneg;
2576 bp->advertising = advertising;
2578 bnx2_set_mac_addr(bp);
2580 val = REG_RD(bp, BNX2_EMAC_MODE);
2582 /* Enable port mode. */
2583 val &= ~BNX2_EMAC_MODE_PORT;
2584 val |= BNX2_EMAC_MODE_PORT_MII |
2585 BNX2_EMAC_MODE_MPKT_RCVD |
2586 BNX2_EMAC_MODE_ACPI_RCVD |
2587 BNX2_EMAC_MODE_MPKT;
2589 REG_WR(bp, BNX2_EMAC_MODE, val);
2591 /* receive all multicast */
2592 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2593 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2596 REG_WR(bp, BNX2_EMAC_RX_MODE,
2597 BNX2_EMAC_RX_MODE_SORT_MODE);
2599 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2600 BNX2_RPM_SORT_USER0_MC_EN;
2601 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2602 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2603 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2604 BNX2_RPM_SORT_USER0_ENA);
2606 /* Need to enable EMAC and RPM for WOL. */
2607 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2608 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2609 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2610 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2612 val = REG_RD(bp, BNX2_RPM_CONFIG);
2613 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2614 REG_WR(bp, BNX2_RPM_CONFIG, val);
2616 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2619 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2622 if (!(bp->flags & NO_WOL_FLAG))
2623 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
2625 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2626 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2627 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2636 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2638 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2641 /* No more memory access after this point until
2642 * device is brought back to D0.
2654 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2659 /* Request access to the flash interface. */
2660 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2661 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2662 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2663 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2669 if (j >= NVRAM_TIMEOUT_COUNT)
2676 bnx2_release_nvram_lock(struct bnx2 *bp)
2681 /* Relinquish nvram interface. */
2682 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2684 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2685 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2686 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2692 if (j >= NVRAM_TIMEOUT_COUNT)
2700 bnx2_enable_nvram_write(struct bnx2 *bp)
2704 val = REG_RD(bp, BNX2_MISC_CFG);
2705 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2707 if (!bp->flash_info->buffered) {
2710 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2711 REG_WR(bp, BNX2_NVM_COMMAND,
2712 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2714 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2717 val = REG_RD(bp, BNX2_NVM_COMMAND);
2718 if (val & BNX2_NVM_COMMAND_DONE)
2722 if (j >= NVRAM_TIMEOUT_COUNT)
2729 bnx2_disable_nvram_write(struct bnx2 *bp)
2733 val = REG_RD(bp, BNX2_MISC_CFG);
2734 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2739 bnx2_enable_nvram_access(struct bnx2 *bp)
2743 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2744 /* Enable both bits, even on read. */
2745 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2746 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2750 bnx2_disable_nvram_access(struct bnx2 *bp)
2754 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2755 /* Disable both bits, even after read. */
2756 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2757 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2758 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2762 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2767 if (bp->flash_info->buffered)
2768 /* Buffered flash, no erase needed */
2771 /* Build an erase command */
2772 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2773 BNX2_NVM_COMMAND_DOIT;
2775 /* Need to clear DONE bit separately. */
2776 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2778 /* Address of the NVRAM to read from. */
2779 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2781 /* Issue an erase command. */
2782 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2784 /* Wait for completion. */
2785 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2790 val = REG_RD(bp, BNX2_NVM_COMMAND);
2791 if (val & BNX2_NVM_COMMAND_DONE)
2795 if (j >= NVRAM_TIMEOUT_COUNT)
2802 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2807 /* Build the command word. */
2808 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2810 /* Calculate an offset of a buffered flash. */
2811 if (bp->flash_info->buffered) {
2812 offset = ((offset / bp->flash_info->page_size) <<
2813 bp->flash_info->page_bits) +
2814 (offset % bp->flash_info->page_size);
2817 /* Need to clear DONE bit separately. */
2818 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2820 /* Address of the NVRAM to read from. */
2821 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2823 /* Issue a read command. */
2824 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2826 /* Wait for completion. */
2827 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2832 val = REG_RD(bp, BNX2_NVM_COMMAND);
2833 if (val & BNX2_NVM_COMMAND_DONE) {
2834 val = REG_RD(bp, BNX2_NVM_READ);
2836 val = be32_to_cpu(val);
2837 memcpy(ret_val, &val, 4);
2841 if (j >= NVRAM_TIMEOUT_COUNT)
2849 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2854 /* Build the command word. */
2855 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2857 /* Calculate an offset of a buffered flash. */
2858 if (bp->flash_info->buffered) {
2859 offset = ((offset / bp->flash_info->page_size) <<
2860 bp->flash_info->page_bits) +
2861 (offset % bp->flash_info->page_size);
2864 /* Need to clear DONE bit separately. */
2865 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2867 memcpy(&val32, val, 4);
2868 val32 = cpu_to_be32(val32);
2870 /* Write the data. */
2871 REG_WR(bp, BNX2_NVM_WRITE, val32);
2873 /* Address of the NVRAM to write to. */
2874 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2876 /* Issue the write command. */
2877 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2879 /* Wait for completion. */
2880 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2883 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2886 if (j >= NVRAM_TIMEOUT_COUNT)
2893 bnx2_init_nvram(struct bnx2 *bp)
2896 int j, entry_count, rc;
2897 struct flash_spec *flash;
2899 /* Determine the selected interface. */
2900 val = REG_RD(bp, BNX2_NVM_CFG1);
2902 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2905 if (val & 0x40000000) {
2907 /* Flash interface has been reconfigured */
2908 for (j = 0, flash = &flash_table[0]; j < entry_count;
2910 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2911 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2912 bp->flash_info = flash;
2919 /* Not yet been reconfigured */
2921 if (val & (1 << 23))
2922 mask = FLASH_BACKUP_STRAP_MASK;
2924 mask = FLASH_STRAP_MASK;
2926 for (j = 0, flash = &flash_table[0]; j < entry_count;
2929 if ((val & mask) == (flash->strapping & mask)) {
2930 bp->flash_info = flash;
2932 /* Request access to the flash interface. */
2933 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2936 /* Enable access to flash interface */
2937 bnx2_enable_nvram_access(bp);
2939 /* Reconfigure the flash interface */
2940 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2941 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2942 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2943 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2945 /* Disable access to flash interface */
2946 bnx2_disable_nvram_access(bp);
2947 bnx2_release_nvram_lock(bp);
2952 } /* if (val & 0x40000000) */
2954 if (j == entry_count) {
2955 bp->flash_info = NULL;
2956 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
2960 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
2961 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
2963 bp->flash_size = val;
2965 bp->flash_size = bp->flash_info->total_size;
2971 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2975 u32 cmd_flags, offset32, len32, extra;
2980 /* Request access to the flash interface. */
2981 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2984 /* Enable access to flash interface */
2985 bnx2_enable_nvram_access(bp);
2998 pre_len = 4 - (offset & 3);
3000 if (pre_len >= len32) {
3002 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3003 BNX2_NVM_COMMAND_LAST;
3006 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3009 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3014 memcpy(ret_buf, buf + (offset & 3), pre_len);
3021 extra = 4 - (len32 & 3);
3022 len32 = (len32 + 4) & ~3;
3029 cmd_flags = BNX2_NVM_COMMAND_LAST;
3031 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3032 BNX2_NVM_COMMAND_LAST;
3034 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3036 memcpy(ret_buf, buf, 4 - extra);
3038 else if (len32 > 0) {
3041 /* Read the first word. */
3045 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3047 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3049 /* Advance to the next dword. */
3054 while (len32 > 4 && rc == 0) {
3055 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3057 /* Advance to the next dword. */
3066 cmd_flags = BNX2_NVM_COMMAND_LAST;
3067 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3069 memcpy(ret_buf, buf, 4 - extra);
3072 /* Disable access to flash interface */
3073 bnx2_disable_nvram_access(bp);
3075 bnx2_release_nvram_lock(bp);
3081 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3084 u32 written, offset32, len32;
3085 u8 *buf, start[4], end[4], *flash_buffer = NULL;
3087 int align_start, align_end;
3092 align_start = align_end = 0;
3094 if ((align_start = (offset32 & 3))) {
3096 len32 += align_start;
3097 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3102 if ((len32 > 4) || !align_start) {
3103 align_end = 4 - (len32 & 3);
3105 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
3112 if (align_start || align_end) {
3113 buf = kmalloc(len32, GFP_KERNEL);
3117 memcpy(buf, start, 4);
3120 memcpy(buf + len32 - 4, end, 4);
3122 memcpy(buf + align_start, data_buf, buf_size);
3125 if (bp->flash_info->buffered == 0) {
3126 flash_buffer = kmalloc(264, GFP_KERNEL);
3127 if (flash_buffer == NULL) {
3129 goto nvram_write_end;
3134 while ((written < len32) && (rc == 0)) {
3135 u32 page_start, page_end, data_start, data_end;
3136 u32 addr, cmd_flags;
3139 /* Find the page_start addr */
3140 page_start = offset32 + written;
3141 page_start -= (page_start % bp->flash_info->page_size);
3142 /* Find the page_end addr */
3143 page_end = page_start + bp->flash_info->page_size;
3144 /* Find the data_start addr */
3145 data_start = (written == 0) ? offset32 : page_start;
3146 /* Find the data_end addr */
3147 data_end = (page_end > offset32 + len32) ?
3148 (offset32 + len32) : page_end;
3150 /* Request access to the flash interface. */
3151 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3152 goto nvram_write_end;
3154 /* Enable access to flash interface */
3155 bnx2_enable_nvram_access(bp);
3157 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3158 if (bp->flash_info->buffered == 0) {
3161 /* Read the whole page into the buffer
3162 * (non-buffer flash only) */
3163 for (j = 0; j < bp->flash_info->page_size; j += 4) {
3164 if (j == (bp->flash_info->page_size - 4)) {
3165 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3167 rc = bnx2_nvram_read_dword(bp,
3173 goto nvram_write_end;
3179 /* Enable writes to flash interface (unlock write-protect) */
3180 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3181 goto nvram_write_end;
3183 /* Erase the page */
3184 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3185 goto nvram_write_end;
3187 /* Re-enable the write again for the actual write */
3188 bnx2_enable_nvram_write(bp);
3190 /* Loop to write back the buffer data from page_start to
3193 if (bp->flash_info->buffered == 0) {
3194 for (addr = page_start; addr < data_start;
3195 addr += 4, i += 4) {
3197 rc = bnx2_nvram_write_dword(bp, addr,
3198 &flash_buffer[i], cmd_flags);
3201 goto nvram_write_end;
3207 /* Loop to write the new data from data_start to data_end */
3208 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
3209 if ((addr == page_end - 4) ||
3210 ((bp->flash_info->buffered) &&
3211 (addr == data_end - 4))) {
3213 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3215 rc = bnx2_nvram_write_dword(bp, addr, buf,
3219 goto nvram_write_end;
3225 /* Loop to write back the buffer data from data_end
3227 if (bp->flash_info->buffered == 0) {
3228 for (addr = data_end; addr < page_end;
3229 addr += 4, i += 4) {
3231 if (addr == page_end-4) {
3232 cmd_flags = BNX2_NVM_COMMAND_LAST;
3234 rc = bnx2_nvram_write_dword(bp, addr,
3235 &flash_buffer[i], cmd_flags);
3238 goto nvram_write_end;
3244 /* Disable writes to flash interface (lock write-protect) */
3245 bnx2_disable_nvram_write(bp);
3247 /* Disable access to flash interface */
3248 bnx2_disable_nvram_access(bp);
3249 bnx2_release_nvram_lock(bp);
3251 /* Increment written */
3252 written += data_end - data_start;
3256 if (bp->flash_info->buffered == 0)
3257 kfree(flash_buffer);
3259 if (align_start || align_end)
3265 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3270 /* Wait for the current PCI transaction to complete before
3271 * issuing a reset. */
3272 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3273 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3274 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3275 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3276 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3277 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3280 /* Wait for the firmware to tell us it is ok to issue a reset. */
3281 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3283 /* Deposit a driver reset signature so the firmware knows that
3284 * this is a soft reset. */
3285 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3286 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3288 /* Do a dummy read to force the chip to complete all current transaction
3289 * before we issue a reset. */
3290 val = REG_RD(bp, BNX2_MISC_ID);
3292 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3293 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3294 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3297 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3299 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3300 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3303 /* Reset takes approximate 30 usec */
3304 for (i = 0; i < 10; i++) {
3305 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3306 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3307 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3313 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3314 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3315 printk(KERN_ERR PFX "Chip reset did not complete\n");
3319 /* Make sure byte swapping is properly configured. */
3320 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3321 if (val != 0x01020304) {
3322 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3326 /* Wait for the firmware to finish its initialization. */
3327 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3331 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3332 /* Adjust the voltage regular to two steps lower. The default
3333 * of this register is 0x0000000e. */
3334 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3336 /* Remove bad rbuf memory from the free pool. */
3337 rc = bnx2_alloc_bad_rbuf(bp);
3344 bnx2_init_chip(struct bnx2 *bp)
3349 /* Make sure the interrupt is not active. */
3350 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3352 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3353 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3355 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3357 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3358 DMA_READ_CHANS << 12 |
3359 DMA_WRITE_CHANS << 16;
3361 val |= (0x2 << 20) | (1 << 11);
3363 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3366 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3367 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3368 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3370 REG_WR(bp, BNX2_DMA_CONFIG, val);
3372 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3373 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3374 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3375 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3378 if (bp->flags & PCIX_FLAG) {
3381 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3383 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3384 val16 & ~PCI_X_CMD_ERO);
3387 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3388 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3389 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3390 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3392 /* Initialize context mapping and zero out the quick contexts. The
3393 * context block must have already been enabled. */
3394 bnx2_init_context(bp);
3396 if ((rc = bnx2_init_cpus(bp)) != 0)
3399 bnx2_init_nvram(bp);
3401 bnx2_set_mac_addr(bp);
3403 val = REG_RD(bp, BNX2_MQ_CONFIG);
3404 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3405 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3406 REG_WR(bp, BNX2_MQ_CONFIG, val);
3408 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3409 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3410 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3412 val = (BCM_PAGE_BITS - 8) << 24;
3413 REG_WR(bp, BNX2_RV2P_CONFIG, val);
3415 /* Configure page size. */
3416 val = REG_RD(bp, BNX2_TBDR_CONFIG);
3417 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3418 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3419 REG_WR(bp, BNX2_TBDR_CONFIG, val);
3421 val = bp->mac_addr[0] +
3422 (bp->mac_addr[1] << 8) +
3423 (bp->mac_addr[2] << 16) +
3425 (bp->mac_addr[4] << 8) +
3426 (bp->mac_addr[5] << 16);
3427 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3429 /* Program the MTU. Also include 4 bytes for CRC32. */
3430 val = bp->dev->mtu + ETH_HLEN + 4;
3431 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3432 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3433 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3435 bp->last_status_idx = 0;
3436 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3438 /* Set up how to generate a link change interrupt. */
3439 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3441 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3442 (u64) bp->status_blk_mapping & 0xffffffff);
3443 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3445 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3446 (u64) bp->stats_blk_mapping & 0xffffffff);
3447 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3448 (u64) bp->stats_blk_mapping >> 32);
3450 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3451 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3453 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3454 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3456 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3457 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3459 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3461 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3463 REG_WR(bp, BNX2_HC_COM_TICKS,
3464 (bp->com_ticks_int << 16) | bp->com_ticks);
3466 REG_WR(bp, BNX2_HC_CMD_TICKS,
3467 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3469 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3470 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3472 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3473 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3475 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3476 BNX2_HC_CONFIG_TX_TMR_MODE |
3477 BNX2_HC_CONFIG_COLLECT_STATS);
3480 /* Clear internal stats counters. */
3481 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3483 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3485 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3486 BNX2_PORT_FEATURE_ASF_ENABLED)
3487 bp->flags |= ASF_ENABLE_FLAG;
3489 /* Initialize the receive filter. */
3490 bnx2_set_rx_mode(bp->dev);
3492 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3495 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3496 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3500 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
3507 bnx2_init_tx_ring(struct bnx2 *bp)
3512 bp->tx_wake_thresh = bp->tx_ring_size / 2;
3514 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3516 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3517 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3522 bp->tx_prod_bseq = 0;
3524 val = BNX2_L2CTX_TYPE_TYPE_L2;
3525 val |= BNX2_L2CTX_TYPE_SIZE_L2;
3526 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3528 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3530 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3532 val = (u64) bp->tx_desc_mapping >> 32;
3533 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3535 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3536 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3540 bnx2_init_rx_ring(struct bnx2 *bp)
3544 u16 prod, ring_prod;
3547 /* 8 for CRC and VLAN */
3548 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3549 /* 8 for alignment */
3550 bp->rx_buf_size = bp->rx_buf_use_size + 8;
3552 ring_prod = prod = bp->rx_prod = 0;
3555 bp->rx_prod_bseq = 0;
3557 for (i = 0; i < bp->rx_max_ring; i++) {
3560 rxbd = &bp->rx_desc_ring[i][0];
3561 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
3562 rxbd->rx_bd_len = bp->rx_buf_use_size;
3563 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3565 if (i == (bp->rx_max_ring - 1))
3569 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
3570 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
3574 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3575 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3577 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3579 val = (u64) bp->rx_desc_mapping[0] >> 32;
3580 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3582 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
3583 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3585 for (i = 0; i < bp->rx_ring_size; i++) {
3586 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3589 prod = NEXT_RX_BD(prod);
3590 ring_prod = RX_RING_IDX(prod);
3594 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3596 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3600 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
3604 bp->rx_ring_size = size;
3606 while (size > MAX_RX_DESC_CNT) {
3607 size -= MAX_RX_DESC_CNT;
3610 /* round to next power of 2 */
3612 while ((max & num_rings) == 0)
3615 if (num_rings != max)
3618 bp->rx_max_ring = max;
3619 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
3623 bnx2_free_tx_skbs(struct bnx2 *bp)
3627 if (bp->tx_buf_ring == NULL)
3630 for (i = 0; i < TX_DESC_CNT; ) {
3631 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3632 struct sk_buff *skb = tx_buf->skb;
3640 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3641 skb_headlen(skb), PCI_DMA_TODEVICE);
3645 last = skb_shinfo(skb)->nr_frags;
3646 for (j = 0; j < last; j++) {
3647 tx_buf = &bp->tx_buf_ring[i + j + 1];
3648 pci_unmap_page(bp->pdev,
3649 pci_unmap_addr(tx_buf, mapping),
3650 skb_shinfo(skb)->frags[j].size,
3660 bnx2_free_rx_skbs(struct bnx2 *bp)
3664 if (bp->rx_buf_ring == NULL)
3667 for (i = 0; i < bp->rx_max_ring_idx; i++) {
3668 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3669 struct sk_buff *skb = rx_buf->skb;
3674 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3675 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3684 bnx2_free_skbs(struct bnx2 *bp)
3686 bnx2_free_tx_skbs(bp);
3687 bnx2_free_rx_skbs(bp);
3691 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3695 rc = bnx2_reset_chip(bp, reset_code);
3700 if ((rc = bnx2_init_chip(bp)) != 0)
3703 bnx2_init_tx_ring(bp);
3704 bnx2_init_rx_ring(bp);
3709 bnx2_init_nic(struct bnx2 *bp)
3713 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3722 bnx2_test_registers(struct bnx2 *bp)
3726 static const struct {
3732 { 0x006c, 0, 0x00000000, 0x0000003f },
3733 { 0x0090, 0, 0xffffffff, 0x00000000 },
3734 { 0x0094, 0, 0x00000000, 0x00000000 },
3736 { 0x0404, 0, 0x00003f00, 0x00000000 },
3737 { 0x0418, 0, 0x00000000, 0xffffffff },
3738 { 0x041c, 0, 0x00000000, 0xffffffff },
3739 { 0x0420, 0, 0x00000000, 0x80ffffff },
3740 { 0x0424, 0, 0x00000000, 0x00000000 },
3741 { 0x0428, 0, 0x00000000, 0x00000001 },
3742 { 0x0450, 0, 0x00000000, 0x0000ffff },
3743 { 0x0454, 0, 0x00000000, 0xffffffff },
3744 { 0x0458, 0, 0x00000000, 0xffffffff },
3746 { 0x0808, 0, 0x00000000, 0xffffffff },
3747 { 0x0854, 0, 0x00000000, 0xffffffff },
3748 { 0x0868, 0, 0x00000000, 0x77777777 },
3749 { 0x086c, 0, 0x00000000, 0x77777777 },
3750 { 0x0870, 0, 0x00000000, 0x77777777 },
3751 { 0x0874, 0, 0x00000000, 0x77777777 },
3753 { 0x0c00, 0, 0x00000000, 0x00000001 },
3754 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3755 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3757 { 0x1000, 0, 0x00000000, 0x00000001 },
3758 { 0x1004, 0, 0x00000000, 0x000f0001 },
3760 { 0x1408, 0, 0x01c00800, 0x00000000 },
3761 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3762 { 0x14a8, 0, 0x00000000, 0x000001ff },
3763 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
3764 { 0x14b0, 0, 0x00000002, 0x00000001 },
3765 { 0x14b8, 0, 0x00000000, 0x00000000 },
3766 { 0x14c0, 0, 0x00000000, 0x00000009 },
3767 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3768 { 0x14cc, 0, 0x00000000, 0x00000001 },
3769 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3771 { 0x1800, 0, 0x00000000, 0x00000001 },
3772 { 0x1804, 0, 0x00000000, 0x00000003 },
3774 { 0x2800, 0, 0x00000000, 0x00000001 },
3775 { 0x2804, 0, 0x00000000, 0x00003f01 },
3776 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3777 { 0x2810, 0, 0xffff0000, 0x00000000 },
3778 { 0x2814, 0, 0xffff0000, 0x00000000 },
3779 { 0x2818, 0, 0xffff0000, 0x00000000 },
3780 { 0x281c, 0, 0xffff0000, 0x00000000 },
3781 { 0x2834, 0, 0xffffffff, 0x00000000 },
3782 { 0x2840, 0, 0x00000000, 0xffffffff },
3783 { 0x2844, 0, 0x00000000, 0xffffffff },
3784 { 0x2848, 0, 0xffffffff, 0x00000000 },
3785 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3787 { 0x2c00, 0, 0x00000000, 0x00000011 },
3788 { 0x2c04, 0, 0x00000000, 0x00030007 },
3790 { 0x3c00, 0, 0x00000000, 0x00000001 },
3791 { 0x3c04, 0, 0x00000000, 0x00070000 },
3792 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3793 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3794 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3795 { 0x3c14, 0, 0x00000000, 0xffffffff },
3796 { 0x3c18, 0, 0x00000000, 0xffffffff },
3797 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3798 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3800 { 0x5004, 0, 0x00000000, 0x0000007f },
3801 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3802 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3804 { 0x5c00, 0, 0x00000000, 0x00000001 },
3805 { 0x5c04, 0, 0x00000000, 0x0003000f },
3806 { 0x5c08, 0, 0x00000003, 0x00000000 },
3807 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3808 { 0x5c10, 0, 0x00000000, 0xffffffff },
3809 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3810 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3811 { 0x5c88, 0, 0x00000000, 0x00077373 },
3812 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3814 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3815 { 0x680c, 0, 0xffffffff, 0x00000000 },
3816 { 0x6810, 0, 0xffffffff, 0x00000000 },
3817 { 0x6814, 0, 0xffffffff, 0x00000000 },
3818 { 0x6818, 0, 0xffffffff, 0x00000000 },
3819 { 0x681c, 0, 0xffffffff, 0x00000000 },
3820 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3821 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3822 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3823 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3824 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3825 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3826 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3827 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3828 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3829 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3830 { 0x684c, 0, 0xffffffff, 0x00000000 },
3831 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3832 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3833 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3834 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3835 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3836 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3838 { 0xffff, 0, 0x00000000, 0x00000000 },
3842 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3843 u32 offset, rw_mask, ro_mask, save_val, val;
3845 offset = (u32) reg_tbl[i].offset;
3846 rw_mask = reg_tbl[i].rw_mask;
3847 ro_mask = reg_tbl[i].ro_mask;
3849 save_val = readl(bp->regview + offset);
3851 writel(0, bp->regview + offset);
3853 val = readl(bp->regview + offset);
3854 if ((val & rw_mask) != 0) {
3858 if ((val & ro_mask) != (save_val & ro_mask)) {
3862 writel(0xffffffff, bp->regview + offset);
3864 val = readl(bp->regview + offset);
3865 if ((val & rw_mask) != rw_mask) {
3869 if ((val & ro_mask) != (save_val & ro_mask)) {
3873 writel(save_val, bp->regview + offset);
3877 writel(save_val, bp->regview + offset);
3885 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3887 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3888 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3891 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3894 for (offset = 0; offset < size; offset += 4) {
3896 REG_WR_IND(bp, start + offset, test_pattern[i]);
3898 if (REG_RD_IND(bp, start + offset) !=
3908 bnx2_test_memory(struct bnx2 *bp)
3912 static const struct {
3916 { 0x60000, 0x4000 },
3917 { 0xa0000, 0x3000 },
3918 { 0xe0000, 0x4000 },
3919 { 0x120000, 0x4000 },
3920 { 0x1a0000, 0x4000 },
3921 { 0x160000, 0x4000 },
3925 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3926 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3927 mem_tbl[i].len)) != 0) {
3935 #define BNX2_MAC_LOOPBACK 0
3936 #define BNX2_PHY_LOOPBACK 1
3939 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
3941 unsigned int pkt_size, num_pkts, i;
3942 struct sk_buff *skb, *rx_skb;
3943 unsigned char *packet;
3944 u16 rx_start_idx, rx_idx;
3947 struct sw_bd *rx_buf;
3948 struct l2_fhdr *rx_hdr;
3951 if (loopback_mode == BNX2_MAC_LOOPBACK) {
3952 bp->loopback = MAC_LOOPBACK;
3953 bnx2_set_mac_loopback(bp);
3955 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
3957 bnx2_set_phy_loopback(bp);
3963 skb = netdev_alloc_skb(bp->dev, pkt_size);
3966 packet = skb_put(skb, pkt_size);
3967 memcpy(packet, bp->mac_addr, 6);
3968 memset(packet + 6, 0x0, 8);
3969 for (i = 14; i < pkt_size; i++)
3970 packet[i] = (unsigned char) (i & 0xff);
3972 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3975 REG_WR(bp, BNX2_HC_COMMAND,
3976 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3978 REG_RD(bp, BNX2_HC_COMMAND);
3981 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3985 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
3987 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3988 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3989 txbd->tx_bd_mss_nbytes = pkt_size;
3990 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3993 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
3994 bp->tx_prod_bseq += pkt_size;
3996 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod);
3997 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4001 REG_WR(bp, BNX2_HC_COMMAND,
4002 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4004 REG_RD(bp, BNX2_HC_COMMAND);
4008 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4011 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
4012 goto loopback_test_done;
4015 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
4016 if (rx_idx != rx_start_idx + num_pkts) {
4017 goto loopback_test_done;
4020 rx_buf = &bp->rx_buf_ring[rx_start_idx];
4021 rx_skb = rx_buf->skb;
4023 rx_hdr = (struct l2_fhdr *) rx_skb->data;
4024 skb_reserve(rx_skb, bp->rx_offset);
4026 pci_dma_sync_single_for_cpu(bp->pdev,
4027 pci_unmap_addr(rx_buf, mapping),
4028 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4030 if (rx_hdr->l2_fhdr_status &
4031 (L2_FHDR_ERRORS_BAD_CRC |
4032 L2_FHDR_ERRORS_PHY_DECODE |
4033 L2_FHDR_ERRORS_ALIGNMENT |
4034 L2_FHDR_ERRORS_TOO_SHORT |
4035 L2_FHDR_ERRORS_GIANT_FRAME)) {
4037 goto loopback_test_done;
4040 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4041 goto loopback_test_done;
4044 for (i = 14; i < pkt_size; i++) {
4045 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4046 goto loopback_test_done;
4057 #define BNX2_MAC_LOOPBACK_FAILED 1
4058 #define BNX2_PHY_LOOPBACK_FAILED 2
4059 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
4060 BNX2_PHY_LOOPBACK_FAILED)
4063 bnx2_test_loopback(struct bnx2 *bp)
4067 if (!netif_running(bp->dev))
4068 return BNX2_LOOPBACK_FAILED;
4070 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
4071 spin_lock_bh(&bp->phy_lock);
4073 spin_unlock_bh(&bp->phy_lock);
4074 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
4075 rc |= BNX2_MAC_LOOPBACK_FAILED;
4076 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
4077 rc |= BNX2_PHY_LOOPBACK_FAILED;
4081 #define NVRAM_SIZE 0x200
4082 #define CRC32_RESIDUAL 0xdebb20e3
4085 bnx2_test_nvram(struct bnx2 *bp)
4087 u32 buf[NVRAM_SIZE / 4];
4088 u8 *data = (u8 *) buf;
4092 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4093 goto test_nvram_done;
4095 magic = be32_to_cpu(buf[0]);
4096 if (magic != 0x669955aa) {
4098 goto test_nvram_done;
4101 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4102 goto test_nvram_done;
4104 csum = ether_crc_le(0x100, data);
4105 if (csum != CRC32_RESIDUAL) {
4107 goto test_nvram_done;
4110 csum = ether_crc_le(0x100, data + 0x100);
4111 if (csum != CRC32_RESIDUAL) {
4120 bnx2_test_link(struct bnx2 *bp)
4124 spin_lock_bh(&bp->phy_lock);
4125 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4126 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4127 spin_unlock_bh(&bp->phy_lock);
4129 if (bmsr & BMSR_LSTATUS) {
4136 bnx2_test_intr(struct bnx2 *bp)
4141 if (!netif_running(bp->dev))
4144 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4146 /* This register is not touched during run-time. */
4147 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
4148 REG_RD(bp, BNX2_HC_COMMAND);
4150 for (i = 0; i < 10; i++) {
4151 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4157 msleep_interruptible(10);
4166 bnx2_timer(unsigned long data)
4168 struct bnx2 *bp = (struct bnx2 *) data;
4171 if (!netif_running(bp->dev))
4174 if (atomic_read(&bp->intr_sem) != 0)
4175 goto bnx2_restart_timer;
4177 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
4178 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
4180 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4182 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4183 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
4185 spin_lock(&bp->phy_lock);
4186 if (bp->serdes_an_pending) {
4187 bp->serdes_an_pending--;
4189 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4192 bp->current_interval = bp->timer_interval;
4194 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4196 if (bmcr & BMCR_ANENABLE) {
4199 bnx2_write_phy(bp, 0x1c, 0x7c00);
4200 bnx2_read_phy(bp, 0x1c, &phy1);
4202 bnx2_write_phy(bp, 0x17, 0x0f01);
4203 bnx2_read_phy(bp, 0x15, &phy2);
4204 bnx2_write_phy(bp, 0x17, 0x0f01);
4205 bnx2_read_phy(bp, 0x15, &phy2);
4207 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4208 !(phy2 & 0x20)) { /* no CONFIG */
4210 bmcr &= ~BMCR_ANENABLE;
4211 bmcr |= BMCR_SPEED1000 |
4213 bnx2_write_phy(bp, MII_BMCR, bmcr);
4215 PHY_PARALLEL_DETECT_FLAG;
4219 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4220 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4223 bnx2_write_phy(bp, 0x17, 0x0f01);
4224 bnx2_read_phy(bp, 0x15, &phy2);
4228 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4229 bmcr |= BMCR_ANENABLE;
4230 bnx2_write_phy(bp, MII_BMCR, bmcr);
4232 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4237 bp->current_interval = bp->timer_interval;
4239 spin_unlock(&bp->phy_lock);
4243 mod_timer(&bp->timer, jiffies + bp->current_interval);
4246 /* Called with rtnl_lock */
4248 bnx2_open(struct net_device *dev)
4250 struct bnx2 *bp = netdev_priv(dev);
4253 bnx2_set_power_state(bp, PCI_D0);
4254 bnx2_disable_int(bp);
4256 rc = bnx2_alloc_mem(bp);
4260 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4261 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4264 if (pci_enable_msi(bp->pdev) == 0) {
4265 bp->flags |= USING_MSI_FLAG;
4266 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4270 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4271 IRQF_SHARED, dev->name, dev);
4275 rc = request_irq(bp->pdev->irq, bnx2_interrupt, IRQF_SHARED,
4283 rc = bnx2_init_nic(bp);
4286 free_irq(bp->pdev->irq, dev);
4287 if (bp->flags & USING_MSI_FLAG) {
4288 pci_disable_msi(bp->pdev);
4289 bp->flags &= ~USING_MSI_FLAG;
4296 mod_timer(&bp->timer, jiffies + bp->current_interval);
4298 atomic_set(&bp->intr_sem, 0);
4300 bnx2_enable_int(bp);
4302 if (bp->flags & USING_MSI_FLAG) {
4303 /* Test MSI to make sure it is working
4304 * If MSI test fails, go back to INTx mode
4306 if (bnx2_test_intr(bp) != 0) {
4307 printk(KERN_WARNING PFX "%s: No interrupt was generated"
4308 " using MSI, switching to INTx mode. Please"
4309 " report this failure to the PCI maintainer"
4310 " and include system chipset information.\n",
4313 bnx2_disable_int(bp);
4314 free_irq(bp->pdev->irq, dev);
4315 pci_disable_msi(bp->pdev);
4316 bp->flags &= ~USING_MSI_FLAG;
4318 rc = bnx2_init_nic(bp);
4321 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4322 IRQF_SHARED, dev->name, dev);
4327 del_timer_sync(&bp->timer);
4330 bnx2_enable_int(bp);
4333 if (bp->flags & USING_MSI_FLAG) {
4334 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4337 netif_start_queue(dev);
4343 bnx2_reset_task(void *data)
4345 struct bnx2 *bp = data;
4347 if (!netif_running(bp->dev))
4350 bp->in_reset_task = 1;
4351 bnx2_netif_stop(bp);
4355 atomic_set(&bp->intr_sem, 1);
4356 bnx2_netif_start(bp);
4357 bp->in_reset_task = 0;
4361 bnx2_tx_timeout(struct net_device *dev)
4363 struct bnx2 *bp = netdev_priv(dev);
4365 /* This allows the netif to be shutdown gracefully before resetting */
4366 schedule_work(&bp->reset_task);
4370 /* Called with rtnl_lock */
4372 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4374 struct bnx2 *bp = netdev_priv(dev);
4376 bnx2_netif_stop(bp);
4379 bnx2_set_rx_mode(dev);
4381 bnx2_netif_start(bp);
4384 /* Called with rtnl_lock */
4386 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4388 struct bnx2 *bp = netdev_priv(dev);
4390 bnx2_netif_stop(bp);
4393 bp->vlgrp->vlan_devices[vid] = NULL;
4394 bnx2_set_rx_mode(dev);
4396 bnx2_netif_start(bp);
4400 /* Called with netif_tx_lock.
4401 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
4402 * netif_wake_queue().
4405 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4407 struct bnx2 *bp = netdev_priv(dev);
4410 struct sw_bd *tx_buf;
4411 u32 len, vlan_tag_flags, last_frag, mss;
4412 u16 prod, ring_prod;
4415 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4416 netif_stop_queue(dev);
4417 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4420 return NETDEV_TX_BUSY;
4422 len = skb_headlen(skb);
4424 ring_prod = TX_RING_IDX(prod);
4427 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4428 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4431 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4433 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4436 if ((mss = skb_shinfo(skb)->gso_size) &&
4437 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4438 u32 tcp_opt_len, ip_tcp_len;
4440 if (skb_header_cloned(skb) &&
4441 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4443 return NETDEV_TX_OK;
4446 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4447 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4450 if (skb->h.th->doff > 5) {
4451 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4453 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4455 skb->nh.iph->check = 0;
4456 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4458 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4462 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4463 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4464 (tcp_opt_len >> 2)) << 8;
4473 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4475 tx_buf = &bp->tx_buf_ring[ring_prod];
4477 pci_unmap_addr_set(tx_buf, mapping, mapping);
4479 txbd = &bp->tx_desc_ring[ring_prod];
4481 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4482 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4483 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4484 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4486 last_frag = skb_shinfo(skb)->nr_frags;
4488 for (i = 0; i < last_frag; i++) {
4489 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4491 prod = NEXT_TX_BD(prod);
4492 ring_prod = TX_RING_IDX(prod);
4493 txbd = &bp->tx_desc_ring[ring_prod];
4496 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4497 len, PCI_DMA_TODEVICE);
4498 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4501 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4502 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4503 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4504 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4507 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4509 prod = NEXT_TX_BD(prod);
4510 bp->tx_prod_bseq += skb->len;
4512 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4513 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4518 dev->trans_start = jiffies;
4520 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4521 netif_stop_queue(dev);
4522 if (bnx2_tx_avail(bp) > bp->tx_wake_thresh)
4523 netif_wake_queue(dev);
4526 return NETDEV_TX_OK;
4529 /* Called with rtnl_lock */
4531 bnx2_close(struct net_device *dev)
4533 struct bnx2 *bp = netdev_priv(dev);
4536 /* Calling flush_scheduled_work() may deadlock because
4537 * linkwatch_event() may be on the workqueue and it will try to get
4538 * the rtnl_lock which we are holding.
4540 while (bp->in_reset_task)
4543 bnx2_netif_stop(bp);
4544 del_timer_sync(&bp->timer);
4545 if (bp->flags & NO_WOL_FLAG)
4546 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
4548 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4550 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4551 bnx2_reset_chip(bp, reset_code);
4552 free_irq(bp->pdev->irq, dev);
4553 if (bp->flags & USING_MSI_FLAG) {
4554 pci_disable_msi(bp->pdev);
4555 bp->flags &= ~USING_MSI_FLAG;
4560 netif_carrier_off(bp->dev);
4561 bnx2_set_power_state(bp, PCI_D3hot);
4565 #define GET_NET_STATS64(ctr) \
4566 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4567 (unsigned long) (ctr##_lo)
4569 #define GET_NET_STATS32(ctr) \
4572 #if (BITS_PER_LONG == 64)
4573 #define GET_NET_STATS GET_NET_STATS64
4575 #define GET_NET_STATS GET_NET_STATS32
4578 static struct net_device_stats *
4579 bnx2_get_stats(struct net_device *dev)
4581 struct bnx2 *bp = netdev_priv(dev);
4582 struct statistics_block *stats_blk = bp->stats_blk;
4583 struct net_device_stats *net_stats = &bp->net_stats;
4585 if (bp->stats_blk == NULL) {
4588 net_stats->rx_packets =
4589 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4590 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4591 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4593 net_stats->tx_packets =
4594 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4595 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4596 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4598 net_stats->rx_bytes =
4599 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4601 net_stats->tx_bytes =
4602 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4604 net_stats->multicast =
4605 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4607 net_stats->collisions =
4608 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4610 net_stats->rx_length_errors =
4611 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4612 stats_blk->stat_EtherStatsOverrsizePkts);
4614 net_stats->rx_over_errors =
4615 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4617 net_stats->rx_frame_errors =
4618 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4620 net_stats->rx_crc_errors =
4621 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4623 net_stats->rx_errors = net_stats->rx_length_errors +
4624 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4625 net_stats->rx_crc_errors;
4627 net_stats->tx_aborted_errors =
4628 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4629 stats_blk->stat_Dot3StatsLateCollisions);
4631 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4632 (CHIP_ID(bp) == CHIP_ID_5708_A0))
4633 net_stats->tx_carrier_errors = 0;
4635 net_stats->tx_carrier_errors =
4637 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4640 net_stats->tx_errors =
4642 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4644 net_stats->tx_aborted_errors +
4645 net_stats->tx_carrier_errors;
4647 net_stats->rx_missed_errors =
4648 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
4649 stats_blk->stat_FwRxDrop);
4654 /* All ethtool functions called with rtnl_lock */
4657 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4659 struct bnx2 *bp = netdev_priv(dev);
4661 cmd->supported = SUPPORTED_Autoneg;
4662 if (bp->phy_flags & PHY_SERDES_FLAG) {
4663 cmd->supported |= SUPPORTED_1000baseT_Full |
4666 cmd->port = PORT_FIBRE;
4669 cmd->supported |= SUPPORTED_10baseT_Half |
4670 SUPPORTED_10baseT_Full |
4671 SUPPORTED_100baseT_Half |
4672 SUPPORTED_100baseT_Full |
4673 SUPPORTED_1000baseT_Full |
4676 cmd->port = PORT_TP;
4679 cmd->advertising = bp->advertising;
4681 if (bp->autoneg & AUTONEG_SPEED) {
4682 cmd->autoneg = AUTONEG_ENABLE;
4685 cmd->autoneg = AUTONEG_DISABLE;
4688 if (netif_carrier_ok(dev)) {
4689 cmd->speed = bp->line_speed;
4690 cmd->duplex = bp->duplex;
4697 cmd->transceiver = XCVR_INTERNAL;
4698 cmd->phy_address = bp->phy_addr;
4704 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4706 struct bnx2 *bp = netdev_priv(dev);
4707 u8 autoneg = bp->autoneg;
4708 u8 req_duplex = bp->req_duplex;
4709 u16 req_line_speed = bp->req_line_speed;
4710 u32 advertising = bp->advertising;
4712 if (cmd->autoneg == AUTONEG_ENABLE) {
4713 autoneg |= AUTONEG_SPEED;
4715 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4717 /* allow advertising 1 speed */
4718 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4719 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4720 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4721 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4723 if (bp->phy_flags & PHY_SERDES_FLAG)
4726 advertising = cmd->advertising;
4729 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4730 advertising = cmd->advertising;
4732 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4736 if (bp->phy_flags & PHY_SERDES_FLAG) {
4737 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4740 advertising = ETHTOOL_ALL_COPPER_SPEED;
4743 advertising |= ADVERTISED_Autoneg;
4746 if (bp->phy_flags & PHY_SERDES_FLAG) {
4747 if ((cmd->speed != SPEED_1000) ||
4748 (cmd->duplex != DUPLEX_FULL)) {
4752 else if (cmd->speed == SPEED_1000) {
4755 autoneg &= ~AUTONEG_SPEED;
4756 req_line_speed = cmd->speed;
4757 req_duplex = cmd->duplex;
4761 bp->autoneg = autoneg;
4762 bp->advertising = advertising;
4763 bp->req_line_speed = req_line_speed;
4764 bp->req_duplex = req_duplex;
4766 spin_lock_bh(&bp->phy_lock);
4770 spin_unlock_bh(&bp->phy_lock);
4776 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4778 struct bnx2 *bp = netdev_priv(dev);
4780 strcpy(info->driver, DRV_MODULE_NAME);
4781 strcpy(info->version, DRV_MODULE_VERSION);
4782 strcpy(info->bus_info, pci_name(bp->pdev));
4783 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4784 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4785 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4786 info->fw_version[1] = info->fw_version[3] = '.';
4787 info->fw_version[5] = 0;
4790 #define BNX2_REGDUMP_LEN (32 * 1024)
4793 bnx2_get_regs_len(struct net_device *dev)
4795 return BNX2_REGDUMP_LEN;
4799 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
4801 u32 *p = _p, i, offset;
4803 struct bnx2 *bp = netdev_priv(dev);
4804 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
4805 0x0800, 0x0880, 0x0c00, 0x0c10,
4806 0x0c30, 0x0d08, 0x1000, 0x101c,
4807 0x1040, 0x1048, 0x1080, 0x10a4,
4808 0x1400, 0x1490, 0x1498, 0x14f0,
4809 0x1500, 0x155c, 0x1580, 0x15dc,
4810 0x1600, 0x1658, 0x1680, 0x16d8,
4811 0x1800, 0x1820, 0x1840, 0x1854,
4812 0x1880, 0x1894, 0x1900, 0x1984,
4813 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
4814 0x1c80, 0x1c94, 0x1d00, 0x1d84,
4815 0x2000, 0x2030, 0x23c0, 0x2400,
4816 0x2800, 0x2820, 0x2830, 0x2850,
4817 0x2b40, 0x2c10, 0x2fc0, 0x3058,
4818 0x3c00, 0x3c94, 0x4000, 0x4010,
4819 0x4080, 0x4090, 0x43c0, 0x4458,
4820 0x4c00, 0x4c18, 0x4c40, 0x4c54,
4821 0x4fc0, 0x5010, 0x53c0, 0x5444,
4822 0x5c00, 0x5c18, 0x5c80, 0x5c90,
4823 0x5fc0, 0x6000, 0x6400, 0x6428,
4824 0x6800, 0x6848, 0x684c, 0x6860,
4825 0x6888, 0x6910, 0x8000 };
4829 memset(p, 0, BNX2_REGDUMP_LEN);
4831 if (!netif_running(bp->dev))
4835 offset = reg_boundaries[0];
4837 while (offset < BNX2_REGDUMP_LEN) {
4838 *p++ = REG_RD(bp, offset);
4840 if (offset == reg_boundaries[i + 1]) {
4841 offset = reg_boundaries[i + 2];
4842 p = (u32 *) (orig_p + offset);
4849 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4851 struct bnx2 *bp = netdev_priv(dev);
4853 if (bp->flags & NO_WOL_FLAG) {
4858 wol->supported = WAKE_MAGIC;
4860 wol->wolopts = WAKE_MAGIC;
4864 memset(&wol->sopass, 0, sizeof(wol->sopass));
4868 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4870 struct bnx2 *bp = netdev_priv(dev);
4872 if (wol->wolopts & ~WAKE_MAGIC)
4875 if (wol->wolopts & WAKE_MAGIC) {
4876 if (bp->flags & NO_WOL_FLAG)
4888 bnx2_nway_reset(struct net_device *dev)
4890 struct bnx2 *bp = netdev_priv(dev);
4893 if (!(bp->autoneg & AUTONEG_SPEED)) {
4897 spin_lock_bh(&bp->phy_lock);
4899 /* Force a link down visible on the other side */
4900 if (bp->phy_flags & PHY_SERDES_FLAG) {
4901 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4902 spin_unlock_bh(&bp->phy_lock);
4906 spin_lock_bh(&bp->phy_lock);
4907 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4908 bp->current_interval = SERDES_AN_TIMEOUT;
4909 bp->serdes_an_pending = 1;
4910 mod_timer(&bp->timer, jiffies + bp->current_interval);
4914 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4915 bmcr &= ~BMCR_LOOPBACK;
4916 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4918 spin_unlock_bh(&bp->phy_lock);
4924 bnx2_get_eeprom_len(struct net_device *dev)
4926 struct bnx2 *bp = netdev_priv(dev);
4928 if (bp->flash_info == NULL)
4931 return (int) bp->flash_size;
4935 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4938 struct bnx2 *bp = netdev_priv(dev);
4941 /* parameters already validated in ethtool_get_eeprom */
4943 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4949 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4952 struct bnx2 *bp = netdev_priv(dev);
4955 /* parameters already validated in ethtool_set_eeprom */
4957 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4963 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4965 struct bnx2 *bp = netdev_priv(dev);
4967 memset(coal, 0, sizeof(struct ethtool_coalesce));
4969 coal->rx_coalesce_usecs = bp->rx_ticks;
4970 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4971 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4972 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4974 coal->tx_coalesce_usecs = bp->tx_ticks;
4975 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4976 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4977 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4979 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4985 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4987 struct bnx2 *bp = netdev_priv(dev);
4989 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4990 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4992 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4993 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4995 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4996 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4998 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4999 if (bp->rx_quick_cons_trip_int > 0xff)
5000 bp->rx_quick_cons_trip_int = 0xff;
5002 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
5003 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
5005 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
5006 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
5008 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
5009 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
5011 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
5012 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
5015 bp->stats_ticks = coal->stats_block_coalesce_usecs;
5016 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
5017 bp->stats_ticks &= 0xffff00;
5019 if (netif_running(bp->dev)) {
5020 bnx2_netif_stop(bp);
5022 bnx2_netif_start(bp);
5029 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5031 struct bnx2 *bp = netdev_priv(dev);
5033 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
5034 ering->rx_mini_max_pending = 0;
5035 ering->rx_jumbo_max_pending = 0;
5037 ering->rx_pending = bp->rx_ring_size;
5038 ering->rx_mini_pending = 0;
5039 ering->rx_jumbo_pending = 0;
5041 ering->tx_max_pending = MAX_TX_DESC_CNT;
5042 ering->tx_pending = bp->tx_ring_size;
5046 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5048 struct bnx2 *bp = netdev_priv(dev);
5050 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
5051 (ering->tx_pending > MAX_TX_DESC_CNT) ||
5052 (ering->tx_pending <= MAX_SKB_FRAGS)) {
5056 if (netif_running(bp->dev)) {
5057 bnx2_netif_stop(bp);
5058 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5063 bnx2_set_rx_ring_size(bp, ering->rx_pending);
5064 bp->tx_ring_size = ering->tx_pending;
5066 if (netif_running(bp->dev)) {
5069 rc = bnx2_alloc_mem(bp);
5073 bnx2_netif_start(bp);
5080 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5082 struct bnx2 *bp = netdev_priv(dev);
5084 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
5085 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
5086 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
5090 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5092 struct bnx2 *bp = netdev_priv(dev);
5094 bp->req_flow_ctrl = 0;
5095 if (epause->rx_pause)
5096 bp->req_flow_ctrl |= FLOW_CTRL_RX;
5097 if (epause->tx_pause)
5098 bp->req_flow_ctrl |= FLOW_CTRL_TX;
5100 if (epause->autoneg) {
5101 bp->autoneg |= AUTONEG_FLOW_CTRL;
5104 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
5107 spin_lock_bh(&bp->phy_lock);
5111 spin_unlock_bh(&bp->phy_lock);
5117 bnx2_get_rx_csum(struct net_device *dev)
5119 struct bnx2 *bp = netdev_priv(dev);
5125 bnx2_set_rx_csum(struct net_device *dev, u32 data)
5127 struct bnx2 *bp = netdev_priv(dev);
5134 bnx2_set_tso(struct net_device *dev, u32 data)
5137 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5139 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
5143 #define BNX2_NUM_STATS 46
5146 char string[ETH_GSTRING_LEN];
5147 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5149 { "rx_error_bytes" },
5151 { "tx_error_bytes" },
5152 { "rx_ucast_packets" },
5153 { "rx_mcast_packets" },
5154 { "rx_bcast_packets" },
5155 { "tx_ucast_packets" },
5156 { "tx_mcast_packets" },
5157 { "tx_bcast_packets" },
5158 { "tx_mac_errors" },
5159 { "tx_carrier_errors" },
5160 { "rx_crc_errors" },
5161 { "rx_align_errors" },
5162 { "tx_single_collisions" },
5163 { "tx_multi_collisions" },
5165 { "tx_excess_collisions" },
5166 { "tx_late_collisions" },
5167 { "tx_total_collisions" },
5170 { "rx_undersize_packets" },
5171 { "rx_oversize_packets" },
5172 { "rx_64_byte_packets" },
5173 { "rx_65_to_127_byte_packets" },
5174 { "rx_128_to_255_byte_packets" },
5175 { "rx_256_to_511_byte_packets" },
5176 { "rx_512_to_1023_byte_packets" },
5177 { "rx_1024_to_1522_byte_packets" },
5178 { "rx_1523_to_9022_byte_packets" },
5179 { "tx_64_byte_packets" },
5180 { "tx_65_to_127_byte_packets" },
5181 { "tx_128_to_255_byte_packets" },
5182 { "tx_256_to_511_byte_packets" },
5183 { "tx_512_to_1023_byte_packets" },
5184 { "tx_1024_to_1522_byte_packets" },
5185 { "tx_1523_to_9022_byte_packets" },
5186 { "rx_xon_frames" },
5187 { "rx_xoff_frames" },
5188 { "tx_xon_frames" },
5189 { "tx_xoff_frames" },
5190 { "rx_mac_ctrl_frames" },
5191 { "rx_filtered_packets" },
5193 { "rx_fw_discards" },
5196 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5198 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5199 STATS_OFFSET32(stat_IfHCInOctets_hi),
5200 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5201 STATS_OFFSET32(stat_IfHCOutOctets_hi),
5202 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5203 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5204 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5205 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5206 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5207 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5208 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5209 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5210 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5211 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5212 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5213 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5214 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5215 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5216 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5217 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5218 STATS_OFFSET32(stat_EtherStatsCollisions),
5219 STATS_OFFSET32(stat_EtherStatsFragments),
5220 STATS_OFFSET32(stat_EtherStatsJabbers),
5221 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5222 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5223 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5224 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5225 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5226 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5227 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5228 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5229 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5230 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5231 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5232 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5233 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5234 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5235 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5236 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5237 STATS_OFFSET32(stat_XonPauseFramesReceived),
5238 STATS_OFFSET32(stat_XoffPauseFramesReceived),
5239 STATS_OFFSET32(stat_OutXonSent),
5240 STATS_OFFSET32(stat_OutXoffSent),
5241 STATS_OFFSET32(stat_MacControlFramesReceived),
5242 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5243 STATS_OFFSET32(stat_IfInMBUFDiscards),
5244 STATS_OFFSET32(stat_FwRxDrop),
5247 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5248 * skipped because of errata.
5250 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
5251 8,0,8,8,8,8,8,8,8,8,
5252 4,0,4,4,4,4,4,4,4,4,
5253 4,4,4,4,4,4,4,4,4,4,
5254 4,4,4,4,4,4,4,4,4,4,
5258 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5259 8,0,8,8,8,8,8,8,8,8,
5260 4,4,4,4,4,4,4,4,4,4,
5261 4,4,4,4,4,4,4,4,4,4,
5262 4,4,4,4,4,4,4,4,4,4,
5266 #define BNX2_NUM_TESTS 6
5269 char string[ETH_GSTRING_LEN];
5270 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5271 { "register_test (offline)" },
5272 { "memory_test (offline)" },
5273 { "loopback_test (offline)" },
5274 { "nvram_test (online)" },
5275 { "interrupt_test (online)" },
5276 { "link_test (online)" },
5280 bnx2_self_test_count(struct net_device *dev)
5282 return BNX2_NUM_TESTS;
5286 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5288 struct bnx2 *bp = netdev_priv(dev);
5290 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5291 if (etest->flags & ETH_TEST_FL_OFFLINE) {
5292 bnx2_netif_stop(bp);
5293 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5296 if (bnx2_test_registers(bp) != 0) {
5298 etest->flags |= ETH_TEST_FL_FAILED;
5300 if (bnx2_test_memory(bp) != 0) {
5302 etest->flags |= ETH_TEST_FL_FAILED;
5304 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
5305 etest->flags |= ETH_TEST_FL_FAILED;
5307 if (!netif_running(bp->dev)) {
5308 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5312 bnx2_netif_start(bp);
5315 /* wait for link up */
5316 msleep_interruptible(3000);
5317 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5318 msleep_interruptible(4000);
5321 if (bnx2_test_nvram(bp) != 0) {
5323 etest->flags |= ETH_TEST_FL_FAILED;
5325 if (bnx2_test_intr(bp) != 0) {
5327 etest->flags |= ETH_TEST_FL_FAILED;
5330 if (bnx2_test_link(bp) != 0) {
5332 etest->flags |= ETH_TEST_FL_FAILED;
5338 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5340 switch (stringset) {
5342 memcpy(buf, bnx2_stats_str_arr,
5343 sizeof(bnx2_stats_str_arr));
5346 memcpy(buf, bnx2_tests_str_arr,
5347 sizeof(bnx2_tests_str_arr));
5353 bnx2_get_stats_count(struct net_device *dev)
5355 return BNX2_NUM_STATS;
5359 bnx2_get_ethtool_stats(struct net_device *dev,
5360 struct ethtool_stats *stats, u64 *buf)
5362 struct bnx2 *bp = netdev_priv(dev);
5364 u32 *hw_stats = (u32 *) bp->stats_blk;
5365 u8 *stats_len_arr = NULL;
5367 if (hw_stats == NULL) {
5368 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5372 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5373 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5374 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5375 (CHIP_ID(bp) == CHIP_ID_5708_A0))
5376 stats_len_arr = bnx2_5706_stats_len_arr;
5378 stats_len_arr = bnx2_5708_stats_len_arr;
5380 for (i = 0; i < BNX2_NUM_STATS; i++) {
5381 if (stats_len_arr[i] == 0) {
5382 /* skip this counter */
5386 if (stats_len_arr[i] == 4) {
5387 /* 4-byte counter */
5389 *(hw_stats + bnx2_stats_offset_arr[i]);
5392 /* 8-byte counter */
5393 buf[i] = (((u64) *(hw_stats +
5394 bnx2_stats_offset_arr[i])) << 32) +
5395 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5400 bnx2_phys_id(struct net_device *dev, u32 data)
5402 struct bnx2 *bp = netdev_priv(dev);
5409 save = REG_RD(bp, BNX2_MISC_CFG);
5410 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5412 for (i = 0; i < (data * 2); i++) {
5414 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5417 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5418 BNX2_EMAC_LED_1000MB_OVERRIDE |
5419 BNX2_EMAC_LED_100MB_OVERRIDE |
5420 BNX2_EMAC_LED_10MB_OVERRIDE |
5421 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5422 BNX2_EMAC_LED_TRAFFIC);
5424 msleep_interruptible(500);
5425 if (signal_pending(current))
5428 REG_WR(bp, BNX2_EMAC_LED, 0);
5429 REG_WR(bp, BNX2_MISC_CFG, save);
5433 static const struct ethtool_ops bnx2_ethtool_ops = {
5434 .get_settings = bnx2_get_settings,
5435 .set_settings = bnx2_set_settings,
5436 .get_drvinfo = bnx2_get_drvinfo,
5437 .get_regs_len = bnx2_get_regs_len,
5438 .get_regs = bnx2_get_regs,
5439 .get_wol = bnx2_get_wol,
5440 .set_wol = bnx2_set_wol,
5441 .nway_reset = bnx2_nway_reset,
5442 .get_link = ethtool_op_get_link,
5443 .get_eeprom_len = bnx2_get_eeprom_len,
5444 .get_eeprom = bnx2_get_eeprom,
5445 .set_eeprom = bnx2_set_eeprom,
5446 .get_coalesce = bnx2_get_coalesce,
5447 .set_coalesce = bnx2_set_coalesce,
5448 .get_ringparam = bnx2_get_ringparam,
5449 .set_ringparam = bnx2_set_ringparam,
5450 .get_pauseparam = bnx2_get_pauseparam,
5451 .set_pauseparam = bnx2_set_pauseparam,
5452 .get_rx_csum = bnx2_get_rx_csum,
5453 .set_rx_csum = bnx2_set_rx_csum,
5454 .get_tx_csum = ethtool_op_get_tx_csum,
5455 .set_tx_csum = ethtool_op_set_tx_csum,
5456 .get_sg = ethtool_op_get_sg,
5457 .set_sg = ethtool_op_set_sg,
5459 .get_tso = ethtool_op_get_tso,
5460 .set_tso = bnx2_set_tso,
5462 .self_test_count = bnx2_self_test_count,
5463 .self_test = bnx2_self_test,
5464 .get_strings = bnx2_get_strings,
5465 .phys_id = bnx2_phys_id,
5466 .get_stats_count = bnx2_get_stats_count,
5467 .get_ethtool_stats = bnx2_get_ethtool_stats,
5468 .get_perm_addr = ethtool_op_get_perm_addr,
5471 /* Called with rtnl_lock */
5473 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5475 struct mii_ioctl_data *data = if_mii(ifr);
5476 struct bnx2 *bp = netdev_priv(dev);
5481 data->phy_id = bp->phy_addr;
5487 spin_lock_bh(&bp->phy_lock);
5488 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5489 spin_unlock_bh(&bp->phy_lock);
5491 data->val_out = mii_regval;
5497 if (!capable(CAP_NET_ADMIN))
5500 spin_lock_bh(&bp->phy_lock);
5501 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5502 spin_unlock_bh(&bp->phy_lock);
5513 /* Called with rtnl_lock */
5515 bnx2_change_mac_addr(struct net_device *dev, void *p)
5517 struct sockaddr *addr = p;
5518 struct bnx2 *bp = netdev_priv(dev);
5520 if (!is_valid_ether_addr(addr->sa_data))
5523 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5524 if (netif_running(dev))
5525 bnx2_set_mac_addr(bp);
5530 /* Called with rtnl_lock */
5532 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5534 struct bnx2 *bp = netdev_priv(dev);
5536 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5537 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5541 if (netif_running(dev)) {
5542 bnx2_netif_stop(bp);
5546 bnx2_netif_start(bp);
5551 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5553 poll_bnx2(struct net_device *dev)
5555 struct bnx2 *bp = netdev_priv(dev);
5557 disable_irq(bp->pdev->irq);
5558 bnx2_interrupt(bp->pdev->irq, dev);
5559 enable_irq(bp->pdev->irq);
5563 static int __devinit
5564 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5567 unsigned long mem_len;
5571 SET_MODULE_OWNER(dev);
5572 SET_NETDEV_DEV(dev, &pdev->dev);
5573 bp = netdev_priv(dev);
5578 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5579 rc = pci_enable_device(pdev);
5581 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.");
5585 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5587 "Cannot find PCI device base address, aborting.\n");
5589 goto err_out_disable;
5592 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5594 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
5595 goto err_out_disable;
5598 pci_set_master(pdev);
5600 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5601 if (bp->pm_cap == 0) {
5603 "Cannot find power management capability, aborting.\n");
5605 goto err_out_release;
5608 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5609 if (bp->pcix_cap == 0) {
5610 dev_err(&pdev->dev, "Cannot find PCIX capability, aborting.\n");
5612 goto err_out_release;
5615 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5616 bp->flags |= USING_DAC_FLAG;
5617 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5619 "pci_set_consistent_dma_mask failed, aborting.\n");
5621 goto err_out_release;
5624 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5625 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
5627 goto err_out_release;
5633 spin_lock_init(&bp->phy_lock);
5634 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5636 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5637 mem_len = MB_GET_CID_ADDR(17);
5638 dev->mem_end = dev->mem_start + mem_len;
5639 dev->irq = pdev->irq;
5641 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5644 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
5646 goto err_out_release;
5649 /* Configure byte swap and enable write to the reg_window registers.
5650 * Rely on CPU to do target byte swapping on big endian systems
5651 * The chip's target access swapping will not swap all accesses
5653 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5654 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5655 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5657 bnx2_set_power_state(bp, PCI_D0);
5659 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5661 /* Get bus information. */
5662 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5663 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5666 bp->flags |= PCIX_FLAG;
5668 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5670 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5672 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5673 bp->bus_speed_mhz = 133;
5676 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5677 bp->bus_speed_mhz = 100;
5680 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5681 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5682 bp->bus_speed_mhz = 66;
5685 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5686 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5687 bp->bus_speed_mhz = 50;
5690 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5691 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5692 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5693 bp->bus_speed_mhz = 33;
5698 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5699 bp->bus_speed_mhz = 66;
5701 bp->bus_speed_mhz = 33;
5704 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5705 bp->flags |= PCI_32BIT_FLAG;
5707 /* 5706A0 may falsely detect SERR and PERR. */
5708 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5709 reg = REG_RD(bp, PCI_COMMAND);
5710 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5711 REG_WR(bp, PCI_COMMAND, reg);
5713 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5714 !(bp->flags & PCIX_FLAG)) {
5717 "5706 A1 can only be used in a PCIX bus, aborting.\n");
5721 bnx2_init_nvram(bp);
5723 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5725 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5726 BNX2_SHM_HDR_SIGNATURE_SIG)
5727 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
5729 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5731 /* Get the permanent MAC address. First we need to make sure the
5732 * firmware is actually running.
5734 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
5736 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5737 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5738 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
5743 bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
5745 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
5746 bp->mac_addr[0] = (u8) (reg >> 8);
5747 bp->mac_addr[1] = (u8) reg;
5749 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
5750 bp->mac_addr[2] = (u8) (reg >> 24);
5751 bp->mac_addr[3] = (u8) (reg >> 16);
5752 bp->mac_addr[4] = (u8) (reg >> 8);
5753 bp->mac_addr[5] = (u8) reg;
5755 bp->tx_ring_size = MAX_TX_DESC_CNT;
5756 bnx2_set_rx_ring_size(bp, 255);
5760 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5762 bp->tx_quick_cons_trip_int = 20;
5763 bp->tx_quick_cons_trip = 20;
5764 bp->tx_ticks_int = 80;
5767 bp->rx_quick_cons_trip_int = 6;
5768 bp->rx_quick_cons_trip = 6;
5769 bp->rx_ticks_int = 18;
5772 bp->stats_ticks = 1000000 & 0xffff00;
5774 bp->timer_interval = HZ;
5775 bp->current_interval = HZ;
5779 /* Disable WOL support if we are running on a SERDES chip. */
5780 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5781 bp->phy_flags |= PHY_SERDES_FLAG;
5782 bp->flags |= NO_WOL_FLAG;
5783 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5785 reg = REG_RD_IND(bp, bp->shmem_base +
5786 BNX2_SHARED_HW_CFG_CONFIG);
5787 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5788 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5792 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
5793 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5794 (CHIP_ID(bp) == CHIP_ID_5708_B1))
5795 bp->flags |= NO_WOL_FLAG;
5797 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5798 bp->tx_quick_cons_trip_int =
5799 bp->tx_quick_cons_trip;
5800 bp->tx_ticks_int = bp->tx_ticks;
5801 bp->rx_quick_cons_trip_int =
5802 bp->rx_quick_cons_trip;
5803 bp->rx_ticks_int = bp->rx_ticks;
5804 bp->comp_prod_trip_int = bp->comp_prod_trip;
5805 bp->com_ticks_int = bp->com_ticks;
5806 bp->cmd_ticks_int = bp->cmd_ticks;
5809 /* Disable MSI on 5706 if AMD 8132 bridge is found.
5811 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
5812 * with byte enables disabled on the unused 32-bit word. This is legal
5813 * but causes problems on the AMD 8132 which will eventually stop
5814 * responding after a while.
5816 * AMD believes this incompatibility is unique to the 5706, and
5817 * prefers to locally disable MSI rather than globally disabling it
5818 * using pci_msi_quirk.
5820 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
5821 struct pci_dev *amd_8132 = NULL;
5823 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
5824 PCI_DEVICE_ID_AMD_8132_BRIDGE,
5828 pci_read_config_byte(amd_8132, PCI_REVISION_ID, &rev);
5829 if (rev >= 0x10 && rev <= 0x13) {
5831 pci_dev_put(amd_8132);
5837 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5838 bp->req_line_speed = 0;
5839 if (bp->phy_flags & PHY_SERDES_FLAG) {
5840 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5842 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
5843 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5844 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5846 bp->req_line_speed = bp->line_speed = SPEED_1000;
5847 bp->req_duplex = DUPLEX_FULL;
5851 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5854 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5856 init_timer(&bp->timer);
5857 bp->timer.expires = RUN_AT(bp->timer_interval);
5858 bp->timer.data = (unsigned long) bp;
5859 bp->timer.function = bnx2_timer;
5865 iounmap(bp->regview);
5870 pci_release_regions(pdev);
5873 pci_disable_device(pdev);
5874 pci_set_drvdata(pdev, NULL);
5880 static int __devinit
5881 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5883 static int version_printed = 0;
5884 struct net_device *dev = NULL;
5888 if (version_printed++ == 0)
5889 printk(KERN_INFO "%s", version);
5891 /* dev zeroed in init_etherdev */
5892 dev = alloc_etherdev(sizeof(*bp));
5897 rc = bnx2_init_board(pdev, dev);
5903 dev->open = bnx2_open;
5904 dev->hard_start_xmit = bnx2_start_xmit;
5905 dev->stop = bnx2_close;
5906 dev->get_stats = bnx2_get_stats;
5907 dev->set_multicast_list = bnx2_set_rx_mode;
5908 dev->do_ioctl = bnx2_ioctl;
5909 dev->set_mac_address = bnx2_change_mac_addr;
5910 dev->change_mtu = bnx2_change_mtu;
5911 dev->tx_timeout = bnx2_tx_timeout;
5912 dev->watchdog_timeo = TX_TIMEOUT;
5914 dev->vlan_rx_register = bnx2_vlan_rx_register;
5915 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5917 dev->poll = bnx2_poll;
5918 dev->ethtool_ops = &bnx2_ethtool_ops;
5921 bp = netdev_priv(dev);
5923 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5924 dev->poll_controller = poll_bnx2;
5927 if ((rc = register_netdev(dev))) {
5928 dev_err(&pdev->dev, "Cannot register net device\n");
5930 iounmap(bp->regview);
5931 pci_release_regions(pdev);
5932 pci_disable_device(pdev);
5933 pci_set_drvdata(pdev, NULL);
5938 pci_set_drvdata(pdev, dev);
5940 memcpy(dev->dev_addr, bp->mac_addr, 6);
5941 memcpy(dev->perm_addr, bp->mac_addr, 6);
5942 bp->name = board_info[ent->driver_data].name,
5943 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5947 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5948 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5949 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5950 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5955 printk("node addr ");
5956 for (i = 0; i < 6; i++)
5957 printk("%2.2x", dev->dev_addr[i]);
5960 dev->features |= NETIF_F_SG;
5961 if (bp->flags & USING_DAC_FLAG)
5962 dev->features |= NETIF_F_HIGHDMA;
5963 dev->features |= NETIF_F_IP_CSUM;
5965 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5968 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5971 netif_carrier_off(bp->dev);
5976 static void __devexit
5977 bnx2_remove_one(struct pci_dev *pdev)
5979 struct net_device *dev = pci_get_drvdata(pdev);
5980 struct bnx2 *bp = netdev_priv(dev);
5982 flush_scheduled_work();
5984 unregister_netdev(dev);
5987 iounmap(bp->regview);
5990 pci_release_regions(pdev);
5991 pci_disable_device(pdev);
5992 pci_set_drvdata(pdev, NULL);
5996 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5998 struct net_device *dev = pci_get_drvdata(pdev);
5999 struct bnx2 *bp = netdev_priv(dev);
6002 if (!netif_running(dev))
6005 flush_scheduled_work();
6006 bnx2_netif_stop(bp);
6007 netif_device_detach(dev);
6008 del_timer_sync(&bp->timer);
6009 if (bp->flags & NO_WOL_FLAG)
6010 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
6012 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
6014 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
6015 bnx2_reset_chip(bp, reset_code);
6017 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
6022 bnx2_resume(struct pci_dev *pdev)
6024 struct net_device *dev = pci_get_drvdata(pdev);
6025 struct bnx2 *bp = netdev_priv(dev);
6027 if (!netif_running(dev))
6030 bnx2_set_power_state(bp, PCI_D0);
6031 netif_device_attach(dev);
6033 bnx2_netif_start(bp);
6037 static struct pci_driver bnx2_pci_driver = {
6038 .name = DRV_MODULE_NAME,
6039 .id_table = bnx2_pci_tbl,
6040 .probe = bnx2_init_one,
6041 .remove = __devexit_p(bnx2_remove_one),
6042 .suspend = bnx2_suspend,
6043 .resume = bnx2_resume,
6046 static int __init bnx2_init(void)
6048 return pci_register_driver(&bnx2_pci_driver);
6051 static void __exit bnx2_cleanup(void)
6053 pci_unregister_driver(&bnx2_pci_driver);
6056 module_init(bnx2_init);
6057 module_exit(bnx2_cleanup);