Merge branch 'linus' into x86/cleanups
[linux-2.6] / arch / powerpc / boot / dts / tqm8548.dts
1 /*
2  * TQM8548 Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
6  *
7  * This program is free software; you can redistribute  it and/or modify it
8  * under  the terms of  the GNU General  Public License as published by the
9  * Free Software Foundation;  either version 2 of the  License, or (at your
10  * option) any later version.
11  */
12
13 /dts-v1/;
14
15 / {
16         model = "tqc,tqm8548";
17         compatible = "tqc,tqm8548";
18         #address-cells = <1>;
19         #size-cells = <1>;
20
21         aliases {
22                 ethernet0 = &enet0;
23                 ethernet1 = &enet1;
24                 ethernet2 = &enet2;
25                 ethernet3 = &enet3;
26
27                 serial0 = &serial0;
28                 serial1 = &serial1;
29                 pci0 = &pci0;
30                 pci1 = &pci1;
31         };
32
33         cpus {
34                 #address-cells = <1>;
35                 #size-cells = <0>;
36
37                 PowerPC,8548@0 {
38                         device_type = "cpu";
39                         reg = <0>;
40                         d-cache-line-size = <32>;       // 32 bytes
41                         i-cache-line-size = <32>;       // 32 bytes
42                         d-cache-size = <0x8000>;        // L1, 32K
43                         i-cache-size = <0x8000>;        // L1, 32K
44                         next-level-cache = <&L2>;
45                 };
46         };
47
48         memory {
49                 device_type = "memory";
50                 reg = <0x00000000 0x00000000>;  // Filled in by U-Boot
51         };
52
53         soc@e0000000 {
54                 #address-cells = <1>;
55                 #size-cells = <1>;
56                 device_type = "soc";
57                 ranges = <0x0 0xe0000000 0x100000>;
58                 reg = <0xe0000000 0x1000>;      // CCSRBAR
59                 bus-frequency = <0>;
60                 compatible = "fsl,mpc8548-immr", "simple-bus";
61
62                 memory-controller@2000 {
63                         compatible = "fsl,mpc8548-memory-controller";
64                         reg = <0x2000 0x1000>;
65                         interrupt-parent = <&mpic>;
66                         interrupts = <18 2>;
67                 };
68
69                 L2: l2-cache-controller@20000 {
70                         compatible = "fsl,mpc8548-l2-cache-controller";
71                         reg = <0x20000 0x1000>;
72                         cache-line-size = <32>; // 32 bytes
73                         cache-size = <0x80000>; // L2, 512K
74                         interrupt-parent = <&mpic>;
75                         interrupts = <16 2>;
76                 };
77
78                 i2c@3000 {
79                         #address-cells = <1>;
80                         #size-cells = <0>;
81                         cell-index = <0>;
82                         compatible = "fsl-i2c";
83                         reg = <0x3000 0x100>;
84                         interrupts = <43 2>;
85                         interrupt-parent = <&mpic>;
86                         dfsrr;
87
88                         rtc@68 {
89                                 compatible = "dallas,ds1337";
90                                 reg = <0x68>;
91                         };
92                 };
93
94                 i2c@3100 {
95                         #address-cells = <1>;
96                         #size-cells = <0>;
97                         cell-index = <1>;
98                         compatible = "fsl-i2c";
99                         reg = <0x3100 0x100>;
100                         interrupts = <43 2>;
101                         interrupt-parent = <&mpic>;
102                         dfsrr;
103                 };
104
105                 dma@21300 {
106                         #address-cells = <1>;
107                         #size-cells = <1>;
108                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
109                         reg = <0x21300 0x4>;
110                         ranges = <0x0 0x21100 0x200>;
111                         cell-index = <0>;
112                         dma-channel@0 {
113                                 compatible = "fsl,mpc8548-dma-channel",
114                                                 "fsl,eloplus-dma-channel";
115                                 reg = <0x0 0x80>;
116                                 cell-index = <0>;
117                                 interrupt-parent = <&mpic>;
118                                 interrupts = <20 2>;
119                         };
120                         dma-channel@80 {
121                                 compatible = "fsl,mpc8548-dma-channel",
122                                                 "fsl,eloplus-dma-channel";
123                                 reg = <0x80 0x80>;
124                                 cell-index = <1>;
125                                 interrupt-parent = <&mpic>;
126                                 interrupts = <21 2>;
127                         };
128                         dma-channel@100 {
129                                 compatible = "fsl,mpc8548-dma-channel",
130                                                 "fsl,eloplus-dma-channel";
131                                 reg = <0x100 0x80>;
132                                 cell-index = <2>;
133                                 interrupt-parent = <&mpic>;
134                                 interrupts = <22 2>;
135                         };
136                         dma-channel@180 {
137                                 compatible = "fsl,mpc8548-dma-channel",
138                                                 "fsl,eloplus-dma-channel";
139                                 reg = <0x180 0x80>;
140                                 cell-index = <3>;
141                                 interrupt-parent = <&mpic>;
142                                 interrupts = <23 2>;
143                         };
144                 };
145
146                 mdio@24520 {
147                         #address-cells = <1>;
148                         #size-cells = <0>;
149                         compatible = "fsl,gianfar-mdio";
150                         reg = <0x24520 0x20>;
151
152                         phy1: ethernet-phy@0 {
153                                 interrupt-parent = <&mpic>;
154                                 interrupts = <8 1>;
155                                 reg = <1>;
156                                 device_type = "ethernet-phy";
157                         };
158                         phy2: ethernet-phy@1 {
159                                 interrupt-parent = <&mpic>;
160                                 interrupts = <8 1>;
161                                 reg = <2>;
162                                 device_type = "ethernet-phy";
163                         };
164                         phy3: ethernet-phy@3 {
165                                 interrupt-parent = <&mpic>;
166                                 interrupts = <8 1>;
167                                 reg = <3>;
168                                 device_type = "ethernet-phy";
169                         };
170                         phy4: ethernet-phy@4 {
171                                 interrupt-parent = <&mpic>;
172                                 interrupts = <8 1>;
173                                 reg = <4>;
174                                 device_type = "ethernet-phy";
175                         };
176                         phy5: ethernet-phy@5 {
177                                 interrupt-parent = <&mpic>;
178                                 interrupts = <8 1>;
179                                 reg = <5>;
180                                 device_type = "ethernet-phy";
181                         };
182                         tbi0: tbi-phy@11 {
183                                 reg = <0x11>;
184                                 device_type = "tbi-phy";
185                         };
186                 };
187
188                 mdio@25520 {
189                         #address-cells = <1>;
190                         #size-cells = <0>;
191                         compatible = "fsl,gianfar-tbi";
192                         reg = <0x25520 0x20>;
193
194                         tbi1: tbi-phy@11 {
195                                 reg = <0x11>;
196                                 device_type = "tbi-phy";
197                         };
198                 };
199
200                 mdio@26520 {
201                         #address-cells = <1>;
202                         #size-cells = <0>;
203                         compatible = "fsl,gianfar-tbi";
204                         reg = <0x26520 0x20>;
205
206                         tbi2: tbi-phy@11 {
207                                 reg = <0x11>;
208                                 device_type = "tbi-phy";
209                         };
210                 };
211
212                 mdio@27520 {
213                         #address-cells = <1>;
214                         #size-cells = <0>;
215                         compatible = "fsl,gianfar-tbi";
216                         reg = <0x27520 0x20>;
217
218                         tbi3: tbi-phy@11 {
219                                 reg = <0x11>;
220                                 device_type = "tbi-phy";
221                         };
222                 };
223
224                 enet0: ethernet@24000 {
225                         cell-index = <0>;
226                         device_type = "network";
227                         model = "eTSEC";
228                         compatible = "gianfar";
229                         reg = <0x24000 0x1000>;
230                         local-mac-address = [ 00 00 00 00 00 00 ];
231                         interrupts = <29 2 30 2 34 2>;
232                         interrupt-parent = <&mpic>;
233                         tbi-handle = <&tbi0>;
234                         phy-handle = <&phy2>;
235                 };
236
237                 enet1: ethernet@25000 {
238                         cell-index = <1>;
239                         device_type = "network";
240                         model = "eTSEC";
241                         compatible = "gianfar";
242                         reg = <0x25000 0x1000>;
243                         local-mac-address = [ 00 00 00 00 00 00 ];
244                         interrupts = <35 2 36 2 40 2>;
245                         interrupt-parent = <&mpic>;
246                         tbi-handle = <&tbi1>;
247                         phy-handle = <&phy1>;
248                 };
249
250                 enet2: ethernet@26000 {
251                         cell-index = <2>;
252                         device_type = "network";
253                         model = "eTSEC";
254                         compatible = "gianfar";
255                         reg = <0x26000 0x1000>;
256                         local-mac-address = [ 00 00 00 00 00 00 ];
257                         interrupts = <31 2 32 2 33 2>;
258                         interrupt-parent = <&mpic>;
259                         tbi-handle = <&tbi2>;
260                         phy-handle = <&phy3>;
261                 };
262
263                 enet3: ethernet@27000 {
264                         cell-index = <3>;
265                         device_type = "network";
266                         model = "eTSEC";
267                         compatible = "gianfar";
268                         reg = <0x27000 0x1000>;
269                         local-mac-address = [ 00 00 00 00 00 00 ];
270                         interrupts = <37 2 38 2 39 2>;
271                         interrupt-parent = <&mpic>;
272                         tbi-handle = <&tbi3>;
273                         phy-handle = <&phy4>;
274                 };
275
276                 serial0: serial@4500 {
277                         cell-index = <0>;
278                         device_type = "serial";
279                         compatible = "ns16550";
280                         reg = <0x4500 0x100>;   // reg base, size
281                         clock-frequency = <0>;  // should we fill in in uboot?
282                         current-speed = <115200>;
283                         interrupts = <42 2>;
284                         interrupt-parent = <&mpic>;
285                 };
286
287                 serial1: serial@4600 {
288                         cell-index = <1>;
289                         device_type = "serial";
290                         compatible = "ns16550";
291                         reg = <0x4600 0x100>;   // reg base, size
292                         clock-frequency = <0>;  // should we fill in in uboot?
293                         current-speed = <115200>;
294                         interrupts = <42 2>;
295                         interrupt-parent = <&mpic>;
296                 };
297
298                 global-utilities@e0000 {        // global utilities reg
299                         compatible = "fsl,mpc8548-guts";
300                         reg = <0xe0000 0x1000>;
301                         fsl,has-rstcr;
302                 };
303
304                 mpic: pic@40000 {
305                         interrupt-controller;
306                         #address-cells = <0>;
307                         #interrupt-cells = <2>;
308                         reg = <0x40000 0x40000>;
309                         compatible = "chrp,open-pic";
310                         device_type = "open-pic";
311                 };
312         };
313
314         localbus@e0005000 {
315                 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
316                              "simple-bus";
317                 #address-cells = <2>;
318                 #size-cells = <1>;
319                 reg = <0xe0005000 0x100>;       // BRx, ORx, etc.
320
321                 ranges = <
322                         0 0x0 0xfc000000 0x04000000     // NOR FLASH bank 1
323                         1 0x0 0xf8000000 0x08000000     // NOR FLASH bank 0
324                         2 0x0 0xe3000000 0x00008000     // CAN (2 x i82527)
325                         3 0x0 0xe3010000 0x00008000     // NAND FLASH
326
327                 >;
328
329                 flash@1,0 {
330                         #address-cells = <1>;
331                         #size-cells = <1>;
332                         compatible = "cfi-flash";
333                         reg = <1 0x0 0x8000000>;
334                         bank-width = <4>;
335                         device-width = <1>;
336
337                         partition@0 {
338                                 label = "kernel";
339                                 reg = <0x00000000 0x00200000>;
340                         };
341                         partition@200000 {
342                                 label = "root";
343                                 reg = <0x00200000 0x00300000>;
344                         };
345                         partition@500000 {
346                                 label = "user";
347                                 reg = <0x00500000 0x07a00000>;
348                         };
349                         partition@7f00000 {
350                                 label = "env1";
351                                 reg = <0x07f00000 0x00040000>;
352                         };
353                         partition@7f40000 {
354                                 label = "env2";
355                                 reg = <0x07f40000 0x00040000>;
356                         };
357                         partition@7f80000 {
358                                 label = "u-boot";
359                                 reg = <0x07f80000 0x00080000>;
360                                 read-only;
361                         };
362                 };
363
364                 /* Note: CAN support needs be enabled in U-Boot */
365                 can0@2,0 {
366                         compatible = "intel,82527"; // Bosch CC770
367                         reg = <2 0x0 0x100>;
368                         interrupts = <4 0>;
369                         interrupt-parent = <&mpic>;
370                 };
371
372                 can1@2,100 {
373                         compatible = "intel,82527"; // Bosch CC770
374                         reg = <2 0x100 0x100>;
375                         interrupts = <4 0>;
376                         interrupt-parent = <&mpic>;
377                 };
378
379                 /* Note: NAND support needs to be enabled in U-Boot */
380                 upm@3,0 {
381                         #address-cells = <0>;
382                         #size-cells = <0>;
383                         compatible = "fsl,upm-nand";
384                         reg = <3 0x0 0x800>;
385                         fsl,upm-addr-offset = <0x10>;
386                         fsl,upm-cmd-offset = <0x08>;
387                         chip-delay = <25>; // in micro-seconds
388
389                         nand@0 {
390                                 #address-cells = <1>;
391                                 #size-cells = <1>;
392
393                                 partition@0 {
394                                             label = "fs";
395                                             reg = <0x00000000 0x01000000>;
396                                 };
397                         };
398                 };
399         };
400
401         pci0: pci@e0008000 {
402                 cell-index = <0>;
403                 #interrupt-cells = <1>;
404                 #size-cells = <2>;
405                 #address-cells = <3>;
406                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
407                 device_type = "pci";
408                 reg = <0xe0008000 0x1000>;
409                 clock-frequency = <33333333>;
410                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
411                 interrupt-map = <
412                                 /* IDSEL 28 */
413                                  0xe000 0 0 1 &mpic 2 1
414                                  0xe000 0 0 2 &mpic 3 1>;
415
416                 interrupt-parent = <&mpic>;
417                 interrupts = <24 2>;
418                 bus-range = <0 0>;
419                 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
420                           0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
421         };
422
423         pci1: pcie@e000a000 {
424                 cell-index = <2>;
425                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
426                 interrupt-map = <
427                         /* IDSEL 0x0 (PEX) */
428                         0x00000 0 0 1 &mpic 0 1
429                         0x00000 0 0 2 &mpic 1 1
430                         0x00000 0 0 3 &mpic 2 1
431                         0x00000 0 0 4 &mpic 3 1>;
432
433                 interrupt-parent = <&mpic>;
434                 interrupts = <26 2>;
435                 bus-range = <0 0xff>;
436                 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x20000000
437                           0x01000000 0 0x00000000 0xef000000 0 0x08000000>;
438                 clock-frequency = <33333333>;
439                 #interrupt-cells = <1>;
440                 #size-cells = <2>;
441                 #address-cells = <3>;
442                 reg = <0xe000a000 0x1000>;
443                 compatible = "fsl,mpc8548-pcie";
444                 device_type = "pci";
445                 pcie@0 {
446                         reg = <0 0 0 0 0>;
447                         #size-cells = <2>;
448                         #address-cells = <3>;
449                         device_type = "pci";
450                         ranges = <0x02000000 0 0xc0000000 0x02000000 0
451                                   0xc0000000 0 0x20000000
452                                   0x01000000 0 0x00000000 0x01000000 0
453                                   0x00000000 0 0x08000000>;
454                 };
455         };
456 };