2 * drivers/net/phy/davicom.c
4 * Driver for Davicom PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/string.h>
20 #include <linux/errno.h>
21 #include <linux/unistd.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/spinlock.h>
31 #include <linux/module.h>
32 #include <linux/version.h>
33 #include <linux/mii.h>
34 #include <linux/ethtool.h>
35 #include <linux/phy.h>
39 #include <asm/uaccess.h>
41 #define MII_DM9161_SCR 0x10
42 #define MII_DM9161_SCR_INIT 0x0610
44 /* DM9161 Interrupt Register */
45 #define MII_DM9161_INTR 0x15
46 #define MII_DM9161_INTR_PEND 0x8000
47 #define MII_DM9161_INTR_DPLX_MASK 0x0800
48 #define MII_DM9161_INTR_SPD_MASK 0x0400
49 #define MII_DM9161_INTR_LINK_MASK 0x0200
50 #define MII_DM9161_INTR_MASK 0x0100
51 #define MII_DM9161_INTR_DPLX_CHANGE 0x0010
52 #define MII_DM9161_INTR_SPD_CHANGE 0x0008
53 #define MII_DM9161_INTR_LINK_CHANGE 0x0004
54 #define MII_DM9161_INTR_INIT 0x0000
55 #define MII_DM9161_INTR_STOP \
56 (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
57 | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
59 /* DM9161 10BT Configuration/Status */
60 #define MII_DM9161_10BTCSR 0x12
61 #define MII_DM9161_10BTCSR_INIT 0x7800
63 MODULE_DESCRIPTION("Davicom PHY driver");
64 MODULE_AUTHOR("Andy Fleming");
65 MODULE_LICENSE("GPL");
68 #define DM9161_DELAY 1
69 static int dm9161_config_intr(struct phy_device *phydev)
73 temp = phy_read(phydev, MII_DM9161_INTR);
78 if(PHY_INTERRUPT_ENABLED == phydev->interrupts )
79 temp &= ~(MII_DM9161_INTR_STOP);
81 temp |= MII_DM9161_INTR_STOP;
83 temp = phy_write(phydev, MII_DM9161_INTR, temp);
88 static int dm9161_config_aneg(struct phy_device *phydev)
93 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
98 /* Configure the new settings */
99 err = genphy_config_aneg(phydev);
107 static int dm9161_config_init(struct phy_device *phydev)
111 /* Isolate the PHY */
112 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
117 /* Do not bypass the scrambler/descrambler */
118 err = phy_write(phydev, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
123 /* Clear 10BTCSR to default */
124 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT);
129 /* Reconnect the PHY, and enable Autonegotiation */
130 err = phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
138 static int dm9161_ack_interrupt(struct phy_device *phydev)
140 int err = phy_read(phydev, MII_DM9161_INTR);
142 return (err < 0) ? err : 0;
145 static struct phy_driver dm9161_driver = {
146 .phy_id = 0x0181b880,
147 .name = "Davicom DM9161E",
148 .phy_id_mask = 0x0ffffff0,
149 .features = PHY_BASIC_FEATURES,
150 .config_init = dm9161_config_init,
151 .config_aneg = dm9161_config_aneg,
152 .read_status = genphy_read_status,
153 .driver = { .owner = THIS_MODULE,},
156 static struct phy_driver dm9131_driver = {
157 .phy_id = 0x00181b80,
158 .name = "Davicom DM9131",
159 .phy_id_mask = 0x0ffffff0,
160 .features = PHY_BASIC_FEATURES,
161 .flags = PHY_HAS_INTERRUPT,
162 .config_aneg = genphy_config_aneg,
163 .read_status = genphy_read_status,
164 .ack_interrupt = dm9161_ack_interrupt,
165 .config_intr = dm9161_config_intr,
166 .driver = { .owner = THIS_MODULE,},
169 static int __init davicom_init(void)
173 ret = phy_driver_register(&dm9161_driver);
177 ret = phy_driver_register(&dm9131_driver);
183 phy_driver_unregister(&dm9161_driver);
188 static void __exit davicom_exit(void)
190 phy_driver_unregister(&dm9161_driver);
191 phy_driver_unregister(&dm9131_driver);
194 module_init(davicom_init);
195 module_exit(davicom_exit);