2 * This file contains the functions and defines necessary to modify and
3 * use the SuperH page table tree.
5 * Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2002 - 2005 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of this
10 * archive for more details.
12 #ifndef __ASM_SH_PGTABLE_H
13 #define __ASM_SH_PGTABLE_H
15 #include <asm-generic/pgtable-nopmd.h>
19 #include <asm/addrspace.h>
20 #include <asm/fixmap.h>
23 * ZERO_PAGE is a global shared page that is always zero: used
24 * for zero-mapped memory areas etc..
26 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
27 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
29 #endif /* !__ASSEMBLY__ */
32 * Effective and physical address definitions, to aid with sign
36 #define NEFF_SIGN (1LL << (NEFF - 1))
37 #define NEFF_MASK (-1LL << NEFF)
45 #define NPHYS_SIGN (1LL << (NPHYS - 1))
46 #define NPHYS_MASK (-1LL << NPHYS)
49 * traditional two-level paging structure
53 # define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */
55 # define PTE_MAGNITUDE 2 /* 32-bit PTEs */
57 #define PTE_SHIFT PAGE_SHIFT
58 #define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE)
61 #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
62 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
63 #define PGDIR_MASK (~(PGDIR_SIZE-1))
65 /* Entries per level */
66 #define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
67 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t))
69 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
70 #define FIRST_USER_ADDRESS 0
72 #define PTE_PHYS_MASK (0x20000000 - PAGE_SIZE)
74 #define VMALLOC_START (P3SEG)
75 #define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
78 * Linux PTEL encoding.
80 * Hardware and software bit definitions for the PTEL value (see below for
81 * notes on SH-X2 MMUs and 64-bit PTEs):
83 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
85 * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
86 * hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
87 * which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT).
89 * In order to keep this relatively clean, do not use these for defining
90 * SH-3 specific flags until all of the other unused bits have been
93 * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
95 * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
96 * Bit 10 is used for _PAGE_ACCESSED, bit 11 remains unused.
98 * - Bits 31, 30, and 29 remain unused by everyone and can be used for future
99 * software flags, although care must be taken to update _PAGE_CLEAR_FLAGS.
101 * XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
103 * SH-X2 MMUs and extended PTEs
105 * SH-X2 supports an extended mode TLB with split data arrays due to the
106 * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
107 * SZ bit placeholders still exist in data array 1, but are implemented as
108 * reserved bits, with the real logic existing in data array 2.
110 * The downside to this is that we can no longer fit everything in to a 32-bit
111 * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
112 * side, this gives us quite a few spare bits to play with for future usage.
114 /* Legacy and compat mode bits */
115 #define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */
116 #define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */
117 #define _PAGE_DIRTY 0x004 /* D-bit : page changed */
118 #define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
119 #define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
120 #define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
121 #define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/
122 #define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
123 #define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
124 #define _PAGE_PROTNONE 0x200 /* software: if not present */
125 #define _PAGE_ACCESSED 0x400 /* software: page referenced */
126 #define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */
128 #define _PAGE_SZ_MASK (_PAGE_SZ0 | _PAGE_SZ1)
129 #define _PAGE_PR_MASK (_PAGE_RW | _PAGE_USER)
131 /* Extended mode bits */
132 #define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */
133 #define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */
134 #define _PAGE_EXT_ESZ2 0x0040 /* ESZ2-bit: Size of page */
135 #define _PAGE_EXT_ESZ3 0x0080 /* ESZ3-bit: Size of page */
137 #define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */
138 #define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */
139 #define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */
141 #define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */
142 #define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */
143 #define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
145 /* Wrapper for extended mode pgprot twiddling */
146 #define _PAGE_EXT(x) ((unsigned long long)(x) << 32)
148 /* software: moves to PTEA.TC (Timing Control) */
149 #define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
150 #define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */
152 /* software: moves to PTEA.SA[2:0] (Space Attributes) */
153 #define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */
154 #define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */
155 #define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */
156 #define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */
157 #define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */
158 #define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
159 #define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
161 /* Mask which drops unused bits from the PTEL value */
162 #if defined(CONFIG_CPU_SH3)
163 #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \
164 _PAGE_FILE | _PAGE_SZ1 | \
166 #elif defined(CONFIG_X2TLB)
167 /* Get rid of the legacy PR/SZ bits when using extended mode */
168 #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | \
169 _PAGE_FILE | _PAGE_PR_MASK | _PAGE_SZ_MASK)
171 #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
174 #define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS))
176 /* Hardware flags, page size encoding */
177 #if defined(CONFIG_X2TLB)
178 # if defined(CONFIG_PAGE_SIZE_4KB)
179 # define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ0)
180 # elif defined(CONFIG_PAGE_SIZE_8KB)
181 # define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ1)
182 # elif defined(CONFIG_PAGE_SIZE_64KB)
183 # define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ2)
186 # if defined(CONFIG_PAGE_SIZE_4KB)
187 # define _PAGE_FLAGS_HARD _PAGE_SZ0
188 # elif defined(CONFIG_PAGE_SIZE_64KB)
189 # define _PAGE_FLAGS_HARD _PAGE_SZ1
193 #if defined(CONFIG_X2TLB)
194 # if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
195 # define _PAGE_SZHUGE (_PAGE_EXT_ESZ2)
196 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
197 # define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
198 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
199 # define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
200 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
201 # define _PAGE_SZHUGE (_PAGE_EXT_ESZ3)
202 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
203 # define _PAGE_SZHUGE (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
206 # if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
207 # define _PAGE_SZHUGE (_PAGE_SZ1)
208 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
209 # define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1)
214 * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
215 * to make pte_mkhuge() happy.
218 # define _PAGE_SZHUGE (_PAGE_FLAGS_HARD)
221 #define _PAGE_CHG_MASK \
222 (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
226 #if defined(CONFIG_X2TLB) /* SH-X2 TLB */
227 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
228 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
230 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
231 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
232 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
233 _PAGE_EXT_KERN_WRITE | \
234 _PAGE_EXT_USER_READ | \
235 _PAGE_EXT_USER_WRITE))
237 #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
238 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
239 _PAGE_EXT(_PAGE_EXT_KERN_EXEC | \
240 _PAGE_EXT_KERN_READ | \
241 _PAGE_EXT_USER_EXEC | \
242 _PAGE_EXT_USER_READ))
244 #define PAGE_COPY PAGE_EXECREAD
246 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
247 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
248 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
249 _PAGE_EXT_USER_READ))
251 #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
252 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
253 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
254 _PAGE_EXT_USER_WRITE))
256 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
257 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
258 _PAGE_EXT(_PAGE_EXT_KERN_WRITE | \
259 _PAGE_EXT_KERN_READ | \
260 _PAGE_EXT_KERN_EXEC | \
261 _PAGE_EXT_USER_WRITE | \
262 _PAGE_EXT_USER_READ | \
263 _PAGE_EXT_USER_EXEC))
265 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
266 _PAGE_DIRTY | _PAGE_ACCESSED | \
267 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
268 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
269 _PAGE_EXT_KERN_WRITE | \
270 _PAGE_EXT_KERN_EXEC))
272 #define PAGE_KERNEL_NOCACHE \
273 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
274 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
276 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
277 _PAGE_EXT_KERN_WRITE | \
278 _PAGE_EXT_KERN_EXEC))
280 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
281 _PAGE_DIRTY | _PAGE_ACCESSED | \
282 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
283 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
284 _PAGE_EXT_KERN_EXEC))
286 #define PAGE_KERNEL_PCC(slot, type) \
287 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
288 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
289 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
290 _PAGE_EXT_KERN_WRITE | \
291 _PAGE_EXT_KERN_EXEC) \
292 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
295 #elif defined(CONFIG_MMU) /* SH-X TLB */
296 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
297 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
299 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
300 _PAGE_CACHABLE | _PAGE_ACCESSED | \
303 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
304 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
306 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
307 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
309 #define PAGE_EXECREAD PAGE_READONLY
310 #define PAGE_RWX PAGE_SHARED
311 #define PAGE_WRITEONLY PAGE_SHARED
313 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
314 _PAGE_DIRTY | _PAGE_ACCESSED | \
315 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
317 #define PAGE_KERNEL_NOCACHE \
318 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
319 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
322 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
323 _PAGE_DIRTY | _PAGE_ACCESSED | \
324 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
326 #define PAGE_KERNEL_PCC(slot, type) \
327 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
328 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
329 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
332 #define PAGE_NONE __pgprot(0)
333 #define PAGE_SHARED __pgprot(0)
334 #define PAGE_COPY __pgprot(0)
335 #define PAGE_EXECREAD __pgprot(0)
336 #define PAGE_RWX __pgprot(0)
337 #define PAGE_READONLY __pgprot(0)
338 #define PAGE_WRITEONLY __pgprot(0)
339 #define PAGE_KERNEL __pgprot(0)
340 #define PAGE_KERNEL_NOCACHE __pgprot(0)
341 #define PAGE_KERNEL_RO __pgprot(0)
343 #define PAGE_KERNEL_PCC(slot, type) \
347 #endif /* __ASSEMBLY__ */
350 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
351 * protection for execute, and considers it the same as a read. Also, write
352 * permission implies read permission. This is the closest we can get..
354 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
355 * not only supporting separate execute, read, and write bits, but having
356 * completely separate permission bits for user and kernel space.
359 #define __P000 PAGE_NONE
360 #define __P001 PAGE_READONLY
361 #define __P010 PAGE_COPY
362 #define __P011 PAGE_COPY
363 #define __P100 PAGE_EXECREAD
364 #define __P101 PAGE_EXECREAD
365 #define __P110 PAGE_COPY
366 #define __P111 PAGE_COPY
368 #define __S000 PAGE_NONE
369 #define __S001 PAGE_READONLY
370 #define __S010 PAGE_WRITEONLY
371 #define __S011 PAGE_SHARED
372 #define __S100 PAGE_EXECREAD
373 #define __S101 PAGE_EXECREAD
374 #define __S110 PAGE_RWX
375 #define __S111 PAGE_RWX
380 * Certain architectures need to do special things when PTEs
381 * within a page table are directly modified. Thus, the following
382 * hook is made available.
385 static inline void set_pte(pte_t *ptep, pte_t pte)
387 ptep->pte_high = pte.pte_high;
389 ptep->pte_low = pte.pte_low;
392 #define set_pte(pteptr, pteval) (*(pteptr) = pteval)
395 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
398 * (pmds are folded into pgds so this doesn't get actually called,
399 * but the define is needed for a generic inline function.)
401 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
403 #define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
405 #define pfn_pte(pfn, prot) \
406 __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
407 #define pfn_pmd(pfn, prot) \
408 __pmd(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
410 #define pte_none(x) (!pte_val(x))
411 #define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
413 #define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
415 #define pmd_none(x) (!pmd_val(x))
416 #define pmd_present(x) (pmd_val(x))
417 #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
418 #define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
420 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
421 #define pte_page(x) pfn_to_page(pte_pfn(x))
424 * The following only work if pte_present() is true.
425 * Undefined behaviour if not..
427 #define pte_not_present(pte) (!((pte).pte_low & _PAGE_PRESENT))
428 #define pte_dirty(pte) ((pte).pte_low & _PAGE_DIRTY)
429 #define pte_young(pte) ((pte).pte_low & _PAGE_ACCESSED)
430 #define pte_file(pte) ((pte).pte_low & _PAGE_FILE)
433 #define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE)
435 #define pte_write(pte) ((pte).pte_low & _PAGE_RW)
438 #define PTE_BIT_FUNC(h,fn,op) \
439 static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
443 * We cheat a bit in the SH-X2 TLB case. As the permission bits are
444 * individually toggled (and user permissions are entirely decoupled from
445 * kernel permissions), we attempt to couple them a bit more sanely here.
447 PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
448 PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
449 PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
451 PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
452 PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
453 PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
456 PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
457 PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
458 PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
459 PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
462 * Macro and implementation to make a page protection as uncachable.
464 #define pgprot_writecombine(prot) \
465 __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
467 #define pgprot_noncached pgprot_writecombine
470 * Conversion functions: convert a page and protection to a page entry,
471 * and a page entry and page directory to the page they refer to.
473 * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
475 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
477 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
479 pte.pte_low &= _PAGE_CHG_MASK;
480 pte.pte_low |= pgprot_val(newprot);
483 pte.pte_high |= pgprot_val(newprot) >> 32;
489 #define pmd_page_vaddr(pmd) ((unsigned long)pmd_val(pmd))
490 #define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
492 /* to find an entry in a page-table-directory. */
493 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
494 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
496 /* to find an entry in a kernel page-table-directory */
497 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
499 /* Find an entry in the third-level page table.. */
500 #define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
501 #define pte_offset_kernel(dir, address) \
502 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
503 #define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
504 #define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
506 #define pte_unmap(pte) do { } while (0)
507 #define pte_unmap_nested(pte) do { } while (0)
510 #define pte_ERROR(e) \
511 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
512 &(e), (e).pte_high, (e).pte_low)
513 #define pgd_ERROR(e) \
514 printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
516 #define pte_ERROR(e) \
517 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
518 #define pgd_ERROR(e) \
519 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
522 struct vm_area_struct;
523 extern void update_mmu_cache(struct vm_area_struct * vma,
524 unsigned long address, pte_t pte);
527 * Encode and de-code a swap entry
530 * _PAGE_FILE at bit 0
531 * _PAGE_PRESENT at bit 8
532 * _PAGE_PROTNONE at bit 9
534 * For the normal case, we encode the swap type into bits 0:7 and the
535 * swap offset into bits 10:30. For the 64-bit PTE case, we keep the
536 * preserved bits in the low 32-bits and use the upper 32 as the swap
537 * offset (along with a 5-bit type), following the same approach as x86
538 * PAE. This keeps the logic quite simple, and allows for a full 32
539 * PTE_FILE_MAX_BITS, as opposed to the 29-bits we're constrained with
540 * in the pte_low case.
542 * As is evident by the Alpha code, if we ever get a 64-bit unsigned
543 * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes
546 * NOTE: We should set ZEROs at the position of _PAGE_PRESENT
547 * and _PAGE_PROTNONE bits
550 #define __swp_type(x) ((x).val & 0x1f)
551 #define __swp_offset(x) ((x).val >> 5)
552 #define __swp_entry(type, offset) ((swp_entry_t){ (type) | (offset) << 5})
553 #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
554 #define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
557 * Encode and decode a nonlinear file mapping entry
559 #define pte_to_pgoff(pte) ((pte).pte_high)
560 #define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
562 #define PTE_FILE_MAX_BITS 32
564 #define __swp_type(x) ((x).val & 0xff)
565 #define __swp_offset(x) ((x).val >> 10)
566 #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) <<10})
568 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 1 })
569 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 1 })
572 * Encode and decode a nonlinear file mapping entry
574 #define PTE_FILE_MAX_BITS 29
575 #define pte_to_pgoff(pte) (pte_val(pte) >> 1)
576 #define pgoff_to_pte(off) ((pte_t) { ((off) << 1) | _PAGE_FILE })
579 typedef pte_t *pte_addr_t;
581 #define kern_addr_valid(addr) (1)
583 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
584 remap_pfn_range(vma, vaddr, pfn, size, prot)
589 * No page table caches to initialise
591 #define pgtable_cache_init() do { } while (0)
594 extern unsigned int kobjsize(const void *objp);
595 #endif /* !CONFIG_MMU */
597 #if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
598 defined(CONFIG_SH7705_CACHE_32KB))
599 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
600 extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
603 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
604 extern void paging_init(void);
606 #include <asm-generic/pgtable.h>
608 #endif /* !__ASSEMBLY__ */
609 #endif /* __ASM_SH_PAGE_H */