git.oblomov.eu Git - linux-2.6/blob - drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,5,6 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Changelog:
  33  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  34  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  35  *                         Check all PCI BARs for the register window.
  36  *                         udelay added to mii_rw.
  37  *      0.03: 06 Oct 2003: Initialize dev->irq.
  38  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  39  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  40  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  41  *                         irq mask updated
  42  *      0.07: 14 Oct 2003: Further irq mask updates.
  43  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  44  *                         added into irq handler, NULL check for drain_ring.
  45  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  46  *                         requested interrupt sources.
  47  *      0.10: 20 Oct 2003: First cleanup for release.
  48  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  49  *                         MAC Address init fix, set_multicast cleanup.
  50  *      0.12: 23 Oct 2003: Cleanups for release.
  51  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  52  *                         Set link speed correctly. start rx before starting
  53  *                         tx (nv_start_rx sets the link speed).
  54  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  55  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  56  *                         open.
  57  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  58  *                         increased to 1628 bytes.
  59  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  60  *                         the tx length.
  61  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  62  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  63  *                         addresses, really stop rx if already running
  64  *                         in nv_start_rx, clean up a bit.
  65  *      0.20: 07 Dec 2003: alloc fixes
  66  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  67  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  68  *                         on close.
  69  *      0.23: 26 Jan 2004: various small cleanups
  70  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  71  *      0.25: 09 Mar 2004: wol support
  72  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  73  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  74  *                         added CK804/MCP04 device IDs, code fixes
  75  *                         for registers, link status and other minor fixes.
  76  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  77  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  78  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  79  *                         into nv_close, otherwise reenabling for wol can
  80  *                         cause DMA to kfree'd memory.
  81  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  82  *                         capabilities.
  83  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  84  *      0.33: 16 May 2005: Support for MCP51 added.
  85  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  86  *      0.35: 26 Jun 2005: Support for MCP55 added.
  87  *      0.36: 28 Jun 2005: Add jumbo frame support.
  88  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  89  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  90  *                         per-packet flags.
  91  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  92  *      0.40: 19 Jul 2005: Add support for mac address change.
  93  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  94  *                         of nv_remove
  95  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  96  *                         in the second (and later) nv_open call
  97  *      0.43: 10 Aug 2005: Add support for tx checksum.
  98  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
  99  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 100  *      0.46: 20 Oct 2005: Add irq optimization modes.
 101  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 102  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 103  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 104  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 105  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 106  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 107  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 108  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 109  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 110  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 111  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 112  *      0.58: 30 Oct 2006: Added support for sideband management unit.
 113  *      0.59: 30 Oct 2006: Added support for recoverable error.
 114  *
 115  * Known bugs:
 116  * We suspect that on some hardware no TX done interrupts are generated.
 117  * This means recovery from netif_stop_queue only happens if the hw timer
 118  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 119  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 120  * If your hardware reliably generates tx done interrupts, then you can remove
 121  * DEV_NEED_TIMERIRQ from the driver_data flags.
 122  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 123  * superfluous timer interrupts from the nic.
 124  */
 125 #ifdef CONFIG_FORCEDETH_NAPI
 126 #define DRIVERNAPI "-NAPI"
 127 #else
 128 #define DRIVERNAPI
 129 #endif
 130 #define FORCEDETH_VERSION               "0.59"
 131 #define DRV_NAME                        "forcedeth"
 132
 133 #include <linux/module.h>
 134 #include <linux/types.h>
 135 #include <linux/pci.h>
 136 #include <linux/interrupt.h>
 137 #include <linux/netdevice.h>
 138 #include <linux/etherdevice.h>
 139 #include <linux/delay.h>
 140 #include <linux/spinlock.h>
 141 #include <linux/ethtool.h>
 142 #include <linux/timer.h>
 143 #include <linux/skbuff.h>
 144 #include <linux/mii.h>
 145 #include <linux/random.h>
 146 #include <linux/init.h>
 147 #include <linux/if_vlan.h>
 148 #include <linux/dma-mapping.h>
 149
 150 #include <asm/irq.h>
 151 #include <asm/io.h>
 152 #include <asm/uaccess.h>
 153 #include <asm/system.h>
 154
 155 #if 0
 156 #define dprintk                 printk
 157 #else
 158 #define dprintk(x...)           do { } while (0)
 159 #endif
 160
 161
 162 /*
 163  * Hardware access:
 164  */
 165
 166 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 167 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 168 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 169 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 170 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 171 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 172 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 173 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 174 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 175 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 176 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
 177 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
 178 #define DEV_HAS_MGMT_UNIT       0x1000  /* device supports management unit */
 179
 180 enum {
 181         NvRegIrqStatus = 0x000,
 182 #define NVREG_IRQSTAT_MIIEVENT  0x040
 183 #define NVREG_IRQSTAT_MASK              0x81ff
 184         NvRegIrqMask = 0x004,
 185 #define NVREG_IRQ_RX_ERROR              0x0001
 186 #define NVREG_IRQ_RX                    0x0002
 187 #define NVREG_IRQ_RX_NOBUF              0x0004
 188 #define NVREG_IRQ_TX_ERR                0x0008
 189 #define NVREG_IRQ_TX_OK                 0x0010
 190 #define NVREG_IRQ_TIMER                 0x0020
 191 #define NVREG_IRQ_LINK                  0x0040
 192 #define NVREG_IRQ_RX_FORCED             0x0080
 193 #define NVREG_IRQ_TX_FORCED             0x0100
 194 #define NVREG_IRQ_RECOVER_ERROR         0x8000
 195 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 196 #define NVREG_IRQMASK_CPU               0x0040
 197 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 198 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 199 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 200
 201 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 202                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 203                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 204
 205         NvRegUnknownSetupReg6 = 0x008,
 206 #define NVREG_UNKSETUP6_VAL             3
 207
 208 /*
 209  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 210  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 211  */
 212         NvRegPollingInterval = 0x00c,
 213 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 214 #define NVREG_POLL_DEFAULT_CPU  13
 215         NvRegMSIMap0 = 0x020,
 216         NvRegMSIMap1 = 0x024,
 217         NvRegMSIIrqMask = 0x030,
 218 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 219         NvRegMisc1 = 0x080,
 220 #define NVREG_MISC1_PAUSE_TX    0x01
 221 #define NVREG_MISC1_HD          0x02
 222 #define NVREG_MISC1_FORCE       0x3b0f3c
 223
 224         NvRegMacReset = 0x3c,
 225 #define NVREG_MAC_RESET_ASSERT  0x0F3
 226         NvRegTransmitterControl = 0x084,
 227 #define NVREG_XMITCTL_START     0x01
 228 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 229 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 230 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 231 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 232 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 233 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 234 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 235 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 236 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 237 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 238         NvRegTransmitterStatus = 0x088,
 239 #define NVREG_XMITSTAT_BUSY     0x01
 240
 241         NvRegPacketFilterFlags = 0x8c,
 242 #define NVREG_PFF_PAUSE_RX      0x08
 243 #define NVREG_PFF_ALWAYS        0x7F0000
 244 #define NVREG_PFF_PROMISC       0x80
 245 #define NVREG_PFF_MYADDR        0x20
 246 #define NVREG_PFF_LOOPBACK      0x10
 247
 248         NvRegOffloadConfig = 0x90,
 249 #define NVREG_OFFLOAD_HOMEPHY   0x601
 250 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 251         NvRegReceiverControl = 0x094,
 252 #define NVREG_RCVCTL_START      0x01
 253 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 254         NvRegReceiverStatus = 0x98,
 255 #define NVREG_RCVSTAT_BUSY      0x01
 256
 257         NvRegRandomSeed = 0x9c,
 258 #define NVREG_RNDSEED_MASK      0x00ff
 259 #define NVREG_RNDSEED_FORCE     0x7f00
 260 #define NVREG_RNDSEED_FORCE2    0x2d00
 261 #define NVREG_RNDSEED_FORCE3    0x7400
 262
 263         NvRegTxDeferral = 0xA0,
 264 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 265 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 266 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 267         NvRegRxDeferral = 0xA4,
 268 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 269         NvRegMacAddrA = 0xA8,
 270         NvRegMacAddrB = 0xAC,
 271         NvRegMulticastAddrA = 0xB0,
 272 #define NVREG_MCASTADDRA_FORCE  0x01
 273         NvRegMulticastAddrB = 0xB4,
 274         NvRegMulticastMaskA = 0xB8,
 275         NvRegMulticastMaskB = 0xBC,
 276
 277         NvRegPhyInterface = 0xC0,
 278 #define PHY_RGMII               0x10000000
 279
 280         NvRegTxRingPhysAddr = 0x100,
 281         NvRegRxRingPhysAddr = 0x104,
 282         NvRegRingSizes = 0x108,
 283 #define NVREG_RINGSZ_TXSHIFT 0
 284 #define NVREG_RINGSZ_RXSHIFT 16
 285         NvRegTransmitPoll = 0x10c,
 286 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 287         NvRegLinkSpeed = 0x110,
 288 #define NVREG_LINKSPEED_FORCE 0x10000
 289 #define NVREG_LINKSPEED_10      1000
 290 #define NVREG_LINKSPEED_100     100
 291 #define NVREG_LINKSPEED_1000    50
 292 #define NVREG_LINKSPEED_MASK    (0xFFF)
 293         NvRegUnknownSetupReg5 = 0x130,
 294 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 295         NvRegTxWatermark = 0x13c,
 296 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 297 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 298 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 299         NvRegTxRxControl = 0x144,
 300 #define NVREG_TXRXCTL_KICK      0x0001
 301 #define NVREG_TXRXCTL_BIT1      0x0002
 302 #define NVREG_TXRXCTL_BIT2      0x0004
 303 #define NVREG_TXRXCTL_IDLE      0x0008
 304 #define NVREG_TXRXCTL_RESET     0x0010
 305 #define NVREG_TXRXCTL_RXCHECK   0x0400
 306 #define NVREG_TXRXCTL_DESC_1    0
 307 #define NVREG_TXRXCTL_DESC_2    0x002100
 308 #define NVREG_TXRXCTL_DESC_3    0xc02200
 309 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 310 #define NVREG_TXRXCTL_VLANINS   0x00080
 311         NvRegTxRingPhysAddrHigh = 0x148,
 312         NvRegRxRingPhysAddrHigh = 0x14C,
 313         NvRegTxPauseFrame = 0x170,
 314 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 315 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 316         NvRegMIIStatus = 0x180,
 317 #define NVREG_MIISTAT_ERROR             0x0001
 318 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 319 #define NVREG_MIISTAT_MASK              0x000f
 320 #define NVREG_MIISTAT_MASK2             0x000f
 321         NvRegMIIMask = 0x184,
 322 #define NVREG_MII_LINKCHANGE            0x0008
 323
 324         NvRegAdapterControl = 0x188,
 325 #define NVREG_ADAPTCTL_START    0x02
 326 #define NVREG_ADAPTCTL_LINKUP   0x04
 327 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 328 #define NVREG_ADAPTCTL_RUNNING  0x100000
 329 #define NVREG_ADAPTCTL_PHYSHIFT 24
 330         NvRegMIISpeed = 0x18c,
 331 #define NVREG_MIISPEED_BIT8     (1<<8)
 332 #define NVREG_MIIDELAY  5
 333         NvRegMIIControl = 0x190,
 334 #define NVREG_MIICTL_INUSE      0x08000
 335 #define NVREG_MIICTL_WRITE      0x00400
 336 #define NVREG_MIICTL_ADDRSHIFT  5
 337         NvRegMIIData = 0x194,
 338         NvRegWakeUpFlags = 0x200,
 339 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 340 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 341 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 342 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 343 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 344 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 345 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 346 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 347 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 348 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 349 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 350
 351         NvRegPatternCRC = 0x204,
 352         NvRegPatternMask = 0x208,
 353         NvRegPowerCap = 0x268,
 354 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 355 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 356 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 357         NvRegPowerState = 0x26c,
 358 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 359 #define NVREG_POWERSTATE_VALID          0x0100
 360 #define NVREG_POWERSTATE_MASK           0x0003
 361 #define NVREG_POWERSTATE_D0             0x0000
 362 #define NVREG_POWERSTATE_D1             0x0001
 363 #define NVREG_POWERSTATE_D2             0x0002
 364 #define NVREG_POWERSTATE_D3             0x0003
 365         NvRegTxCnt = 0x280,
 366         NvRegTxZeroReXmt = 0x284,
 367         NvRegTxOneReXmt = 0x288,
 368         NvRegTxManyReXmt = 0x28c,
 369         NvRegTxLateCol = 0x290,
 370         NvRegTxUnderflow = 0x294,
 371         NvRegTxLossCarrier = 0x298,
 372         NvRegTxExcessDef = 0x29c,
 373         NvRegTxRetryErr = 0x2a0,
 374         NvRegRxFrameErr = 0x2a4,
 375         NvRegRxExtraByte = 0x2a8,
 376         NvRegRxLateCol = 0x2ac,
 377         NvRegRxRunt = 0x2b0,
 378         NvRegRxFrameTooLong = 0x2b4,
 379         NvRegRxOverflow = 0x2b8,
 380         NvRegRxFCSErr = 0x2bc,
 381         NvRegRxFrameAlignErr = 0x2c0,
 382         NvRegRxLenErr = 0x2c4,
 383         NvRegRxUnicast = 0x2c8,
 384         NvRegRxMulticast = 0x2cc,
 385         NvRegRxBroadcast = 0x2d0,
 386         NvRegTxDef = 0x2d4,
 387         NvRegTxFrame = 0x2d8,
 388         NvRegRxCnt = 0x2dc,
 389         NvRegTxPause = 0x2e0,
 390         NvRegRxPause = 0x2e4,
 391         NvRegRxDropFrame = 0x2e8,
 392         NvRegVlanControl = 0x300,
 393 #define NVREG_VLANCONTROL_ENABLE        0x2000
 394         NvRegMSIXMap0 = 0x3e0,
 395         NvRegMSIXMap1 = 0x3e4,
 396         NvRegMSIXIrqStatus = 0x3f0,
 397
 398         NvRegPowerState2 = 0x600,
 399 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 400 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 401 };
 402
 403 /* Big endian: should work, but is untested */
 404 struct ring_desc {
 405         __le32 buf;
 406         __le32 flaglen;
 407 };
 408
 409 struct ring_desc_ex {
 410         __le32 bufhigh;
 411         __le32 buflow;
 412         __le32 txvlan;
 413         __le32 flaglen;
 414 };
 415
 416 union ring_type {
 417         struct ring_desc* orig;
 418         struct ring_desc_ex* ex;
 419 };
 420
 421 #define FLAG_MASK_V1 0xffff0000
 422 #define FLAG_MASK_V2 0xffffc000
 423 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 424 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 425
 426 #define NV_TX_LASTPACKET        (1<<16)
 427 #define NV_TX_RETRYERROR        (1<<19)
 428 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 429 #define NV_TX_DEFERRED          (1<<26)
 430 #define NV_TX_CARRIERLOST       (1<<27)
 431 #define NV_TX_LATECOLLISION     (1<<28)
 432 #define NV_TX_UNDERFLOW         (1<<29)
 433 #define NV_TX_ERROR             (1<<30)
 434 #define NV_TX_VALID             (1<<31)
 435
 436 #define NV_TX2_LASTPACKET       (1<<29)
 437 #define NV_TX2_RETRYERROR       (1<<18)
 438 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 439 #define NV_TX2_DEFERRED         (1<<25)
 440 #define NV_TX2_CARRIERLOST      (1<<26)
 441 #define NV_TX2_LATECOLLISION    (1<<27)
 442 #define NV_TX2_UNDERFLOW        (1<<28)
 443 /* error and valid are the same for both */
 444 #define NV_TX2_ERROR            (1<<30)
 445 #define NV_TX2_VALID            (1<<31)
 446 #define NV_TX2_TSO              (1<<28)
 447 #define NV_TX2_TSO_SHIFT        14
 448 #define NV_TX2_TSO_MAX_SHIFT    14
 449 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 450 #define NV_TX2_CHECKSUM_L3      (1<<27)
 451 #define NV_TX2_CHECKSUM_L4      (1<<26)
 452
 453 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 454
 455 #define NV_RX_DESCRIPTORVALID   (1<<16)
 456 #define NV_RX_MISSEDFRAME       (1<<17)
 457 #define NV_RX_SUBSTRACT1        (1<<18)
 458 #define NV_RX_ERROR1            (1<<23)
 459 #define NV_RX_ERROR2            (1<<24)
 460 #define NV_RX_ERROR3            (1<<25)
 461 #define NV_RX_ERROR4            (1<<26)
 462 #define NV_RX_CRCERR            (1<<27)
 463 #define NV_RX_OVERFLOW          (1<<28)
 464 #define NV_RX_FRAMINGERR        (1<<29)
 465 #define NV_RX_ERROR             (1<<30)
 466 #define NV_RX_AVAIL             (1<<31)
 467
 468 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 469 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 470 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 471 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 472 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 473 #define NV_RX2_SUBSTRACT1       (1<<25)
 474 #define NV_RX2_ERROR1           (1<<18)
 475 #define NV_RX2_ERROR2           (1<<19)
 476 #define NV_RX2_ERROR3           (1<<20)
 477 #define NV_RX2_ERROR4           (1<<21)
 478 #define NV_RX2_CRCERR           (1<<22)
 479 #define NV_RX2_OVERFLOW         (1<<23)
 480 #define NV_RX2_FRAMINGERR       (1<<24)
 481 /* error and avail are the same for both */
 482 #define NV_RX2_ERROR            (1<<30)
 483 #define NV_RX2_AVAIL            (1<<31)
 484
 485 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 486 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 487
 488 /* Miscelaneous hardware related defines: */
 489 #define NV_PCI_REGSZ_VER1       0x270
 490 #define NV_PCI_REGSZ_VER2       0x604
 491
 492 /* various timeout delays: all in usec */
 493 #define NV_TXRX_RESET_DELAY     4
 494 #define NV_TXSTOP_DELAY1        10
 495 #define NV_TXSTOP_DELAY1MAX     500000
 496 #define NV_TXSTOP_DELAY2        100
 497 #define NV_RXSTOP_DELAY1        10
 498 #define NV_RXSTOP_DELAY1MAX     500000
 499 #define NV_RXSTOP_DELAY2        100
 500 #define NV_SETUP5_DELAY         5
 501 #define NV_SETUP5_DELAYMAX      50000
 502 #define NV_POWERUP_DELAY        5
 503 #define NV_POWERUP_DELAYMAX     5000
 504 #define NV_MIIBUSY_DELAY        50
 505 #define NV_MIIPHY_DELAY 10
 506 #define NV_MIIPHY_DELAYMAX      10000
 507 #define NV_MAC_RESET_DELAY      64
 508
 509 #define NV_WAKEUPPATTERNS       5
 510 #define NV_WAKEUPMASKENTRIES    4
 511
 512 /* General driver defaults */
 513 #define NV_WATCHDOG_TIMEO       (5*HZ)
 514
 515 #define RX_RING_DEFAULT         128
 516 #define TX_RING_DEFAULT         256
 517 #define RX_RING_MIN             128
 518 #define TX_RING_MIN             64
 519 #define RING_MAX_DESC_VER_1     1024
 520 #define RING_MAX_DESC_VER_2_3   16384
 521 /*
 522  * Difference between the get and put pointers for the tx ring.
 523  * This is used to throttle the amount of data outstanding in the
 524  * tx ring.
 525  */
 526 #define TX_LIMIT_DIFFERENCE     1
 527
 528 /* rx/tx mac addr + type + vlan + align + slack*/
 529 #define NV_RX_HEADERS           (64)
 530 /* even more slack. */
 531 #define NV_RX_ALLOC_PAD         (64)
 532
 533 /* maximum mtu size */
 534 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 535 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 536
 537 #define OOM_REFILL      (1+HZ/20)
 538 #define POLL_WAIT       (1+HZ/100)
 539 #define LINK_TIMEOUT    (3*HZ)
 540 #define STATS_INTERVAL  (10*HZ)
 541
 542 /*
 543  * desc_ver values:
 544  * The nic supports three different descriptor types:
 545  * - DESC_VER_1: Original
 546  * - DESC_VER_2: support for jumbo frames.
 547  * - DESC_VER_3: 64-bit format.
 548  */
 549 #define DESC_VER_1      1
 550 #define DESC_VER_2      2
 551 #define DESC_VER_3      3
 552
 553 /* PHY defines */
 554 #define PHY_OUI_MARVELL 0x5043
 555 #define PHY_OUI_CICADA  0x03f1
 556 #define PHYID1_OUI_MASK 0x03ff
 557 #define PHYID1_OUI_SHFT 6
 558 #define PHYID2_OUI_MASK 0xfc00
 559 #define PHYID2_OUI_SHFT 10
 560 #define PHYID2_MODEL_MASK               0x03f0
 561 #define PHY_MODEL_MARVELL_E3016         0x220
 562 #define PHY_MARVELL_E3016_INITMASK      0x0300
 563 #define PHY_INIT1       0x0f000
 564 #define PHY_INIT2       0x0e00
 565 #define PHY_INIT3       0x01000
 566 #define PHY_INIT4       0x0200
 567 #define PHY_INIT5       0x0004
 568 #define PHY_INIT6       0x02000
 569 #define PHY_GIGABIT     0x0100
 570
 571 #define PHY_TIMEOUT     0x1
 572 #define PHY_ERROR       0x2
 573
 574 #define PHY_100 0x1
 575 #define PHY_1000        0x2
 576 #define PHY_HALF        0x100
 577
 578 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 579 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 580 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 581 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 582 #define NV_PAUSEFRAME_RX_REQ     0x0010
 583 #define NV_PAUSEFRAME_TX_REQ     0x0020
 584 #define NV_PAUSEFRAME_AUTONEG    0x0040
 585
 586 /* MSI/MSI-X defines */
 587 #define NV_MSI_X_MAX_VECTORS  8
 588 #define NV_MSI_X_VECTORS_MASK 0x000f
 589 #define NV_MSI_CAPABLE        0x0010
 590 #define NV_MSI_X_CAPABLE      0x0020
 591 #define NV_MSI_ENABLED        0x0040
 592 #define NV_MSI_X_ENABLED      0x0080
 593
 594 #define NV_MSI_X_VECTOR_ALL   0x0
 595 #define NV_MSI_X_VECTOR_RX    0x0
 596 #define NV_MSI_X_VECTOR_TX    0x1
 597 #define NV_MSI_X_VECTOR_OTHER 0x2
 598
 599 /* statistics */
 600 struct nv_ethtool_str {
 601         char name[ETH_GSTRING_LEN];
 602 };
 603
 604 static const struct nv_ethtool_str nv_estats_str[] = {
 605         { "tx_bytes" },
 606         { "tx_zero_rexmt" },
 607         { "tx_one_rexmt" },
 608         { "tx_many_rexmt" },
 609         { "tx_late_collision" },
 610         { "tx_fifo_errors" },
 611         { "tx_carrier_errors" },
 612         { "tx_excess_deferral" },
 613         { "tx_retry_error" },
 614         { "tx_deferral" },
 615         { "tx_packets" },
 616         { "tx_pause" },
 617         { "rx_frame_error" },
 618         { "rx_extra_byte" },
 619         { "rx_late_collision" },
 620         { "rx_runt" },
 621         { "rx_frame_too_long" },
 622         { "rx_over_errors" },
 623         { "rx_crc_errors" },
 624         { "rx_frame_align_error" },
 625         { "rx_length_error" },
 626         { "rx_unicast" },
 627         { "rx_multicast" },
 628         { "rx_broadcast" },
 629         { "rx_bytes" },
 630         { "rx_pause" },
 631         { "rx_drop_frame" },
 632         { "rx_packets" },
 633         { "rx_errors_total" }
 634 };
 635
 636 struct nv_ethtool_stats {
 637         u64 tx_bytes;
 638         u64 tx_zero_rexmt;
 639         u64 tx_one_rexmt;
 640         u64 tx_many_rexmt;
 641         u64 tx_late_collision;
 642         u64 tx_fifo_errors;
 643         u64 tx_carrier_errors;
 644         u64 tx_excess_deferral;
 645         u64 tx_retry_error;
 646         u64 tx_deferral;
 647         u64 tx_packets;
 648         u64 tx_pause;
 649         u64 rx_frame_error;
 650         u64 rx_extra_byte;
 651         u64 rx_late_collision;
 652         u64 rx_runt;
 653         u64 rx_frame_too_long;
 654         u64 rx_over_errors;
 655         u64 rx_crc_errors;
 656         u64 rx_frame_align_error;
 657         u64 rx_length_error;
 658         u64 rx_unicast;
 659         u64 rx_multicast;
 660         u64 rx_broadcast;
 661         u64 rx_bytes;
 662         u64 rx_pause;
 663         u64 rx_drop_frame;
 664         u64 rx_packets;
 665         u64 rx_errors_total;
 666 };
 667
 668 /* diagnostics */
 669 #define NV_TEST_COUNT_BASE 3
 670 #define NV_TEST_COUNT_EXTENDED 4
 671
 672 static const struct nv_ethtool_str nv_etests_str[] = {
 673         { "link      (online/offline)" },
 674         { "register  (offline)       " },
 675         { "interrupt (offline)       " },
 676         { "loopback  (offline)       " }
 677 };
 678
 679 struct register_test {
 680         __le32 reg;
 681         __le32 mask;
 682 };
 683
 684 static const struct register_test nv_registers_test[] = {
 685         { NvRegUnknownSetupReg6, 0x01 },
 686         { NvRegMisc1, 0x03c },
 687         { NvRegOffloadConfig, 0x03ff },
 688         { NvRegMulticastAddrA, 0xffffffff },
 689         { NvRegTxWatermark, 0x0ff },
 690         { NvRegWakeUpFlags, 0x07777 },
 691         { 0,0 }
 692 };
 693
 694 struct nv_skb_map {
 695         struct sk_buff *skb;
 696         dma_addr_t dma;
 697         unsigned int dma_len;
 698 };
 699
 700 /*
 701  * SMP locking:
 702  * All hardware access under dev->priv->lock, except the performance
 703  * critical parts:
 704  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 705  *      by the arch code for interrupts.
 706  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 707  *      needs dev->priv->lock :-(
 708  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 709  */
 710
 711 /* in dev: base, irq */
 712 struct fe_priv {
 713         spinlock_t lock;
 714
 715         /* General data:
 716          * Locking: spin_lock(&np->lock); */
 717         struct net_device_stats stats;
 718         struct nv_ethtool_stats estats;
 719         int in_shutdown;
 720         u32 linkspeed;
 721         int duplex;
 722         int autoneg;
 723         int fixed_mode;
 724         int phyaddr;
 725         int wolenabled;
 726         unsigned int phy_oui;
 727         unsigned int phy_model;
 728         u16 gigabit;
 729         int intr_test;
 730         int recover_error;
 731
 732         /* General data: RO fields */
 733         dma_addr_t ring_addr;
 734         struct pci_dev *pci_dev;
 735         u32 orig_mac[2];
 736         u32 irqmask;
 737         u32 desc_ver;
 738         u32 txrxctl_bits;
 739         u32 vlanctl_bits;
 740         u32 driver_data;
 741         u32 register_size;
 742         int rx_csum;
 743         u32 mac_in_use;
 744
 745         void __iomem *base;
 746
 747         /* rx specific fields.
 748          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 749          */
 750         union ring_type get_rx, put_rx, first_rx, last_rx;
 751         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 752         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 753         struct nv_skb_map *rx_skb;
 754
 755         union ring_type rx_ring;
 756         unsigned int rx_buf_sz;
 757         unsigned int pkt_limit;
 758         struct timer_list oom_kick;
 759         struct timer_list nic_poll;
 760         struct timer_list stats_poll;
 761         u32 nic_poll_irq;
 762         int rx_ring_size;
 763
 764         /* media detection workaround.
 765          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 766          */
 767         int need_linktimer;
 768         unsigned long link_timeout;
 769         /*
 770          * tx specific fields.
 771          */
 772         union ring_type get_tx, put_tx, first_tx, last_tx;
 773         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 774         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 775         struct nv_skb_map *tx_skb;
 776
 777         union ring_type tx_ring;
 778         u32 tx_flags;
 779         int tx_ring_size;
 780         int tx_limit_start;
 781         int tx_limit_stop;
 782
 783         /* vlan fields */
 784         struct vlan_group *vlangrp;
 785
 786         /* msi/msi-x fields */
 787         u32 msi_flags;
 788         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 789
 790         /* flow control */
 791         u32 pause_flags;
 792 };
 793
 794 /*
 795  * Maximum number of loops until we assume that a bit in the irq mask
 796  * is stuck. Overridable with module param.
 797  */
 798 static int max_interrupt_work = 5;
 799
 800 /*
 801  * Optimization can be either throuput mode or cpu mode
 802  *
 803  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 804  * CPU Mode: Interrupts are controlled by a timer.
 805  */
 806 enum {
 807         NV_OPTIMIZATION_MODE_THROUGHPUT,
 808         NV_OPTIMIZATION_MODE_CPU
 809 };
 810 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 811
 812 /*
 813  * Poll interval for timer irq
 814  *
 815  * This interval determines how frequent an interrupt is generated.
 816  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 817  * Min = 0, and Max = 65535
 818  */
 819 static int poll_interval = -1;
 820
 821 /*
 822  * MSI interrupts
 823  */
 824 enum {
 825         NV_MSI_INT_DISABLED,
 826         NV_MSI_INT_ENABLED
 827 };
 828 static int msi = NV_MSI_INT_ENABLED;
 829
 830 /*
 831  * MSIX interrupts
 832  */
 833 enum {
 834         NV_MSIX_INT_DISABLED,
 835         NV_MSIX_INT_ENABLED
 836 };
 837 static int msix = NV_MSIX_INT_ENABLED;
 838
 839 /*
 840  * DMA 64bit
 841  */
 842 enum {
 843         NV_DMA_64BIT_DISABLED,
 844         NV_DMA_64BIT_ENABLED
 845 };
 846 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 847
 848 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 849 {
 850         return netdev_priv(dev);
 851 }
 852
 853 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 854 {
 855         return ((struct fe_priv *)netdev_priv(dev))->base;
 856 }
 857
 858 static inline void pci_push(u8 __iomem *base)
 859 {
 860         /* force out pending posted writes */
 861         readl(base);
 862 }
 863
 864 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 865 {
 866         return le32_to_cpu(prd->flaglen)
 867                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 868 }
 869
 870 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 871 {
 872         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 873 }
 874
 875 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 876                                 int delay, int delaymax, const char *msg)
 877 {
 878         u8 __iomem *base = get_hwbase(dev);
 879
 880         pci_push(base);
 881         do {
 882                 udelay(delay);
 883                 delaymax -= delay;
 884                 if (delaymax < 0) {
 885                         if (msg)
 886                                 printk(msg);
 887                         return 1;
 888                 }
 889         } while ((readl(base + offset) & mask) != target);
 890         return 0;
 891 }
 892
 893 #define NV_SETUP_RX_RING 0x01
 894 #define NV_SETUP_TX_RING 0x02
 895
 896 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 897 {
 898         struct fe_priv *np = get_nvpriv(dev);
 899         u8 __iomem *base = get_hwbase(dev);
 900
 901         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 902                 if (rxtx_flags & NV_SETUP_RX_RING) {
 903                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 904                 }
 905                 if (rxtx_flags & NV_SETUP_TX_RING) {
 906                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 907                 }
 908         } else {
 909                 if (rxtx_flags & NV_SETUP_RX_RING) {
 910                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 911                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 912                 }
 913                 if (rxtx_flags & NV_SETUP_TX_RING) {
 914                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 915                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 916                 }
 917         }
 918 }
 919
 920 static void free_rings(struct net_device *dev)
 921 {
 922         struct fe_priv *np = get_nvpriv(dev);
 923
 924         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 925                 if (np->rx_ring.orig)
 926                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 927                                             np->rx_ring.orig, np->ring_addr);
 928         } else {
 929                 if (np->rx_ring.ex)
 930                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 931                                             np->rx_ring.ex, np->ring_addr);
 932         }
 933         if (np->rx_skb)
 934                 kfree(np->rx_skb);
 935         if (np->tx_skb)
 936                 kfree(np->tx_skb);
 937 }
 938
 939 static int using_multi_irqs(struct net_device *dev)
 940 {
 941         struct fe_priv *np = get_nvpriv(dev);
 942
 943         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 944             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 945              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 946                 return 0;
 947         else
 948                 return 1;
 949 }
 950
 951 static void nv_enable_irq(struct net_device *dev)
 952 {
 953         struct fe_priv *np = get_nvpriv(dev);
 954
 955         if (!using_multi_irqs(dev)) {
 956                 if (np->msi_flags & NV_MSI_X_ENABLED)
 957                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 958                 else
 959                         enable_irq(dev->irq);
 960         } else {
 961                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 962                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 963                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 964         }
 965 }
 966
 967 static void nv_disable_irq(struct net_device *dev)
 968 {
 969         struct fe_priv *np = get_nvpriv(dev);
 970
 971         if (!using_multi_irqs(dev)) {
 972                 if (np->msi_flags & NV_MSI_X_ENABLED)
 973                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 974                 else
 975                         disable_irq(dev->irq);
 976         } else {
 977                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 978                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 979                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 980         }
 981 }
 982
 983 /* In MSIX mode, a write to irqmask behaves as XOR */
 984 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 985 {
 986         u8 __iomem *base = get_hwbase(dev);
 987
 988         writel(mask, base + NvRegIrqMask);
 989 }
 990
 991 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 992 {
 993         struct fe_priv *np = get_nvpriv(dev);
 994         u8 __iomem *base = get_hwbase(dev);
 995
 996         if (np->msi_flags & NV_MSI_X_ENABLED) {
 997                 writel(mask, base + NvRegIrqMask);
 998         } else {
 999                 if (np->msi_flags & NV_MSI_ENABLED)
1000                         writel(0, base + NvRegMSIIrqMask);
1001                 writel(0, base + NvRegIrqMask);
1002         }
1003 }
1004
1005 #define MII_READ        (-1)
1006 /* mii_rw: read/write a register on the PHY.
1007  *
1008  * Caller must guarantee serialization
1009  */
1010 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1011 {
1012         u8 __iomem *base = get_hwbase(dev);
1013         u32 reg;
1014         int retval;
1015
1016         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1017
1018         reg = readl(base + NvRegMIIControl);
1019         if (reg & NVREG_MIICTL_INUSE) {
1020                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1021                 udelay(NV_MIIBUSY_DELAY);
1022         }
1023
1024         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1025         if (value != MII_READ) {
1026                 writel(value, base + NvRegMIIData);
1027                 reg |= NVREG_MIICTL_WRITE;
1028         }
1029         writel(reg, base + NvRegMIIControl);
1030
1031         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1032                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1033                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1034                                 dev->name, miireg, addr);
1035                 retval = -1;
1036         } else if (value != MII_READ) {
1037                 /* it was a write operation - fewer failures are detectable */
1038                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1039                                 dev->name, value, miireg, addr);
1040                 retval = 0;
1041         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1042                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1043                                 dev->name, miireg, addr);
1044                 retval = -1;
1045         } else {
1046                 retval = readl(base + NvRegMIIData);
1047                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1048                                 dev->name, miireg, addr, retval);
1049         }
1050
1051         return retval;
1052 }
1053
1054 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1055 {
1056         struct fe_priv *np = netdev_priv(dev);
1057         u32 miicontrol;
1058         unsigned int tries = 0;
1059
1060         miicontrol = BMCR_RESET | bmcr_setup;
1061         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1062                 return -1;
1063         }
1064
1065         /* wait for 500ms */
1066         msleep(500);
1067
1068         /* must wait till reset is deasserted */
1069         while (miicontrol & BMCR_RESET) {
1070                 msleep(10);
1071                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1072                 /* FIXME: 100 tries seem excessive */
1073                 if (tries++ > 100)
1074                         return -1;
1075         }
1076         return 0;
1077 }
1078
1079 static int phy_init(struct net_device *dev)
1080 {
1081         struct fe_priv *np = get_nvpriv(dev);
1082         u8 __iomem *base = get_hwbase(dev);
1083         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1084
1085         /* phy errata for E3016 phy */
1086         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1087                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1088                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1089                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1090                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1091                         return PHY_ERROR;
1092                 }
1093         }
1094
1095         /* set advertise register */
1096         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1097         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1098         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1099                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1100                 return PHY_ERROR;
1101         }
1102
1103         /* get phy interface type */
1104         phyinterface = readl(base + NvRegPhyInterface);
1105
1106         /* see if gigabit phy */
1107         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1108         if (mii_status & PHY_GIGABIT) {
1109                 np->gigabit = PHY_GIGABIT;
1110                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1111                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1112                 if (phyinterface & PHY_RGMII)
1113                         mii_control_1000 |= ADVERTISE_1000FULL;
1114                 else
1115                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1116
1117                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1118                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1119                         return PHY_ERROR;
1120                 }
1121         }
1122         else
1123                 np->gigabit = 0;
1124
1125         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1126         mii_control |= BMCR_ANENABLE;
1127
1128         /* reset the phy
1129          * (certain phys need bmcr to be setup with reset)
1130          */
1131         if (phy_reset(dev, mii_control)) {
1132                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1133                 return PHY_ERROR;
1134         }
1135
1136         /* phy vendor specific configuration */
1137         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1138                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1139                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1140                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1141                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1142                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1143                         return PHY_ERROR;
1144                 }
1145                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1146                 phy_reserved |= PHY_INIT5;
1147                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1148                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1149                         return PHY_ERROR;
1150                 }
1151         }
1152         if (np->phy_oui == PHY_OUI_CICADA) {
1153                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1154                 phy_reserved |= PHY_INIT6;
1155                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1156                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1157                         return PHY_ERROR;
1158                 }
1159         }
1160         /* some phys clear out pause advertisment on reset, set it back */
1161         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1162
1163         /* restart auto negotiation */
1164         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1165         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1166         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1167                 return PHY_ERROR;
1168         }
1169
1170         return 0;
1171 }
1172
1173 static void nv_start_rx(struct net_device *dev)
1174 {
1175         struct fe_priv *np = netdev_priv(dev);
1176         u8 __iomem *base = get_hwbase(dev);
1177         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1178
1179         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1180         /* Already running? Stop it. */
1181         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1182                 rx_ctrl &= ~NVREG_RCVCTL_START;
1183                 writel(rx_ctrl, base + NvRegReceiverControl);
1184                 pci_push(base);
1185         }
1186         writel(np->linkspeed, base + NvRegLinkSpeed);
1187         pci_push(base);
1188         rx_ctrl |= NVREG_RCVCTL_START;
1189         if (np->mac_in_use)
1190                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1191         writel(rx_ctrl, base + NvRegReceiverControl);
1192         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1193                                 dev->name, np->duplex, np->linkspeed);
1194         pci_push(base);
1195 }
1196
1197 static void nv_stop_rx(struct net_device *dev)
1198 {
1199         struct fe_priv *np = netdev_priv(dev);
1200         u8 __iomem *base = get_hwbase(dev);
1201         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1202
1203         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1204         if (!np->mac_in_use)
1205                 rx_ctrl &= ~NVREG_RCVCTL_START;
1206         else
1207                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1208         writel(rx_ctrl, base + NvRegReceiverControl);
1209         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1210                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1211                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1212
1213         udelay(NV_RXSTOP_DELAY2);
1214         if (!np->mac_in_use)
1215                 writel(0, base + NvRegLinkSpeed);
1216 }
1217
1218 static void nv_start_tx(struct net_device *dev)
1219 {
1220         struct fe_priv *np = netdev_priv(dev);
1221         u8 __iomem *base = get_hwbase(dev);
1222         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1223
1224         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1225         tx_ctrl |= NVREG_XMITCTL_START;
1226         if (np->mac_in_use)
1227                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1228         writel(tx_ctrl, base + NvRegTransmitterControl);
1229         pci_push(base);
1230 }
1231
1232 static void nv_stop_tx(struct net_device *dev)
1233 {
1234         struct fe_priv *np = netdev_priv(dev);
1235         u8 __iomem *base = get_hwbase(dev);
1236         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1237
1238         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1239         if (!np->mac_in_use)
1240                 tx_ctrl &= ~NVREG_XMITCTL_START;
1241         else
1242                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1243         writel(tx_ctrl, base + NvRegTransmitterControl);
1244         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1245                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1246                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1247
1248         udelay(NV_TXSTOP_DELAY2);
1249         if (!np->mac_in_use)
1250                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1251                        base + NvRegTransmitPoll);
1252 }
1253
1254 static void nv_txrx_reset(struct net_device *dev)
1255 {
1256         struct fe_priv *np = netdev_priv(dev);
1257         u8 __iomem *base = get_hwbase(dev);
1258
1259         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1260         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1261         pci_push(base);
1262         udelay(NV_TXRX_RESET_DELAY);
1263         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1264         pci_push(base);
1265 }
1266
1267 static void nv_mac_reset(struct net_device *dev)
1268 {
1269         struct fe_priv *np = netdev_priv(dev);
1270         u8 __iomem *base = get_hwbase(dev);
1271
1272         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1273         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1274         pci_push(base);
1275         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1276         pci_push(base);
1277         udelay(NV_MAC_RESET_DELAY);
1278         writel(0, base + NvRegMacReset);
1279         pci_push(base);
1280         udelay(NV_MAC_RESET_DELAY);
1281         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1282         pci_push(base);
1283 }
1284
1285 /*
1286  * nv_get_stats: dev->get_stats function
1287  * Get latest stats value from the nic.
1288  * Called with read_lock(&dev_base_lock) held for read -
1289  * only synchronized against unregister_netdevice.
1290  */
1291 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1292 {
1293         struct fe_priv *np = netdev_priv(dev);
1294
1295         /* It seems that the nic always generates interrupts and doesn't
1296          * accumulate errors internally. Thus the current values in np->stats
1297          * are already up to date.
1298          */
1299         return &np->stats;
1300 }
1301
1302 /*
1303  * nv_alloc_rx: fill rx ring entries.
1304  * Return 1 if the allocations for the skbs failed and the
1305  * rx engine is without Available descriptors
1306  */
1307 static int nv_alloc_rx(struct net_device *dev)
1308 {
1309         struct fe_priv *np = netdev_priv(dev);
1310         union ring_type less_rx;
1311
1312         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1313                 less_rx.orig = np->get_rx.orig;
1314                 if (less_rx.orig-- == np->first_rx.orig)
1315                         less_rx.orig = np->last_rx.orig;
1316         } else {
1317                 less_rx.ex = np->get_rx.ex;
1318                 if (less_rx.ex-- == np->first_rx.ex)
1319                         less_rx.ex = np->last_rx.ex;
1320         }
1321
1322         while (1) {
1323                 struct sk_buff *skb;
1324
1325                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1326                         if (np->put_rx.orig == less_rx.orig)
1327                                 break;
1328                 } else {
1329                         if (np->put_rx.ex == less_rx.ex)
1330                                 break;
1331                 }
1332
1333                 if (np->put_rx_ctx->skb == NULL) {
1334
1335                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1336                         if (!skb)
1337                                 return 1;
1338
1339                         skb->dev = dev;
1340                         np->put_rx_ctx->skb = skb;
1341                 } else {
1342                         skb = np->put_rx_ctx->skb;
1343                 }
1344                 np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1345                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
1346                 np->put_rx_ctx->dma_len = skb->end-skb->data;
1347                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1348                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1349                         wmb();
1350                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1351                         if (np->put_rx.orig++ == np->last_rx.orig)
1352                                 np->put_rx.orig = np->first_rx.orig;
1353                 } else {
1354                         np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
1355                         np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
1356                         wmb();
1357                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1358                         if (np->put_rx.ex++ == np->last_rx.ex)
1359                                 np->put_rx.ex = np->first_rx.ex;
1360                 }
1361                 if (np->put_rx_ctx++ == np->last_rx_ctx)
1362                         np->put_rx_ctx = np->first_rx_ctx;
1363         }
1364         return 0;
1365 }
1366
1367 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1368 #ifdef CONFIG_FORCEDETH_NAPI
1369 static void nv_do_rx_refill(unsigned long data)
1370 {
1371         struct net_device *dev = (struct net_device *) data;
1372
1373         /* Just reschedule NAPI rx processing */
1374         netif_rx_schedule(dev);
1375 }
1376 #else
1377 static void nv_do_rx_refill(unsigned long data)
1378 {
1379         struct net_device *dev = (struct net_device *) data;
1380         struct fe_priv *np = netdev_priv(dev);
1381
1382         if (!using_multi_irqs(dev)) {
1383                 if (np->msi_flags & NV_MSI_X_ENABLED)
1384                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1385                 else
1386                         disable_irq(dev->irq);
1387         } else {
1388                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1389         }
1390         if (nv_alloc_rx(dev)) {
1391                 spin_lock_irq(&np->lock);
1392                 if (!np->in_shutdown)
1393                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1394                 spin_unlock_irq(&np->lock);
1395         }
1396         if (!using_multi_irqs(dev)) {
1397                 if (np->msi_flags & NV_MSI_X_ENABLED)
1398                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1399                 else
1400                         enable_irq(dev->irq);
1401         } else {
1402                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1403         }
1404 }
1405 #endif
1406
1407 static void nv_init_rx(struct net_device *dev)
1408 {
1409         struct fe_priv *np = netdev_priv(dev);
1410         int i;
1411         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1412         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1413                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1414         else
1415                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1416         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1417         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1418
1419         for (i = 0; i < np->rx_ring_size; i++) {
1420                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1421                         np->rx_ring.orig[i].flaglen = 0;
1422                         np->rx_ring.orig[i].buf = 0;
1423                 } else {
1424                         np->rx_ring.ex[i].flaglen = 0;
1425                         np->rx_ring.ex[i].txvlan = 0;
1426                         np->rx_ring.ex[i].bufhigh = 0;
1427                         np->rx_ring.ex[i].buflow = 0;
1428                 }
1429                 np->rx_skb[i].skb = NULL;
1430                 np->rx_skb[i].dma = 0;
1431         }
1432 }
1433
1434 static void nv_init_tx(struct net_device *dev)
1435 {
1436         struct fe_priv *np = netdev_priv(dev);
1437         int i;
1438         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1439         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1440                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1441         else
1442                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1443         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1444         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1445
1446         for (i = 0; i < np->tx_ring_size; i++) {
1447                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1448                         np->tx_ring.orig[i].flaglen = 0;
1449                         np->tx_ring.orig[i].buf = 0;
1450                 } else {
1451                         np->tx_ring.ex[i].flaglen = 0;
1452                         np->tx_ring.ex[i].txvlan = 0;
1453                         np->tx_ring.ex[i].bufhigh = 0;
1454                         np->tx_ring.ex[i].buflow = 0;
1455                 }
1456                 np->tx_skb[i].skb = NULL;
1457                 np->tx_skb[i].dma = 0;
1458         }
1459 }
1460
1461 static int nv_init_ring(struct net_device *dev)
1462 {
1463         nv_init_tx(dev);
1464         nv_init_rx(dev);
1465         return nv_alloc_rx(dev);
1466 }
1467
1468 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1469 {
1470         struct fe_priv *np = netdev_priv(dev);
1471
1472         if (tx_skb->dma) {
1473                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1474                                tx_skb->dma_len,
1475                                PCI_DMA_TODEVICE);
1476                 tx_skb->dma = 0;
1477         }
1478         if (tx_skb->skb) {
1479                 dev_kfree_skb_any(tx_skb->skb);
1480                 tx_skb->skb = NULL;
1481                 return 1;
1482         } else {
1483                 return 0;
1484         }
1485 }
1486
1487 static void nv_drain_tx(struct net_device *dev)
1488 {
1489         struct fe_priv *np = netdev_priv(dev);
1490         unsigned int i;
1491
1492         for (i = 0; i < np->tx_ring_size; i++) {
1493                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1494                         np->tx_ring.orig[i].flaglen = 0;
1495                         np->tx_ring.orig[i].buf = 0;
1496                 } else {
1497                         np->tx_ring.ex[i].flaglen = 0;
1498                         np->tx_ring.ex[i].txvlan = 0;
1499                         np->tx_ring.ex[i].bufhigh = 0;
1500                         np->tx_ring.ex[i].buflow = 0;
1501                 }
1502                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1503                         np->stats.tx_dropped++;
1504         }
1505 }
1506
1507 static void nv_drain_rx(struct net_device *dev)
1508 {
1509         struct fe_priv *np = netdev_priv(dev);
1510         int i;
1511
1512         for (i = 0; i < np->rx_ring_size; i++) {
1513                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1514                         np->rx_ring.orig[i].flaglen = 0;
1515                         np->rx_ring.orig[i].buf = 0;
1516                 } else {
1517                         np->rx_ring.ex[i].flaglen = 0;
1518                         np->rx_ring.ex[i].txvlan = 0;
1519                         np->rx_ring.ex[i].bufhigh = 0;
1520                         np->rx_ring.ex[i].buflow = 0;
1521                 }
1522                 wmb();
1523                 if (np->rx_skb[i].skb) {
1524                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1525                                                 np->rx_skb[i].skb->end-np->rx_skb[i].skb->data,
1526                                                 PCI_DMA_FROMDEVICE);
1527                         dev_kfree_skb(np->rx_skb[i].skb);
1528                         np->rx_skb[i].skb = NULL;
1529                 }
1530         }
1531 }
1532
1533 static void drain_ring(struct net_device *dev)
1534 {
1535         nv_drain_tx(dev);
1536         nv_drain_rx(dev);
1537 }
1538
1539 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1540 {
1541         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1542 }
1543
1544 /*
1545  * nv_start_xmit: dev->hard_start_xmit function
1546  * Called with netif_tx_lock held.
1547  */
1548 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1549 {
1550         struct fe_priv *np = netdev_priv(dev);
1551         u32 tx_flags = 0;
1552         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1553         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1554         unsigned int i;
1555         u32 offset = 0;
1556         u32 bcnt;
1557         u32 size = skb->len-skb->data_len;
1558         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1559         u32 empty_slots;
1560         u32 tx_flags_vlan = 0;
1561         union ring_type put_tx;
1562         union ring_type start_tx;
1563         union ring_type prev_tx;
1564         struct nv_skb_map* prev_tx_ctx;
1565
1566         /* add fragments to entries count */
1567         for (i = 0; i < fragments; i++) {
1568                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1569                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1570         }
1571
1572         spin_lock_irq(&np->lock);
1573
1574         empty_slots = nv_get_empty_tx_slots(np);
1575         if ((empty_slots - np->tx_limit_stop) <= entries) {
1576                 spin_unlock_irq(&np->lock);
1577                 netif_stop_queue(dev);
1578                 return NETDEV_TX_BUSY;
1579         }
1580
1581         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1582                 start_tx.orig = put_tx.orig = np->put_tx.orig;
1583         else
1584                 start_tx.ex = put_tx.ex = np->put_tx.ex;
1585
1586         /* setup the header buffer */
1587         do {
1588                 prev_tx = put_tx;
1589                 prev_tx_ctx = np->put_tx_ctx;
1590                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1591                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1592                                                 PCI_DMA_TODEVICE);
1593                 np->put_tx_ctx->dma_len = bcnt;
1594                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1595                         put_tx.orig->buf = cpu_to_le32(np->put_tx_ctx->dma);
1596                         put_tx.orig->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1597                 } else {
1598                         put_tx.ex->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1599                         put_tx.ex->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1600                         put_tx.ex->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1601                 }
1602                 tx_flags = np->tx_flags;
1603                 offset += bcnt;
1604                 size -= bcnt;
1605                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1606                         if (put_tx.orig++ == np->last_tx.orig)
1607                                 put_tx.orig = np->first_tx.orig;
1608                 } else {
1609                         if (put_tx.ex++ == np->last_tx.ex)
1610                                 put_tx.ex = np->first_tx.ex;
1611                 }
1612                 if (np->put_tx_ctx++ == np->last_tx_ctx)
1613                         np->put_tx_ctx = np->first_tx_ctx;
1614         } while (size);
1615
1616         /* setup the fragments */
1617         for (i = 0; i < fragments; i++) {
1618                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1619                 u32 size = frag->size;
1620                 offset = 0;
1621
1622                 do {
1623                         prev_tx = put_tx;
1624                         prev_tx_ctx = np->put_tx_ctx;
1625                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1626                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1627                                                            PCI_DMA_TODEVICE);
1628                         np->put_tx_ctx->dma_len = bcnt;
1629
1630                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1631                                 put_tx.orig->buf = cpu_to_le32(np->put_tx_ctx->dma);
1632                                 put_tx.orig->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1633                         } else {
1634                                 put_tx.ex->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1635                                 put_tx.ex->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1636                                 put_tx.ex->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1637                         }
1638                         offset += bcnt;
1639                         size -= bcnt;
1640                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1641                                 if (put_tx.orig++ == np->last_tx.orig)
1642                                         put_tx.orig = np->first_tx.orig;
1643                         } else {
1644                                 if (put_tx.ex++ == np->last_tx.ex)
1645                                         put_tx.ex = np->first_tx.ex;
1646                         }
1647                         if (np->put_tx_ctx++ == np->last_tx_ctx)
1648                                 np->put_tx_ctx = np->first_tx_ctx;
1649                 } while (size);
1650         }
1651
1652         /* set last fragment flag  */
1653         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1654                 prev_tx.orig->flaglen |= cpu_to_le32(tx_flags_extra);
1655         else
1656                 prev_tx.ex->flaglen |= cpu_to_le32(tx_flags_extra);
1657
1658         /* save skb in this slot's context area */
1659         prev_tx_ctx->skb = skb;
1660
1661         if (skb_is_gso(skb))
1662                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1663         else
1664                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1665                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1666
1667         /* vlan tag */
1668         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1669                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1670         }
1671
1672         /* set tx flags */
1673         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1674                 start_tx.orig->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1675                 np->put_tx.orig = put_tx.orig;
1676         } else {
1677                 start_tx.ex->txvlan = cpu_to_le32(tx_flags_vlan);
1678                 start_tx.ex->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1679                 np->put_tx.ex = put_tx.ex;
1680         }
1681
1682
1683         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1684                 dev->name, entries, tx_flags_extra);
1685         {
1686                 int j;
1687                 for (j=0; j<64; j++) {
1688                         if ((j%16) == 0)
1689                                 dprintk("\n%03x:", j);
1690                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1691                 }
1692                 dprintk("\n");
1693         }
1694
1695         dev->trans_start = jiffies;
1696         spin_unlock_irq(&np->lock);
1697         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1698         pci_push(get_hwbase(dev));
1699         return NETDEV_TX_OK;
1700 }
1701
1702 /*
1703  * nv_tx_done: check for completed packets, release the skbs.
1704  *
1705  * Caller must own np->lock.
1706  */
1707 static void nv_tx_done(struct net_device *dev)
1708 {
1709         struct fe_priv *np = netdev_priv(dev);
1710         u32 flags;
1711         struct sk_buff *skb;
1712
1713         while (1) {
1714                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1715                         if (np->get_tx.orig == np->put_tx.orig)
1716                                 break;
1717                         flags = le32_to_cpu(np->get_tx.orig->flaglen);
1718                 } else {
1719                         if (np->get_tx.ex == np->put_tx.ex)
1720                                 break;
1721                         flags = le32_to_cpu(np->get_tx.ex->flaglen);
1722                 }
1723
1724                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
1725                                         dev->name, flags);
1726                 if (flags & NV_TX_VALID)
1727                         break;
1728                 if (np->desc_ver == DESC_VER_1) {
1729                         if (flags & NV_TX_LASTPACKET) {
1730                                 skb = np->get_tx_ctx->skb;
1731                                 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1732                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1733                                         if (flags & NV_TX_UNDERFLOW)
1734                                                 np->stats.tx_fifo_errors++;
1735                                         if (flags & NV_TX_CARRIERLOST)
1736                                                 np->stats.tx_carrier_errors++;
1737                                         np->stats.tx_errors++;
1738                                 } else {
1739                                         np->stats.tx_packets++;
1740                                         np->stats.tx_bytes += skb->len;
1741                                 }
1742                         }
1743                 } else {
1744                         if (flags & NV_TX2_LASTPACKET) {
1745                                 skb = np->get_tx_ctx->skb;
1746                                 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1747                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1748                                         if (flags & NV_TX2_UNDERFLOW)
1749                                                 np->stats.tx_fifo_errors++;
1750                                         if (flags & NV_TX2_CARRIERLOST)
1751                                                 np->stats.tx_carrier_errors++;
1752                                         np->stats.tx_errors++;
1753                                 } else {
1754                                         np->stats.tx_packets++;
1755                                         np->stats.tx_bytes += skb->len;
1756                                 }
1757                         }
1758                 }
1759                 nv_release_txskb(dev, np->get_tx_ctx);
1760                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1761                         if (np->get_tx.orig++ == np->last_tx.orig)
1762                                 np->get_tx.orig = np->first_tx.orig;
1763                 } else {
1764                         if (np->get_tx.ex++ == np->last_tx.ex)
1765                                 np->get_tx.ex = np->first_tx.ex;
1766                 }
1767                 if (np->get_tx_ctx++ == np->last_tx_ctx)
1768                         np->get_tx_ctx = np->first_tx_ctx;
1769         }
1770         if (nv_get_empty_tx_slots(np) > np->tx_limit_start)
1771                 netif_wake_queue(dev);
1772 }
1773
1774 /*
1775  * nv_tx_timeout: dev->tx_timeout function
1776  * Called with netif_tx_lock held.
1777  */
1778 static void nv_tx_timeout(struct net_device *dev)
1779 {
1780         struct fe_priv *np = netdev_priv(dev);
1781         u8 __iomem *base = get_hwbase(dev);
1782         u32 status;
1783
1784         if (np->msi_flags & NV_MSI_X_ENABLED)
1785                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1786         else
1787                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1788
1789         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1790
1791         {
1792                 int i;
1793
1794                 printk(KERN_INFO "%s: Ring at %lx\n",
1795                        dev->name, (unsigned long)np->ring_addr);
1796                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1797                 for (i=0;i<=np->register_size;i+= 32) {
1798                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1799                                         i,
1800                                         readl(base + i + 0), readl(base + i + 4),
1801                                         readl(base + i + 8), readl(base + i + 12),
1802                                         readl(base + i + 16), readl(base + i + 20),
1803                                         readl(base + i + 24), readl(base + i + 28));
1804                 }
1805                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1806                 for (i=0;i<np->tx_ring_size;i+= 4) {
1807                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1808                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1809                                        i,
1810                                        le32_to_cpu(np->tx_ring.orig[i].buf),
1811                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
1812                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
1813                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1814                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
1815                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1816                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
1817                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1818                         } else {
1819                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1820                                        i,
1821                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1822                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
1823                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
1824                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1825                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1826                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1827                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1828                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1829                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1830                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1831                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1832                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1833                         }
1834                 }
1835         }
1836
1837         spin_lock_irq(&np->lock);
1838
1839         /* 1) stop tx engine */
1840         nv_stop_tx(dev);
1841
1842         /* 2) check that the packets were not sent already: */
1843         nv_tx_done(dev);
1844
1845         /* 3) if there are dead entries: clear everything */
1846         if (np->get_tx_ctx != np->put_tx_ctx) {
1847                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1848                 nv_drain_tx(dev);
1849                 nv_init_tx(dev);
1850                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1851                 netif_wake_queue(dev);
1852         }
1853
1854         /* 4) restart tx engine */
1855         nv_start_tx(dev);
1856         spin_unlock_irq(&np->lock);
1857 }
1858
1859 /*
1860  * Called when the nic notices a mismatch between the actual data len on the
1861  * wire and the len indicated in the 802 header
1862  */
1863 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1864 {
1865         int hdrlen;     /* length of the 802 header */
1866         int protolen;   /* length as stored in the proto field */
1867
1868         /* 1) calculate len according to header */
1869         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
1870                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1871                 hdrlen = VLAN_HLEN;
1872         } else {
1873                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1874                 hdrlen = ETH_HLEN;
1875         }
1876         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1877                                 dev->name, datalen, protolen, hdrlen);
1878         if (protolen > ETH_DATA_LEN)
1879                 return datalen; /* Value in proto field not a len, no checks possible */
1880
1881         protolen += hdrlen;
1882         /* consistency checks: */
1883         if (datalen > ETH_ZLEN) {
1884                 if (datalen >= protolen) {
1885                         /* more data on wire than in 802 header, trim of
1886                          * additional data.
1887                          */
1888                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1889                                         dev->name, protolen);
1890                         return protolen;
1891                 } else {
1892                         /* less data on wire than mentioned in header.
1893                          * Discard the packet.
1894                          */
1895                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1896                                         dev->name);
1897                         return -1;
1898                 }
1899         } else {
1900                 /* short packet. Accept only if 802 values are also short */
1901                 if (protolen > ETH_ZLEN) {
1902                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1903                                         dev->name);
1904                         return -1;
1905                 }
1906                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1907                                 dev->name, datalen);
1908                 return datalen;
1909         }
1910 }
1911
1912 static int nv_rx_process(struct net_device *dev, int limit)
1913 {
1914         struct fe_priv *np = netdev_priv(dev);
1915         u32 flags;
1916         u32 vlanflags = 0;
1917         int count;
1918
1919         for (count = 0; count < limit; ++count) {
1920                 struct sk_buff *skb;
1921                 int len;
1922
1923                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1924                         if (np->get_rx.orig == np->put_rx.orig)
1925                                 break;  /* we scanned the whole ring - do not continue */
1926                         flags = le32_to_cpu(np->get_rx.orig->flaglen);
1927                         len = nv_descr_getlength(np->get_rx.orig, np->desc_ver);
1928                 } else {
1929                         if (np->get_rx.ex == np->put_rx.ex)
1930                                 break;  /* we scanned the whole ring - do not continue */
1931                         flags = le32_to_cpu(np->get_rx.ex->flaglen);
1932                         len = nv_descr_getlength_ex(np->get_rx.ex, np->desc_ver);
1933                         vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
1934                 }
1935
1936                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
1937                                         dev->name, flags);
1938
1939                 if (flags & NV_RX_AVAIL)
1940                         break;  /* still owned by hardware, */
1941
1942                 /*
1943                  * the packet is for us - immediately tear down the pci mapping.
1944                  * TODO: check if a prefetch of the first cacheline improves
1945                  * the performance.
1946                  */
1947                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
1948                                 np->get_rx_ctx->dma_len,
1949                                 PCI_DMA_FROMDEVICE);
1950
1951                 {
1952                         int j;
1953                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
1954                         for (j=0; j<64; j++) {
1955                                 if ((j%16) == 0)
1956                                         dprintk("\n%03x:", j);
1957                                 dprintk(" %02x", ((unsigned char*)np->get_rx_ctx->skb->data)[j]);
1958                         }
1959                         dprintk("\n");
1960                 }
1961                 /* look at what we actually got: */
1962                 if (np->desc_ver == DESC_VER_1) {
1963                         if (!(flags & NV_RX_DESCRIPTORVALID))
1964                                 goto next_pkt;
1965
1966                         if (flags & NV_RX_ERROR) {
1967                                 if (flags & NV_RX_MISSEDFRAME) {
1968                                         np->stats.rx_missed_errors++;
1969                                         np->stats.rx_errors++;
1970                                         goto next_pkt;
1971                                 }
1972                                 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1973                                         np->stats.rx_errors++;
1974                                         goto next_pkt;
1975                                 }
1976                                 if (flags & NV_RX_CRCERR) {
1977                                         np->stats.rx_crc_errors++;
1978                                         np->stats.rx_errors++;
1979                                         goto next_pkt;
1980                                 }
1981                                 if (flags & NV_RX_OVERFLOW) {
1982                                         np->stats.rx_over_errors++;
1983                                         np->stats.rx_errors++;
1984                                         goto next_pkt;
1985                                 }
1986                                 if (flags & NV_RX_ERROR4) {
1987                                         len = nv_getlen(dev, np->get_rx_ctx->skb->data, len);
1988                                         if (len < 0) {
1989                                                 np->stats.rx_errors++;
1990                                                 goto next_pkt;
1991                                         }
1992                                 }
1993                                 /* framing errors are soft errors. */
1994                                 if (flags & NV_RX_FRAMINGERR) {
1995                                         if (flags & NV_RX_SUBSTRACT1) {
1996                                                 len--;
1997                                         }
1998                                 }
1999                         }
2000                 } else {
2001                         if (!(flags & NV_RX2_DESCRIPTORVALID))
2002                                 goto next_pkt;
2003
2004                         if (flags & NV_RX2_ERROR) {
2005                                 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
2006                                         np->stats.rx_errors++;
2007                                         goto next_pkt;
2008                                 }
2009                                 if (flags & NV_RX2_CRCERR) {
2010                                         np->stats.rx_crc_errors++;
2011                                         np->stats.rx_errors++;
2012                                         goto next_pkt;
2013                                 }
2014                                 if (flags & NV_RX2_OVERFLOW) {
2015                                         np->stats.rx_over_errors++;
2016                                         np->stats.rx_errors++;
2017                                         goto next_pkt;
2018                                 }
2019                                 if (flags & NV_RX2_ERROR4) {
2020                                         len = nv_getlen(dev, np->get_rx_ctx->skb->data, len);
2021                                         if (len < 0) {
2022                                                 np->stats.rx_errors++;
2023                                                 goto next_pkt;
2024                                         }
2025                                 }
2026                                 /* framing errors are soft errors */
2027                                 if (flags & NV_RX2_FRAMINGERR) {
2028                                         if (flags & NV_RX2_SUBSTRACT1) {
2029                                                 len--;
2030                                         }
2031                                 }
2032                         }
2033                         if (np->rx_csum) {
2034                                 flags &= NV_RX2_CHECKSUMMASK;
2035                                 if (flags == NV_RX2_CHECKSUMOK1 ||
2036                                     flags == NV_RX2_CHECKSUMOK2 ||
2037                                     flags == NV_RX2_CHECKSUMOK3) {
2038                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
2039                                         np->get_rx_ctx->skb->ip_summed = CHECKSUM_UNNECESSARY;
2040                                 } else {
2041                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
2042                                 }
2043                         }
2044                 }
2045                 /* got a valid packet - forward it to the network core */
2046                 skb = np->get_rx_ctx->skb;
2047                 np->get_rx_ctx->skb = NULL;
2048
2049                 skb_put(skb, len);
2050                 skb->protocol = eth_type_trans(skb, dev);
2051                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2052                                         dev->name, len, skb->protocol);
2053 #ifdef CONFIG_FORCEDETH_NAPI
2054                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2055                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2056                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2057                 else
2058                         netif_receive_skb(skb);
2059 #else
2060                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2061                         vlan_hwaccel_rx(skb, np->vlangrp,
2062                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2063                 else
2064                         netif_rx(skb);
2065 #endif
2066                 dev->last_rx = jiffies;
2067                 np->stats.rx_packets++;
2068                 np->stats.rx_bytes += len;
2069 next_pkt:
2070                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2071                         if (np->get_rx.orig++ == np->last_rx.orig)
2072                                 np->get_rx.orig = np->first_rx.orig;
2073                 } else {
2074                         if (np->get_rx.ex++ == np->last_rx.ex)
2075                                 np->get_rx.ex = np->first_rx.ex;
2076                 }
2077                 if (np->get_rx_ctx++ == np->last_rx_ctx)
2078                         np->get_rx_ctx = np->first_rx_ctx;
2079         }
2080
2081         return count;
2082 }
2083
2084 static void set_bufsize(struct net_device *dev)
2085 {
2086         struct fe_priv *np = netdev_priv(dev);
2087
2088         if (dev->mtu <= ETH_DATA_LEN)
2089                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2090         else
2091                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2092 }
2093
2094 /*
2095  * nv_change_mtu: dev->change_mtu function
2096  * Called with dev_base_lock held for read.
2097  */
2098 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2099 {
2100         struct fe_priv *np = netdev_priv(dev);
2101         int old_mtu;
2102
2103         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2104                 return -EINVAL;
2105
2106         old_mtu = dev->mtu;
2107         dev->mtu = new_mtu;
2108
2109         /* return early if the buffer sizes will not change */
2110         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2111                 return 0;
2112         if (old_mtu == new_mtu)
2113                 return 0;
2114
2115         /* synchronized against open : rtnl_lock() held by caller */
2116         if (netif_running(dev)) {
2117                 u8 __iomem *base = get_hwbase(dev);
2118                 /*
2119                  * It seems that the nic preloads valid ring entries into an
2120                  * internal buffer. The procedure for flushing everything is
2121                  * guessed, there is probably a simpler approach.
2122                  * Changing the MTU is a rare event, it shouldn't matter.
2123                  */
2124                 nv_disable_irq(dev);
2125                 netif_tx_lock_bh(dev);
2126                 spin_lock(&np->lock);
2127                 /* stop engines */
2128                 nv_stop_rx(dev);
2129                 nv_stop_tx(dev);
2130                 nv_txrx_reset(dev);
2131                 /* drain rx queue */
2132                 nv_drain_rx(dev);
2133                 nv_drain_tx(dev);
2134                 /* reinit driver view of the rx queue */
2135                 set_bufsize(dev);
2136                 if (nv_init_ring(dev)) {
2137                         if (!np->in_shutdown)
2138                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2139                 }
2140                 /* reinit nic view of the rx queue */
2141                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2142                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2143                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2144                         base + NvRegRingSizes);
2145                 pci_push(base);
2146                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2147                 pci_push(base);
2148
2149                 /* restart rx engine */
2150                 nv_start_rx(dev);
2151                 nv_start_tx(dev);
2152                 spin_unlock(&np->lock);
2153                 netif_tx_unlock_bh(dev);
2154                 nv_enable_irq(dev);
2155         }
2156         return 0;
2157 }
2158
2159 static void nv_copy_mac_to_hw(struct net_device *dev)
2160 {
2161         u8 __iomem *base = get_hwbase(dev);
2162         u32 mac[2];
2163
2164         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2165                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2166         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2167
2168         writel(mac[0], base + NvRegMacAddrA);
2169         writel(mac[1], base + NvRegMacAddrB);
2170 }
2171
2172 /*
2173  * nv_set_mac_address: dev->set_mac_address function
2174  * Called with rtnl_lock() held.
2175  */
2176 static int nv_set_mac_address(struct net_device *dev, void *addr)
2177 {
2178         struct fe_priv *np = netdev_priv(dev);
2179         struct sockaddr *macaddr = (struct sockaddr*)addr;
2180
2181         if (!is_valid_ether_addr(macaddr->sa_data))
2182                 return -EADDRNOTAVAIL;
2183
2184         /* synchronized against open : rtnl_lock() held by caller */
2185         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2186
2187         if (netif_running(dev)) {
2188                 netif_tx_lock_bh(dev);
2189                 spin_lock_irq(&np->lock);
2190
2191                 /* stop rx engine */
2192                 nv_stop_rx(dev);
2193
2194                 /* set mac address */
2195                 nv_copy_mac_to_hw(dev);
2196
2197                 /* restart rx engine */
2198                 nv_start_rx(dev);
2199                 spin_unlock_irq(&np->lock);
2200                 netif_tx_unlock_bh(dev);
2201         } else {
2202                 nv_copy_mac_to_hw(dev);
2203         }
2204         return 0;
2205 }
2206
2207 /*
2208  * nv_set_multicast: dev->set_multicast function
2209  * Called with netif_tx_lock held.
2210  */
2211 static void nv_set_multicast(struct net_device *dev)
2212 {
2213         struct fe_priv *np = netdev_priv(dev);
2214         u8 __iomem *base = get_hwbase(dev);
2215         u32 addr[2];
2216         u32 mask[2];
2217         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2218
2219         memset(addr, 0, sizeof(addr));
2220         memset(mask, 0, sizeof(mask));
2221
2222         if (dev->flags & IFF_PROMISC) {
2223                 pff |= NVREG_PFF_PROMISC;
2224         } else {
2225                 pff |= NVREG_PFF_MYADDR;
2226
2227                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2228                         u32 alwaysOff[2];
2229                         u32 alwaysOn[2];
2230
2231                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2232                         if (dev->flags & IFF_ALLMULTI) {
2233                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2234                         } else {
2235                                 struct dev_mc_list *walk;
2236
2237                                 walk = dev->mc_list;
2238                                 while (walk != NULL) {
2239                                         u32 a, b;
2240                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2241                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2242                                         alwaysOn[0] &= a;
2243                                         alwaysOff[0] &= ~a;
2244                                         alwaysOn[1] &= b;
2245                                         alwaysOff[1] &= ~b;
2246                                         walk = walk->next;
2247                                 }
2248                         }
2249                         addr[0] = alwaysOn[0];
2250                         addr[1] = alwaysOn[1];
2251                         mask[0] = alwaysOn[0] | alwaysOff[0];
2252                         mask[1] = alwaysOn[1] | alwaysOff[1];
2253                 }
2254         }
2255         addr[0] |= NVREG_MCASTADDRA_FORCE;
2256         pff |= NVREG_PFF_ALWAYS;
2257         spin_lock_irq(&np->lock);
2258         nv_stop_rx(dev);
2259         writel(addr[0], base + NvRegMulticastAddrA);
2260         writel(addr[1], base + NvRegMulticastAddrB);
2261         writel(mask[0], base + NvRegMulticastMaskA);
2262         writel(mask[1], base + NvRegMulticastMaskB);
2263         writel(pff, base + NvRegPacketFilterFlags);
2264         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2265                 dev->name);
2266         nv_start_rx(dev);
2267         spin_unlock_irq(&np->lock);
2268 }
2269
2270 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2271 {
2272         struct fe_priv *np = netdev_priv(dev);
2273         u8 __iomem *base = get_hwbase(dev);
2274
2275         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2276
2277         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2278                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2279                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2280                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2281                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2282                 } else {
2283                         writel(pff, base + NvRegPacketFilterFlags);
2284                 }
2285         }
2286         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2287                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2288                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2289                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2290                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2291                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2292                 } else {
2293                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2294                         writel(regmisc, base + NvRegMisc1);
2295                 }
2296         }
2297 }
2298
2299 /**
2300  * nv_update_linkspeed: Setup the MAC according to the link partner
2301  * @dev: Network device to be configured
2302  *
2303  * The function queries the PHY and checks if there is a link partner.
2304  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2305  * set to 10 MBit HD.
2306  *
2307  * The function returns 0 if there is no link partner and 1 if there is
2308  * a good link partner.
2309  */
2310 static int nv_update_linkspeed(struct net_device *dev)
2311 {
2312         struct fe_priv *np = netdev_priv(dev);
2313         u8 __iomem *base = get_hwbase(dev);
2314         int adv = 0;
2315         int lpa = 0;
2316         int adv_lpa, adv_pause, lpa_pause;
2317         int newls = np->linkspeed;
2318         int newdup = np->duplex;
2319         int mii_status;
2320         int retval = 0;
2321         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2322
2323         /* BMSR_LSTATUS is latched, read it twice:
2324          * we want the current value.
2325          */
2326         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2327         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2328
2329         if (!(mii_status & BMSR_LSTATUS)) {
2330                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2331                                 dev->name);
2332                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2333                 newdup = 0;
2334                 retval = 0;
2335                 goto set_speed;
2336         }
2337
2338         if (np->autoneg == 0) {
2339                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2340                                 dev->name, np->fixed_mode);
2341                 if (np->fixed_mode & LPA_100FULL) {
2342                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2343                         newdup = 1;
2344                 } else if (np->fixed_mode & LPA_100HALF) {
2345                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2346                         newdup = 0;
2347                 } else if (np->fixed_mode & LPA_10FULL) {
2348                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2349                         newdup = 1;
2350                 } else {
2351                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2352                         newdup = 0;
2353                 }
2354                 retval = 1;
2355                 goto set_speed;
2356         }
2357         /* check auto negotiation is complete */
2358         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2359                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2360                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2361                 newdup = 0;
2362                 retval = 0;
2363                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2364                 goto set_speed;
2365         }
2366
2367         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2368         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2369         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2370                                 dev->name, adv, lpa);
2371
2372         retval = 1;
2373         if (np->gigabit == PHY_GIGABIT) {
2374                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2375                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2376
2377                 if ((control_1000 & ADVERTISE_1000FULL) &&
2378                         (status_1000 & LPA_1000FULL)) {
2379                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2380                                 dev->name);
2381                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2382                         newdup = 1;
2383                         goto set_speed;
2384                 }
2385         }
2386
2387         /* FIXME: handle parallel detection properly */
2388         adv_lpa = lpa & adv;
2389         if (adv_lpa & LPA_100FULL) {
2390                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2391                 newdup = 1;
2392         } else if (adv_lpa & LPA_100HALF) {
2393                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2394                 newdup = 0;
2395         } else if (adv_lpa & LPA_10FULL) {
2396                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2397                 newdup = 1;
2398         } else if (adv_lpa & LPA_10HALF) {
2399                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2400                 newdup = 0;
2401         } else {
2402                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2403                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2404                 newdup = 0;
2405         }
2406
2407 set_speed:
2408         if (np->duplex == newdup && np->linkspeed == newls)
2409                 return retval;
2410
2411         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2412                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2413
2414         np->duplex = newdup;
2415         np->linkspeed = newls;
2416
2417         if (np->gigabit == PHY_GIGABIT) {
2418                 phyreg = readl(base + NvRegRandomSeed);
2419                 phyreg &= ~(0x3FF00);
2420                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2421                         phyreg |= NVREG_RNDSEED_FORCE3;
2422                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2423                         phyreg |= NVREG_RNDSEED_FORCE2;
2424                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2425                         phyreg |= NVREG_RNDSEED_FORCE;
2426                 writel(phyreg, base + NvRegRandomSeed);
2427         }
2428
2429         phyreg = readl(base + NvRegPhyInterface);
2430         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2431         if (np->duplex == 0)
2432                 phyreg |= PHY_HALF;
2433         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2434                 phyreg |= PHY_100;
2435         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2436                 phyreg |= PHY_1000;
2437         writel(phyreg, base + NvRegPhyInterface);
2438
2439         if (phyreg & PHY_RGMII) {
2440                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2441                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2442                 else
2443                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2444         } else {
2445                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2446         }
2447         writel(txreg, base + NvRegTxDeferral);
2448
2449         if (np->desc_ver == DESC_VER_1) {
2450                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2451         } else {
2452                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2453                         txreg = NVREG_TX_WM_DESC2_3_1000;
2454                 else
2455                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2456         }
2457         writel(txreg, base + NvRegTxWatermark);
2458
2459         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2460                 base + NvRegMisc1);
2461         pci_push(base);
2462         writel(np->linkspeed, base + NvRegLinkSpeed);
2463         pci_push(base);
2464
2465         pause_flags = 0;
2466         /* setup pause frame */
2467         if (np->duplex != 0) {
2468                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2469                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2470                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2471
2472                         switch (adv_pause) {
2473                         case ADVERTISE_PAUSE_CAP:
2474                                 if (lpa_pause & LPA_PAUSE_CAP) {
2475                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2476                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2477                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2478                                 }
2479                                 break;
2480                         case ADVERTISE_PAUSE_ASYM:
2481                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2482                                 {
2483                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2484                                 }
2485                                 break;
2486                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2487                                 if (lpa_pause & LPA_PAUSE_CAP)
2488                                 {
2489                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2490                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2491                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2492                                 }
2493                                 if (lpa_pause == LPA_PAUSE_ASYM)
2494                                 {
2495                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2496                                 }
2497                                 break;
2498                         }
2499                 } else {
2500                         pause_flags = np->pause_flags;
2501                 }
2502         }
2503         nv_update_pause(dev, pause_flags);
2504
2505         return retval;
2506 }
2507
2508 static void nv_linkchange(struct net_device *dev)
2509 {
2510         if (nv_update_linkspeed(dev)) {
2511                 if (!netif_carrier_ok(dev)) {
2512                         netif_carrier_on(dev);
2513                         printk(KERN_INFO "%s: link up.\n", dev->name);
2514                         nv_start_rx(dev);
2515                 }
2516         } else {
2517                 if (netif_carrier_ok(dev)) {
2518                         netif_carrier_off(dev);
2519                         printk(KERN_INFO "%s: link down.\n", dev->name);
2520                         nv_stop_rx(dev);
2521                 }
2522         }
2523 }
2524
2525 static void nv_link_irq(struct net_device *dev)
2526 {
2527         u8 __iomem *base = get_hwbase(dev);
2528         u32 miistat;
2529
2530         miistat = readl(base + NvRegMIIStatus);
2531         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2532         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2533
2534         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2535                 nv_linkchange(dev);
2536         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2537 }
2538
2539 static irqreturn_t nv_nic_irq(int foo, void *data)
2540 {
2541         struct net_device *dev = (struct net_device *) data;
2542         struct fe_priv *np = netdev_priv(dev);
2543         u8 __iomem *base = get_hwbase(dev);
2544         u32 events;
2545         int i;
2546
2547         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2548
2549         for (i=0; ; i++) {
2550                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2551                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2552                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2553                 } else {
2554                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2555                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2556                 }
2557                 pci_push(base);
2558                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2559                 if (!(events & np->irqmask))
2560                         break;
2561
2562                 spin_lock(&np->lock);
2563                 nv_tx_done(dev);
2564                 spin_unlock(&np->lock);
2565
2566                 if (events & NVREG_IRQ_LINK) {
2567                         spin_lock(&np->lock);
2568                         nv_link_irq(dev);
2569                         spin_unlock(&np->lock);
2570                 }
2571                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2572                         spin_lock(&np->lock);
2573                         nv_linkchange(dev);
2574                         spin_unlock(&np->lock);
2575                         np->link_timeout = jiffies + LINK_TIMEOUT;
2576                 }
2577                 if (events & (NVREG_IRQ_TX_ERR)) {
2578                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2579                                                 dev->name, events);
2580                 }
2581                 if (events & (NVREG_IRQ_UNKNOWN)) {
2582                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2583                                                 dev->name, events);
2584                 }
2585                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2586                         spin_lock(&np->lock);
2587                         /* disable interrupts on the nic */
2588                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2589                                 writel(0, base + NvRegIrqMask);
2590                         else
2591                                 writel(np->irqmask, base + NvRegIrqMask);
2592                         pci_push(base);
2593
2594                         if (!np->in_shutdown) {
2595                                 np->nic_poll_irq = np->irqmask;
2596                                 np->recover_error = 1;
2597                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2598                         }
2599                         spin_unlock(&np->lock);
2600                         break;
2601                 }
2602 #ifdef CONFIG_FORCEDETH_NAPI
2603                 if (events & NVREG_IRQ_RX_ALL) {
2604                         netif_rx_schedule(dev);
2605
2606                         /* Disable furthur receive irq's */
2607                         spin_lock(&np->lock);
2608                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2609
2610                         if (np->msi_flags & NV_MSI_X_ENABLED)
2611                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2612                         else
2613                                 writel(np->irqmask, base + NvRegIrqMask);
2614                         spin_unlock(&np->lock);
2615                 }
2616 #else
2617                 nv_rx_process(dev, dev->weight);
2618                 if (nv_alloc_rx(dev)) {
2619                         spin_lock(&np->lock);
2620                         if (!np->in_shutdown)
2621                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2622                         spin_unlock(&np->lock);
2623                 }
2624 #endif
2625                 if (i > max_interrupt_work) {
2626                         spin_lock(&np->lock);
2627                         /* disable interrupts on the nic */
2628                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2629                                 writel(0, base + NvRegIrqMask);
2630                         else
2631                                 writel(np->irqmask, base + NvRegIrqMask);
2632                         pci_push(base);
2633
2634                         if (!np->in_shutdown) {
2635                                 np->nic_poll_irq = np->irqmask;
2636                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2637                         }
2638                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2639                         spin_unlock(&np->lock);
2640                         break;
2641                 }
2642
2643         }
2644         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2645
2646         return IRQ_RETVAL(i);
2647 }
2648
2649 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
2650 {
2651         struct net_device *dev = (struct net_device *) data;
2652         struct fe_priv *np = netdev_priv(dev);
2653         u8 __iomem *base = get_hwbase(dev);
2654         u32 events;
2655         int i;
2656         unsigned long flags;
2657
2658         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2659
2660         for (i=0; ; i++) {
2661                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2662                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2663                 pci_push(base);
2664                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2665                 if (!(events & np->irqmask))
2666                         break;
2667
2668                 spin_lock_irqsave(&np->lock, flags);
2669                 nv_tx_done(dev);
2670                 spin_unlock_irqrestore(&np->lock, flags);
2671
2672                 if (events & (NVREG_IRQ_TX_ERR)) {
2673                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2674                                                 dev->name, events);
2675                 }
2676                 if (i > max_interrupt_work) {
2677                         spin_lock_irqsave(&np->lock, flags);
2678                         /* disable interrupts on the nic */
2679                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2680                         pci_push(base);
2681
2682                         if (!np->in_shutdown) {
2683                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2684                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2685                         }
2686                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2687                         spin_unlock_irqrestore(&np->lock, flags);
2688                         break;
2689                 }
2690
2691         }
2692         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2693
2694         return IRQ_RETVAL(i);
2695 }
2696
2697 #ifdef CONFIG_FORCEDETH_NAPI
2698 static int nv_napi_poll(struct net_device *dev, int *budget)
2699 {
2700         int pkts, limit = min(*budget, dev->quota);
2701         struct fe_priv *np = netdev_priv(dev);
2702         u8 __iomem *base = get_hwbase(dev);
2703         unsigned long flags;
2704
2705         pkts = nv_rx_process(dev, limit);
2706
2707         if (nv_alloc_rx(dev)) {
2708                 spin_lock_irqsave(&np->lock, flags);
2709                 if (!np->in_shutdown)
2710                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2711                 spin_unlock_irqrestore(&np->lock, flags);
2712         }
2713
2714         if (pkts < limit) {
2715                 /* all done, no more packets present */
2716                 netif_rx_complete(dev);
2717
2718                 /* re-enable receive interrupts */
2719                 spin_lock_irqsave(&np->lock, flags);
2720
2721                 np->irqmask |= NVREG_IRQ_RX_ALL;
2722                 if (np->msi_flags & NV_MSI_X_ENABLED)
2723                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2724                 else
2725                         writel(np->irqmask, base + NvRegIrqMask);
2726
2727                 spin_unlock_irqrestore(&np->lock, flags);
2728                 return 0;
2729         } else {
2730                 /* used up our quantum, so reschedule */
2731                 dev->quota -= pkts;
2732                 *budget -= pkts;
2733                 return 1;
2734         }
2735 }
2736 #endif
2737
2738 #ifdef CONFIG_FORCEDETH_NAPI
2739 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2740 {
2741         struct net_device *dev = (struct net_device *) data;
2742         u8 __iomem *base = get_hwbase(dev);
2743         u32 events;
2744
2745         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2746         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2747
2748         if (events) {
2749                 netif_rx_schedule(dev);
2750                 /* disable receive interrupts on the nic */
2751                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2752                 pci_push(base);
2753         }
2754         return IRQ_HANDLED;
2755 }
2756 #else
2757 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2758 {
2759         struct net_device *dev = (struct net_device *) data;
2760         struct fe_priv *np = netdev_priv(dev);
2761         u8 __iomem *base = get_hwbase(dev);
2762         u32 events;
2763         int i;
2764         unsigned long flags;
2765
2766         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2767
2768         for (i=0; ; i++) {
2769                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2770                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2771                 pci_push(base);
2772                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2773                 if (!(events & np->irqmask))
2774                         break;
2775
2776                 nv_rx_process(dev, dev->weight);
2777                 if (nv_alloc_rx(dev)) {
2778                         spin_lock_irqsave(&np->lock, flags);
2779                         if (!np->in_shutdown)
2780                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2781                         spin_unlock_irqrestore(&np->lock, flags);
2782                 }
2783
2784                 if (i > max_interrupt_work) {
2785                         spin_lock_irqsave(&np->lock, flags);
2786                         /* disable interrupts on the nic */
2787                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2788                         pci_push(base);
2789
2790                         if (!np->in_shutdown) {
2791                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2792                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2793                         }
2794                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2795                         spin_unlock_irqrestore(&np->lock, flags);
2796                         break;
2797                 }
2798         }
2799         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2800
2801         return IRQ_RETVAL(i);
2802 }
2803 #endif
2804
2805 static irqreturn_t nv_nic_irq_other(int foo, void *data)
2806 {
2807         struct net_device *dev = (struct net_device *) data;
2808         struct fe_priv *np = netdev_priv(dev);
2809         u8 __iomem *base = get_hwbase(dev);
2810         u32 events;
2811         int i;
2812         unsigned long flags;
2813
2814         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2815
2816         for (i=0; ; i++) {
2817                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2818                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2819                 pci_push(base);
2820                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2821                 if (!(events & np->irqmask))
2822                         break;
2823
2824                 if (events & NVREG_IRQ_LINK) {
2825                         spin_lock_irqsave(&np->lock, flags);
2826                         nv_link_irq(dev);
2827                         spin_unlock_irqrestore(&np->lock, flags);
2828                 }
2829                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2830                         spin_lock_irqsave(&np->lock, flags);
2831                         nv_linkchange(dev);
2832                         spin_unlock_irqrestore(&np->lock, flags);
2833                         np->link_timeout = jiffies + LINK_TIMEOUT;
2834                 }
2835                 if (events & NVREG_IRQ_RECOVER_ERROR) {
2836                         spin_lock_irq(&np->lock);
2837                         /* disable interrupts on the nic */
2838                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2839                         pci_push(base);
2840
2841                         if (!np->in_shutdown) {
2842                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2843                                 np->recover_error = 1;
2844                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2845                         }
2846                         spin_unlock_irq(&np->lock);
2847                         break;
2848                 }
2849                 if (events & (NVREG_IRQ_UNKNOWN)) {
2850                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2851                                                 dev->name, events);
2852                 }
2853                 if (i > max_interrupt_work) {
2854                         spin_lock_irqsave(&np->lock, flags);
2855                         /* disable interrupts on the nic */
2856                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2857                         pci_push(base);
2858
2859                         if (!np->in_shutdown) {
2860                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2861                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2862                         }
2863                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2864                         spin_unlock_irqrestore(&np->lock, flags);
2865                         break;
2866                 }
2867
2868         }
2869         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2870
2871         return IRQ_RETVAL(i);
2872 }
2873
2874 static irqreturn_t nv_nic_irq_test(int foo, void *data)
2875 {
2876         struct net_device *dev = (struct net_device *) data;
2877         struct fe_priv *np = netdev_priv(dev);
2878         u8 __iomem *base = get_hwbase(dev);
2879         u32 events;
2880
2881         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2882
2883         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2884                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2885                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2886         } else {
2887                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2888                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2889         }
2890         pci_push(base);
2891         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2892         if (!(events & NVREG_IRQ_TIMER))
2893                 return IRQ_RETVAL(0);
2894
2895         spin_lock(&np->lock);
2896         np->intr_test = 1;
2897         spin_unlock(&np->lock);
2898
2899         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2900
2901         return IRQ_RETVAL(1);
2902 }
2903
2904 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2905 {
2906         u8 __iomem *base = get_hwbase(dev);
2907         int i;
2908         u32 msixmap = 0;
2909
2910         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2911          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2912          * the remaining 8 interrupts.
2913          */
2914         for (i = 0; i < 8; i++) {
2915                 if ((irqmask >> i) & 0x1) {
2916                         msixmap |= vector << (i << 2);
2917                 }
2918         }
2919         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2920
2921         msixmap = 0;
2922         for (i = 0; i < 8; i++) {
2923                 if ((irqmask >> (i + 8)) & 0x1) {
2924                         msixmap |= vector << (i << 2);
2925                 }
2926         }
2927         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2928 }
2929
2930 static int nv_request_irq(struct net_device *dev, int intr_test)
2931 {
2932         struct fe_priv *np = get_nvpriv(dev);
2933         u8 __iomem *base = get_hwbase(dev);
2934         int ret = 1;
2935         int i;
2936
2937         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2938                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2939                         np->msi_x_entry[i].entry = i;
2940                 }
2941                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2942                         np->msi_flags |= NV_MSI_X_ENABLED;
2943                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2944                                 /* Request irq for rx handling */
2945                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2946                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2947                                         pci_disable_msix(np->pci_dev);
2948                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2949                                         goto out_err;
2950                                 }
2951                                 /* Request irq for tx handling */
2952                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2953                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2954                                         pci_disable_msix(np->pci_dev);
2955                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2956                                         goto out_free_rx;
2957                                 }
2958                                 /* Request irq for link and timer handling */
2959                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2960                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2961                                         pci_disable_msix(np->pci_dev);
2962                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2963                                         goto out_free_tx;
2964                                 }
2965                                 /* map interrupts to their respective vector */
2966                                 writel(0, base + NvRegMSIXMap0);
2967                                 writel(0, base + NvRegMSIXMap1);
2968                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2969                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2970                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2971                         } else {
2972                                 /* Request irq for all interrupts */
2973                                 if ((!intr_test &&
2974                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2975                                     (intr_test &&
2976                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2977                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2978                                         pci_disable_msix(np->pci_dev);
2979                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2980                                         goto out_err;
2981                                 }
2982
2983                                 /* map interrupts to vector 0 */
2984                                 writel(0, base + NvRegMSIXMap0);
2985                                 writel(0, base + NvRegMSIXMap1);
2986                         }
2987                 }
2988         }
2989         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2990                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2991                         np->msi_flags |= NV_MSI_ENABLED;
2992                         if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2993                             (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2994                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2995                                 pci_disable_msi(np->pci_dev);
2996                                 np->msi_flags &= ~NV_MSI_ENABLED;
2997                                 goto out_err;
2998                         }
2999
3000                         /* map interrupts to vector 0 */
3001                         writel(0, base + NvRegMSIMap0);
3002                         writel(0, base + NvRegMSIMap1);
3003                         /* enable msi vector 0 */
3004                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3005                 }
3006         }
3007         if (ret != 0) {
3008                 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
3009                     (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
3010                         goto out_err;
3011
3012         }
3013
3014         return 0;
3015 out_free_tx:
3016         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3017 out_free_rx:
3018         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3019 out_err:
3020         return 1;
3021 }
3022
3023 static void nv_free_irq(struct net_device *dev)
3024 {
3025         struct fe_priv *np = get_nvpriv(dev);
3026         int i;
3027
3028         if (np->msi_flags & NV_MSI_X_ENABLED) {
3029                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3030                         free_irq(np->msi_x_entry[i].vector, dev);
3031                 }
3032                 pci_disable_msix(np->pci_dev);
3033                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3034         } else {
3035                 free_irq(np->pci_dev->irq, dev);
3036                 if (np->msi_flags & NV_MSI_ENABLED) {
3037                         pci_disable_msi(np->pci_dev);
3038                         np->msi_flags &= ~NV_MSI_ENABLED;
3039                 }
3040         }
3041 }
3042
3043 static void nv_do_nic_poll(unsigned long data)
3044 {
3045         struct net_device *dev = (struct net_device *) data;
3046         struct fe_priv *np = netdev_priv(dev);
3047         u8 __iomem *base = get_hwbase(dev);
3048         u32 mask = 0;
3049
3050         /*
3051          * First disable irq(s) and then
3052          * reenable interrupts on the nic, we have to do this before calling
3053          * nv_nic_irq because that may decide to do otherwise
3054          */
3055
3056         if (!using_multi_irqs(dev)) {
3057                 if (np->msi_flags & NV_MSI_X_ENABLED)
3058                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3059                 else
3060                         disable_irq_lockdep(dev->irq);
3061                 mask = np->irqmask;
3062         } else {
3063                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3064                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3065                         mask |= NVREG_IRQ_RX_ALL;
3066                 }
3067                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3068                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3069                         mask |= NVREG_IRQ_TX_ALL;
3070                 }
3071                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3072                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3073                         mask |= NVREG_IRQ_OTHER;
3074                 }
3075         }
3076         np->nic_poll_irq = 0;
3077
3078         if (np->recover_error) {
3079                 np->recover_error = 0;
3080                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3081                 if (netif_running(dev)) {
3082                         netif_tx_lock_bh(dev);
3083                         spin_lock(&np->lock);
3084                         /* stop engines */
3085                         nv_stop_rx(dev);
3086                         nv_stop_tx(dev);
3087                         nv_txrx_reset(dev);
3088                         /* drain rx queue */
3089                         nv_drain_rx(dev);
3090                         nv_drain_tx(dev);
3091                         /* reinit driver view of the rx queue */
3092                         set_bufsize(dev);
3093                         if (nv_init_ring(dev)) {
3094                                 if (!np->in_shutdown)
3095                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3096                         }
3097                         /* reinit nic view of the rx queue */
3098                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3099                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3100                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3101                                 base + NvRegRingSizes);
3102                         pci_push(base);
3103                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3104                         pci_push(base);
3105
3106                         /* restart rx engine */
3107                         nv_start_rx(dev);
3108                         nv_start_tx(dev);
3109                         spin_unlock(&np->lock);
3110                         netif_tx_unlock_bh(dev);
3111                 }
3112         }
3113
3114         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
3115
3116         writel(mask, base + NvRegIrqMask);
3117         pci_push(base);
3118
3119         if (!using_multi_irqs(dev)) {
3120                 nv_nic_irq(0, dev);
3121                 if (np->msi_flags & NV_MSI_X_ENABLED)
3122                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3123                 else
3124                         enable_irq_lockdep(dev->irq);
3125         } else {
3126                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3127                         nv_nic_irq_rx(0, dev);
3128                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3129                 }
3130                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3131                         nv_nic_irq_tx(0, dev);
3132                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3133                 }
3134                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3135                         nv_nic_irq_other(0, dev);
3136                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3137                 }
3138         }
3139 }
3140
3141 #ifdef CONFIG_NET_POLL_CONTROLLER
3142 static void nv_poll_controller(struct net_device *dev)
3143 {
3144         nv_do_nic_poll((unsigned long) dev);
3145 }
3146 #endif
3147
3148 static void nv_do_stats_poll(unsigned long data)
3149 {
3150         struct net_device *dev = (struct net_device *) data;
3151         struct fe_priv *np = netdev_priv(dev);
3152         u8 __iomem *base = get_hwbase(dev);
3153
3154         np->estats.tx_bytes += readl(base + NvRegTxCnt);
3155         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
3156         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
3157         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
3158         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
3159         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
3160         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
3161         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
3162         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
3163         np->estats.tx_deferral += readl(base + NvRegTxDef);
3164         np->estats.tx_packets += readl(base + NvRegTxFrame);
3165         np->estats.tx_pause += readl(base + NvRegTxPause);
3166         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
3167         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
3168         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
3169         np->estats.rx_runt += readl(base + NvRegRxRunt);
3170         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
3171         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
3172         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
3173         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
3174         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
3175         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
3176         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
3177         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
3178         np->estats.rx_bytes += readl(base + NvRegRxCnt);
3179         np->estats.rx_pause += readl(base + NvRegRxPause);
3180         np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
3181         np->estats.rx_packets =
3182                 np->estats.rx_unicast +
3183                 np->estats.rx_multicast +
3184                 np->estats.rx_broadcast;
3185         np->estats.rx_errors_total =
3186                 np->estats.rx_crc_errors +
3187                 np->estats.rx_over_errors +
3188                 np->estats.rx_frame_error +
3189                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
3190                 np->estats.rx_late_collision +
3191                 np->estats.rx_runt +
3192                 np->estats.rx_frame_too_long;
3193
3194         if (!np->in_shutdown)
3195                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3196 }
3197
3198 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3199 {
3200         struct fe_priv *np = netdev_priv(dev);
3201         strcpy(info->driver, "forcedeth");
3202         strcpy(info->version, FORCEDETH_VERSION);
3203         strcpy(info->bus_info, pci_name(np->pci_dev));
3204 }
3205
3206 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3207 {
3208         struct fe_priv *np = netdev_priv(dev);
3209         wolinfo->supported = WAKE_MAGIC;
3210
3211         spin_lock_irq(&np->lock);
3212         if (np->wolenabled)
3213                 wolinfo->wolopts = WAKE_MAGIC;
3214         spin_unlock_irq(&np->lock);
3215 }
3216
3217 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3218 {
3219         struct fe_priv *np = netdev_priv(dev);
3220         u8 __iomem *base = get_hwbase(dev);
3221         u32 flags = 0;
3222
3223         if (wolinfo->wolopts == 0) {
3224                 np->wolenabled = 0;
3225         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3226                 np->wolenabled = 1;
3227                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3228         }
3229         if (netif_running(dev)) {
3230                 spin_lock_irq(&np->lock);
3231                 writel(flags, base + NvRegWakeUpFlags);
3232                 spin_unlock_irq(&np->lock);
3233         }
3234         return 0;
3235 }
3236
3237 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3238 {
3239         struct fe_priv *np = netdev_priv(dev);
3240         int adv;
3241
3242         spin_lock_irq(&np->lock);
3243         ecmd->port = PORT_MII;
3244         if (!netif_running(dev)) {
3245                 /* We do not track link speed / duplex setting if the
3246                  * interface is disabled. Force a link check */
3247                 if (nv_update_linkspeed(dev)) {
3248                         if (!netif_carrier_ok(dev))
3249                                 netif_carrier_on(dev);
3250                 } else {
3251                         if (netif_carrier_ok(dev))
3252                                 netif_carrier_off(dev);
3253                 }
3254         }
3255
3256         if (netif_carrier_ok(dev)) {
3257                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3258                 case NVREG_LINKSPEED_10:
3259                         ecmd->speed = SPEED_10;
3260                         break;
3261                 case NVREG_LINKSPEED_100:
3262                         ecmd->speed = SPEED_100;
3263                         break;
3264                 case NVREG_LINKSPEED_1000:
3265                         ecmd->speed = SPEED_1000;
3266                         break;
3267                 }
3268                 ecmd->duplex = DUPLEX_HALF;
3269                 if (np->duplex)
3270                         ecmd->duplex = DUPLEX_FULL;
3271         } else {
3272                 ecmd->speed = -1;
3273                 ecmd->duplex = -1;
3274         }
3275
3276         ecmd->autoneg = np->autoneg;
3277
3278         ecmd->advertising = ADVERTISED_MII;
3279         if (np->autoneg) {
3280                 ecmd->advertising |= ADVERTISED_Autoneg;
3281                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3282                 if (adv & ADVERTISE_10HALF)
3283                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3284                 if (adv & ADVERTISE_10FULL)
3285                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3286                 if (adv & ADVERTISE_100HALF)
3287                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3288                 if (adv & ADVERTISE_100FULL)
3289                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3290                 if (np->gigabit == PHY_GIGABIT) {
3291                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3292                         if (adv & ADVERTISE_1000FULL)
3293                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3294                 }
3295         }
3296         ecmd->supported = (SUPPORTED_Autoneg |
3297                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3298                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3299                 SUPPORTED_MII);
3300         if (np->gigabit == PHY_GIGABIT)
3301                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3302
3303         ecmd->phy_address = np->phyaddr;
3304         ecmd->transceiver = XCVR_EXTERNAL;
3305
3306         /* ignore maxtxpkt, maxrxpkt for now */
3307         spin_unlock_irq(&np->lock);
3308         return 0;
3309 }
3310
3311 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3312 {
3313         struct fe_priv *np = netdev_priv(dev);
3314
3315         if (ecmd->port != PORT_MII)
3316                 return -EINVAL;
3317         if (ecmd->transceiver != XCVR_EXTERNAL)
3318                 return -EINVAL;
3319         if (ecmd->phy_address != np->phyaddr) {
3320                 /* TODO: support switching between multiple phys. Should be
3321                  * trivial, but not enabled due to lack of test hardware. */
3322                 return -EINVAL;
3323         }
3324         if (ecmd->autoneg == AUTONEG_ENABLE) {
3325                 u32 mask;
3326
3327                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3328                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3329                 if (np->gigabit == PHY_GIGABIT)
3330                         mask |= ADVERTISED_1000baseT_Full;
3331
3332                 if ((ecmd->advertising & mask) == 0)
3333                         return -EINVAL;
3334
3335         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3336                 /* Note: autonegotiation disable, speed 1000 intentionally
3337                  * forbidden - noone should need that. */
3338
3339                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3340                         return -EINVAL;
3341                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3342                         return -EINVAL;
3343         } else {
3344                 return -EINVAL;
3345         }
3346
3347         netif_carrier_off(dev);
3348         if (netif_running(dev)) {
3349                 nv_disable_irq(dev);
3350                 netif_tx_lock_bh(dev);
3351                 spin_lock(&np->lock);
3352                 /* stop engines */
3353                 nv_stop_rx(dev);
3354                 nv_stop_tx(dev);
3355                 spin_unlock(&np->lock);
3356                 netif_tx_unlock_bh(dev);
3357         }
3358
3359         if (ecmd->autoneg == AUTONEG_ENABLE) {
3360                 int adv, bmcr;
3361
3362                 np->autoneg = 1;
3363
3364                 /* advertise only what has been requested */
3365                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3366                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3367                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3368                         adv |= ADVERTISE_10HALF;
3369                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3370                         adv |= ADVERTISE_10FULL;
3371                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3372                         adv |= ADVERTISE_100HALF;
3373                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3374                         adv |= ADVERTISE_100FULL;
3375                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3376                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3377                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3378                         adv |=  ADVERTISE_PAUSE_ASYM;
3379                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3380
3381                 if (np->gigabit == PHY_GIGABIT) {
3382                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3383                         adv &= ~ADVERTISE_1000FULL;
3384                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3385                                 adv |= ADVERTISE_1000FULL;
3386                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3387                 }
3388
3389                 if (netif_running(dev))
3390                         printk(KERN_INFO "%s: link down.\n", dev->name);
3391                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3392                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3393                         bmcr |= BMCR_ANENABLE;
3394                         /* reset the phy in order for settings to stick,
3395                          * and cause autoneg to start */
3396                         if (phy_reset(dev, bmcr)) {
3397                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3398                                 return -EINVAL;
3399                         }
3400                 } else {
3401                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3402                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3403                 }
3404         } else {
3405                 int adv, bmcr;
3406
3407                 np->autoneg = 0;
3408
3409                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3410                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3411                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3412                         adv |= ADVERTISE_10HALF;
3413                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3414                         adv |= ADVERTISE_10FULL;
3415                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3416                         adv |= ADVERTISE_100HALF;
3417                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3418                         adv |= ADVERTISE_100FULL;
3419                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3420                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3421                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3422                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3423                 }
3424                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3425                         adv |=  ADVERTISE_PAUSE_ASYM;
3426                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3427                 }
3428                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3429                 np->fixed_mode = adv;
3430
3431                 if (np->gigabit == PHY_GIGABIT) {
3432                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3433                         adv &= ~ADVERTISE_1000FULL;
3434                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3435                 }
3436
3437                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3438                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3439                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3440                         bmcr |= BMCR_FULLDPLX;
3441                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3442                         bmcr |= BMCR_SPEED100;
3443                 if (np->phy_oui == PHY_OUI_MARVELL) {
3444                         /* reset the phy in order for forced mode settings to stick */
3445                         if (phy_reset(dev, bmcr)) {
3446                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3447                                 return -EINVAL;
3448                         }
3449                 } else {
3450                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3451                         if (netif_running(dev)) {
3452                                 /* Wait a bit and then reconfigure the nic. */
3453                                 udelay(10);
3454                                 nv_linkchange(dev);
3455                         }
3456                 }
3457         }
3458
3459         if (netif_running(dev)) {
3460                 nv_start_rx(dev);
3461                 nv_start_tx(dev);
3462                 nv_enable_irq(dev);
3463         }
3464
3465         return 0;
3466 }
3467
3468 #define FORCEDETH_REGS_VER      1
3469
3470 static int nv_get_regs_len(struct net_device *dev)
3471 {
3472         struct fe_priv *np = netdev_priv(dev);
3473         return np->register_size;
3474 }
3475
3476 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3477 {
3478         struct fe_priv *np = netdev_priv(dev);
3479         u8 __iomem *base = get_hwbase(dev);
3480         u32 *rbuf = buf;
3481         int i;
3482
3483         regs->version = FORCEDETH_REGS_VER;
3484         spin_lock_irq(&np->lock);
3485         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3486                 rbuf[i] = readl(base + i*sizeof(u32));
3487         spin_unlock_irq(&np->lock);
3488 }
3489
3490 static int nv_nway_reset(struct net_device *dev)
3491 {
3492         struct fe_priv *np = netdev_priv(dev);
3493         int ret;
3494
3495         if (np->autoneg) {
3496                 int bmcr;
3497
3498                 netif_carrier_off(dev);
3499                 if (netif_running(dev)) {
3500                         nv_disable_irq(dev);
3501                         netif_tx_lock_bh(dev);
3502                         spin_lock(&np->lock);
3503                         /* stop engines */
3504                         nv_stop_rx(dev);
3505                         nv_stop_tx(dev);
3506                         spin_unlock(&np->lock);
3507                         netif_tx_unlock_bh(dev);
3508                         printk(KERN_INFO "%s: link down.\n", dev->name);
3509                 }
3510
3511                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3512                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3513                         bmcr |= BMCR_ANENABLE;
3514                         /* reset the phy in order for settings to stick*/
3515                         if (phy_reset(dev, bmcr)) {
3516                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3517                                 return -EINVAL;
3518                         }
3519                 } else {
3520                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3521                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3522                 }
3523
3524                 if (netif_running(dev)) {
3525                         nv_start_rx(dev);
3526                         nv_start_tx(dev);
3527                         nv_enable_irq(dev);
3528                 }
3529                 ret = 0;
3530         } else {
3531                 ret = -EINVAL;
3532         }
3533
3534         return ret;
3535 }
3536
3537 static int nv_set_tso(struct net_device *dev, u32 value)
3538 {
3539         struct fe_priv *np = netdev_priv(dev);
3540
3541         if ((np->driver_data & DEV_HAS_CHECKSUM))
3542                 return ethtool_op_set_tso(dev, value);
3543         else
3544                 return -EOPNOTSUPP;
3545 }
3546
3547 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3548 {
3549         struct fe_priv *np = netdev_priv(dev);
3550
3551         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3552         ring->rx_mini_max_pending = 0;
3553         ring->rx_jumbo_max_pending = 0;
3554         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3555
3556         ring->rx_pending = np->rx_ring_size;
3557         ring->rx_mini_pending = 0;
3558         ring->rx_jumbo_pending = 0;
3559         ring->tx_pending = np->tx_ring_size;
3560 }
3561
3562 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3563 {
3564         struct fe_priv *np = netdev_priv(dev);
3565         u8 __iomem *base = get_hwbase(dev);
3566         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
3567         dma_addr_t ring_addr;
3568
3569         if (ring->rx_pending < RX_RING_MIN ||
3570             ring->tx_pending < TX_RING_MIN ||
3571             ring->rx_mini_pending != 0 ||
3572             ring->rx_jumbo_pending != 0 ||
3573             (np->desc_ver == DESC_VER_1 &&
3574              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3575               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3576             (np->desc_ver != DESC_VER_1 &&
3577              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3578               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3579                 return -EINVAL;
3580         }
3581
3582         /* allocate new rings */
3583         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3584                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3585                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3586                                             &ring_addr);
3587         } else {
3588                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3589                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3590                                             &ring_addr);
3591         }
3592         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
3593         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
3594         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
3595                 /* fall back to old rings */
3596                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3597                         if (rxtx_ring)
3598                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3599                                                     rxtx_ring, ring_addr);
3600                 } else {
3601                         if (rxtx_ring)
3602                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3603                                                     rxtx_ring, ring_addr);
3604                 }
3605                 if (rx_skbuff)
3606                         kfree(rx_skbuff);
3607                 if (tx_skbuff)
3608                         kfree(tx_skbuff);
3609                 goto exit;
3610         }
3611
3612         if (netif_running(dev)) {
3613                 nv_disable_irq(dev);
3614                 netif_tx_lock_bh(dev);
3615                 spin_lock(&np->lock);
3616                 /* stop engines */
3617                 nv_stop_rx(dev);
3618                 nv_stop_tx(dev);
3619                 nv_txrx_reset(dev);
3620                 /* drain queues */
3621                 nv_drain_rx(dev);
3622                 nv_drain_tx(dev);
3623                 /* delete queues */
3624                 free_rings(dev);
3625         }
3626
3627         /* set new values */
3628         np->rx_ring_size = ring->rx_pending;
3629         np->tx_ring_size = ring->tx_pending;
3630         np->tx_limit_stop = TX_LIMIT_DIFFERENCE;
3631         np->tx_limit_start = TX_LIMIT_DIFFERENCE;
3632         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3633                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3634                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3635         } else {
3636                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3637                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3638         }
3639         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
3640         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
3641         np->ring_addr = ring_addr;
3642
3643         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
3644         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
3645
3646         if (netif_running(dev)) {
3647                 /* reinit driver view of the queues */
3648                 set_bufsize(dev);
3649                 if (nv_init_ring(dev)) {
3650                         if (!np->in_shutdown)
3651                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3652                 }
3653
3654                 /* reinit nic view of the queues */
3655                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3656                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3657                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3658                         base + NvRegRingSizes);
3659                 pci_push(base);
3660                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3661                 pci_push(base);
3662
3663                 /* restart engines */
3664                 nv_start_rx(dev);
3665                 nv_start_tx(dev);
3666                 spin_unlock(&np->lock);
3667                 netif_tx_unlock_bh(dev);
3668                 nv_enable_irq(dev);
3669         }
3670         return 0;
3671 exit:
3672         return -ENOMEM;
3673 }
3674
3675 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3676 {
3677         struct fe_priv *np = netdev_priv(dev);
3678
3679         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3680         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3681         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3682 }
3683
3684 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3685 {
3686         struct fe_priv *np = netdev_priv(dev);
3687         int adv, bmcr;
3688
3689         if ((!np->autoneg && np->duplex == 0) ||
3690             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3691                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3692                        dev->name);
3693                 return -EINVAL;
3694         }
3695         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3696                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3697                 return -EINVAL;
3698         }
3699
3700         netif_carrier_off(dev);
3701         if (netif_running(dev)) {
3702                 nv_disable_irq(dev);
3703                 netif_tx_lock_bh(dev);
3704                 spin_lock(&np->lock);
3705                 /* stop engines */
3706                 nv_stop_rx(dev);
3707                 nv_stop_tx(dev);
3708                 spin_unlock(&np->lock);
3709                 netif_tx_unlock_bh(dev);
3710         }
3711
3712         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3713         if (pause->rx_pause)
3714                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3715         if (pause->tx_pause)
3716                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3717
3718         if (np->autoneg && pause->autoneg) {
3719                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3720
3721                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3722                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3723                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3724                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3725                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3726                         adv |=  ADVERTISE_PAUSE_ASYM;
3727                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3728
3729                 if (netif_running(dev))
3730                         printk(KERN_INFO "%s: link down.\n", dev->name);
3731                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3732                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3733                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3734         } else {
3735                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3736                 if (pause->rx_pause)
3737                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3738                 if (pause->tx_pause)
3739                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3740
3741                 if (!netif_running(dev))
3742                         nv_update_linkspeed(dev);
3743                 else
3744                         nv_update_pause(dev, np->pause_flags);
3745         }
3746
3747         if (netif_running(dev)) {
3748                 nv_start_rx(dev);
3749                 nv_start_tx(dev);
3750                 nv_enable_irq(dev);
3751         }
3752         return 0;
3753 }
3754
3755 static u32 nv_get_rx_csum(struct net_device *dev)
3756 {
3757         struct fe_priv *np = netdev_priv(dev);
3758         return (np->rx_csum) != 0;
3759 }
3760
3761 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3762 {
3763         struct fe_priv *np = netdev_priv(dev);
3764         u8 __iomem *base = get_hwbase(dev);
3765         int retcode = 0;
3766
3767         if (np->driver_data & DEV_HAS_CHECKSUM) {
3768                 if (data) {
3769                         np->rx_csum = 1;
3770                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3771                 } else {
3772                         np->rx_csum = 0;
3773                         /* vlan is dependent on rx checksum offload */
3774                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
3775                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3776                 }
3777                 if (netif_running(dev)) {
3778                         spin_lock_irq(&np->lock);
3779                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3780                         spin_unlock_irq(&np->lock);
3781                 }
3782         } else {
3783                 return -EINVAL;
3784         }
3785
3786         return retcode;
3787 }
3788
3789 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3790 {
3791         struct fe_priv *np = netdev_priv(dev);
3792
3793         if (np->driver_data & DEV_HAS_CHECKSUM)
3794                 return ethtool_op_set_tx_hw_csum(dev, data);
3795         else
3796                 return -EOPNOTSUPP;
3797 }
3798
3799 static int nv_set_sg(struct net_device *dev, u32 data)
3800 {
3801         struct fe_priv *np = netdev_priv(dev);
3802
3803         if (np->driver_data & DEV_HAS_CHECKSUM)
3804                 return ethtool_op_set_sg(dev, data);
3805         else
3806                 return -EOPNOTSUPP;
3807 }
3808
3809 static int nv_get_stats_count(struct net_device *dev)
3810 {
3811         struct fe_priv *np = netdev_priv(dev);
3812
3813         if (np->driver_data & DEV_HAS_STATISTICS)
3814                 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
3815         else
3816                 return 0;
3817 }
3818
3819 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3820 {
3821         struct fe_priv *np = netdev_priv(dev);
3822
3823         /* update stats */
3824         nv_do_stats_poll((unsigned long)dev);
3825
3826         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3827 }
3828
3829 static int nv_self_test_count(struct net_device *dev)
3830 {
3831         struct fe_priv *np = netdev_priv(dev);
3832
3833         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3834                 return NV_TEST_COUNT_EXTENDED;
3835         else
3836                 return NV_TEST_COUNT_BASE;
3837 }
3838
3839 static int nv_link_test(struct net_device *dev)
3840 {
3841         struct fe_priv *np = netdev_priv(dev);
3842         int mii_status;
3843
3844         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3845         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3846
3847         /* check phy link status */
3848         if (!(mii_status & BMSR_LSTATUS))
3849                 return 0;
3850         else
3851                 return 1;
3852 }
3853
3854 static int nv_register_test(struct net_device *dev)
3855 {
3856         u8 __iomem *base = get_hwbase(dev);
3857         int i = 0;
3858         u32 orig_read, new_read;
3859
3860         do {
3861                 orig_read = readl(base + nv_registers_test[i].reg);
3862
3863                 /* xor with mask to toggle bits */
3864                 orig_read ^= nv_registers_test[i].mask;
3865
3866                 writel(orig_read, base + nv_registers_test[i].reg);
3867
3868                 new_read = readl(base + nv_registers_test[i].reg);
3869
3870                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3871                         return 0;
3872
3873                 /* restore original value */
3874                 orig_read ^= nv_registers_test[i].mask;
3875                 writel(orig_read, base + nv_registers_test[i].reg);
3876
3877         } while (nv_registers_test[++i].reg != 0);
3878
3879         return 1;
3880 }
3881
3882 static int nv_interrupt_test(struct net_device *dev)
3883 {
3884         struct fe_priv *np = netdev_priv(dev);
3885         u8 __iomem *base = get_hwbase(dev);
3886         int ret = 1;
3887         int testcnt;
3888         u32 save_msi_flags, save_poll_interval = 0;
3889
3890         if (netif_running(dev)) {
3891                 /* free current irq */
3892                 nv_free_irq(dev);
3893                 save_poll_interval = readl(base+NvRegPollingInterval);
3894         }
3895
3896         /* flag to test interrupt handler */
3897         np->intr_test = 0;
3898
3899         /* setup test irq */
3900         save_msi_flags = np->msi_flags;
3901         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3902         np->msi_flags |= 0x001; /* setup 1 vector */
3903         if (nv_request_irq(dev, 1))
3904                 return 0;
3905
3906         /* setup timer interrupt */
3907         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3908         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3909
3910         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3911
3912         /* wait for at least one interrupt */
3913         msleep(100);
3914
3915         spin_lock_irq(&np->lock);
3916
3917         /* flag should be set within ISR */
3918         testcnt = np->intr_test;
3919         if (!testcnt)
3920                 ret = 2;
3921
3922         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3923         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3924                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3925         else
3926                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3927
3928         spin_unlock_irq(&np->lock);
3929
3930         nv_free_irq(dev);
3931
3932         np->msi_flags = save_msi_flags;
3933
3934         if (netif_running(dev)) {
3935                 writel(save_poll_interval, base + NvRegPollingInterval);
3936                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3937                 /* restore original irq */
3938                 if (nv_request_irq(dev, 0))
3939                         return 0;
3940         }
3941
3942         return ret;
3943 }
3944
3945 static int nv_loopback_test(struct net_device *dev)
3946 {
3947         struct fe_priv *np = netdev_priv(dev);
3948         u8 __iomem *base = get_hwbase(dev);
3949         struct sk_buff *tx_skb, *rx_skb;
3950         dma_addr_t test_dma_addr;
3951         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3952         u32 flags;
3953         int len, i, pkt_len;
3954         u8 *pkt_data;
3955         u32 filter_flags = 0;
3956         u32 misc1_flags = 0;
3957         int ret = 1;
3958
3959         if (netif_running(dev)) {
3960                 nv_disable_irq(dev);
3961                 filter_flags = readl(base + NvRegPacketFilterFlags);
3962                 misc1_flags = readl(base + NvRegMisc1);
3963         } else {
3964                 nv_txrx_reset(dev);
3965         }
3966
3967         /* reinit driver view of the rx queue */
3968         set_bufsize(dev);
3969         nv_init_ring(dev);
3970
3971         /* setup hardware for loopback */
3972         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3973         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3974
3975         /* reinit nic view of the rx queue */
3976         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3977         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3978         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3979                 base + NvRegRingSizes);
3980         pci_push(base);
3981
3982         /* restart rx engine */
3983         nv_start_rx(dev);
3984         nv_start_tx(dev);
3985
3986         /* setup packet for tx */
3987         pkt_len = ETH_DATA_LEN;
3988         tx_skb = dev_alloc_skb(pkt_len);
3989         if (!tx_skb) {
3990                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
3991                          " of %s\n", dev->name);
3992                 ret = 0;
3993                 goto out;
3994         }
3995         pkt_data = skb_put(tx_skb, pkt_len);
3996         for (i = 0; i < pkt_len; i++)
3997                 pkt_data[i] = (u8)(i & 0xff);
3998         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3999                                        tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
4000
4001         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4002                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4003                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4004         } else {
4005                 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
4006                 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
4007                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4008         }
4009         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4010         pci_push(get_hwbase(dev));
4011
4012         msleep(500);
4013
4014         /* check for rx of the packet */
4015         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4016                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4017                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4018
4019         } else {
4020                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4021                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4022         }
4023
4024         if (flags & NV_RX_AVAIL) {
4025                 ret = 0;
4026         } else if (np->desc_ver == DESC_VER_1) {
4027                 if (flags & NV_RX_ERROR)
4028                         ret = 0;
4029         } else {
4030                 if (flags & NV_RX2_ERROR) {
4031                         ret = 0;
4032                 }
4033         }
4034
4035         if (ret) {
4036                 if (len != pkt_len) {
4037                         ret = 0;
4038                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4039                                 dev->name, len, pkt_len);
4040                 } else {
4041                         rx_skb = np->rx_skb[0].skb;
4042                         for (i = 0; i < pkt_len; i++) {
4043                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4044                                         ret = 0;
4045                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4046                                                 dev->name, i);
4047                                         break;
4048                                 }
4049                         }
4050                 }
4051         } else {
4052                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4053         }
4054
4055         pci_unmap_page(np->pci_dev, test_dma_addr,
4056                        tx_skb->end-tx_skb->data,
4057                        PCI_DMA_TODEVICE);
4058         dev_kfree_skb_any(tx_skb);
4059  out:
4060         /* stop engines */
4061         nv_stop_rx(dev);
4062         nv_stop_tx(dev);
4063         nv_txrx_reset(dev);
4064         /* drain rx queue */
4065         nv_drain_rx(dev);
4066         nv_drain_tx(dev);
4067
4068         if (netif_running(dev)) {
4069                 writel(misc1_flags, base + NvRegMisc1);
4070                 writel(filter_flags, base + NvRegPacketFilterFlags);
4071                 nv_enable_irq(dev);
4072         }
4073
4074         return ret;
4075 }
4076
4077 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4078 {
4079         struct fe_priv *np = netdev_priv(dev);
4080         u8 __iomem *base = get_hwbase(dev);
4081         int result;
4082         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
4083
4084         if (!nv_link_test(dev)) {
4085                 test->flags |= ETH_TEST_FL_FAILED;
4086                 buffer[0] = 1;
4087         }
4088
4089         if (test->flags & ETH_TEST_FL_OFFLINE) {
4090                 if (netif_running(dev)) {
4091                         netif_stop_queue(dev);
4092                         netif_poll_disable(dev);
4093                         netif_tx_lock_bh(dev);
4094                         spin_lock_irq(&np->lock);
4095                         nv_disable_hw_interrupts(dev, np->irqmask);
4096                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4097                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4098                         } else {
4099                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4100                         }
4101                         /* stop engines */
4102                         nv_stop_rx(dev);
4103                         nv_stop_tx(dev);
4104                         nv_txrx_reset(dev);
4105                         /* drain rx queue */
4106                         nv_drain_rx(dev);
4107                         nv_drain_tx(dev);
4108                         spin_unlock_irq(&np->lock);
4109                         netif_tx_unlock_bh(dev);
4110                 }
4111
4112                 if (!nv_register_test(dev)) {
4113                         test->flags |= ETH_TEST_FL_FAILED;
4114                         buffer[1] = 1;
4115                 }
4116
4117                 result = nv_interrupt_test(dev);
4118                 if (result != 1) {
4119                         test->flags |= ETH_TEST_FL_FAILED;
4120                         buffer[2] = 1;
4121                 }
4122                 if (result == 0) {
4123                         /* bail out */
4124                         return;
4125                 }
4126
4127                 if (!nv_loopback_test(dev)) {
4128                         test->flags |= ETH_TEST_FL_FAILED;
4129                         buffer[3] = 1;
4130                 }
4131
4132                 if (netif_running(dev)) {
4133                         /* reinit driver view of the rx queue */
4134                         set_bufsize(dev);
4135                         if (nv_init_ring(dev)) {
4136                                 if (!np->in_shutdown)
4137                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4138                         }
4139                         /* reinit nic view of the rx queue */
4140                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4141                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4142                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4143                                 base + NvRegRingSizes);
4144                         pci_push(base);
4145                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4146                         pci_push(base);
4147                         /* restart rx engine */
4148                         nv_start_rx(dev);
4149                         nv_start_tx(dev);
4150                         netif_start_queue(dev);
4151                         netif_poll_enable(dev);
4152                         nv_enable_hw_interrupts(dev, np->irqmask);
4153                 }
4154         }
4155 }
4156
4157 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4158 {
4159         switch (stringset) {
4160         case ETH_SS_STATS:
4161                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
4162                 break;
4163         case ETH_SS_TEST:
4164                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
4165                 break;
4166         }
4167 }
4168
4169 static const struct ethtool_ops ops = {
4170         .get_drvinfo = nv_get_drvinfo,
4171         .get_link = ethtool_op_get_link,
4172         .get_wol = nv_get_wol,
4173         .set_wol = nv_set_wol,
4174         .get_settings = nv_get_settings,
4175         .set_settings = nv_set_settings,
4176         .get_regs_len = nv_get_regs_len,
4177         .get_regs = nv_get_regs,
4178         .nway_reset = nv_nway_reset,
4179         .get_perm_addr = ethtool_op_get_perm_addr,
4180         .get_tso = ethtool_op_get_tso,
4181         .set_tso = nv_set_tso,
4182         .get_ringparam = nv_get_ringparam,
4183         .set_ringparam = nv_set_ringparam,
4184         .get_pauseparam = nv_get_pauseparam,
4185         .set_pauseparam = nv_set_pauseparam,
4186         .get_rx_csum = nv_get_rx_csum,
4187         .set_rx_csum = nv_set_rx_csum,
4188         .get_tx_csum = ethtool_op_get_tx_csum,
4189         .set_tx_csum = nv_set_tx_csum,
4190         .get_sg = ethtool_op_get_sg,
4191         .set_sg = nv_set_sg,
4192         .get_strings = nv_get_strings,
4193         .get_stats_count = nv_get_stats_count,
4194         .get_ethtool_stats = nv_get_ethtool_stats,
4195         .self_test_count = nv_self_test_count,
4196         .self_test = nv_self_test,
4197 };
4198
4199 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4200 {
4201         struct fe_priv *np = get_nvpriv(dev);
4202
4203         spin_lock_irq(&np->lock);
4204
4205         /* save vlan group */
4206         np->vlangrp = grp;
4207
4208         if (grp) {
4209                 /* enable vlan on MAC */
4210                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4211         } else {
4212                 /* disable vlan on MAC */
4213                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4214                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4215         }
4216
4217         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4218
4219         spin_unlock_irq(&np->lock);
4220 };
4221
4222 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4223 {
4224         /* nothing to do */
4225 };
4226
4227 /* The mgmt unit and driver use a semaphore to access the phy during init */
4228 static int nv_mgmt_acquire_sema(struct net_device *dev)
4229 {
4230         u8 __iomem *base = get_hwbase(dev);
4231         int i;
4232         u32 tx_ctrl, mgmt_sema;
4233
4234         for (i = 0; i < 10; i++) {
4235                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4236                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4237                         break;
4238                 msleep(500);
4239         }
4240
4241         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4242                 return 0;
4243
4244         for (i = 0; i < 2; i++) {
4245                 tx_ctrl = readl(base + NvRegTransmitterControl);
4246                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4247                 writel(tx_ctrl, base + NvRegTransmitterControl);
4248
4249                 /* verify that semaphore was acquired */
4250                 tx_ctrl = readl(base + NvRegTransmitterControl);
4251                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4252                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4253                         return 1;
4254                 else
4255                         udelay(50);
4256         }
4257
4258         return 0;
4259 }
4260
4261 static int nv_open(struct net_device *dev)
4262 {
4263         struct fe_priv *np = netdev_priv(dev);
4264         u8 __iomem *base = get_hwbase(dev);
4265         int ret = 1;
4266         int oom, i;
4267
4268         dprintk(KERN_DEBUG "nv_open: begin\n");
4269
4270         /* erase previous misconfiguration */
4271         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4272                 nv_mac_reset(dev);
4273         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4274         writel(0, base + NvRegMulticastAddrB);
4275         writel(0, base + NvRegMulticastMaskA);
4276         writel(0, base + NvRegMulticastMaskB);
4277         writel(0, base + NvRegPacketFilterFlags);
4278
4279         writel(0, base + NvRegTransmitterControl);
4280         writel(0, base + NvRegReceiverControl);
4281
4282         writel(0, base + NvRegAdapterControl);
4283
4284         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4285                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4286
4287         /* initialize descriptor rings */
4288         set_bufsize(dev);
4289         oom = nv_init_ring(dev);
4290
4291         writel(0, base + NvRegLinkSpeed);
4292         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4293         nv_txrx_reset(dev);
4294         writel(0, base + NvRegUnknownSetupReg6);
4295
4296         np->in_shutdown = 0;
4297
4298         /* give hw rings */
4299         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4300         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4301                 base + NvRegRingSizes);
4302
4303         writel(np->linkspeed, base + NvRegLinkSpeed);
4304         if (np->desc_ver == DESC_VER_1)
4305                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4306         else
4307                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4308         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4309         writel(np->vlanctl_bits, base + NvRegVlanControl);
4310         pci_push(base);
4311         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4312         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4313                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4314                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4315
4316         writel(0, base + NvRegMIIMask);
4317         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4318         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4319
4320         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4321         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4322         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4323         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4324
4325         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4326         get_random_bytes(&i, sizeof(i));
4327         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4328         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4329         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4330         if (poll_interval == -1) {
4331                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4332                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4333                 else
4334                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4335         }
4336         else
4337                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4338         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4339         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4340                         base + NvRegAdapterControl);
4341         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4342         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4343         if (np->wolenabled)
4344                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4345
4346         i = readl(base + NvRegPowerState);
4347         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4348                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4349
4350         pci_push(base);
4351         udelay(10);
4352         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4353
4354         nv_disable_hw_interrupts(dev, np->irqmask);
4355         pci_push(base);
4356         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4357         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4358         pci_push(base);
4359
4360         if (nv_request_irq(dev, 0)) {
4361                 goto out_drain;
4362         }
4363
4364         /* ask for interrupts */
4365         nv_enable_hw_interrupts(dev, np->irqmask);
4366
4367         spin_lock_irq(&np->lock);
4368         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4369         writel(0, base + NvRegMulticastAddrB);
4370         writel(0, base + NvRegMulticastMaskA);
4371         writel(0, base + NvRegMulticastMaskB);
4372         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4373         /* One manual link speed update: Interrupts are enabled, future link
4374          * speed changes cause interrupts and are handled by nv_link_irq().
4375          */
4376         {
4377                 u32 miistat;
4378                 miistat = readl(base + NvRegMIIStatus);
4379                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4380                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4381         }
4382         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4383          * to init hw */
4384         np->linkspeed = 0;
4385         ret = nv_update_linkspeed(dev);
4386         nv_start_rx(dev);
4387         nv_start_tx(dev);
4388         netif_start_queue(dev);
4389         netif_poll_enable(dev);
4390
4391         if (ret) {
4392                 netif_carrier_on(dev);
4393         } else {
4394                 printk("%s: no link during initialization.\n", dev->name);
4395                 netif_carrier_off(dev);
4396         }
4397         if (oom)
4398                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4399
4400         /* start statistics timer */
4401         if (np->driver_data & DEV_HAS_STATISTICS)
4402                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4403
4404         spin_unlock_irq(&np->lock);
4405
4406         return 0;
4407 out_drain:
4408         drain_ring(dev);
4409         return ret;
4410 }
4411
4412 static int nv_close(struct net_device *dev)
4413 {
4414         struct fe_priv *np = netdev_priv(dev);
4415         u8 __iomem *base;
4416
4417         spin_lock_irq(&np->lock);
4418         np->in_shutdown = 1;
4419         spin_unlock_irq(&np->lock);
4420         netif_poll_disable(dev);
4421         synchronize_irq(dev->irq);
4422
4423         del_timer_sync(&np->oom_kick);
4424         del_timer_sync(&np->nic_poll);
4425         del_timer_sync(&np->stats_poll);
4426
4427         netif_stop_queue(dev);
4428         spin_lock_irq(&np->lock);
4429         nv_stop_tx(dev);
4430         nv_stop_rx(dev);
4431         nv_txrx_reset(dev);
4432
4433         /* disable interrupts on the nic or we will lock up */
4434         base = get_hwbase(dev);
4435         nv_disable_hw_interrupts(dev, np->irqmask);
4436         pci_push(base);
4437         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4438
4439         spin_unlock_irq(&np->lock);
4440
4441         nv_free_irq(dev);
4442
4443         drain_ring(dev);
4444
4445         if (np->wolenabled)
4446                 nv_start_rx(dev);
4447
4448         /* FIXME: power down nic */
4449
4450         return 0;
4451 }
4452
4453 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4454 {
4455         struct net_device *dev;
4456         struct fe_priv *np;
4457         unsigned long addr;
4458         u8 __iomem *base;
4459         int err, i;
4460         u32 powerstate, txreg;
4461         u32 phystate_orig = 0, phystate;
4462         int phyinitialized = 0;
4463
4464         dev = alloc_etherdev(sizeof(struct fe_priv));
4465         err = -ENOMEM;
4466         if (!dev)
4467                 goto out;
4468
4469         np = netdev_priv(dev);
4470         np->pci_dev = pci_dev;
4471         spin_lock_init(&np->lock);
4472         SET_MODULE_OWNER(dev);
4473         SET_NETDEV_DEV(dev, &pci_dev->dev);
4474
4475         init_timer(&np->oom_kick);
4476         np->oom_kick.data = (unsigned long) dev;
4477         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4478         init_timer(&np->nic_poll);
4479         np->nic_poll.data = (unsigned long) dev;
4480         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4481         init_timer(&np->stats_poll);
4482         np->stats_poll.data = (unsigned long) dev;
4483         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4484
4485         err = pci_enable_device(pci_dev);
4486         if (err) {
4487                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4488                                 err, pci_name(pci_dev));
4489                 goto out_free;
4490         }
4491
4492         pci_set_master(pci_dev);
4493
4494         err = pci_request_regions(pci_dev, DRV_NAME);
4495         if (err < 0)
4496                 goto out_disable;
4497
4498         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4499                 np->register_size = NV_PCI_REGSZ_VER2;
4500         else
4501                 np->register_size = NV_PCI_REGSZ_VER1;
4502
4503         err = -EINVAL;
4504         addr = 0;
4505         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4506                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4507                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4508                                 pci_resource_len(pci_dev, i),
4509                                 pci_resource_flags(pci_dev, i));
4510                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4511                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4512                         addr = pci_resource_start(pci_dev, i);
4513                         break;
4514                 }
4515         }
4516         if (i == DEVICE_COUNT_RESOURCE) {
4517                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4518                                         pci_name(pci_dev));
4519                 goto out_relreg;
4520         }
4521
4522         /* copy of driver data */
4523         np->driver_data = id->driver_data;
4524
4525         /* handle different descriptor versions */
4526         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4527                 /* packet format 3: supports 40-bit addressing */
4528                 np->desc_ver = DESC_VER_3;
4529                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4530                 if (dma_64bit) {
4531                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4532                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4533                                        pci_name(pci_dev));
4534                         } else {
4535                                 dev->features |= NETIF_F_HIGHDMA;
4536                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4537                         }
4538                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4539                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4540                                        pci_name(pci_dev));
4541                         }
4542                 }
4543         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4544                 /* packet format 2: supports jumbo frames */
4545                 np->desc_ver = DESC_VER_2;
4546                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4547         } else {
4548                 /* original packet format */
4549                 np->desc_ver = DESC_VER_1;
4550                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4551         }
4552
4553         np->pkt_limit = NV_PKTLIMIT_1;
4554         if (id->driver_data & DEV_HAS_LARGEDESC)
4555                 np->pkt_limit = NV_PKTLIMIT_2;
4556
4557         if (id->driver_data & DEV_HAS_CHECKSUM) {
4558                 np->rx_csum = 1;
4559                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4560                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4561                 dev->features |= NETIF_F_TSO;
4562         }
4563
4564         np->vlanctl_bits = 0;
4565         if (id->driver_data & DEV_HAS_VLAN) {
4566                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4567                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4568                 dev->vlan_rx_register = nv_vlan_rx_register;
4569                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4570         }
4571
4572         np->msi_flags = 0;
4573         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4574                 np->msi_flags |= NV_MSI_CAPABLE;
4575         }
4576         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4577                 np->msi_flags |= NV_MSI_X_CAPABLE;
4578         }
4579
4580         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4581         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4582                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4583         }
4584
4585
4586         err = -ENOMEM;
4587         np->base = ioremap(addr, np->register_size);
4588         if (!np->base)
4589                 goto out_relreg;
4590         dev->base_addr = (unsigned long)np->base;
4591
4592         dev->irq = pci_dev->irq;
4593
4594         np->rx_ring_size = RX_RING_DEFAULT;
4595         np->tx_ring_size = TX_RING_DEFAULT;
4596         np->tx_limit_stop = TX_LIMIT_DIFFERENCE;
4597         np->tx_limit_start = TX_LIMIT_DIFFERENCE;
4598
4599         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4600                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4601                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4602                                         &np->ring_addr);
4603                 if (!np->rx_ring.orig)
4604                         goto out_unmap;
4605                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4606         } else {
4607                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4608                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4609                                         &np->ring_addr);
4610                 if (!np->rx_ring.ex)
4611                         goto out_unmap;
4612                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4613         }
4614         np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL);
4615         np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL);
4616         if (!np->rx_skb || !np->tx_skb)
4617                 goto out_freering;
4618         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4619         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4620
4621         dev->open = nv_open;
4622         dev->stop = nv_close;
4623         dev->hard_start_xmit = nv_start_xmit;
4624         dev->get_stats = nv_get_stats;
4625         dev->change_mtu = nv_change_mtu;
4626         dev->set_mac_address = nv_set_mac_address;
4627         dev->set_multicast_list = nv_set_multicast;
4628 #ifdef CONFIG_NET_POLL_CONTROLLER
4629         dev->poll_controller = nv_poll_controller;
4630 #endif
4631         dev->weight = 64;
4632 #ifdef CONFIG_FORCEDETH_NAPI
4633         dev->poll = nv_napi_poll;
4634 #endif
4635         SET_ETHTOOL_OPS(dev, &ops);
4636         dev->tx_timeout = nv_tx_timeout;
4637         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4638
4639         pci_set_drvdata(pci_dev, dev);
4640
4641         /* read the mac address */
4642         base = get_hwbase(dev);
4643         np->orig_mac[0] = readl(base + NvRegMacAddrA);
4644         np->orig_mac[1] = readl(base + NvRegMacAddrB);
4645
4646         /* check the workaround bit for correct mac address order */
4647         txreg = readl(base + NvRegTransmitPoll);
4648         if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
4649                 /* mac address is already in correct order */
4650                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
4651                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
4652                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
4653                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
4654                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
4655                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
4656         } else {
4657                 /* need to reverse mac address to correct order */
4658                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
4659                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
4660                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4661                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4662                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
4663                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
4664                 /* set permanent address to be correct aswell */
4665                 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
4666                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
4667                 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
4668                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4669         }
4670         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4671
4672         if (!is_valid_ether_addr(dev->perm_addr)) {
4673                 /*
4674                  * Bad mac address. At least one bios sets the mac address
4675                  * to 01:23:45:67:89:ab
4676                  */
4677                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4678                         pci_name(pci_dev),
4679                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4680                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4681                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4682                 dev->dev_addr[0] = 0x00;
4683                 dev->dev_addr[1] = 0x00;
4684                 dev->dev_addr[2] = 0x6c;
4685                 get_random_bytes(&dev->dev_addr[3], 3);
4686         }
4687
4688         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4689                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4690                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4691
4692         /* set mac address */
4693         nv_copy_mac_to_hw(dev);
4694
4695         /* disable WOL */
4696         writel(0, base + NvRegWakeUpFlags);
4697         np->wolenabled = 0;
4698
4699         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4700                 u8 revision_id;
4701                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4702
4703                 /* take phy and nic out of low power mode */
4704                 powerstate = readl(base + NvRegPowerState2);
4705                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4706                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4707                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4708                     revision_id >= 0xA3)
4709                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4710                 writel(powerstate, base + NvRegPowerState2);
4711         }
4712
4713         if (np->desc_ver == DESC_VER_1) {
4714                 np->tx_flags = NV_TX_VALID;
4715         } else {
4716                 np->tx_flags = NV_TX2_VALID;
4717         }
4718         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4719                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4720                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4721                         np->msi_flags |= 0x0003;
4722         } else {
4723                 np->irqmask = NVREG_IRQMASK_CPU;
4724                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4725                         np->msi_flags |= 0x0001;
4726         }
4727
4728         if (id->driver_data & DEV_NEED_TIMERIRQ)
4729                 np->irqmask |= NVREG_IRQ_TIMER;
4730         if (id->driver_data & DEV_NEED_LINKTIMER) {
4731                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4732                 np->need_linktimer = 1;
4733                 np->link_timeout = jiffies + LINK_TIMEOUT;
4734         } else {
4735                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4736                 np->need_linktimer = 0;
4737         }
4738
4739         /* clear phy state and temporarily halt phy interrupts */
4740         writel(0, base + NvRegMIIMask);
4741         phystate = readl(base + NvRegAdapterControl);
4742         if (phystate & NVREG_ADAPTCTL_RUNNING) {
4743                 phystate_orig = 1;
4744                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
4745                 writel(phystate, base + NvRegAdapterControl);
4746         }
4747         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4748
4749         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
4750                 /* management unit running on the mac? */
4751                 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
4752                         np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
4753                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
4754                         for (i = 0; i < 5000; i++) {
4755                                 msleep(1);
4756                                 if (nv_mgmt_acquire_sema(dev)) {
4757                                         /* management unit setup the phy already? */
4758                                         if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
4759                                             NVREG_XMITCTL_SYNC_PHY_INIT) {
4760                                                 /* phy is inited by mgmt unit */
4761                                                 phyinitialized = 1;
4762                                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
4763                                         } else {
4764                                                 /* we need to init the phy */
4765                                         }
4766                                         break;
4767                                 }
4768                         }
4769                 }
4770         }
4771
4772         /* find a suitable phy */
4773         for (i = 1; i <= 32; i++) {
4774                 int id1, id2;
4775                 int phyaddr = i & 0x1F;
4776
4777                 spin_lock_irq(&np->lock);
4778                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4779                 spin_unlock_irq(&np->lock);
4780                 if (id1 < 0 || id1 == 0xffff)
4781                         continue;
4782                 spin_lock_irq(&np->lock);
4783                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4784                 spin_unlock_irq(&np->lock);
4785                 if (id2 < 0 || id2 == 0xffff)
4786                         continue;
4787
4788                 np->phy_model = id2 & PHYID2_MODEL_MASK;
4789                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4790                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4791                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4792                         pci_name(pci_dev), id1, id2, phyaddr);
4793                 np->phyaddr = phyaddr;
4794                 np->phy_oui = id1 | id2;
4795                 break;
4796         }
4797         if (i == 33) {
4798                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4799                        pci_name(pci_dev));
4800                 goto out_error;
4801         }
4802
4803         if (!phyinitialized) {
4804                 /* reset it */
4805                 phy_init(dev);
4806         } else {
4807                 /* see if it is a gigabit phy */
4808                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4809                 if (mii_status & PHY_GIGABIT) {
4810                         np->gigabit = PHY_GIGABIT;
4811                 }
4812         }
4813
4814         /* set default link speed settings */
4815         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4816         np->duplex = 0;
4817         np->autoneg = 1;
4818
4819         err = register_netdev(dev);
4820         if (err) {
4821                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4822                 goto out_error;
4823         }
4824         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4825                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4826                         pci_name(pci_dev));
4827
4828         return 0;
4829
4830 out_error:
4831         if (phystate_orig)
4832                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
4833         pci_set_drvdata(pci_dev, NULL);
4834 out_freering:
4835         free_rings(dev);
4836 out_unmap:
4837         iounmap(get_hwbase(dev));
4838 out_relreg:
4839         pci_release_regions(pci_dev);
4840 out_disable:
4841         pci_disable_device(pci_dev);
4842 out_free:
4843         free_netdev(dev);
4844 out:
4845         return err;
4846 }
4847
4848 static void __devexit nv_remove(struct pci_dev *pci_dev)
4849 {
4850         struct net_device *dev = pci_get_drvdata(pci_dev);
4851         struct fe_priv *np = netdev_priv(dev);
4852         u8 __iomem *base = get_hwbase(dev);
4853
4854         unregister_netdev(dev);
4855
4856         /* special op: write back the misordered MAC address - otherwise
4857          * the next nv_probe would see a wrong address.
4858          */
4859         writel(np->orig_mac[0], base + NvRegMacAddrA);
4860         writel(np->orig_mac[1], base + NvRegMacAddrB);
4861
4862         /* free all structures */
4863         free_rings(dev);
4864         iounmap(get_hwbase(dev));
4865         pci_release_regions(pci_dev);
4866         pci_disable_device(pci_dev);
4867         free_netdev(dev);
4868         pci_set_drvdata(pci_dev, NULL);
4869 }
4870
4871 #ifdef CONFIG_PM
4872 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
4873 {
4874         struct net_device *dev = pci_get_drvdata(pdev);
4875         struct fe_priv *np = netdev_priv(dev);
4876
4877         if (!netif_running(dev))
4878                 goto out;
4879
4880         netif_device_detach(dev);
4881
4882         // Gross.
4883         nv_close(dev);
4884
4885         pci_save_state(pdev);
4886         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
4887         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4888 out:
4889         return 0;
4890 }
4891
4892 static int nv_resume(struct pci_dev *pdev)
4893 {
4894         struct net_device *dev = pci_get_drvdata(pdev);
4895         int rc = 0;
4896
4897         if (!netif_running(dev))
4898                 goto out;
4899
4900         netif_device_attach(dev);
4901
4902         pci_set_power_state(pdev, PCI_D0);
4903         pci_restore_state(pdev);
4904         pci_enable_wake(pdev, PCI_D0, 0);
4905
4906         rc = nv_open(dev);
4907 out:
4908         return rc;
4909 }
4910 #else
4911 #define nv_suspend NULL
4912 #define nv_resume NULL
4913 #endif /* CONFIG_PM */
4914
4915 static struct pci_device_id pci_tbl[] = {
4916         {       /* nForce Ethernet Controller */
4917                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4918                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4919         },
4920         {       /* nForce2 Ethernet Controller */
4921                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4922                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4923         },
4924         {       /* nForce3 Ethernet Controller */
4925                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4926                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4927         },
4928         {       /* nForce3 Ethernet Controller */
4929                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4930                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4931         },
4932         {       /* nForce3 Ethernet Controller */
4933                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4934                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4935         },
4936         {       /* nForce3 Ethernet Controller */
4937                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4938                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4939         },
4940         {       /* nForce3 Ethernet Controller */
4941                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4942                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4943         },
4944         {       /* CK804 Ethernet Controller */
4945                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4946                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4947         },
4948         {       /* CK804 Ethernet Controller */
4949                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4950                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4951         },
4952         {       /* MCP04 Ethernet Controller */
4953                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4954                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4955         },
4956         {       /* MCP04 Ethernet Controller */
4957                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4958                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4959         },
4960         {       /* MCP51 Ethernet Controller */
4961                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4962                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4963         },
4964         {       /* MCP51 Ethernet Controller */
4965                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4966                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4967         },
4968         {       /* MCP55 Ethernet Controller */
4969                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4970                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4971         },
4972         {       /* MCP55 Ethernet Controller */
4973                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4974                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4975         },
4976         {       /* MCP61 Ethernet Controller */
4977                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4978                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4979         },
4980         {       /* MCP61 Ethernet Controller */
4981                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4982                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4983         },
4984         {       /* MCP61 Ethernet Controller */
4985                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4986                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4987         },
4988         {       /* MCP61 Ethernet Controller */
4989                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4990                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4991         },
4992         {       /* MCP65 Ethernet Controller */
4993                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4994                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4995         },
4996         {       /* MCP65 Ethernet Controller */
4997                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4998                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4999         },
5000         {       /* MCP65 Ethernet Controller */
5001                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5002                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5003         },
5004         {       /* MCP65 Ethernet Controller */
5005                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5006                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5007         },
5008         {       /* MCP67 Ethernet Controller */
5009                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5010                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5011         },
5012         {       /* MCP67 Ethernet Controller */
5013                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5014                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5015         },
5016         {       /* MCP67 Ethernet Controller */
5017                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5018                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5019         },
5020         {       /* MCP67 Ethernet Controller */
5021                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5022                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5023         },
5024         {0,},
5025 };
5026
5027 static struct pci_driver driver = {
5028         .name = "forcedeth",
5029         .id_table = pci_tbl,
5030         .probe = nv_probe,
5031         .remove = __devexit_p(nv_remove),
5032         .suspend = nv_suspend,
5033         .resume = nv_resume,
5034 };
5035
5036 static int __init init_nic(void)
5037 {
5038         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
5039         return pci_register_driver(&driver);
5040 }
5041
5042 static void __exit exit_nic(void)
5043 {
5044         pci_unregister_driver(&driver);
5045 }
5046
5047 module_param(max_interrupt_work, int, 0);
5048 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5049 module_param(optimization_mode, int, 0);
5050 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5051 module_param(poll_interval, int, 0);
5052 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5053 module_param(msi, int, 0);
5054 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5055 module_param(msix, int, 0);
5056 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5057 module_param(dma_64bit, int, 0);
5058 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5059
5060 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5061 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5062 MODULE_LICENSE("GPL");
5063
5064 MODULE_DEVICE_TABLE(pci, pci_tbl);
5065
5066 module_init(init_nic);
5067 module_exit(exit_nic);