git.oblomov.eu Git - linux-2.6/blob - drivers/serial/8250_pci.c

   1 /*
   2  *  linux/drivers/char/8250_pci.c
   3  *
   4  *  Probe module for 8250/16550-type PCI serial ports.
   5  *
   6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   7  *
   8  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17 #include <linux/string.h>
  18 #include <linux/kernel.h>
  19 #include <linux/slab.h>
  20 #include <linux/delay.h>
  21 #include <linux/tty.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/8250_pci.h>
  24 #include <linux/bitops.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/io.h>
  28
  29 #include "8250.h"
  30
  31 #undef SERIAL_DEBUG_PCI
  32
  33 /*
  34  * init function returns:
  35  *  > 0 - number of ports
  36  *  = 0 - use board->num_ports
  37  *  < 0 - error
  38  */
  39 struct pci_serial_quirk {
  40         u32     vendor;
  41         u32     device;
  42         u32     subvendor;
  43         u32     subdevice;
  44         int     (*init)(struct pci_dev *dev);
  45         int     (*setup)(struct serial_private *,
  46                          const struct pciserial_board *,
  47                          struct uart_port *, int);
  48         void    (*exit)(struct pci_dev *dev);
  49 };
  50
  51 #define PCI_NUM_BAR_RESOURCES   6
  52
  53 struct serial_private {
  54         struct pci_dev          *dev;
  55         unsigned int            nr;
  56         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  57         struct pci_serial_quirk *quirk;
  58         int                     line[0];
  59 };
  60
  61 static void moan_device(const char *str, struct pci_dev *dev)
  62 {
  63         printk(KERN_WARNING
  64                "%s: %s\n"
  65                "Please send the output of lspci -vv, this\n"
  66                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  67                "manufacturer and name of serial board or\n"
  68                "modem board to rmk+serial@arm.linux.org.uk.\n",
  69                pci_name(dev), str, dev->vendor, dev->device,
  70                dev->subsystem_vendor, dev->subsystem_device);
  71 }
  72
  73 static int
  74 setup_port(struct serial_private *priv, struct uart_port *port,
  75            int bar, int offset, int regshift)
  76 {
  77         struct pci_dev *dev = priv->dev;
  78         unsigned long base, len;
  79
  80         if (bar >= PCI_NUM_BAR_RESOURCES)
  81                 return -EINVAL;
  82
  83         base = pci_resource_start(dev, bar);
  84
  85         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  86                 len =  pci_resource_len(dev, bar);
  87
  88                 if (!priv->remapped_bar[bar])
  89                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  90                 if (!priv->remapped_bar[bar])
  91                         return -ENOMEM;
  92
  93                 port->iotype = UPIO_MEM;
  94                 port->iobase = 0;
  95                 port->mapbase = base + offset;
  96                 port->membase = priv->remapped_bar[bar] + offset;
  97                 port->regshift = regshift;
  98         } else {
  99                 port->iotype = UPIO_PORT;
 100                 port->iobase = base + offset;
 101                 port->mapbase = 0;
 102                 port->membase = NULL;
 103                 port->regshift = 0;
 104         }
 105         return 0;
 106 }
 107
 108 /*
 109  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 110  */
 111 static int addidata_apci7800_setup(struct serial_private *priv,
 112                                 const struct pciserial_board *board,
 113                                 struct uart_port *port, int idx)
 114 {
 115         unsigned int bar = 0, offset = board->first_offset;
 116         bar = FL_GET_BASE(board->flags);
 117
 118         if (idx < 2) {
 119                 offset += idx * board->uart_offset;
 120         } else if ((idx >= 2) && (idx < 4)) {
 121                 bar += 1;
 122                 offset += ((idx - 2) * board->uart_offset);
 123         } else if ((idx >= 4) && (idx < 6)) {
 124                 bar += 2;
 125                 offset += ((idx - 4) * board->uart_offset);
 126         } else if (idx >= 6) {
 127                 bar += 3;
 128                 offset += ((idx - 6) * board->uart_offset);
 129         }
 130
 131         return setup_port(priv, port, bar, offset, board->reg_shift);
 132 }
 133
 134 /*
 135  * AFAVLAB uses a different mixture of BARs and offsets
 136  * Not that ugly ;) -- HW
 137  */
 138 static int
 139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 140               struct uart_port *port, int idx)
 141 {
 142         unsigned int bar, offset = board->first_offset;
 143
 144         bar = FL_GET_BASE(board->flags);
 145         if (idx < 4)
 146                 bar += idx;
 147         else {
 148                 bar = 4;
 149                 offset += (idx - 4) * board->uart_offset;
 150         }
 151
 152         return setup_port(priv, port, bar, offset, board->reg_shift);
 153 }
 154
 155 /*
 156  * HP's Remote Management Console.  The Diva chip came in several
 157  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 158  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 159  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 160  * one Diva chip, but it has been expanded to 5 UARTs.
 161  */
 162 static int pci_hp_diva_init(struct pci_dev *dev)
 163 {
 164         int rc = 0;
 165
 166         switch (dev->subsystem_device) {
 167         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 168         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 169         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 170         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 171                 rc = 3;
 172                 break;
 173         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 174                 rc = 2;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 177                 rc = 4;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 180         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 181                 rc = 1;
 182                 break;
 183         }
 184
 185         return rc;
 186 }
 187
 188 /*
 189  * HP's Diva chip puts the 4th/5th serial port further out, and
 190  * some serial ports are supposed to be hidden on certain models.
 191  */
 192 static int
 193 pci_hp_diva_setup(struct serial_private *priv,
 194                 const struct pciserial_board *board,
 195                 struct uart_port *port, int idx)
 196 {
 197         unsigned int offset = board->first_offset;
 198         unsigned int bar = FL_GET_BASE(board->flags);
 199
 200         switch (priv->dev->subsystem_device) {
 201         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 202                 if (idx == 3)
 203                         idx++;
 204                 break;
 205         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 206                 if (idx > 0)
 207                         idx++;
 208                 if (idx > 2)
 209                         idx++;
 210                 break;
 211         }
 212         if (idx > 2)
 213                 offset = 0x18;
 214
 215         offset += idx * board->uart_offset;
 216
 217         return setup_port(priv, port, bar, offset, board->reg_shift);
 218 }
 219
 220 /*
 221  * Added for EKF Intel i960 serial boards
 222  */
 223 static int pci_inteli960ni_init(struct pci_dev *dev)
 224 {
 225         unsigned long oldval;
 226
 227         if (!(dev->subsystem_device & 0x1000))
 228                 return -ENODEV;
 229
 230         /* is firmware started? */
 231         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 232         if (oldval == 0x00001000L) { /* RESET value */
 233                 printk(KERN_DEBUG "Local i960 firmware missing");
 234                 return -ENODEV;
 235         }
 236         return 0;
 237 }
 238
 239 /*
 240  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 241  * that the card interrupt be explicitly enabled or disabled.  This
 242  * seems to be mainly needed on card using the PLX which also use I/O
 243  * mapped memory.
 244  */
 245 static int pci_plx9050_init(struct pci_dev *dev)
 246 {
 247         u8 irq_config;
 248         void __iomem *p;
 249
 250         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 251                 moan_device("no memory in bar 0", dev);
 252                 return 0;
 253         }
 254
 255         irq_config = 0x41;
 256         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 257             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 258                 irq_config = 0x43;
 259
 260         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 261             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 262                 /*
 263                  * As the megawolf cards have the int pins active
 264                  * high, and have 2 UART chips, both ints must be
 265                  * enabled on the 9050. Also, the UARTS are set in
 266                  * 16450 mode by default, so we have to enable the
 267                  * 16C950 'enhanced' mode so that we can use the
 268                  * deep FIFOs
 269                  */
 270                 irq_config = 0x5b;
 271         /*
 272          * enable/disable interrupts
 273          */
 274         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 275         if (p == NULL)
 276                 return -ENOMEM;
 277         writel(irq_config, p + 0x4c);
 278
 279         /*
 280          * Read the register back to ensure that it took effect.
 281          */
 282         readl(p + 0x4c);
 283         iounmap(p);
 284
 285         return 0;
 286 }
 287
 288 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 289 {
 290         u8 __iomem *p;
 291
 292         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 293                 return;
 294
 295         /*
 296          * disable interrupts
 297          */
 298         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 299         if (p != NULL) {
 300                 writel(0, p + 0x4c);
 301
 302                 /*
 303                  * Read the register back to ensure that it took effect.
 304                  */
 305                 readl(p + 0x4c);
 306                 iounmap(p);
 307         }
 308 }
 309
 310 #define NI8420_INT_ENABLE_REG   0x38
 311 #define NI8420_INT_ENABLE_BIT   0x2000
 312
 313 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 314 {
 315         void __iomem *p;
 316         unsigned long base, len;
 317         unsigned int bar = 0;
 318
 319         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 320                 moan_device("no memory in bar", dev);
 321                 return;
 322         }
 323
 324         base = pci_resource_start(dev, bar);
 325         len =  pci_resource_len(dev, bar);
 326         p = ioremap_nocache(base, len);
 327         if (p == NULL)
 328                 return;
 329
 330         /* Disable the CPU Interrupt */
 331         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 332                p + NI8420_INT_ENABLE_REG);
 333         iounmap(p);
 334 }
 335
 336
 337 /* MITE registers */
 338 #define MITE_IOWBSR1    0xc4
 339 #define MITE_IOWCR1     0xf4
 340 #define MITE_LCIMR1     0x08
 341 #define MITE_LCIMR2     0x10
 342
 343 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 344
 345 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 346 {
 347         void __iomem *p;
 348         unsigned long base, len;
 349         unsigned int bar = 0;
 350
 351         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 352                 moan_device("no memory in bar", dev);
 353                 return;
 354         }
 355
 356         base = pci_resource_start(dev, bar);
 357         len =  pci_resource_len(dev, bar);
 358         p = ioremap_nocache(base, len);
 359         if (p == NULL)
 360                 return;
 361
 362         /* Disable the CPU Interrupt */
 363         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 364         iounmap(p);
 365 }
 366
 367 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 368 static int
 369 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 370                 struct uart_port *port, int idx)
 371 {
 372         unsigned int bar, offset = board->first_offset;
 373
 374         bar = 0;
 375
 376         if (idx < 4) {
 377                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 378                 offset += idx * board->uart_offset;
 379         } else if (idx < 8) {
 380                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 381                 offset += idx * board->uart_offset + 0xC00;
 382         } else /* we have only 8 ports on PMC-OCTALPRO */
 383                 return 1;
 384
 385         return setup_port(priv, port, bar, offset, board->reg_shift);
 386 }
 387
 388 /*
 389 * This does initialization for PMC OCTALPRO cards:
 390 * maps the device memory, resets the UARTs (needed, bc
 391 * if the module is removed and inserted again, the card
 392 * is in the sleep mode) and enables global interrupt.
 393 */
 394
 395 /* global control register offset for SBS PMC-OctalPro */
 396 #define OCT_REG_CR_OFF          0x500
 397
 398 static int sbs_init(struct pci_dev *dev)
 399 {
 400         u8 __iomem *p;
 401
 402         p = pci_ioremap_bar(dev, 0);
 403
 404         if (p == NULL)
 405                 return -ENOMEM;
 406         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 407         writeb(0x10, p + OCT_REG_CR_OFF);
 408         udelay(50);
 409         writeb(0x0, p + OCT_REG_CR_OFF);
 410
 411         /* Set bit-2 (INTENABLE) of Control Register */
 412         writeb(0x4, p + OCT_REG_CR_OFF);
 413         iounmap(p);
 414
 415         return 0;
 416 }
 417
 418 /*
 419  * Disables the global interrupt of PMC-OctalPro
 420  */
 421
 422 static void __devexit sbs_exit(struct pci_dev *dev)
 423 {
 424         u8 __iomem *p;
 425
 426         p = pci_ioremap_bar(dev, 0);
 427         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 428         if (p != NULL)
 429                 writeb(0, p + OCT_REG_CR_OFF);
 430         iounmap(p);
 431 }
 432
 433 /*
 434  * SIIG serial cards have an PCI interface chip which also controls
 435  * the UART clocking frequency. Each UART can be clocked independently
 436  * (except cards equiped with 4 UARTs) and initial clocking settings
 437  * are stored in the EEPROM chip. It can cause problems because this
 438  * version of serial driver doesn't support differently clocked UART's
 439  * on single PCI card. To prevent this, initialization functions set
 440  * high frequency clocking for all UART's on given card. It is safe (I
 441  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 442  * with other OSes (like M$ DOS).
 443  *
 444  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 445  *
 446  * There is two family of SIIG serial cards with different PCI
 447  * interface chip and different configuration methods:
 448  *     - 10x cards have control registers in IO and/or memory space;
 449  *     - 20x cards have control registers in standard PCI configuration space.
 450  *
 451  * Note: all 10x cards have PCI device ids 0x10..
 452  *       all 20x cards have PCI device ids 0x20..
 453  *
 454  * There are also Quartet Serial cards which use Oxford Semiconductor
 455  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 456  *
 457  * Note: some SIIG cards are probed by the parport_serial object.
 458  */
 459
 460 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 461 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 462
 463 static int pci_siig10x_init(struct pci_dev *dev)
 464 {
 465         u16 data;
 466         void __iomem *p;
 467
 468         switch (dev->device & 0xfff8) {
 469         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 470                 data = 0xffdf;
 471                 break;
 472         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 473                 data = 0xf7ff;
 474                 break;
 475         default:                        /* 1S1P, 4S */
 476                 data = 0xfffb;
 477                 break;
 478         }
 479
 480         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 481         if (p == NULL)
 482                 return -ENOMEM;
 483
 484         writew(readw(p + 0x28) & data, p + 0x28);
 485         readw(p + 0x28);
 486         iounmap(p);
 487         return 0;
 488 }
 489
 490 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 491 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 492
 493 static int pci_siig20x_init(struct pci_dev *dev)
 494 {
 495         u8 data;
 496
 497         /* Change clock frequency for the first UART. */
 498         pci_read_config_byte(dev, 0x6f, &data);
 499         pci_write_config_byte(dev, 0x6f, data & 0xef);
 500
 501         /* If this card has 2 UART, we have to do the same with second UART. */
 502         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 503             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 504                 pci_read_config_byte(dev, 0x73, &data);
 505                 pci_write_config_byte(dev, 0x73, data & 0xef);
 506         }
 507         return 0;
 508 }
 509
 510 static int pci_siig_init(struct pci_dev *dev)
 511 {
 512         unsigned int type = dev->device & 0xff00;
 513
 514         if (type == 0x1000)
 515                 return pci_siig10x_init(dev);
 516         else if (type == 0x2000)
 517                 return pci_siig20x_init(dev);
 518
 519         moan_device("Unknown SIIG card", dev);
 520         return -ENODEV;
 521 }
 522
 523 static int pci_siig_setup(struct serial_private *priv,
 524                           const struct pciserial_board *board,
 525                           struct uart_port *port, int idx)
 526 {
 527         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 528
 529         if (idx > 3) {
 530                 bar = 4;
 531                 offset = (idx - 4) * 8;
 532         }
 533
 534         return setup_port(priv, port, bar, offset, 0);
 535 }
 536
 537 /*
 538  * Timedia has an explosion of boards, and to avoid the PCI table from
 539  * growing *huge*, we use this function to collapse some 70 entries
 540  * in the PCI table into one, for sanity's and compactness's sake.
 541  */
 542 static const unsigned short timedia_single_port[] = {
 543         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 544 };
 545
 546 static const unsigned short timedia_dual_port[] = {
 547         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 548         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 549         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 550         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 551         0xD079, 0
 552 };
 553
 554 static const unsigned short timedia_quad_port[] = {
 555         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 556         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 557         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 558         0xB157, 0
 559 };
 560
 561 static const unsigned short timedia_eight_port[] = {
 562         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 563         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 564 };
 565
 566 static const struct timedia_struct {
 567         int num;
 568         const unsigned short *ids;
 569 } timedia_data[] = {
 570         { 1, timedia_single_port },
 571         { 2, timedia_dual_port },
 572         { 4, timedia_quad_port },
 573         { 8, timedia_eight_port }
 574 };
 575
 576 static int pci_timedia_init(struct pci_dev *dev)
 577 {
 578         const unsigned short *ids;
 579         int i, j;
 580
 581         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 582                 ids = timedia_data[i].ids;
 583                 for (j = 0; ids[j]; j++)
 584                         if (dev->subsystem_device == ids[j])
 585                                 return timedia_data[i].num;
 586         }
 587         return 0;
 588 }
 589
 590 /*
 591  * Timedia/SUNIX uses a mixture of BARs and offsets
 592  * Ugh, this is ugly as all hell --- TYT
 593  */
 594 static int
 595 pci_timedia_setup(struct serial_private *priv,
 596                   const struct pciserial_board *board,
 597                   struct uart_port *port, int idx)
 598 {
 599         unsigned int bar = 0, offset = board->first_offset;
 600
 601         switch (idx) {
 602         case 0:
 603                 bar = 0;
 604                 break;
 605         case 1:
 606                 offset = board->uart_offset;
 607                 bar = 0;
 608                 break;
 609         case 2:
 610                 bar = 1;
 611                 break;
 612         case 3:
 613                 offset = board->uart_offset;
 614                 /* FALLTHROUGH */
 615         case 4: /* BAR 2 */
 616         case 5: /* BAR 3 */
 617         case 6: /* BAR 4 */
 618         case 7: /* BAR 5 */
 619                 bar = idx - 2;
 620         }
 621
 622         return setup_port(priv, port, bar, offset, board->reg_shift);
 623 }
 624
 625 /*
 626  * Some Titan cards are also a little weird
 627  */
 628 static int
 629 titan_400l_800l_setup(struct serial_private *priv,
 630                       const struct pciserial_board *board,
 631                       struct uart_port *port, int idx)
 632 {
 633         unsigned int bar, offset = board->first_offset;
 634
 635         switch (idx) {
 636         case 0:
 637                 bar = 1;
 638                 break;
 639         case 1:
 640                 bar = 2;
 641                 break;
 642         default:
 643                 bar = 4;
 644                 offset = (idx - 2) * board->uart_offset;
 645         }
 646
 647         return setup_port(priv, port, bar, offset, board->reg_shift);
 648 }
 649
 650 static int pci_xircom_init(struct pci_dev *dev)
 651 {
 652         msleep(100);
 653         return 0;
 654 }
 655
 656 static int pci_ni8420_init(struct pci_dev *dev)
 657 {
 658         void __iomem *p;
 659         unsigned long base, len;
 660         unsigned int bar = 0;
 661
 662         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 663                 moan_device("no memory in bar", dev);
 664                 return 0;
 665         }
 666
 667         base = pci_resource_start(dev, bar);
 668         len =  pci_resource_len(dev, bar);
 669         p = ioremap_nocache(base, len);
 670         if (p == NULL)
 671                 return -ENOMEM;
 672
 673         /* Enable CPU Interrupt */
 674         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 675                p + NI8420_INT_ENABLE_REG);
 676
 677         iounmap(p);
 678         return 0;
 679 }
 680
 681 #define MITE_IOWBSR1_WSIZE      0xa
 682 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 683 #define MITE_IOWBSR1_WENAB      (1 << 7)
 684 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 685 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 686 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 687
 688 static int pci_ni8430_init(struct pci_dev *dev)
 689 {
 690         void __iomem *p;
 691         unsigned long base, len;
 692         u32 device_window;
 693         unsigned int bar = 0;
 694
 695         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 696                 moan_device("no memory in bar", dev);
 697                 return 0;
 698         }
 699
 700         base = pci_resource_start(dev, bar);
 701         len =  pci_resource_len(dev, bar);
 702         p = ioremap_nocache(base, len);
 703         if (p == NULL)
 704                 return -ENOMEM;
 705
 706         /* Set device window address and size in BAR0 */
 707         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 708                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 709         writel(device_window, p + MITE_IOWBSR1);
 710
 711         /* Set window access to go to RAMSEL IO address space */
 712         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 713                p + MITE_IOWCR1);
 714
 715         /* Enable IO Bus Interrupt 0 */
 716         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 717
 718         /* Enable CPU Interrupt */
 719         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 720
 721         iounmap(p);
 722         return 0;
 723 }
 724
 725 /* UART Port Control Register */
 726 #define NI8430_PORTCON  0x0f
 727 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 728
 729 static int
 730 pci_ni8430_setup(struct serial_private *priv,
 731                  const struct pciserial_board *board,
 732                  struct uart_port *port, int idx)
 733 {
 734         void __iomem *p;
 735         unsigned long base, len;
 736         unsigned int bar, offset = board->first_offset;
 737
 738         if (idx >= board->num_ports)
 739                 return 1;
 740
 741         bar = FL_GET_BASE(board->flags);
 742         offset += idx * board->uart_offset;
 743
 744         base = pci_resource_start(priv->dev, bar);
 745         len =  pci_resource_len(priv->dev, bar);
 746         p = ioremap_nocache(base, len);
 747
 748         /* enable the transciever */
 749         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 750                p + offset + NI8430_PORTCON);
 751
 752         iounmap(p);
 753
 754         return setup_port(priv, port, bar, offset, board->reg_shift);
 755 }
 756
 757
 758 static int pci_netmos_init(struct pci_dev *dev)
 759 {
 760         /* subdevice 0x00PS means <P> parallel, <S> serial */
 761         unsigned int num_serial = dev->subsystem_device & 0xf;
 762
 763         if (dev->device == PCI_DEVICE_ID_NETMOS_9901)
 764                 return 0;
 765         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 766                         dev->subsystem_device == 0x0299)
 767                 return 0;
 768
 769         if (num_serial == 0)
 770                 return -ENODEV;
 771         return num_serial;
 772 }
 773
 774 /*
 775  * These chips are available with optionally one parallel port and up to
 776  * two serial ports. Unfortunately they all have the same product id.
 777  *
 778  * Basic configuration is done over a region of 32 I/O ports. The base
 779  * ioport is called INTA or INTC, depending on docs/other drivers.
 780  *
 781  * The region of the 32 I/O ports is configured in POSIO0R...
 782  */
 783
 784 /* registers */
 785 #define ITE_887x_MISCR          0x9c
 786 #define ITE_887x_INTCBAR        0x78
 787 #define ITE_887x_UARTBAR        0x7c
 788 #define ITE_887x_PS0BAR         0x10
 789 #define ITE_887x_POSIO0         0x60
 790
 791 /* I/O space size */
 792 #define ITE_887x_IOSIZE         32
 793 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 794 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 795 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 796 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 797 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 798 #define ITE_887x_POSIO_SPEED            (3 << 29)
 799 /* enable IO_Space bit */
 800 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 801
 802 static int pci_ite887x_init(struct pci_dev *dev)
 803 {
 804         /* inta_addr are the configuration addresses of the ITE */
 805         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 806                                                         0x200, 0x280, 0 };
 807         int ret, i, type;
 808         struct resource *iobase = NULL;
 809         u32 miscr, uartbar, ioport;
 810
 811         /* search for the base-ioport */
 812         i = 0;
 813         while (inta_addr[i] && iobase == NULL) {
 814                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 815                                                                 "ite887x");
 816                 if (iobase != NULL) {
 817                         /* write POSIO0R - speed | size | ioport */
 818                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 819                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 820                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 821                         /* write INTCBAR - ioport */
 822                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 823                                                                 inta_addr[i]);
 824                         ret = inb(inta_addr[i]);
 825                         if (ret != 0xff) {
 826                                 /* ioport connected */
 827                                 break;
 828                         }
 829                         release_region(iobase->start, ITE_887x_IOSIZE);
 830                         iobase = NULL;
 831                 }
 832                 i++;
 833         }
 834
 835         if (!inta_addr[i]) {
 836                 printk(KERN_ERR "ite887x: could not find iobase\n");
 837                 return -ENODEV;
 838         }
 839
 840         /* start of undocumented type checking (see parport_pc.c) */
 841         type = inb(iobase->start + 0x18) & 0x0f;
 842
 843         switch (type) {
 844         case 0x2:       /* ITE8871 (1P) */
 845         case 0xa:       /* ITE8875 (1P) */
 846                 ret = 0;
 847                 break;
 848         case 0xe:       /* ITE8872 (2S1P) */
 849                 ret = 2;
 850                 break;
 851         case 0x6:       /* ITE8873 (1S) */
 852                 ret = 1;
 853                 break;
 854         case 0x8:       /* ITE8874 (2S) */
 855                 ret = 2;
 856                 break;
 857         default:
 858                 moan_device("Unknown ITE887x", dev);
 859                 ret = -ENODEV;
 860         }
 861
 862         /* configure all serial ports */
 863         for (i = 0; i < ret; i++) {
 864                 /* read the I/O port from the device */
 865                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 866                                                                 &ioport);
 867                 ioport &= 0x0000FF00;   /* the actual base address */
 868                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 869                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 870                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 871
 872                 /* write the ioport to the UARTBAR */
 873                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 874                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 875                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 876                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 877
 878                 /* get current config */
 879                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 880                 /* disable interrupts (UARTx_Routing[3:0]) */
 881                 miscr &= ~(0xf << (12 - 4 * i));
 882                 /* activate the UART (UARTx_En) */
 883                 miscr |= 1 << (23 - i);
 884                 /* write new config with activated UART */
 885                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 886         }
 887
 888         if (ret <= 0) {
 889                 /* the device has no UARTs if we get here */
 890                 release_region(iobase->start, ITE_887x_IOSIZE);
 891         }
 892
 893         return ret;
 894 }
 895
 896 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 897 {
 898         u32 ioport;
 899         /* the ioport is bit 0-15 in POSIO0R */
 900         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 901         ioport &= 0xffff;
 902         release_region(ioport, ITE_887x_IOSIZE);
 903 }
 904
 905 /*
 906  * Oxford Semiconductor Inc.
 907  * Check that device is part of the Tornado range of devices, then determine
 908  * the number of ports available on the device.
 909  */
 910 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
 911 {
 912         u8 __iomem *p;
 913         unsigned long deviceID;
 914         unsigned int  number_uarts = 0;
 915
 916         /* OxSemi Tornado devices are all 0xCxxx */
 917         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
 918             (dev->device & 0xF000) != 0xC000)
 919                 return 0;
 920
 921         p = pci_iomap(dev, 0, 5);
 922         if (p == NULL)
 923                 return -ENOMEM;
 924
 925         deviceID = ioread32(p);
 926         /* Tornado device */
 927         if (deviceID == 0x07000200) {
 928                 number_uarts = ioread8(p + 4);
 929                 printk(KERN_DEBUG
 930                         "%d ports detected on Oxford PCI Express device\n",
 931                                                                 number_uarts);
 932         }
 933         pci_iounmap(dev, p);
 934         return number_uarts;
 935 }
 936
 937 static int
 938 pci_default_setup(struct serial_private *priv,
 939                   const struct pciserial_board *board,
 940                   struct uart_port *port, int idx)
 941 {
 942         unsigned int bar, offset = board->first_offset, maxnr;
 943
 944         bar = FL_GET_BASE(board->flags);
 945         if (board->flags & FL_BASE_BARS)
 946                 bar += idx;
 947         else
 948                 offset += idx * board->uart_offset;
 949
 950         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
 951                 (board->reg_shift + 3);
 952
 953         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
 954                 return 1;
 955
 956         return setup_port(priv, port, bar, offset, board->reg_shift);
 957 }
 958
 959 static int skip_tx_en_setup(struct serial_private *priv,
 960                         const struct pciserial_board *board,
 961                         struct uart_port *port, int idx)
 962 {
 963         port->flags |= UPF_NO_TXEN_TEST;
 964         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
 965                           "[%04x:%04x] subsystem [%04x:%04x]\n",
 966                           priv->dev->vendor,
 967                           priv->dev->device,
 968                           priv->dev->subsystem_vendor,
 969                           priv->dev->subsystem_device);
 970
 971         return pci_default_setup(priv, board, port, idx);
 972 }
 973
 974 /* This should be in linux/pci_ids.h */
 975 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
 976 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
 977 #define PCI_DEVICE_ID_OCTPRO            0x0001
 978 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
 979 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
 980 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
 981 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
 982 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
 983 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
 984
 985 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
 986 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
 987
 988 /*
 989  * Master list of serial port init/setup/exit quirks.
 990  * This does not describe the general nature of the port.
 991  * (ie, baud base, number and location of ports, etc)
 992  *
 993  * This list is ordered alphabetically by vendor then device.
 994  * Specific entries must come before more generic entries.
 995  */
 996 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
 997         /*
 998         * ADDI-DATA GmbH communication cards <info@addi-data.com>
 999         */
1000         {
1001                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1002                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1003                 .subvendor      = PCI_ANY_ID,
1004                 .subdevice      = PCI_ANY_ID,
1005                 .setup          = addidata_apci7800_setup,
1006         },
1007         /*
1008          * AFAVLAB cards - these may be called via parport_serial
1009          *  It is not clear whether this applies to all products.
1010          */
1011         {
1012                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1013                 .device         = PCI_ANY_ID,
1014                 .subvendor      = PCI_ANY_ID,
1015                 .subdevice      = PCI_ANY_ID,
1016                 .setup          = afavlab_setup,
1017         },
1018         /*
1019          * HP Diva
1020          */
1021         {
1022                 .vendor         = PCI_VENDOR_ID_HP,
1023                 .device         = PCI_DEVICE_ID_HP_DIVA,
1024                 .subvendor      = PCI_ANY_ID,
1025                 .subdevice      = PCI_ANY_ID,
1026                 .init           = pci_hp_diva_init,
1027                 .setup          = pci_hp_diva_setup,
1028         },
1029         /*
1030          * Intel
1031          */
1032         {
1033                 .vendor         = PCI_VENDOR_ID_INTEL,
1034                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1035                 .subvendor      = 0xe4bf,
1036                 .subdevice      = PCI_ANY_ID,
1037                 .init           = pci_inteli960ni_init,
1038                 .setup          = pci_default_setup,
1039         },
1040         {
1041                 .vendor         = PCI_VENDOR_ID_INTEL,
1042                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1043                 .subvendor      = PCI_ANY_ID,
1044                 .subdevice      = PCI_ANY_ID,
1045                 .setup          = skip_tx_en_setup,
1046         },
1047         {
1048                 .vendor         = PCI_VENDOR_ID_INTEL,
1049                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1050                 .subvendor      = PCI_ANY_ID,
1051                 .subdevice      = PCI_ANY_ID,
1052                 .setup          = skip_tx_en_setup,
1053         },
1054         {
1055                 .vendor         = PCI_VENDOR_ID_INTEL,
1056                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1057                 .subvendor      = PCI_ANY_ID,
1058                 .subdevice      = PCI_ANY_ID,
1059                 .setup          = skip_tx_en_setup,
1060         },
1061         /*
1062          * ITE
1063          */
1064         {
1065                 .vendor         = PCI_VENDOR_ID_ITE,
1066                 .device         = PCI_DEVICE_ID_ITE_8872,
1067                 .subvendor      = PCI_ANY_ID,
1068                 .subdevice      = PCI_ANY_ID,
1069                 .init           = pci_ite887x_init,
1070                 .setup          = pci_default_setup,
1071                 .exit           = __devexit_p(pci_ite887x_exit),
1072         },
1073         /*
1074          * National Instruments
1075          */
1076         {
1077                 .vendor         = PCI_VENDOR_ID_NI,
1078                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1079                 .subvendor      = PCI_ANY_ID,
1080                 .subdevice      = PCI_ANY_ID,
1081                 .init           = pci_ni8420_init,
1082                 .setup          = pci_default_setup,
1083                 .exit           = __devexit_p(pci_ni8420_exit),
1084         },
1085         {
1086                 .vendor         = PCI_VENDOR_ID_NI,
1087                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1088                 .subvendor      = PCI_ANY_ID,
1089                 .subdevice      = PCI_ANY_ID,
1090                 .init           = pci_ni8420_init,
1091                 .setup          = pci_default_setup,
1092                 .exit           = __devexit_p(pci_ni8420_exit),
1093         },
1094         {
1095                 .vendor         = PCI_VENDOR_ID_NI,
1096                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1097                 .subvendor      = PCI_ANY_ID,
1098                 .subdevice      = PCI_ANY_ID,
1099                 .init           = pci_ni8420_init,
1100                 .setup          = pci_default_setup,
1101                 .exit           = __devexit_p(pci_ni8420_exit),
1102         },
1103         {
1104                 .vendor         = PCI_VENDOR_ID_NI,
1105                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1106                 .subvendor      = PCI_ANY_ID,
1107                 .subdevice      = PCI_ANY_ID,
1108                 .init           = pci_ni8420_init,
1109                 .setup          = pci_default_setup,
1110                 .exit           = __devexit_p(pci_ni8420_exit),
1111         },
1112         {
1113                 .vendor         = PCI_VENDOR_ID_NI,
1114                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1115                 .subvendor      = PCI_ANY_ID,
1116                 .subdevice      = PCI_ANY_ID,
1117                 .init           = pci_ni8420_init,
1118                 .setup          = pci_default_setup,
1119                 .exit           = __devexit_p(pci_ni8420_exit),
1120         },
1121         {
1122                 .vendor         = PCI_VENDOR_ID_NI,
1123                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1124                 .subvendor      = PCI_ANY_ID,
1125                 .subdevice      = PCI_ANY_ID,
1126                 .init           = pci_ni8420_init,
1127                 .setup          = pci_default_setup,
1128                 .exit           = __devexit_p(pci_ni8420_exit),
1129         },
1130         {
1131                 .vendor         = PCI_VENDOR_ID_NI,
1132                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1133                 .subvendor      = PCI_ANY_ID,
1134                 .subdevice      = PCI_ANY_ID,
1135                 .init           = pci_ni8420_init,
1136                 .setup          = pci_default_setup,
1137                 .exit           = __devexit_p(pci_ni8420_exit),
1138         },
1139         {
1140                 .vendor         = PCI_VENDOR_ID_NI,
1141                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1142                 .subvendor      = PCI_ANY_ID,
1143                 .subdevice      = PCI_ANY_ID,
1144                 .init           = pci_ni8420_init,
1145                 .setup          = pci_default_setup,
1146                 .exit           = __devexit_p(pci_ni8420_exit),
1147         },
1148         {
1149                 .vendor         = PCI_VENDOR_ID_NI,
1150                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1151                 .subvendor      = PCI_ANY_ID,
1152                 .subdevice      = PCI_ANY_ID,
1153                 .init           = pci_ni8420_init,
1154                 .setup          = pci_default_setup,
1155                 .exit           = __devexit_p(pci_ni8420_exit),
1156         },
1157         {
1158                 .vendor         = PCI_VENDOR_ID_NI,
1159                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1160                 .subvendor      = PCI_ANY_ID,
1161                 .subdevice      = PCI_ANY_ID,
1162                 .init           = pci_ni8420_init,
1163                 .setup          = pci_default_setup,
1164                 .exit           = __devexit_p(pci_ni8420_exit),
1165         },
1166         {
1167                 .vendor         = PCI_VENDOR_ID_NI,
1168                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1169                 .subvendor      = PCI_ANY_ID,
1170                 .subdevice      = PCI_ANY_ID,
1171                 .init           = pci_ni8420_init,
1172                 .setup          = pci_default_setup,
1173                 .exit           = __devexit_p(pci_ni8420_exit),
1174         },
1175         {
1176                 .vendor         = PCI_VENDOR_ID_NI,
1177                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1178                 .subvendor      = PCI_ANY_ID,
1179                 .subdevice      = PCI_ANY_ID,
1180                 .init           = pci_ni8420_init,
1181                 .setup          = pci_default_setup,
1182                 .exit           = __devexit_p(pci_ni8420_exit),
1183         },
1184         {
1185                 .vendor         = PCI_VENDOR_ID_NI,
1186                 .device         = PCI_ANY_ID,
1187                 .subvendor      = PCI_ANY_ID,
1188                 .subdevice      = PCI_ANY_ID,
1189                 .init           = pci_ni8430_init,
1190                 .setup          = pci_ni8430_setup,
1191                 .exit           = __devexit_p(pci_ni8430_exit),
1192         },
1193         /*
1194          * Panacom
1195          */
1196         {
1197                 .vendor         = PCI_VENDOR_ID_PANACOM,
1198                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1199                 .subvendor      = PCI_ANY_ID,
1200                 .subdevice      = PCI_ANY_ID,
1201                 .init           = pci_plx9050_init,
1202                 .setup          = pci_default_setup,
1203                 .exit           = __devexit_p(pci_plx9050_exit),
1204         },
1205         {
1206                 .vendor         = PCI_VENDOR_ID_PANACOM,
1207                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1208                 .subvendor      = PCI_ANY_ID,
1209                 .subdevice      = PCI_ANY_ID,
1210                 .init           = pci_plx9050_init,
1211                 .setup          = pci_default_setup,
1212                 .exit           = __devexit_p(pci_plx9050_exit),
1213         },
1214         /*
1215          * PLX
1216          */
1217         {
1218                 .vendor         = PCI_VENDOR_ID_PLX,
1219                 .device         = PCI_DEVICE_ID_PLX_9030,
1220                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1221                 .subdevice      = PCI_ANY_ID,
1222                 .setup          = pci_default_setup,
1223         },
1224         {
1225                 .vendor         = PCI_VENDOR_ID_PLX,
1226                 .device         = PCI_DEVICE_ID_PLX_9050,
1227                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1228                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1229                 .init           = pci_plx9050_init,
1230                 .setup          = pci_default_setup,
1231                 .exit           = __devexit_p(pci_plx9050_exit),
1232         },
1233         {
1234                 .vendor         = PCI_VENDOR_ID_PLX,
1235                 .device         = PCI_DEVICE_ID_PLX_9050,
1236                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1237                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1238                 .init           = pci_plx9050_init,
1239                 .setup          = pci_default_setup,
1240                 .exit           = __devexit_p(pci_plx9050_exit),
1241         },
1242         {
1243                 .vendor         = PCI_VENDOR_ID_PLX,
1244                 .device         = PCI_DEVICE_ID_PLX_9050,
1245                 .subvendor      = PCI_VENDOR_ID_PLX,
1246                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1247                 .init           = pci_plx9050_init,
1248                 .setup          = pci_default_setup,
1249                 .exit           = __devexit_p(pci_plx9050_exit),
1250         },
1251         {
1252                 .vendor         = PCI_VENDOR_ID_PLX,
1253                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1254                 .subvendor      = PCI_VENDOR_ID_PLX,
1255                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1256                 .init           = pci_plx9050_init,
1257                 .setup          = pci_default_setup,
1258                 .exit           = __devexit_p(pci_plx9050_exit),
1259         },
1260         /*
1261          * SBS Technologies, Inc., PMC-OCTALPRO 232
1262          */
1263         {
1264                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1265                 .device         = PCI_DEVICE_ID_OCTPRO,
1266                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1267                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1268                 .init           = sbs_init,
1269                 .setup          = sbs_setup,
1270                 .exit           = __devexit_p(sbs_exit),
1271         },
1272         /*
1273          * SBS Technologies, Inc., PMC-OCTALPRO 422
1274          */
1275         {
1276                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1277                 .device         = PCI_DEVICE_ID_OCTPRO,
1278                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1279                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1280                 .init           = sbs_init,
1281                 .setup          = sbs_setup,
1282                 .exit           = __devexit_p(sbs_exit),
1283         },
1284         /*
1285          * SBS Technologies, Inc., P-Octal 232
1286          */
1287         {
1288                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1289                 .device         = PCI_DEVICE_ID_OCTPRO,
1290                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1291                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1292                 .init           = sbs_init,
1293                 .setup          = sbs_setup,
1294                 .exit           = __devexit_p(sbs_exit),
1295         },
1296         /*
1297          * SBS Technologies, Inc., P-Octal 422
1298          */
1299         {
1300                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1301                 .device         = PCI_DEVICE_ID_OCTPRO,
1302                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1303                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1304                 .init           = sbs_init,
1305                 .setup          = sbs_setup,
1306                 .exit           = __devexit_p(sbs_exit),
1307         },
1308         /*
1309          * SIIG cards - these may be called via parport_serial
1310          */
1311         {
1312                 .vendor         = PCI_VENDOR_ID_SIIG,
1313                 .device         = PCI_ANY_ID,
1314                 .subvendor      = PCI_ANY_ID,
1315                 .subdevice      = PCI_ANY_ID,
1316                 .init           = pci_siig_init,
1317                 .setup          = pci_siig_setup,
1318         },
1319         /*
1320          * Titan cards
1321          */
1322         {
1323                 .vendor         = PCI_VENDOR_ID_TITAN,
1324                 .device         = PCI_DEVICE_ID_TITAN_400L,
1325                 .subvendor      = PCI_ANY_ID,
1326                 .subdevice      = PCI_ANY_ID,
1327                 .setup          = titan_400l_800l_setup,
1328         },
1329         {
1330                 .vendor         = PCI_VENDOR_ID_TITAN,
1331                 .device         = PCI_DEVICE_ID_TITAN_800L,
1332                 .subvendor      = PCI_ANY_ID,
1333                 .subdevice      = PCI_ANY_ID,
1334                 .setup          = titan_400l_800l_setup,
1335         },
1336         /*
1337          * Timedia cards
1338          */
1339         {
1340                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1341                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1342                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1343                 .subdevice      = PCI_ANY_ID,
1344                 .init           = pci_timedia_init,
1345                 .setup          = pci_timedia_setup,
1346         },
1347         {
1348                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1349                 .device         = PCI_ANY_ID,
1350                 .subvendor      = PCI_ANY_ID,
1351                 .subdevice      = PCI_ANY_ID,
1352                 .setup          = pci_timedia_setup,
1353         },
1354         /*
1355          * Xircom cards
1356          */
1357         {
1358                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1359                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1360                 .subvendor      = PCI_ANY_ID,
1361                 .subdevice      = PCI_ANY_ID,
1362                 .init           = pci_xircom_init,
1363                 .setup          = pci_default_setup,
1364         },
1365         /*
1366          * Netmos cards - these may be called via parport_serial
1367          */
1368         {
1369                 .vendor         = PCI_VENDOR_ID_NETMOS,
1370                 .device         = PCI_ANY_ID,
1371                 .subvendor      = PCI_ANY_ID,
1372                 .subdevice      = PCI_ANY_ID,
1373                 .init           = pci_netmos_init,
1374                 .setup          = pci_default_setup,
1375         },
1376         /*
1377          * For Oxford Semiconductor and Mainpine
1378          */
1379         {
1380                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1381                 .device         = PCI_ANY_ID,
1382                 .subvendor      = PCI_ANY_ID,
1383                 .subdevice      = PCI_ANY_ID,
1384                 .init           = pci_oxsemi_tornado_init,
1385                 .setup          = pci_default_setup,
1386         },
1387         {
1388                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1389                 .device         = PCI_ANY_ID,
1390                 .subvendor      = PCI_ANY_ID,
1391                 .subdevice      = PCI_ANY_ID,
1392                 .init           = pci_oxsemi_tornado_init,
1393                 .setup          = pci_default_setup,
1394         },
1395         /*
1396          * Default "match everything" terminator entry
1397          */
1398         {
1399                 .vendor         = PCI_ANY_ID,
1400                 .device         = PCI_ANY_ID,
1401                 .subvendor      = PCI_ANY_ID,
1402                 .subdevice      = PCI_ANY_ID,
1403                 .setup          = pci_default_setup,
1404         }
1405 };
1406
1407 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1408 {
1409         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1410 }
1411
1412 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1413 {
1414         struct pci_serial_quirk *quirk;
1415
1416         for (quirk = pci_serial_quirks; ; quirk++)
1417                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1418                     quirk_id_matches(quirk->device, dev->device) &&
1419                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1420                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1421                         break;
1422         return quirk;
1423 }
1424
1425 static inline int get_pci_irq(struct pci_dev *dev,
1426                                 const struct pciserial_board *board)
1427 {
1428         if (board->flags & FL_NOIRQ)
1429                 return 0;
1430         else
1431                 return dev->irq;
1432 }
1433
1434 /*
1435  * This is the configuration table for all of the PCI serial boards
1436  * which we support.  It is directly indexed by the pci_board_num_t enum
1437  * value, which is encoded in the pci_device_id PCI probe table's
1438  * driver_data member.
1439  *
1440  * The makeup of these names are:
1441  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1442  *
1443  *  bn          = PCI BAR number
1444  *  bt          = Index using PCI BARs
1445  *  n           = number of serial ports
1446  *  baud        = baud rate
1447  *  offsetinhex = offset for each sequential port (in hex)
1448  *
1449  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1450  *
1451  * Please note: in theory if n = 1, _bt infix should make no difference.
1452  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1453  */
1454 enum pci_board_num_t {
1455         pbn_default = 0,
1456
1457         pbn_b0_1_115200,
1458         pbn_b0_2_115200,
1459         pbn_b0_4_115200,
1460         pbn_b0_5_115200,
1461         pbn_b0_8_115200,
1462
1463         pbn_b0_1_921600,
1464         pbn_b0_2_921600,
1465         pbn_b0_4_921600,
1466
1467         pbn_b0_2_1130000,
1468
1469         pbn_b0_4_1152000,
1470
1471         pbn_b0_2_1843200,
1472         pbn_b0_4_1843200,
1473
1474         pbn_b0_2_1843200_200,
1475         pbn_b0_4_1843200_200,
1476         pbn_b0_8_1843200_200,
1477
1478         pbn_b0_1_4000000,
1479
1480         pbn_b0_bt_1_115200,
1481         pbn_b0_bt_2_115200,
1482         pbn_b0_bt_8_115200,
1483
1484         pbn_b0_bt_1_460800,
1485         pbn_b0_bt_2_460800,
1486         pbn_b0_bt_4_460800,
1487
1488         pbn_b0_bt_1_921600,
1489         pbn_b0_bt_2_921600,
1490         pbn_b0_bt_4_921600,
1491         pbn_b0_bt_8_921600,
1492
1493         pbn_b1_1_115200,
1494         pbn_b1_2_115200,
1495         pbn_b1_4_115200,
1496         pbn_b1_8_115200,
1497         pbn_b1_16_115200,
1498
1499         pbn_b1_1_921600,
1500         pbn_b1_2_921600,
1501         pbn_b1_4_921600,
1502         pbn_b1_8_921600,
1503
1504         pbn_b1_2_1250000,
1505
1506         pbn_b1_bt_1_115200,
1507         pbn_b1_bt_2_115200,
1508         pbn_b1_bt_4_115200,
1509
1510         pbn_b1_bt_2_921600,
1511
1512         pbn_b1_1_1382400,
1513         pbn_b1_2_1382400,
1514         pbn_b1_4_1382400,
1515         pbn_b1_8_1382400,
1516
1517         pbn_b2_1_115200,
1518         pbn_b2_2_115200,
1519         pbn_b2_4_115200,
1520         pbn_b2_8_115200,
1521
1522         pbn_b2_1_460800,
1523         pbn_b2_4_460800,
1524         pbn_b2_8_460800,
1525         pbn_b2_16_460800,
1526
1527         pbn_b2_1_921600,
1528         pbn_b2_4_921600,
1529         pbn_b2_8_921600,
1530
1531         pbn_b2_bt_1_115200,
1532         pbn_b2_bt_2_115200,
1533         pbn_b2_bt_4_115200,
1534
1535         pbn_b2_bt_2_921600,
1536         pbn_b2_bt_4_921600,
1537
1538         pbn_b3_2_115200,
1539         pbn_b3_4_115200,
1540         pbn_b3_8_115200,
1541
1542         /*
1543          * Board-specific versions.
1544          */
1545         pbn_panacom,
1546         pbn_panacom2,
1547         pbn_panacom4,
1548         pbn_exsys_4055,
1549         pbn_plx_romulus,
1550         pbn_oxsemi,
1551         pbn_oxsemi_1_4000000,
1552         pbn_oxsemi_2_4000000,
1553         pbn_oxsemi_4_4000000,
1554         pbn_oxsemi_8_4000000,
1555         pbn_intel_i960,
1556         pbn_sgi_ioc3,
1557         pbn_computone_4,
1558         pbn_computone_6,
1559         pbn_computone_8,
1560         pbn_sbsxrsio,
1561         pbn_exar_XR17C152,
1562         pbn_exar_XR17C154,
1563         pbn_exar_XR17C158,
1564         pbn_pasemi_1682M,
1565         pbn_ni8430_2,
1566         pbn_ni8430_4,
1567         pbn_ni8430_8,
1568         pbn_ni8430_16,
1569 };
1570
1571 /*
1572  * uart_offset - the space between channels
1573  * reg_shift   - describes how the UART registers are mapped
1574  *               to PCI memory by the card.
1575  * For example IER register on SBS, Inc. PMC-OctPro is located at
1576  * offset 0x10 from the UART base, while UART_IER is defined as 1
1577  * in include/linux/serial_reg.h,
1578  * see first lines of serial_in() and serial_out() in 8250.c
1579 */
1580
1581 static struct pciserial_board pci_boards[] __devinitdata = {
1582         [pbn_default] = {
1583                 .flags          = FL_BASE0,
1584                 .num_ports      = 1,
1585                 .base_baud      = 115200,
1586                 .uart_offset    = 8,
1587         },
1588         [pbn_b0_1_115200] = {
1589                 .flags          = FL_BASE0,
1590                 .num_ports      = 1,
1591                 .base_baud      = 115200,
1592                 .uart_offset    = 8,
1593         },
1594         [pbn_b0_2_115200] = {
1595                 .flags          = FL_BASE0,
1596                 .num_ports      = 2,
1597                 .base_baud      = 115200,
1598                 .uart_offset    = 8,
1599         },
1600         [pbn_b0_4_115200] = {
1601                 .flags          = FL_BASE0,
1602                 .num_ports      = 4,
1603                 .base_baud      = 115200,
1604                 .uart_offset    = 8,
1605         },
1606         [pbn_b0_5_115200] = {
1607                 .flags          = FL_BASE0,
1608                 .num_ports      = 5,
1609                 .base_baud      = 115200,
1610                 .uart_offset    = 8,
1611         },
1612         [pbn_b0_8_115200] = {
1613                 .flags          = FL_BASE0,
1614                 .num_ports      = 8,
1615                 .base_baud      = 115200,
1616                 .uart_offset    = 8,
1617         },
1618         [pbn_b0_1_921600] = {
1619                 .flags          = FL_BASE0,
1620                 .num_ports      = 1,
1621                 .base_baud      = 921600,
1622                 .uart_offset    = 8,
1623         },
1624         [pbn_b0_2_921600] = {
1625                 .flags          = FL_BASE0,
1626                 .num_ports      = 2,
1627                 .base_baud      = 921600,
1628                 .uart_offset    = 8,
1629         },
1630         [pbn_b0_4_921600] = {
1631                 .flags          = FL_BASE0,
1632                 .num_ports      = 4,
1633                 .base_baud      = 921600,
1634                 .uart_offset    = 8,
1635         },
1636
1637         [pbn_b0_2_1130000] = {
1638                 .flags          = FL_BASE0,
1639                 .num_ports      = 2,
1640                 .base_baud      = 1130000,
1641                 .uart_offset    = 8,
1642         },
1643
1644         [pbn_b0_4_1152000] = {
1645                 .flags          = FL_BASE0,
1646                 .num_ports      = 4,
1647                 .base_baud      = 1152000,
1648                 .uart_offset    = 8,
1649         },
1650
1651         [pbn_b0_2_1843200] = {
1652                 .flags          = FL_BASE0,
1653                 .num_ports      = 2,
1654                 .base_baud      = 1843200,
1655                 .uart_offset    = 8,
1656         },
1657         [pbn_b0_4_1843200] = {
1658                 .flags          = FL_BASE0,
1659                 .num_ports      = 4,
1660                 .base_baud      = 1843200,
1661                 .uart_offset    = 8,
1662         },
1663
1664         [pbn_b0_2_1843200_200] = {
1665                 .flags          = FL_BASE0,
1666                 .num_ports      = 2,
1667                 .base_baud      = 1843200,
1668                 .uart_offset    = 0x200,
1669         },
1670         [pbn_b0_4_1843200_200] = {
1671                 .flags          = FL_BASE0,
1672                 .num_ports      = 4,
1673                 .base_baud      = 1843200,
1674                 .uart_offset    = 0x200,
1675         },
1676         [pbn_b0_8_1843200_200] = {
1677                 .flags          = FL_BASE0,
1678                 .num_ports      = 8,
1679                 .base_baud      = 1843200,
1680                 .uart_offset    = 0x200,
1681         },
1682         [pbn_b0_1_4000000] = {
1683                 .flags          = FL_BASE0,
1684                 .num_ports      = 1,
1685                 .base_baud      = 4000000,
1686                 .uart_offset    = 8,
1687         },
1688
1689         [pbn_b0_bt_1_115200] = {
1690                 .flags          = FL_BASE0|FL_BASE_BARS,
1691                 .num_ports      = 1,
1692                 .base_baud      = 115200,
1693                 .uart_offset    = 8,
1694         },
1695         [pbn_b0_bt_2_115200] = {
1696                 .flags          = FL_BASE0|FL_BASE_BARS,
1697                 .num_ports      = 2,
1698                 .base_baud      = 115200,
1699                 .uart_offset    = 8,
1700         },
1701         [pbn_b0_bt_8_115200] = {
1702                 .flags          = FL_BASE0|FL_BASE_BARS,
1703                 .num_ports      = 8,
1704                 .base_baud      = 115200,
1705                 .uart_offset    = 8,
1706         },
1707
1708         [pbn_b0_bt_1_460800] = {
1709                 .flags          = FL_BASE0|FL_BASE_BARS,
1710                 .num_ports      = 1,
1711                 .base_baud      = 460800,
1712                 .uart_offset    = 8,
1713         },
1714         [pbn_b0_bt_2_460800] = {
1715                 .flags          = FL_BASE0|FL_BASE_BARS,
1716                 .num_ports      = 2,
1717                 .base_baud      = 460800,
1718                 .uart_offset    = 8,
1719         },
1720         [pbn_b0_bt_4_460800] = {
1721                 .flags          = FL_BASE0|FL_BASE_BARS,
1722                 .num_ports      = 4,
1723                 .base_baud      = 460800,
1724                 .uart_offset    = 8,
1725         },
1726
1727         [pbn_b0_bt_1_921600] = {
1728                 .flags          = FL_BASE0|FL_BASE_BARS,
1729                 .num_ports      = 1,
1730                 .base_baud      = 921600,
1731                 .uart_offset    = 8,
1732         },
1733         [pbn_b0_bt_2_921600] = {
1734                 .flags          = FL_BASE0|FL_BASE_BARS,
1735                 .num_ports      = 2,
1736                 .base_baud      = 921600,
1737                 .uart_offset    = 8,
1738         },
1739         [pbn_b0_bt_4_921600] = {
1740                 .flags          = FL_BASE0|FL_BASE_BARS,
1741                 .num_ports      = 4,
1742                 .base_baud      = 921600,
1743                 .uart_offset    = 8,
1744         },
1745         [pbn_b0_bt_8_921600] = {
1746                 .flags          = FL_BASE0|FL_BASE_BARS,
1747                 .num_ports      = 8,
1748                 .base_baud      = 921600,
1749                 .uart_offset    = 8,
1750         },
1751
1752         [pbn_b1_1_115200] = {
1753                 .flags          = FL_BASE1,
1754                 .num_ports      = 1,
1755                 .base_baud      = 115200,
1756                 .uart_offset    = 8,
1757         },
1758         [pbn_b1_2_115200] = {
1759                 .flags          = FL_BASE1,
1760                 .num_ports      = 2,
1761                 .base_baud      = 115200,
1762                 .uart_offset    = 8,
1763         },
1764         [pbn_b1_4_115200] = {
1765                 .flags          = FL_BASE1,
1766                 .num_ports      = 4,
1767                 .base_baud      = 115200,
1768                 .uart_offset    = 8,
1769         },
1770         [pbn_b1_8_115200] = {
1771                 .flags          = FL_BASE1,
1772                 .num_ports      = 8,
1773                 .base_baud      = 115200,
1774                 .uart_offset    = 8,
1775         },
1776         [pbn_b1_16_115200] = {
1777                 .flags          = FL_BASE1,
1778                 .num_ports      = 16,
1779                 .base_baud      = 115200,
1780                 .uart_offset    = 8,
1781         },
1782
1783         [pbn_b1_1_921600] = {
1784                 .flags          = FL_BASE1,
1785                 .num_ports      = 1,
1786                 .base_baud      = 921600,
1787                 .uart_offset    = 8,
1788         },
1789         [pbn_b1_2_921600] = {
1790                 .flags          = FL_BASE1,
1791                 .num_ports      = 2,
1792                 .base_baud      = 921600,
1793                 .uart_offset    = 8,
1794         },
1795         [pbn_b1_4_921600] = {
1796                 .flags          = FL_BASE1,
1797                 .num_ports      = 4,
1798                 .base_baud      = 921600,
1799                 .uart_offset    = 8,
1800         },
1801         [pbn_b1_8_921600] = {
1802                 .flags          = FL_BASE1,
1803                 .num_ports      = 8,
1804                 .base_baud      = 921600,
1805                 .uart_offset    = 8,
1806         },
1807         [pbn_b1_2_1250000] = {
1808                 .flags          = FL_BASE1,
1809                 .num_ports      = 2,
1810                 .base_baud      = 1250000,
1811                 .uart_offset    = 8,
1812         },
1813
1814         [pbn_b1_bt_1_115200] = {
1815                 .flags          = FL_BASE1|FL_BASE_BARS,
1816                 .num_ports      = 1,
1817                 .base_baud      = 115200,
1818                 .uart_offset    = 8,
1819         },
1820         [pbn_b1_bt_2_115200] = {
1821                 .flags          = FL_BASE1|FL_BASE_BARS,
1822                 .num_ports      = 2,
1823                 .base_baud      = 115200,
1824                 .uart_offset    = 8,
1825         },
1826         [pbn_b1_bt_4_115200] = {
1827                 .flags          = FL_BASE1|FL_BASE_BARS,
1828                 .num_ports      = 4,
1829                 .base_baud      = 115200,
1830                 .uart_offset    = 8,
1831         },
1832
1833         [pbn_b1_bt_2_921600] = {
1834                 .flags          = FL_BASE1|FL_BASE_BARS,
1835                 .num_ports      = 2,
1836                 .base_baud      = 921600,
1837                 .uart_offset    = 8,
1838         },
1839
1840         [pbn_b1_1_1382400] = {
1841                 .flags          = FL_BASE1,
1842                 .num_ports      = 1,
1843                 .base_baud      = 1382400,
1844                 .uart_offset    = 8,
1845         },
1846         [pbn_b1_2_1382400] = {
1847                 .flags          = FL_BASE1,
1848                 .num_ports      = 2,
1849                 .base_baud      = 1382400,
1850                 .uart_offset    = 8,
1851         },
1852         [pbn_b1_4_1382400] = {
1853                 .flags          = FL_BASE1,
1854                 .num_ports      = 4,
1855                 .base_baud      = 1382400,
1856                 .uart_offset    = 8,
1857         },
1858         [pbn_b1_8_1382400] = {
1859                 .flags          = FL_BASE1,
1860                 .num_ports      = 8,
1861                 .base_baud      = 1382400,
1862                 .uart_offset    = 8,
1863         },
1864
1865         [pbn_b2_1_115200] = {
1866                 .flags          = FL_BASE2,
1867                 .num_ports      = 1,
1868                 .base_baud      = 115200,
1869                 .uart_offset    = 8,
1870         },
1871         [pbn_b2_2_115200] = {
1872                 .flags          = FL_BASE2,
1873                 .num_ports      = 2,
1874                 .base_baud      = 115200,
1875                 .uart_offset    = 8,
1876         },
1877         [pbn_b2_4_115200] = {
1878                 .flags          = FL_BASE2,
1879                 .num_ports      = 4,
1880                 .base_baud      = 115200,
1881                 .uart_offset    = 8,
1882         },
1883         [pbn_b2_8_115200] = {
1884                 .flags          = FL_BASE2,
1885                 .num_ports      = 8,
1886                 .base_baud      = 115200,
1887                 .uart_offset    = 8,
1888         },
1889
1890         [pbn_b2_1_460800] = {
1891                 .flags          = FL_BASE2,
1892                 .num_ports      = 1,
1893                 .base_baud      = 460800,
1894                 .uart_offset    = 8,
1895         },
1896         [pbn_b2_4_460800] = {
1897                 .flags          = FL_BASE2,
1898                 .num_ports      = 4,
1899                 .base_baud      = 460800,
1900                 .uart_offset    = 8,
1901         },
1902         [pbn_b2_8_460800] = {
1903                 .flags          = FL_BASE2,
1904                 .num_ports      = 8,
1905                 .base_baud      = 460800,
1906                 .uart_offset    = 8,
1907         },
1908         [pbn_b2_16_460800] = {
1909                 .flags          = FL_BASE2,
1910                 .num_ports      = 16,
1911                 .base_baud      = 460800,
1912                 .uart_offset    = 8,
1913          },
1914
1915         [pbn_b2_1_921600] = {
1916                 .flags          = FL_BASE2,
1917                 .num_ports      = 1,
1918                 .base_baud      = 921600,
1919                 .uart_offset    = 8,
1920         },
1921         [pbn_b2_4_921600] = {
1922                 .flags          = FL_BASE2,
1923                 .num_ports      = 4,
1924                 .base_baud      = 921600,
1925                 .uart_offset    = 8,
1926         },
1927         [pbn_b2_8_921600] = {
1928                 .flags          = FL_BASE2,
1929                 .num_ports      = 8,
1930                 .base_baud      = 921600,
1931                 .uart_offset    = 8,
1932         },
1933
1934         [pbn_b2_bt_1_115200] = {
1935                 .flags          = FL_BASE2|FL_BASE_BARS,
1936                 .num_ports      = 1,
1937                 .base_baud      = 115200,
1938                 .uart_offset    = 8,
1939         },
1940         [pbn_b2_bt_2_115200] = {
1941                 .flags          = FL_BASE2|FL_BASE_BARS,
1942                 .num_ports      = 2,
1943                 .base_baud      = 115200,
1944                 .uart_offset    = 8,
1945         },
1946         [pbn_b2_bt_4_115200] = {
1947                 .flags          = FL_BASE2|FL_BASE_BARS,
1948                 .num_ports      = 4,
1949                 .base_baud      = 115200,
1950                 .uart_offset    = 8,
1951         },
1952
1953         [pbn_b2_bt_2_921600] = {
1954                 .flags          = FL_BASE2|FL_BASE_BARS,
1955                 .num_ports      = 2,
1956                 .base_baud      = 921600,
1957                 .uart_offset    = 8,
1958         },
1959         [pbn_b2_bt_4_921600] = {
1960                 .flags          = FL_BASE2|FL_BASE_BARS,
1961                 .num_ports      = 4,
1962                 .base_baud      = 921600,
1963                 .uart_offset    = 8,
1964         },
1965
1966         [pbn_b3_2_115200] = {
1967                 .flags          = FL_BASE3,
1968                 .num_ports      = 2,
1969                 .base_baud      = 115200,
1970                 .uart_offset    = 8,
1971         },
1972         [pbn_b3_4_115200] = {
1973                 .flags          = FL_BASE3,
1974                 .num_ports      = 4,
1975                 .base_baud      = 115200,
1976                 .uart_offset    = 8,
1977         },
1978         [pbn_b3_8_115200] = {
1979                 .flags          = FL_BASE3,
1980                 .num_ports      = 8,
1981                 .base_baud      = 115200,
1982                 .uart_offset    = 8,
1983         },
1984
1985         /*
1986          * Entries following this are board-specific.
1987          */
1988
1989         /*
1990          * Panacom - IOMEM
1991          */
1992         [pbn_panacom] = {
1993                 .flags          = FL_BASE2,
1994                 .num_ports      = 2,
1995                 .base_baud      = 921600,
1996                 .uart_offset    = 0x400,
1997                 .reg_shift      = 7,
1998         },
1999         [pbn_panacom2] = {
2000                 .flags          = FL_BASE2|FL_BASE_BARS,
2001                 .num_ports      = 2,
2002                 .base_baud      = 921600,
2003                 .uart_offset    = 0x400,
2004                 .reg_shift      = 7,
2005         },
2006         [pbn_panacom4] = {
2007                 .flags          = FL_BASE2|FL_BASE_BARS,
2008                 .num_ports      = 4,
2009                 .base_baud      = 921600,
2010                 .uart_offset    = 0x400,
2011                 .reg_shift      = 7,
2012         },
2013
2014         [pbn_exsys_4055] = {
2015                 .flags          = FL_BASE2,
2016                 .num_ports      = 4,
2017                 .base_baud      = 115200,
2018                 .uart_offset    = 8,
2019         },
2020
2021         /* I think this entry is broken - the first_offset looks wrong --rmk */
2022         [pbn_plx_romulus] = {
2023                 .flags          = FL_BASE2,
2024                 .num_ports      = 4,
2025                 .base_baud      = 921600,
2026                 .uart_offset    = 8 << 2,
2027                 .reg_shift      = 2,
2028                 .first_offset   = 0x03,
2029         },
2030
2031         /*
2032          * This board uses the size of PCI Base region 0 to
2033          * signal now many ports are available
2034          */
2035         [pbn_oxsemi] = {
2036                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2037                 .num_ports      = 32,
2038                 .base_baud      = 115200,
2039                 .uart_offset    = 8,
2040         },
2041         [pbn_oxsemi_1_4000000] = {
2042                 .flags          = FL_BASE0,
2043                 .num_ports      = 1,
2044                 .base_baud      = 4000000,
2045                 .uart_offset    = 0x200,
2046                 .first_offset   = 0x1000,
2047         },
2048         [pbn_oxsemi_2_4000000] = {
2049                 .flags          = FL_BASE0,
2050                 .num_ports      = 2,
2051                 .base_baud      = 4000000,
2052                 .uart_offset    = 0x200,
2053                 .first_offset   = 0x1000,
2054         },
2055         [pbn_oxsemi_4_4000000] = {
2056                 .flags          = FL_BASE0,
2057                 .num_ports      = 4,
2058                 .base_baud      = 4000000,
2059                 .uart_offset    = 0x200,
2060                 .first_offset   = 0x1000,
2061         },
2062         [pbn_oxsemi_8_4000000] = {
2063                 .flags          = FL_BASE0,
2064                 .num_ports      = 8,
2065                 .base_baud      = 4000000,
2066                 .uart_offset    = 0x200,
2067                 .first_offset   = 0x1000,
2068         },
2069
2070
2071         /*
2072          * EKF addition for i960 Boards form EKF with serial port.
2073          * Max 256 ports.
2074          */
2075         [pbn_intel_i960] = {
2076                 .flags          = FL_BASE0,
2077                 .num_ports      = 32,
2078                 .base_baud      = 921600,
2079                 .uart_offset    = 8 << 2,
2080                 .reg_shift      = 2,
2081                 .first_offset   = 0x10000,
2082         },
2083         [pbn_sgi_ioc3] = {
2084                 .flags          = FL_BASE0|FL_NOIRQ,
2085                 .num_ports      = 1,
2086                 .base_baud      = 458333,
2087                 .uart_offset    = 8,
2088                 .reg_shift      = 0,
2089                 .first_offset   = 0x20178,
2090         },
2091
2092         /*
2093          * Computone - uses IOMEM.
2094          */
2095         [pbn_computone_4] = {
2096                 .flags          = FL_BASE0,
2097                 .num_ports      = 4,
2098                 .base_baud      = 921600,
2099                 .uart_offset    = 0x40,
2100                 .reg_shift      = 2,
2101                 .first_offset   = 0x200,
2102         },
2103         [pbn_computone_6] = {
2104                 .flags          = FL_BASE0,
2105                 .num_ports      = 6,
2106                 .base_baud      = 921600,
2107                 .uart_offset    = 0x40,
2108                 .reg_shift      = 2,
2109                 .first_offset   = 0x200,
2110         },
2111         [pbn_computone_8] = {
2112                 .flags          = FL_BASE0,
2113                 .num_ports      = 8,
2114                 .base_baud      = 921600,
2115                 .uart_offset    = 0x40,
2116                 .reg_shift      = 2,
2117                 .first_offset   = 0x200,
2118         },
2119         [pbn_sbsxrsio] = {
2120                 .flags          = FL_BASE0,
2121                 .num_ports      = 8,
2122                 .base_baud      = 460800,
2123                 .uart_offset    = 256,
2124                 .reg_shift      = 4,
2125         },
2126         /*
2127          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2128          *  Only basic 16550A support.
2129          *  XR17C15[24] are not tested, but they should work.
2130          */
2131         [pbn_exar_XR17C152] = {
2132                 .flags          = FL_BASE0,
2133                 .num_ports      = 2,
2134                 .base_baud      = 921600,
2135                 .uart_offset    = 0x200,
2136         },
2137         [pbn_exar_XR17C154] = {
2138                 .flags          = FL_BASE0,
2139                 .num_ports      = 4,
2140                 .base_baud      = 921600,
2141                 .uart_offset    = 0x200,
2142         },
2143         [pbn_exar_XR17C158] = {
2144                 .flags          = FL_BASE0,
2145                 .num_ports      = 8,
2146                 .base_baud      = 921600,
2147                 .uart_offset    = 0x200,
2148         },
2149         /*
2150          * PA Semi PWRficient PA6T-1682M on-chip UART
2151          */
2152         [pbn_pasemi_1682M] = {
2153                 .flags          = FL_BASE0,
2154                 .num_ports      = 1,
2155                 .base_baud      = 8333333,
2156         },
2157         /*
2158          * National Instruments 843x
2159          */
2160         [pbn_ni8430_16] = {
2161                 .flags          = FL_BASE0,
2162                 .num_ports      = 16,
2163                 .base_baud      = 3686400,
2164                 .uart_offset    = 0x10,
2165                 .first_offset   = 0x800,
2166         },
2167         [pbn_ni8430_8] = {
2168                 .flags          = FL_BASE0,
2169                 .num_ports      = 8,
2170                 .base_baud      = 3686400,
2171                 .uart_offset    = 0x10,
2172                 .first_offset   = 0x800,
2173         },
2174         [pbn_ni8430_4] = {
2175                 .flags          = FL_BASE0,
2176                 .num_ports      = 4,
2177                 .base_baud      = 3686400,
2178                 .uart_offset    = 0x10,
2179                 .first_offset   = 0x800,
2180         },
2181         [pbn_ni8430_2] = {
2182                 .flags          = FL_BASE0,
2183                 .num_ports      = 2,
2184                 .base_baud      = 3686400,
2185                 .uart_offset    = 0x10,
2186                 .first_offset   = 0x800,
2187         },
2188 };
2189
2190 static const struct pci_device_id softmodem_blacklist[] = {
2191         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2192 };
2193
2194 /*
2195  * Given a complete unknown PCI device, try to use some heuristics to
2196  * guess what the configuration might be, based on the pitiful PCI
2197  * serial specs.  Returns 0 on success, 1 on failure.
2198  */
2199 static int __devinit
2200 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2201 {
2202         const struct pci_device_id *blacklist;
2203         int num_iomem, num_port, first_port = -1, i;
2204
2205         /*
2206          * If it is not a communications device or the programming
2207          * interface is greater than 6, give up.
2208          *
2209          * (Should we try to make guesses for multiport serial devices
2210          * later?)
2211          */
2212         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2213              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2214             (dev->class & 0xff) > 6)
2215                 return -ENODEV;
2216
2217         /*
2218          * Do not access blacklisted devices that are known not to
2219          * feature serial ports.
2220          */
2221         for (blacklist = softmodem_blacklist;
2222              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2223              blacklist++) {
2224                 if (dev->vendor == blacklist->vendor &&
2225                     dev->device == blacklist->device)
2226                         return -ENODEV;
2227         }
2228
2229         num_iomem = num_port = 0;
2230         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2231                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2232                         num_port++;
2233                         if (first_port == -1)
2234                                 first_port = i;
2235                 }
2236                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2237                         num_iomem++;
2238         }
2239
2240         /*
2241          * If there is 1 or 0 iomem regions, and exactly one port,
2242          * use it.  We guess the number of ports based on the IO
2243          * region size.
2244          */
2245         if (num_iomem <= 1 && num_port == 1) {
2246                 board->flags = first_port;
2247                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2248                 return 0;
2249         }
2250
2251         /*
2252          * Now guess if we've got a board which indexes by BARs.
2253          * Each IO BAR should be 8 bytes, and they should follow
2254          * consecutively.
2255          */
2256         first_port = -1;
2257         num_port = 0;
2258         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2259                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2260                     pci_resource_len(dev, i) == 8 &&
2261                     (first_port == -1 || (first_port + num_port) == i)) {
2262                         num_port++;
2263                         if (first_port == -1)
2264                                 first_port = i;
2265                 }
2266         }
2267
2268         if (num_port > 1) {
2269                 board->flags = first_port | FL_BASE_BARS;
2270                 board->num_ports = num_port;
2271                 return 0;
2272         }
2273
2274         return -ENODEV;
2275 }
2276
2277 static inline int
2278 serial_pci_matches(const struct pciserial_board *board,
2279                    const struct pciserial_board *guessed)
2280 {
2281         return
2282             board->num_ports == guessed->num_ports &&
2283             board->base_baud == guessed->base_baud &&
2284             board->uart_offset == guessed->uart_offset &&
2285             board->reg_shift == guessed->reg_shift &&
2286             board->first_offset == guessed->first_offset;
2287 }
2288
2289 struct serial_private *
2290 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2291 {
2292         struct uart_port serial_port;
2293         struct serial_private *priv;
2294         struct pci_serial_quirk *quirk;
2295         int rc, nr_ports, i;
2296
2297         nr_ports = board->num_ports;
2298
2299         /*
2300          * Find an init and setup quirks.
2301          */
2302         quirk = find_quirk(dev);
2303
2304         /*
2305          * Run the new-style initialization function.
2306          * The initialization function returns:
2307          *  <0  - error
2308          *   0  - use board->num_ports
2309          *  >0  - number of ports
2310          */
2311         if (quirk->init) {
2312                 rc = quirk->init(dev);
2313                 if (rc < 0) {
2314                         priv = ERR_PTR(rc);
2315                         goto err_out;
2316                 }
2317                 if (rc)
2318                         nr_ports = rc;
2319         }
2320
2321         priv = kzalloc(sizeof(struct serial_private) +
2322                        sizeof(unsigned int) * nr_ports,
2323                        GFP_KERNEL);
2324         if (!priv) {
2325                 priv = ERR_PTR(-ENOMEM);
2326                 goto err_deinit;
2327         }
2328
2329         priv->dev = dev;
2330         priv->quirk = quirk;
2331
2332         memset(&serial_port, 0, sizeof(struct uart_port));
2333         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2334         serial_port.uartclk = board->base_baud * 16;
2335         serial_port.irq = get_pci_irq(dev, board);
2336         serial_port.dev = &dev->dev;
2337
2338         for (i = 0; i < nr_ports; i++) {
2339                 if (quirk->setup(priv, board, &serial_port, i))
2340                         break;
2341
2342 #ifdef SERIAL_DEBUG_PCI
2343                 printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
2344                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2345 #endif
2346
2347                 priv->line[i] = serial8250_register_port(&serial_port);
2348                 if (priv->line[i] < 0) {
2349                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2350                         break;
2351                 }
2352         }
2353         priv->nr = i;
2354         return priv;
2355
2356 err_deinit:
2357         if (quirk->exit)
2358                 quirk->exit(dev);
2359 err_out:
2360         return priv;
2361 }
2362 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2363
2364 void pciserial_remove_ports(struct serial_private *priv)
2365 {
2366         struct pci_serial_quirk *quirk;
2367         int i;
2368
2369         for (i = 0; i < priv->nr; i++)
2370                 serial8250_unregister_port(priv->line[i]);
2371
2372         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2373                 if (priv->remapped_bar[i])
2374                         iounmap(priv->remapped_bar[i]);
2375                 priv->remapped_bar[i] = NULL;
2376         }
2377
2378         /*
2379          * Find the exit quirks.
2380          */
2381         quirk = find_quirk(priv->dev);
2382         if (quirk->exit)
2383                 quirk->exit(priv->dev);
2384
2385         kfree(priv);
2386 }
2387 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2388
2389 void pciserial_suspend_ports(struct serial_private *priv)
2390 {
2391         int i;
2392
2393         for (i = 0; i < priv->nr; i++)
2394                 if (priv->line[i] >= 0)
2395                         serial8250_suspend_port(priv->line[i]);
2396 }
2397 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2398
2399 void pciserial_resume_ports(struct serial_private *priv)
2400 {
2401         int i;
2402
2403         /*
2404          * Ensure that the board is correctly configured.
2405          */
2406         if (priv->quirk->init)
2407                 priv->quirk->init(priv->dev);
2408
2409         for (i = 0; i < priv->nr; i++)
2410                 if (priv->line[i] >= 0)
2411                         serial8250_resume_port(priv->line[i]);
2412 }
2413 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2414
2415 /*
2416  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2417  * to the arrangement of serial ports on a PCI card.
2418  */
2419 static int __devinit
2420 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2421 {
2422         struct serial_private *priv;
2423         const struct pciserial_board *board;
2424         struct pciserial_board tmp;
2425         int rc;
2426
2427         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2428                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2429                         ent->driver_data);
2430                 return -EINVAL;
2431         }
2432
2433         board = &pci_boards[ent->driver_data];
2434
2435         rc = pci_enable_device(dev);
2436         if (rc)
2437                 return rc;
2438
2439         if (ent->driver_data == pbn_default) {
2440                 /*
2441                  * Use a copy of the pci_board entry for this;
2442                  * avoid changing entries in the table.
2443                  */
2444                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2445                 board = &tmp;
2446
2447                 /*
2448                  * We matched one of our class entries.  Try to
2449                  * determine the parameters of this board.
2450                  */
2451                 rc = serial_pci_guess_board(dev, &tmp);
2452                 if (rc)
2453                         goto disable;
2454         } else {
2455                 /*
2456                  * We matched an explicit entry.  If we are able to
2457                  * detect this boards settings with our heuristic,
2458                  * then we no longer need this entry.
2459                  */
2460                 memcpy(&tmp, &pci_boards[pbn_default],
2461                        sizeof(struct pciserial_board));
2462                 rc = serial_pci_guess_board(dev, &tmp);
2463                 if (rc == 0 && serial_pci_matches(board, &tmp))
2464                         moan_device("Redundant entry in serial pci_table.",
2465                                     dev);
2466         }
2467
2468         priv = pciserial_init_ports(dev, board);
2469         if (!IS_ERR(priv)) {
2470                 pci_set_drvdata(dev, priv);
2471                 return 0;
2472         }
2473
2474         rc = PTR_ERR(priv);
2475
2476  disable:
2477         pci_disable_device(dev);
2478         return rc;
2479 }
2480
2481 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2482 {
2483         struct serial_private *priv = pci_get_drvdata(dev);
2484
2485         pci_set_drvdata(dev, NULL);
2486
2487         pciserial_remove_ports(priv);
2488
2489         pci_disable_device(dev);
2490 }
2491
2492 #ifdef CONFIG_PM
2493 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2494 {
2495         struct serial_private *priv = pci_get_drvdata(dev);
2496
2497         if (priv)
2498                 pciserial_suspend_ports(priv);
2499
2500         pci_save_state(dev);
2501         pci_set_power_state(dev, pci_choose_state(dev, state));
2502         return 0;
2503 }
2504
2505 static int pciserial_resume_one(struct pci_dev *dev)
2506 {
2507         int err;
2508         struct serial_private *priv = pci_get_drvdata(dev);
2509
2510         pci_set_power_state(dev, PCI_D0);
2511         pci_restore_state(dev);
2512
2513         if (priv) {
2514                 /*
2515                  * The device may have been disabled.  Re-enable it.
2516                  */
2517                 err = pci_enable_device(dev);
2518                 /* FIXME: We cannot simply error out here */
2519                 if (err)
2520                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2521                 pciserial_resume_ports(priv);
2522         }
2523         return 0;
2524 }
2525 #endif
2526
2527 static struct pci_device_id serial_pci_tbl[] = {
2528         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2529         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2530                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2531                 pbn_b2_8_921600 },
2532         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2533                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2534                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2535                 pbn_b1_8_1382400 },
2536         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2537                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2538                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2539                 pbn_b1_4_1382400 },
2540         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2541                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2542                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2543                 pbn_b1_2_1382400 },
2544         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2545                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2546                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2547                 pbn_b1_8_1382400 },
2548         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2549                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2550                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2551                 pbn_b1_4_1382400 },
2552         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2553                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2554                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2555                 pbn_b1_2_1382400 },
2556         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2557                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2558                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2559                 pbn_b1_8_921600 },
2560         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2561                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2562                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2563                 pbn_b1_8_921600 },
2564         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2565                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2566                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2567                 pbn_b1_4_921600 },
2568         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2569                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2570                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2571                 pbn_b1_4_921600 },
2572         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2573                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2574                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2575                 pbn_b1_2_921600 },
2576         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2577                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2578                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2579                 pbn_b1_8_921600 },
2580         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2581                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2582                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2583                 pbn_b1_8_921600 },
2584         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2585                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2586                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2587                 pbn_b1_4_921600 },
2588         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2589                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2590                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2591                 pbn_b1_2_1250000 },
2592         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2593                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2594                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2595                 pbn_b0_2_1843200 },
2596         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2597                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2598                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2599                 pbn_b0_4_1843200 },
2600         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2601                 PCI_VENDOR_ID_AFAVLAB,
2602                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2603                 pbn_b0_4_1152000 },
2604         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2605                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2606                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2607                 pbn_b0_2_1843200_200 },
2608         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2609                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2610                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2611                 pbn_b0_4_1843200_200 },
2612         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2613                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2614                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2615                 pbn_b0_8_1843200_200 },
2616         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2617                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2618                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2619                 pbn_b0_2_1843200_200 },
2620         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2621                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2622                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2623                 pbn_b0_4_1843200_200 },
2624         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2625                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2626                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2627                 pbn_b0_8_1843200_200 },
2628         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2629                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2630                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2631                 pbn_b0_2_1843200_200 },
2632         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2633                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2634                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2635                 pbn_b0_4_1843200_200 },
2636         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2637                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2638                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2639                 pbn_b0_8_1843200_200 },
2640         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2641                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2642                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2643                 pbn_b0_2_1843200_200 },
2644         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2645                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2646                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2647                 pbn_b0_4_1843200_200 },
2648         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2649                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2650                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2651                 pbn_b0_8_1843200_200 },
2652
2653         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2654                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2655                 pbn_b2_bt_1_115200 },
2656         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2657                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2658                 pbn_b2_bt_2_115200 },
2659         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2660                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2661                 pbn_b2_bt_4_115200 },
2662         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2663                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2664                 pbn_b2_bt_2_115200 },
2665         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2666                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2667                 pbn_b2_bt_4_115200 },
2668         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2669                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2670                 pbn_b2_8_115200 },
2671         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2672                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2673                 pbn_b2_8_460800 },
2674         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2675                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2676                 pbn_b2_8_115200 },
2677
2678         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2679                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2680                 pbn_b2_bt_2_115200 },
2681         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2682                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2683                 pbn_b2_bt_2_921600 },
2684         /*
2685          * VScom SPCOM800, from sl@s.pl
2686          */
2687         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2688                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2689                 pbn_b2_8_921600 },
2690         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2691                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2692                 pbn_b2_4_921600 },
2693         /* Unknown card - subdevice 0x1584 */
2694         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2695                 PCI_VENDOR_ID_PLX,
2696                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2697                 pbn_b0_4_115200 },
2698         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2699                 PCI_SUBVENDOR_ID_KEYSPAN,
2700                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2701                 pbn_panacom },
2702         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2703                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2704                 pbn_panacom4 },
2705         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2706                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2707                 pbn_panacom2 },
2708         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2709                 PCI_VENDOR_ID_ESDGMBH,
2710                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2711                 pbn_b2_4_115200 },
2712         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2713                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2714                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2715                 pbn_b2_4_460800 },
2716         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2717                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2718                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2719                 pbn_b2_8_460800 },
2720         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2721                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2722                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2723                 pbn_b2_16_460800 },
2724         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2725                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2726                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2727                 pbn_b2_16_460800 },
2728         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2729                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2730                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2731                 pbn_b2_4_460800 },
2732         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2733                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2734                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2735                 pbn_b2_8_460800 },
2736         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2737                 PCI_SUBVENDOR_ID_EXSYS,
2738                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2739                 pbn_exsys_4055 },
2740         /*
2741          * Megawolf Romulus PCI Serial Card, from Mike Hudson
2742          * (Exoray@isys.ca)
2743          */
2744         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2745                 0x10b5, 0x106a, 0, 0,
2746                 pbn_plx_romulus },
2747         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2748                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2749                 pbn_b1_4_115200 },
2750         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2751                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2752                 pbn_b1_2_115200 },
2753         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2754                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2755                 pbn_b1_8_115200 },
2756         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2757                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2758                 pbn_b1_8_115200 },
2759         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2760                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2761                 0, 0,
2762                 pbn_b0_4_921600 },
2763         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2764                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2765                 0, 0,
2766                 pbn_b0_4_1152000 },
2767
2768                 /*
2769                  * The below card is a little controversial since it is the
2770                  * subject of a PCI vendor/device ID clash.  (See
2771                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2772                  * For now just used the hex ID 0x950a.
2773                  */
2774         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2775                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2776                 pbn_b0_2_115200 },
2777         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
2778                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2779                 pbn_b0_2_1130000 },
2780         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2781                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2782                 pbn_b0_1_921600 },
2783         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2784                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2785                 pbn_b0_4_115200 },
2786         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2787                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2788                 pbn_b0_bt_2_921600 },
2789
2790         /*
2791          * Oxford Semiconductor Inc. Tornado PCI express device range.
2792          */
2793         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
2794                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2795                 pbn_b0_1_4000000 },
2796         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
2797                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2798                 pbn_b0_1_4000000 },
2799         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
2800                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2801                 pbn_oxsemi_1_4000000 },
2802         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
2803                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2804                 pbn_oxsemi_1_4000000 },
2805         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
2806                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2807                 pbn_b0_1_4000000 },
2808         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
2809                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2810                 pbn_b0_1_4000000 },
2811         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
2812                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2813                 pbn_oxsemi_1_4000000 },
2814         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
2815                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2816                 pbn_oxsemi_1_4000000 },
2817         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
2818                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2819                 pbn_b0_1_4000000 },
2820         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
2821                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2822                 pbn_b0_1_4000000 },
2823         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
2824                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2825                 pbn_b0_1_4000000 },
2826         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
2827                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2828                 pbn_b0_1_4000000 },
2829         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
2830                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2831                 pbn_oxsemi_2_4000000 },
2832         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
2833                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2834                 pbn_oxsemi_2_4000000 },
2835         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
2836                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2837                 pbn_oxsemi_4_4000000 },
2838         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
2839                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2840                 pbn_oxsemi_4_4000000 },
2841         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
2842                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2843                 pbn_oxsemi_8_4000000 },
2844         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
2845                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2846                 pbn_oxsemi_8_4000000 },
2847         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
2848                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2849                 pbn_oxsemi_1_4000000 },
2850         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
2851                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2852                 pbn_oxsemi_1_4000000 },
2853         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
2854                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2855                 pbn_oxsemi_1_4000000 },
2856         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
2857                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2858                 pbn_oxsemi_1_4000000 },
2859         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
2860                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2861                 pbn_oxsemi_1_4000000 },
2862         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
2863                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2864                 pbn_oxsemi_1_4000000 },
2865         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
2866                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2867                 pbn_oxsemi_1_4000000 },
2868         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
2869                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2870                 pbn_oxsemi_1_4000000 },
2871         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
2872                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2873                 pbn_oxsemi_1_4000000 },
2874         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
2875                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2876                 pbn_oxsemi_1_4000000 },
2877         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
2878                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2879                 pbn_oxsemi_1_4000000 },
2880         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
2881                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2882                 pbn_oxsemi_1_4000000 },
2883         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
2884                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2885                 pbn_oxsemi_1_4000000 },
2886         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
2887                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2888                 pbn_oxsemi_1_4000000 },
2889         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
2890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2891                 pbn_oxsemi_1_4000000 },
2892         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
2893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2894                 pbn_oxsemi_1_4000000 },
2895         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
2896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2897                 pbn_oxsemi_1_4000000 },
2898         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
2899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2900                 pbn_oxsemi_1_4000000 },
2901         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
2902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2903                 pbn_oxsemi_1_4000000 },
2904         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
2905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2906                 pbn_oxsemi_1_4000000 },
2907         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
2908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2909                 pbn_oxsemi_1_4000000 },
2910         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
2911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2912                 pbn_oxsemi_1_4000000 },
2913         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
2914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2915                 pbn_oxsemi_1_4000000 },
2916         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
2917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2918                 pbn_oxsemi_1_4000000 },
2919         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
2920                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2921                 pbn_oxsemi_1_4000000 },
2922         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
2923                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2924                 pbn_oxsemi_1_4000000 },
2925         /*
2926          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2927          */
2928         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2929                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
2930                 pbn_oxsemi_1_4000000 },
2931         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2932                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
2933                 pbn_oxsemi_2_4000000 },
2934         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2935                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
2936                 pbn_oxsemi_4_4000000 },
2937         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2938                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
2939                 pbn_oxsemi_8_4000000 },
2940         /*
2941          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2942          * from skokodyn@yahoo.com
2943          */
2944         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2945                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2946                 pbn_sbsxrsio },
2947         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2948                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2949                 pbn_sbsxrsio },
2950         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2951                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2952                 pbn_sbsxrsio },
2953         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2954                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2955                 pbn_sbsxrsio },
2956
2957         /*
2958          * Digitan DS560-558, from jimd@esoft.com
2959          */
2960         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2961                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2962                 pbn_b1_1_115200 },
2963
2964         /*
2965          * Titan Electronic cards
2966          *  The 400L and 800L have a custom setup quirk.
2967          */
2968         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2969                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2970                 pbn_b0_1_921600 },
2971         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2972                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2973                 pbn_b0_2_921600 },
2974         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2975                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2976                 pbn_b0_4_921600 },
2977         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2978                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2979                 pbn_b0_4_921600 },
2980         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2981                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2982                 pbn_b1_1_921600 },
2983         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2984                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2985                 pbn_b1_bt_2_921600 },
2986         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2987                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2988                 pbn_b0_bt_4_921600 },
2989         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2990                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2991                 pbn_b0_bt_8_921600 },
2992
2993         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2994                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2995                 pbn_b2_1_460800 },
2996         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2997                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2998                 pbn_b2_1_460800 },
2999         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3000                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3001                 pbn_b2_1_460800 },
3002         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3003                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3004                 pbn_b2_bt_2_921600 },
3005         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3006                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3007                 pbn_b2_bt_2_921600 },
3008         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3009                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3010                 pbn_b2_bt_2_921600 },
3011         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3012                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3013                 pbn_b2_bt_4_921600 },
3014         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3015                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3016                 pbn_b2_bt_4_921600 },
3017         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3018                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3019                 pbn_b2_bt_4_921600 },
3020         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3021                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3022                 pbn_b0_1_921600 },
3023         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3024                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3025                 pbn_b0_1_921600 },
3026         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3027                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3028                 pbn_b0_1_921600 },
3029         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3030                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3031                 pbn_b0_bt_2_921600 },
3032         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3033                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3034                 pbn_b0_bt_2_921600 },
3035         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3036                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3037                 pbn_b0_bt_2_921600 },
3038         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3039                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3040                 pbn_b0_bt_4_921600 },
3041         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3042                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3043                 pbn_b0_bt_4_921600 },
3044         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3045                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3046                 pbn_b0_bt_4_921600 },
3047         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3048                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3049                 pbn_b0_bt_8_921600 },
3050         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3051                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3052                 pbn_b0_bt_8_921600 },
3053         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3054                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3055                 pbn_b0_bt_8_921600 },
3056
3057         /*
3058          * Computone devices submitted by Doug McNash dmcnash@computone.com
3059          */
3060         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3061                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3062                 0, 0, pbn_computone_4 },
3063         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3064                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3065                 0, 0, pbn_computone_8 },
3066         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3067                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3068                 0, 0, pbn_computone_6 },
3069
3070         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3071                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3072                 pbn_oxsemi },
3073         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3074                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3075                 pbn_b0_bt_1_921600 },
3076
3077         /*
3078          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3079          */
3080         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3081                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3082                 pbn_b0_bt_8_115200 },
3083         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3084                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3085                 pbn_b0_bt_8_115200 },
3086
3087         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3088                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3089                 pbn_b0_bt_2_115200 },
3090         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3091                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3092                 pbn_b0_bt_2_115200 },
3093         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3094                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3095                 pbn_b0_bt_2_115200 },
3096         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3097                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3098                 pbn_b0_bt_4_460800 },
3099         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3100                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3101                 pbn_b0_bt_4_460800 },
3102         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3103                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3104                 pbn_b0_bt_2_460800 },
3105         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3106                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3107                 pbn_b0_bt_2_460800 },
3108         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3109                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3110                 pbn_b0_bt_2_460800 },
3111         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3112                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3113                 pbn_b0_bt_1_115200 },
3114         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3115                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3116                 pbn_b0_bt_1_460800 },
3117
3118         /*
3119          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3120          * Cards are identified by their subsystem vendor IDs, which
3121          * (in hex) match the model number.
3122          *
3123          * Note that JC140x are RS422/485 cards which require ox950
3124          * ACR = 0x10, and as such are not currently fully supported.
3125          */
3126         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3127                 0x1204, 0x0004, 0, 0,
3128                 pbn_b0_4_921600 },
3129         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3130                 0x1208, 0x0004, 0, 0,
3131                 pbn_b0_4_921600 },
3132 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3133                 0x1402, 0x0002, 0, 0,
3134                 pbn_b0_2_921600 }, */
3135 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3136                 0x1404, 0x0004, 0, 0,
3137                 pbn_b0_4_921600 }, */
3138         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3139                 0x1208, 0x0004, 0, 0,
3140                 pbn_b0_4_921600 },
3141
3142         /*
3143          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3144          */
3145         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3146                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3147                 pbn_b1_1_1382400 },
3148
3149         /*
3150          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3151          */
3152         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3153                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3154                 pbn_b1_1_1382400 },
3155
3156         /*
3157          * RAStel 2 port modem, gerg@moreton.com.au
3158          */
3159         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3160                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3161                 pbn_b2_bt_2_115200 },
3162
3163         /*
3164          * EKF addition for i960 Boards form EKF with serial port
3165          */
3166         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3167                 0xE4BF, PCI_ANY_ID, 0, 0,
3168                 pbn_intel_i960 },
3169
3170         /*
3171          * Xircom Cardbus/Ethernet combos
3172          */
3173         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3175                 pbn_b0_1_115200 },
3176         /*
3177          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3178          */
3179         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3181                 pbn_b0_1_115200 },
3182
3183         /*
3184          * Untested PCI modems, sent in from various folks...
3185          */
3186
3187         /*
3188          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3189          */
3190         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3191                 0x1048, 0x1500, 0, 0,
3192                 pbn_b1_1_115200 },
3193
3194         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3195                 0xFF00, 0, 0, 0,
3196                 pbn_sgi_ioc3 },
3197
3198         /*
3199          * HP Diva card
3200          */
3201         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3202                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3203                 pbn_b1_1_115200 },
3204         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3205                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3206                 pbn_b0_5_115200 },
3207         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3208                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3209                 pbn_b2_1_115200 },
3210
3211         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3212                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3213                 pbn_b3_2_115200 },
3214         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3215                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3216                 pbn_b3_4_115200 },
3217         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3218                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3219                 pbn_b3_8_115200 },
3220
3221         /*
3222          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3223          */
3224         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3225                 PCI_ANY_ID, PCI_ANY_ID,
3226                 0,
3227                 0, pbn_exar_XR17C152 },
3228         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3229                 PCI_ANY_ID, PCI_ANY_ID,
3230                 0,
3231                 0, pbn_exar_XR17C154 },
3232         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3233                 PCI_ANY_ID, PCI_ANY_ID,
3234                 0,
3235                 0, pbn_exar_XR17C158 },
3236
3237         /*
3238          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3239          */
3240         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242                 pbn_b0_1_115200 },
3243         /*
3244          * ITE
3245          */
3246         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3247                 PCI_ANY_ID, PCI_ANY_ID,
3248                 0, 0,
3249                 pbn_b1_bt_1_115200 },
3250
3251         /*
3252          * IntaShield IS-200
3253          */
3254         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3255                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3256                 pbn_b2_2_115200 },
3257         /*
3258          * IntaShield IS-400
3259          */
3260         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3261                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3262                 pbn_b2_4_115200 },
3263         /*
3264          * Perle PCI-RAS cards
3265          */
3266         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3267                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3268                 0, 0, pbn_b2_4_921600 },
3269         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3270                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3271                 0, 0, pbn_b2_8_921600 },
3272
3273         /*
3274          * Mainpine series cards: Fairly standard layout but fools
3275          * parts of the autodetect in some cases and uses otherwise
3276          * unmatched communications subclasses in the PCI Express case
3277          */
3278
3279         {       /* RockForceDUO */
3280                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3281                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3282                 0, 0, pbn_b0_2_115200 },
3283         {       /* RockForceQUATRO */
3284                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3285                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3286                 0, 0, pbn_b0_4_115200 },
3287         {       /* RockForceDUO+ */
3288                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3289                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3290                 0, 0, pbn_b0_2_115200 },
3291         {       /* RockForceQUATRO+ */
3292                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3293                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3294                 0, 0, pbn_b0_4_115200 },
3295         {       /* RockForce+ */
3296                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3297                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3298                 0, 0, pbn_b0_2_115200 },
3299         {       /* RockForce+ */
3300                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3301                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3302                 0, 0, pbn_b0_4_115200 },
3303         {       /* RockForceOCTO+ */
3304                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3305                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3306                 0, 0, pbn_b0_8_115200 },
3307         {       /* RockForceDUO+ */
3308                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3309                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3310                 0, 0, pbn_b0_2_115200 },
3311         {       /* RockForceQUARTRO+ */
3312                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3313                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3314                 0, 0, pbn_b0_4_115200 },
3315         {       /* RockForceOCTO+ */
3316                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3317                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3318                 0, 0, pbn_b0_8_115200 },
3319         {       /* RockForceD1 */
3320                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3321                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3322                 0, 0, pbn_b0_1_115200 },
3323         {       /* RockForceF1 */
3324                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3325                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3326                 0, 0, pbn_b0_1_115200 },
3327         {       /* RockForceD2 */
3328                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3329                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3330                 0, 0, pbn_b0_2_115200 },
3331         {       /* RockForceF2 */
3332                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3333                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3334                 0, 0, pbn_b0_2_115200 },
3335         {       /* RockForceD4 */
3336                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3337                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3338                 0, 0, pbn_b0_4_115200 },
3339         {       /* RockForceF4 */
3340                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3341                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3342                 0, 0, pbn_b0_4_115200 },
3343         {       /* RockForceD8 */
3344                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3345                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3346                 0, 0, pbn_b0_8_115200 },
3347         {       /* RockForceF8 */
3348                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3349                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3350                 0, 0, pbn_b0_8_115200 },
3351         {       /* IQ Express D1 */
3352                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3353                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3354                 0, 0, pbn_b0_1_115200 },
3355         {       /* IQ Express F1 */
3356                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3357                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3358                 0, 0, pbn_b0_1_115200 },
3359         {       /* IQ Express D2 */
3360                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3361                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3362                 0, 0, pbn_b0_2_115200 },
3363         {       /* IQ Express F2 */
3364                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3365                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3366                 0, 0, pbn_b0_2_115200 },
3367         {       /* IQ Express D4 */
3368                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3369                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3370                 0, 0, pbn_b0_4_115200 },
3371         {       /* IQ Express F4 */
3372                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3373                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3374                 0, 0, pbn_b0_4_115200 },
3375         {       /* IQ Express D8 */
3376                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3377                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3378                 0, 0, pbn_b0_8_115200 },
3379         {       /* IQ Express F8 */
3380                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3381                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3382                 0, 0, pbn_b0_8_115200 },
3383
3384
3385         /*
3386          * PA Semi PA6T-1682M on-chip UART
3387          */
3388         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3389                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3390                 pbn_pasemi_1682M },
3391
3392         /*
3393          * National Instruments
3394          */
3395         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3397                 pbn_b1_16_115200 },
3398         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3400                 pbn_b1_8_115200 },
3401         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3402                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3403                 pbn_b1_bt_4_115200 },
3404         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3405                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3406                 pbn_b1_bt_2_115200 },
3407         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3408                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3409                 pbn_b1_bt_4_115200 },
3410         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3411                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3412                 pbn_b1_bt_2_115200 },
3413         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3415                 pbn_b1_16_115200 },
3416         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3417                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3418                 pbn_b1_8_115200 },
3419         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3420                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3421                 pbn_b1_bt_4_115200 },
3422         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3423                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3424                 pbn_b1_bt_2_115200 },
3425         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3426                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3427                 pbn_b1_bt_4_115200 },
3428         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3429                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3430                 pbn_b1_bt_2_115200 },
3431         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3432                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3433                 pbn_ni8430_2 },
3434         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3435                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3436                 pbn_ni8430_2 },
3437         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3438                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3439                 pbn_ni8430_4 },
3440         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3441                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3442                 pbn_ni8430_4 },
3443         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3444                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3445                 pbn_ni8430_8 },
3446         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3447                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3448                 pbn_ni8430_8 },
3449         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3450                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3451                 pbn_ni8430_16 },
3452         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3453                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3454                 pbn_ni8430_16 },
3455         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3456                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3457                 pbn_ni8430_2 },
3458         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3459                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3460                 pbn_ni8430_2 },
3461         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3462                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3463                 pbn_ni8430_4 },
3464         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3465                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3466                 pbn_ni8430_4 },
3467
3468         /*
3469         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3470         */
3471         {       PCI_VENDOR_ID_ADDIDATA,
3472                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3473                 PCI_ANY_ID,
3474                 PCI_ANY_ID,
3475                 0,
3476                 0,
3477                 pbn_b0_4_115200 },
3478
3479         {       PCI_VENDOR_ID_ADDIDATA,
3480                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3481                 PCI_ANY_ID,
3482                 PCI_ANY_ID,
3483                 0,
3484                 0,
3485                 pbn_b0_2_115200 },
3486
3487         {       PCI_VENDOR_ID_ADDIDATA,
3488                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3489                 PCI_ANY_ID,
3490                 PCI_ANY_ID,
3491                 0,
3492                 0,
3493                 pbn_b0_1_115200 },
3494
3495         {       PCI_VENDOR_ID_ADDIDATA_OLD,
3496                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3497                 PCI_ANY_ID,
3498                 PCI_ANY_ID,
3499                 0,
3500                 0,
3501                 pbn_b1_8_115200 },
3502
3503         {       PCI_VENDOR_ID_ADDIDATA,
3504                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3505                 PCI_ANY_ID,
3506                 PCI_ANY_ID,
3507                 0,
3508                 0,
3509                 pbn_b0_4_115200 },
3510
3511         {       PCI_VENDOR_ID_ADDIDATA,
3512                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3513                 PCI_ANY_ID,
3514                 PCI_ANY_ID,
3515                 0,
3516                 0,
3517                 pbn_b0_2_115200 },
3518
3519         {       PCI_VENDOR_ID_ADDIDATA,
3520                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3521                 PCI_ANY_ID,
3522                 PCI_ANY_ID,
3523                 0,
3524                 0,
3525                 pbn_b0_1_115200 },
3526
3527         {       PCI_VENDOR_ID_ADDIDATA,
3528                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3529                 PCI_ANY_ID,
3530                 PCI_ANY_ID,
3531                 0,
3532                 0,
3533                 pbn_b0_4_115200 },
3534
3535         {       PCI_VENDOR_ID_ADDIDATA,
3536                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3537                 PCI_ANY_ID,
3538                 PCI_ANY_ID,
3539                 0,
3540                 0,
3541                 pbn_b0_2_115200 },
3542
3543         {       PCI_VENDOR_ID_ADDIDATA,
3544                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3545                 PCI_ANY_ID,
3546                 PCI_ANY_ID,
3547                 0,
3548                 0,
3549                 pbn_b0_1_115200 },
3550
3551         {       PCI_VENDOR_ID_ADDIDATA,
3552                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3553                 PCI_ANY_ID,
3554                 PCI_ANY_ID,
3555                 0,
3556                 0,
3557                 pbn_b0_8_115200 },
3558
3559         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3560                 PCI_VENDOR_ID_IBM, 0x0299,
3561                 0, 0, pbn_b0_bt_2_115200 },
3562
3563         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3564                 0xA000, 0x1000,
3565                 0, 0, pbn_b0_1_115200 },
3566
3567         /*
3568          * These entries match devices with class COMMUNICATION_SERIAL,
3569          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3570          */
3571         {       PCI_ANY_ID, PCI_ANY_ID,
3572                 PCI_ANY_ID, PCI_ANY_ID,
3573                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3574                 0xffff00, pbn_default },
3575         {       PCI_ANY_ID, PCI_ANY_ID,
3576                 PCI_ANY_ID, PCI_ANY_ID,
3577                 PCI_CLASS_COMMUNICATION_MODEM << 8,
3578                 0xffff00, pbn_default },
3579         {       PCI_ANY_ID, PCI_ANY_ID,
3580                 PCI_ANY_ID, PCI_ANY_ID,
3581                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3582                 0xffff00, pbn_default },
3583         { 0, }
3584 };
3585
3586 static struct pci_driver serial_pci_driver = {
3587         .name           = "serial",
3588         .probe          = pciserial_init_one,
3589         .remove         = __devexit_p(pciserial_remove_one),
3590 #ifdef CONFIG_PM
3591         .suspend        = pciserial_suspend_one,
3592         .resume         = pciserial_resume_one,
3593 #endif
3594         .id_table       = serial_pci_tbl,
3595 };
3596
3597 static int __init serial8250_pci_init(void)
3598 {
3599         return pci_register_driver(&serial_pci_driver);
3600 }
3601
3602 static void __exit serial8250_pci_exit(void)
3603 {
3604         pci_unregister_driver(&serial_pci_driver);
3605 }
3606
3607 module_init(serial8250_pci_init);
3608 module_exit(serial8250_pci_exit);
3609
3610 MODULE_LICENSE("GPL");
3611 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3612 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);