Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6
[linux-2.6] / arch / mips / kernel / cpu-probe.c
1 /*
2  * Processor capabilities determination functions.
3  *
4  * Copyright (C) xxxx  the Anonymous
5  * Copyright (C) 1994 - 2006 Ralf Baechle
6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
7  * Copyright (C) 2001, 2004  MIPS Inc.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
18
19 #include <asm/cpu.h>
20 #include <asm/fpu.h>
21 #include <asm/mipsregs.h>
22 #include <asm/system.h>
23
24 /*
25  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
26  * the implementation of the "wait" feature differs between CPU families. This
27  * points to the function that implements CPU specific wait.
28  * The wait instruction stops the pipeline and reduces the power consumption of
29  * the CPU very much.
30  */
31 void (*cpu_wait)(void) = NULL;
32
33 static void r3081_wait(void)
34 {
35         unsigned long cfg = read_c0_conf();
36         write_c0_conf(cfg | R30XX_CONF_HALT);
37 }
38
39 static void r39xx_wait(void)
40 {
41         local_irq_disable();
42         if (!need_resched())
43                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
44         local_irq_enable();
45 }
46
47 /*
48  * There is a race when WAIT instruction executed with interrupt
49  * enabled.
50  * But it is implementation-dependent wheter the pipelie restarts when
51  * a non-enabled interrupt is requested.
52  */
53 static void r4k_wait(void)
54 {
55         __asm__("       .set    mips3                   \n"
56                 "       wait                            \n"
57                 "       .set    mips0                   \n");
58 }
59
60 /*
61  * This variant is preferable as it allows testing need_resched and going to
62  * sleep depending on the outcome atomically.  Unfortunately the "It is
63  * implementation-dependent whether the pipeline restarts when a non-enabled
64  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
65  * using this version a gamble.
66  */
67 static void r4k_wait_irqoff(void)
68 {
69         local_irq_disable();
70         if (!need_resched())
71                 __asm__("       .set    mips3           \n"
72                         "       wait                    \n"
73                         "       .set    mips0           \n");
74         local_irq_enable();
75 }
76
77 /* The Au1xxx wait is available only if using 32khz counter or
78  * external timer source, but specifically not CP0 Counter. */
79 int allow_au1k_wait;
80
81 static void au1k_wait(void)
82 {
83         /* using the wait instruction makes CP0 counter unusable */
84         __asm__("       .set    mips3                   \n"
85                 "       cache   0x14, 0(%0)             \n"
86                 "       cache   0x14, 32(%0)            \n"
87                 "       sync                            \n"
88                 "       nop                             \n"
89                 "       wait                            \n"
90                 "       nop                             \n"
91                 "       nop                             \n"
92                 "       nop                             \n"
93                 "       nop                             \n"
94                 "       .set    mips0                   \n"
95                 : : "r" (au1k_wait));
96 }
97
98 static int __initdata nowait = 0;
99
100 int __init wait_disable(char *s)
101 {
102         nowait = 1;
103
104         return 1;
105 }
106
107 __setup("nowait", wait_disable);
108
109 static inline void check_wait(void)
110 {
111         struct cpuinfo_mips *c = &current_cpu_data;
112
113         if (nowait) {
114                 printk("Wait instruction disabled.\n");
115                 return;
116         }
117
118         switch (c->cputype) {
119         case CPU_R3081:
120         case CPU_R3081E:
121                 cpu_wait = r3081_wait;
122                 break;
123         case CPU_TX3927:
124                 cpu_wait = r39xx_wait;
125                 break;
126         case CPU_R4200:
127 /*      case CPU_R4300: */
128         case CPU_R4600:
129         case CPU_R4640:
130         case CPU_R4650:
131         case CPU_R4700:
132         case CPU_R5000:
133         case CPU_NEVADA:
134         case CPU_RM7000:
135         case CPU_4KC:
136         case CPU_4KEC:
137         case CPU_4KSC:
138         case CPU_5KC:
139 /*      case CPU_20KC:*/
140         case CPU_24K:
141         case CPU_25KF:
142         case CPU_34K:
143         case CPU_74K:
144         case CPU_PR4450:
145                 cpu_wait = r4k_wait;
146                 break;
147         case CPU_TX49XX:
148                 cpu_wait = r4k_wait_irqoff;
149                 break;
150         case CPU_AU1000:
151         case CPU_AU1100:
152         case CPU_AU1500:
153         case CPU_AU1550:
154         case CPU_AU1200:
155                 if (allow_au1k_wait)
156                         cpu_wait = au1k_wait;
157                 break;
158         case CPU_RM9000:
159                 if ((c->processor_id & 0x00ff) >= 0x40)
160                         cpu_wait = r4k_wait;
161                 break;
162         default:
163                 break;
164         }
165 }
166
167 void __init check_bugs32(void)
168 {
169         check_wait();
170 }
171
172 /*
173  * Probe whether cpu has config register by trying to play with
174  * alternate cache bit and see whether it matters.
175  * It's used by cpu_probe to distinguish between R3000A and R3081.
176  */
177 static inline int cpu_has_confreg(void)
178 {
179 #ifdef CONFIG_CPU_R3000
180         extern unsigned long r3k_cache_size(unsigned long);
181         unsigned long size1, size2;
182         unsigned long cfg = read_c0_conf();
183
184         size1 = r3k_cache_size(ST0_ISC);
185         write_c0_conf(cfg ^ R30XX_CONF_AC);
186         size2 = r3k_cache_size(ST0_ISC);
187         write_c0_conf(cfg);
188         return size1 != size2;
189 #else
190         return 0;
191 #endif
192 }
193
194 /*
195  * Get the FPU Implementation/Revision.
196  */
197 static inline unsigned long cpu_get_fpu_id(void)
198 {
199         unsigned long tmp, fpu_id;
200
201         tmp = read_c0_status();
202         __enable_fpu();
203         fpu_id = read_32bit_cp1_register(CP1_REVISION);
204         write_c0_status(tmp);
205         return fpu_id;
206 }
207
208 /*
209  * Check the CPU has an FPU the official way.
210  */
211 static inline int __cpu_has_fpu(void)
212 {
213         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
214 }
215
216 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
217                 | MIPS_CPU_COUNTER)
218
219 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
220 {
221         switch (c->processor_id & 0xff00) {
222         case PRID_IMP_R2000:
223                 c->cputype = CPU_R2000;
224                 c->isa_level = MIPS_CPU_ISA_I;
225                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
226                              MIPS_CPU_NOFPUEX;
227                 if (__cpu_has_fpu())
228                         c->options |= MIPS_CPU_FPU;
229                 c->tlbsize = 64;
230                 break;
231         case PRID_IMP_R3000:
232                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
233                         if (cpu_has_confreg())
234                                 c->cputype = CPU_R3081E;
235                         else
236                                 c->cputype = CPU_R3000A;
237                 else
238                         c->cputype = CPU_R3000;
239                 c->isa_level = MIPS_CPU_ISA_I;
240                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
241                              MIPS_CPU_NOFPUEX;
242                 if (__cpu_has_fpu())
243                         c->options |= MIPS_CPU_FPU;
244                 c->tlbsize = 64;
245                 break;
246         case PRID_IMP_R4000:
247                 if (read_c0_config() & CONF_SC) {
248                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
249                                 c->cputype = CPU_R4400PC;
250                         else
251                                 c->cputype = CPU_R4000PC;
252                 } else {
253                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
254                                 c->cputype = CPU_R4400SC;
255                         else
256                                 c->cputype = CPU_R4000SC;
257                 }
258
259                 c->isa_level = MIPS_CPU_ISA_III;
260                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
261                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
262                              MIPS_CPU_LLSC;
263                 c->tlbsize = 48;
264                 break;
265         case PRID_IMP_VR41XX:
266                 switch (c->processor_id & 0xf0) {
267                 case PRID_REV_VR4111:
268                         c->cputype = CPU_VR4111;
269                         break;
270                 case PRID_REV_VR4121:
271                         c->cputype = CPU_VR4121;
272                         break;
273                 case PRID_REV_VR4122:
274                         if ((c->processor_id & 0xf) < 0x3)
275                                 c->cputype = CPU_VR4122;
276                         else
277                                 c->cputype = CPU_VR4181A;
278                         break;
279                 case PRID_REV_VR4130:
280                         if ((c->processor_id & 0xf) < 0x4)
281                                 c->cputype = CPU_VR4131;
282                         else
283                                 c->cputype = CPU_VR4133;
284                         break;
285                 default:
286                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
287                         c->cputype = CPU_VR41XX;
288                         break;
289                 }
290                 c->isa_level = MIPS_CPU_ISA_III;
291                 c->options = R4K_OPTS;
292                 c->tlbsize = 32;
293                 break;
294         case PRID_IMP_R4300:
295                 c->cputype = CPU_R4300;
296                 c->isa_level = MIPS_CPU_ISA_III;
297                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
298                              MIPS_CPU_LLSC;
299                 c->tlbsize = 32;
300                 break;
301         case PRID_IMP_R4600:
302                 c->cputype = CPU_R4600;
303                 c->isa_level = MIPS_CPU_ISA_III;
304                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
305                              MIPS_CPU_LLSC;
306                 c->tlbsize = 48;
307                 break;
308         #if 0
309         case PRID_IMP_R4650:
310                 /*
311                  * This processor doesn't have an MMU, so it's not
312                  * "real easy" to run Linux on it. It is left purely
313                  * for documentation.  Commented out because it shares
314                  * it's c0_prid id number with the TX3900.
315                  */
316                 c->cputype = CPU_R4650;
317                 c->isa_level = MIPS_CPU_ISA_III;
318                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
319                 c->tlbsize = 48;
320                 break;
321         #endif
322         case PRID_IMP_TX39:
323                 c->isa_level = MIPS_CPU_ISA_I;
324                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
325
326                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
327                         c->cputype = CPU_TX3927;
328                         c->tlbsize = 64;
329                 } else {
330                         switch (c->processor_id & 0xff) {
331                         case PRID_REV_TX3912:
332                                 c->cputype = CPU_TX3912;
333                                 c->tlbsize = 32;
334                                 break;
335                         case PRID_REV_TX3922:
336                                 c->cputype = CPU_TX3922;
337                                 c->tlbsize = 64;
338                                 break;
339                         default:
340                                 c->cputype = CPU_UNKNOWN;
341                                 break;
342                         }
343                 }
344                 break;
345         case PRID_IMP_R4700:
346                 c->cputype = CPU_R4700;
347                 c->isa_level = MIPS_CPU_ISA_III;
348                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
349                              MIPS_CPU_LLSC;
350                 c->tlbsize = 48;
351                 break;
352         case PRID_IMP_TX49:
353                 c->cputype = CPU_TX49XX;
354                 c->isa_level = MIPS_CPU_ISA_III;
355                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
356                 if (!(c->processor_id & 0x08))
357                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
358                 c->tlbsize = 48;
359                 break;
360         case PRID_IMP_R5000:
361                 c->cputype = CPU_R5000;
362                 c->isa_level = MIPS_CPU_ISA_IV;
363                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
364                              MIPS_CPU_LLSC;
365                 c->tlbsize = 48;
366                 break;
367         case PRID_IMP_R5432:
368                 c->cputype = CPU_R5432;
369                 c->isa_level = MIPS_CPU_ISA_IV;
370                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
371                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
372                 c->tlbsize = 48;
373                 break;
374         case PRID_IMP_R5500:
375                 c->cputype = CPU_R5500;
376                 c->isa_level = MIPS_CPU_ISA_IV;
377                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
378                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
379                 c->tlbsize = 48;
380                 break;
381         case PRID_IMP_NEVADA:
382                 c->cputype = CPU_NEVADA;
383                 c->isa_level = MIPS_CPU_ISA_IV;
384                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
385                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
386                 c->tlbsize = 48;
387                 break;
388         case PRID_IMP_R6000:
389                 c->cputype = CPU_R6000;
390                 c->isa_level = MIPS_CPU_ISA_II;
391                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
392                              MIPS_CPU_LLSC;
393                 c->tlbsize = 32;
394                 break;
395         case PRID_IMP_R6000A:
396                 c->cputype = CPU_R6000A;
397                 c->isa_level = MIPS_CPU_ISA_II;
398                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
399                              MIPS_CPU_LLSC;
400                 c->tlbsize = 32;
401                 break;
402         case PRID_IMP_RM7000:
403                 c->cputype = CPU_RM7000;
404                 c->isa_level = MIPS_CPU_ISA_IV;
405                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
406                              MIPS_CPU_LLSC;
407                 /*
408                  * Undocumented RM7000:  Bit 29 in the info register of
409                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
410                  * entries.
411                  *
412                  * 29      1 =>    64 entry JTLB
413                  *         0 =>    48 entry JTLB
414                  */
415                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
416                 break;
417         case PRID_IMP_RM9000:
418                 c->cputype = CPU_RM9000;
419                 c->isa_level = MIPS_CPU_ISA_IV;
420                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
421                              MIPS_CPU_LLSC;
422                 /*
423                  * Bit 29 in the info register of the RM9000
424                  * indicates if the TLB has 48 or 64 entries.
425                  *
426                  * 29      1 =>    64 entry JTLB
427                  *         0 =>    48 entry JTLB
428                  */
429                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
430                 break;
431         case PRID_IMP_R8000:
432                 c->cputype = CPU_R8000;
433                 c->isa_level = MIPS_CPU_ISA_IV;
434                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
435                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
436                              MIPS_CPU_LLSC;
437                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
438                 break;
439         case PRID_IMP_R10000:
440                 c->cputype = CPU_R10000;
441                 c->isa_level = MIPS_CPU_ISA_IV;
442                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
443                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
444                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
445                              MIPS_CPU_LLSC;
446                 c->tlbsize = 64;
447                 break;
448         case PRID_IMP_R12000:
449                 c->cputype = CPU_R12000;
450                 c->isa_level = MIPS_CPU_ISA_IV;
451                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
452                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
453                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
454                              MIPS_CPU_LLSC;
455                 c->tlbsize = 64;
456                 break;
457         case PRID_IMP_R14000:
458                 c->cputype = CPU_R14000;
459                 c->isa_level = MIPS_CPU_ISA_IV;
460                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
461                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
462                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
463                              MIPS_CPU_LLSC;
464                 c->tlbsize = 64;
465                 break;
466         }
467 }
468
469 static char unknown_isa[] __initdata = KERN_ERR \
470         "Unsupported ISA type, c0.config0: %d.";
471
472 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
473 {
474         unsigned int config0;
475         int isa;
476
477         config0 = read_c0_config();
478
479         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
480                 c->options |= MIPS_CPU_TLB;
481         isa = (config0 & MIPS_CONF_AT) >> 13;
482         switch (isa) {
483         case 0:
484                 switch ((config0 & MIPS_CONF_AR) >> 10) {
485                 case 0:
486                         c->isa_level = MIPS_CPU_ISA_M32R1;
487                         break;
488                 case 1:
489                         c->isa_level = MIPS_CPU_ISA_M32R2;
490                         break;
491                 default:
492                         goto unknown;
493                 }
494                 break;
495         case 2:
496                 switch ((config0 & MIPS_CONF_AR) >> 10) {
497                 case 0:
498                         c->isa_level = MIPS_CPU_ISA_M64R1;
499                         break;
500                 case 1:
501                         c->isa_level = MIPS_CPU_ISA_M64R2;
502                         break;
503                 default:
504                         goto unknown;
505                 }
506                 break;
507         default:
508                 goto unknown;
509         }
510
511         return config0 & MIPS_CONF_M;
512
513 unknown:
514         panic(unknown_isa, config0);
515 }
516
517 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
518 {
519         unsigned int config1;
520
521         config1 = read_c0_config1();
522
523         if (config1 & MIPS_CONF1_MD)
524                 c->ases |= MIPS_ASE_MDMX;
525         if (config1 & MIPS_CONF1_WR)
526                 c->options |= MIPS_CPU_WATCH;
527         if (config1 & MIPS_CONF1_CA)
528                 c->ases |= MIPS_ASE_MIPS16;
529         if (config1 & MIPS_CONF1_EP)
530                 c->options |= MIPS_CPU_EJTAG;
531         if (config1 & MIPS_CONF1_FP) {
532                 c->options |= MIPS_CPU_FPU;
533                 c->options |= MIPS_CPU_32FPR;
534         }
535         if (cpu_has_tlb)
536                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
537
538         return config1 & MIPS_CONF_M;
539 }
540
541 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
542 {
543         unsigned int config2;
544
545         config2 = read_c0_config2();
546
547         if (config2 & MIPS_CONF2_SL)
548                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
549
550         return config2 & MIPS_CONF_M;
551 }
552
553 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
554 {
555         unsigned int config3;
556
557         config3 = read_c0_config3();
558
559         if (config3 & MIPS_CONF3_SM)
560                 c->ases |= MIPS_ASE_SMARTMIPS;
561         if (config3 & MIPS_CONF3_DSP)
562                 c->ases |= MIPS_ASE_DSP;
563         if (config3 & MIPS_CONF3_VINT)
564                 c->options |= MIPS_CPU_VINT;
565         if (config3 & MIPS_CONF3_VEIC)
566                 c->options |= MIPS_CPU_VEIC;
567         if (config3 & MIPS_CONF3_MT)
568                 c->ases |= MIPS_ASE_MIPSMT;
569
570         return config3 & MIPS_CONF_M;
571 }
572
573 static void __init decode_configs(struct cpuinfo_mips *c)
574 {
575         /* MIPS32 or MIPS64 compliant CPU.  */
576         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
577                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
578
579         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
580
581         /* Read Config registers.  */
582         if (!decode_config0(c))
583                 return;                 /* actually worth a panic() */
584         if (!decode_config1(c))
585                 return;
586         if (!decode_config2(c))
587                 return;
588         if (!decode_config3(c))
589                 return;
590 }
591
592 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
593 {
594         decode_configs(c);
595         switch (c->processor_id & 0xff00) {
596         case PRID_IMP_4KC:
597                 c->cputype = CPU_4KC;
598                 break;
599         case PRID_IMP_4KEC:
600                 c->cputype = CPU_4KEC;
601                 break;
602         case PRID_IMP_4KECR2:
603                 c->cputype = CPU_4KEC;
604                 break;
605         case PRID_IMP_4KSC:
606         case PRID_IMP_4KSD:
607                 c->cputype = CPU_4KSC;
608                 break;
609         case PRID_IMP_5KC:
610                 c->cputype = CPU_5KC;
611                 break;
612         case PRID_IMP_20KC:
613                 c->cputype = CPU_20KC;
614                 break;
615         case PRID_IMP_24K:
616         case PRID_IMP_24KE:
617                 c->cputype = CPU_24K;
618                 break;
619         case PRID_IMP_25KF:
620                 c->cputype = CPU_25KF;
621                 break;
622         case PRID_IMP_34K:
623                 c->cputype = CPU_34K;
624                 break;
625         case PRID_IMP_74K:
626                 c->cputype = CPU_74K;
627                 break;
628         }
629 }
630
631 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
632 {
633         decode_configs(c);
634         switch (c->processor_id & 0xff00) {
635         case PRID_IMP_AU1_REV1:
636         case PRID_IMP_AU1_REV2:
637                 switch ((c->processor_id >> 24) & 0xff) {
638                 case 0:
639                         c->cputype = CPU_AU1000;
640                         break;
641                 case 1:
642                         c->cputype = CPU_AU1500;
643                         break;
644                 case 2:
645                         c->cputype = CPU_AU1100;
646                         break;
647                 case 3:
648                         c->cputype = CPU_AU1550;
649                         break;
650                 case 4:
651                         c->cputype = CPU_AU1200;
652                         break;
653                 default:
654                         panic("Unknown Au Core!");
655                         break;
656                 }
657                 break;
658         }
659 }
660
661 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
662 {
663         decode_configs(c);
664
665         /*
666          * For historical reasons the SB1 comes with it's own variant of
667          * cache code which eventually will be folded into c-r4k.c.  Until
668          * then we pretend it's got it's own cache architecture.
669          */
670         c->options &= ~MIPS_CPU_4K_CACHE;
671         c->options |= MIPS_CPU_SB1_CACHE;
672
673         switch (c->processor_id & 0xff00) {
674         case PRID_IMP_SB1:
675                 c->cputype = CPU_SB1;
676                 /* FPU in pass1 is known to have issues. */
677                 if ((c->processor_id & 0xff) < 0x02)
678                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
679                 break;
680         case PRID_IMP_SB1A:
681                 c->cputype = CPU_SB1A;
682                 break;
683         }
684 }
685
686 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
687 {
688         decode_configs(c);
689         switch (c->processor_id & 0xff00) {
690         case PRID_IMP_SR71000:
691                 c->cputype = CPU_SR71000;
692                 c->scache.ways = 8;
693                 c->tlbsize = 64;
694                 break;
695         }
696 }
697
698 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
699 {
700         decode_configs(c);
701         switch (c->processor_id & 0xff00) {
702         case PRID_IMP_PR4450:
703                 c->cputype = CPU_PR4450;
704                 c->isa_level = MIPS_CPU_ISA_M32R1;
705                 break;
706         default:
707                 panic("Unknown Philips Core!"); /* REVISIT: die? */
708                 break;
709         }
710 }
711
712
713 __init void cpu_probe(void)
714 {
715         struct cpuinfo_mips *c = &current_cpu_data;
716
717         c->processor_id = PRID_IMP_UNKNOWN;
718         c->fpu_id       = FPIR_IMP_NONE;
719         c->cputype      = CPU_UNKNOWN;
720
721         c->processor_id = read_c0_prid();
722         switch (c->processor_id & 0xff0000) {
723         case PRID_COMP_LEGACY:
724                 cpu_probe_legacy(c);
725                 break;
726         case PRID_COMP_MIPS:
727                 cpu_probe_mips(c);
728                 break;
729         case PRID_COMP_ALCHEMY:
730                 cpu_probe_alchemy(c);
731                 break;
732         case PRID_COMP_SIBYTE:
733                 cpu_probe_sibyte(c);
734                 break;
735         case PRID_COMP_SANDCRAFT:
736                 cpu_probe_sandcraft(c);
737                 break;
738         case PRID_COMP_PHILIPS:
739                 cpu_probe_philips(c);
740                 break;
741         default:
742                 c->cputype = CPU_UNKNOWN;
743         }
744         if (c->options & MIPS_CPU_FPU) {
745                 c->fpu_id = cpu_get_fpu_id();
746
747                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
748                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
749                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
750                     c->isa_level == MIPS_CPU_ISA_M64R2) {
751                         if (c->fpu_id & MIPS_FPIR_3D)
752                                 c->ases |= MIPS_ASE_MIPS3D;
753                 }
754         }
755 }
756
757 __init void cpu_report(void)
758 {
759         struct cpuinfo_mips *c = &current_cpu_data;
760
761         printk("CPU revision is: %08x\n", c->processor_id);
762         if (c->options & MIPS_CPU_FPU)
763                 printk("FPU revision is: %08x\n", c->fpu_id);
764 }