2 * Microchip ENC28J60 ethernet driver (MAC + PHY)
4 * Copyright (C) 2007 Eurek srl
5 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
6 * based on enc28j60.c written by David Anders for 2.4 kernel version
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/fcntl.h>
20 #include <linux/interrupt.h>
21 #include <linux/slab.h>
22 #include <linux/string.h>
23 #include <linux/errno.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/tcp.h>
29 #include <linux/skbuff.h>
30 #include <linux/delay.h>
31 #include <linux/spi/spi.h>
33 #include "enc28j60_hw.h"
35 #define DRV_NAME "enc28j60"
36 #define DRV_VERSION "1.01"
40 #define ENC28J60_MSG_DEFAULT \
41 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
43 /* Buffer size required for the largest SPI transfer (i.e., reading a
45 #define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
47 #define TX_TIMEOUT (4 * HZ)
49 /* Max TX retries in case of collision as suggested by errata datasheet */
50 #define MAX_TX_RETRYCOUNT 16
58 /* Driver local data */
60 struct net_device *netdev;
61 struct spi_device *spi;
63 struct sk_buff *tx_skb;
64 struct work_struct tx_work;
65 struct work_struct irq_work;
66 struct work_struct setrx_work;
67 struct work_struct restart_work;
68 u8 bank; /* current register bank selected */
69 u16 next_pk_ptr; /* next packet pointer within FIFO */
70 u16 max_pk_counter; /* statistics: max packet counter */
76 u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
79 /* use ethtool to change the level for any given device */
86 * wait for the SPI transfer and copy received data to destination
89 spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
91 u8 *rx_buf = priv->spi_transfer_buf + 4;
92 u8 *tx_buf = priv->spi_transfer_buf;
93 struct spi_transfer t = {
96 .len = SPI_OPLEN + len,
98 struct spi_message msg;
101 tx_buf[0] = ENC28J60_READ_BUF_MEM;
102 tx_buf[1] = tx_buf[2] = tx_buf[3] = 0; /* don't care */
104 spi_message_init(&msg);
105 spi_message_add_tail(&t, &msg);
106 ret = spi_sync(priv->spi, &msg);
108 memcpy(data, &rx_buf[SPI_OPLEN], len);
111 if (ret && netif_msg_drv(priv))
112 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
121 static int spi_write_buf(struct enc28j60_net *priv, int len,
126 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
129 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
130 memcpy(&priv->spi_transfer_buf[1], data, len);
131 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
132 if (ret && netif_msg_drv(priv))
133 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
140 * basic SPI read operation
142 static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
149 int slen = SPI_OPLEN;
151 /* do dummy read if needed */
152 if (addr & SPRD_MASK)
155 tx_buf[0] = op | (addr & ADDR_MASK);
156 ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
158 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
161 val = rx_buf[slen - 1];
167 * basic SPI write operation
169 static int spi_write_op(struct enc28j60_net *priv, u8 op,
174 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
175 priv->spi_transfer_buf[1] = val;
176 ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
177 if (ret && netif_msg_drv(priv))
178 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
183 static void enc28j60_soft_reset(struct enc28j60_net *priv)
185 if (netif_msg_hw(priv))
186 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
188 spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
189 /* Errata workaround #1, CLKRDY check is unreliable,
190 * delay at least 1 mS instead */
195 * select the current register bank if necessary
197 static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
199 if ((addr & BANK_MASK) != priv->bank) {
200 u8 b = (addr & BANK_MASK) >> 5;
202 if (b != (ECON1_BSEL1 | ECON1_BSEL0))
203 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
204 ECON1_BSEL1 | ECON1_BSEL0);
206 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, b);
207 priv->bank = (addr & BANK_MASK);
212 * Register access routines through the SPI bus.
213 * Every register access comes in two flavours:
214 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
215 * atomically more than one register
216 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
218 * Some registers can be accessed through the bit field clear and
219 * bit field set to avoid a read modify write cycle.
223 * Register bit field Set
225 static void nolock_reg_bfset(struct enc28j60_net *priv,
228 enc28j60_set_bank(priv, addr);
229 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
232 static void locked_reg_bfset(struct enc28j60_net *priv,
235 mutex_lock(&priv->lock);
236 nolock_reg_bfset(priv, addr, mask);
237 mutex_unlock(&priv->lock);
241 * Register bit field Clear
243 static void nolock_reg_bfclr(struct enc28j60_net *priv,
246 enc28j60_set_bank(priv, addr);
247 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
250 static void locked_reg_bfclr(struct enc28j60_net *priv,
253 mutex_lock(&priv->lock);
254 nolock_reg_bfclr(priv, addr, mask);
255 mutex_unlock(&priv->lock);
261 static int nolock_regb_read(struct enc28j60_net *priv,
264 enc28j60_set_bank(priv, address);
265 return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
268 static int locked_regb_read(struct enc28j60_net *priv,
273 mutex_lock(&priv->lock);
274 ret = nolock_regb_read(priv, address);
275 mutex_unlock(&priv->lock);
283 static int nolock_regw_read(struct enc28j60_net *priv,
288 enc28j60_set_bank(priv, address);
289 rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
290 rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
292 return (rh << 8) | rl;
295 static int locked_regw_read(struct enc28j60_net *priv,
300 mutex_lock(&priv->lock);
301 ret = nolock_regw_read(priv, address);
302 mutex_unlock(&priv->lock);
308 * Register byte write
310 static void nolock_regb_write(struct enc28j60_net *priv,
313 enc28j60_set_bank(priv, address);
314 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
317 static void locked_regb_write(struct enc28j60_net *priv,
320 mutex_lock(&priv->lock);
321 nolock_regb_write(priv, address, data);
322 mutex_unlock(&priv->lock);
326 * Register word write
328 static void nolock_regw_write(struct enc28j60_net *priv,
329 u8 address, u16 data)
331 enc28j60_set_bank(priv, address);
332 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
333 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
337 static void locked_regw_write(struct enc28j60_net *priv,
338 u8 address, u16 data)
340 mutex_lock(&priv->lock);
341 nolock_regw_write(priv, address, data);
342 mutex_unlock(&priv->lock);
347 * Select the starting address and execute a SPI buffer read
349 static void enc28j60_mem_read(struct enc28j60_net *priv,
350 u16 addr, int len, u8 *data)
352 mutex_lock(&priv->lock);
353 nolock_regw_write(priv, ERDPTL, addr);
354 #ifdef CONFIG_ENC28J60_WRITEVERIFY
355 if (netif_msg_drv(priv)) {
357 reg = nolock_regw_read(priv, ERDPTL);
359 printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
360 "(0x%04x - 0x%04x)\n", __FUNCTION__, reg, addr);
363 spi_read_buf(priv, len, data);
364 mutex_unlock(&priv->lock);
368 * Write packet to enc28j60 TX buffer memory
371 enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
373 mutex_lock(&priv->lock);
374 /* Set the write pointer to start of transmit buffer area */
375 nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
376 #ifdef CONFIG_ENC28J60_WRITEVERIFY
377 if (netif_msg_drv(priv)) {
379 reg = nolock_regw_read(priv, EWRPTL);
380 if (reg != TXSTART_INIT)
381 printk(KERN_DEBUG DRV_NAME
382 ": %s() ERWPT:0x%04x != 0x%04x\n",
383 __FUNCTION__, reg, TXSTART_INIT);
386 /* Set the TXND pointer to correspond to the packet size given */
387 nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
388 /* write per-packet control byte */
389 spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
390 if (netif_msg_hw(priv))
391 printk(KERN_DEBUG DRV_NAME
392 ": %s() after control byte ERWPT:0x%04x\n",
393 __FUNCTION__, nolock_regw_read(priv, EWRPTL));
394 /* copy the packet into the transmit buffer */
395 spi_write_buf(priv, len, data);
396 if (netif_msg_hw(priv))
397 printk(KERN_DEBUG DRV_NAME
398 ": %s() after write packet ERWPT:0x%04x, len=%d\n",
399 __FUNCTION__, nolock_regw_read(priv, EWRPTL), len);
400 mutex_unlock(&priv->lock);
403 static unsigned long msec20_to_jiffies;
405 static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
407 unsigned long timeout = jiffies + msec20_to_jiffies;
409 /* 20 msec timeout read */
410 while ((nolock_regb_read(priv, reg) & mask) != val) {
411 if (time_after(jiffies, timeout)) {
412 if (netif_msg_drv(priv))
413 dev_dbg(&priv->spi->dev,
414 "reg %02x ready timeout!\n", reg);
423 * Wait until the PHY operation is complete.
425 static int wait_phy_ready(struct enc28j60_net *priv)
427 return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
432 * PHY registers are not accessed directly, but through the MII
434 static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
438 mutex_lock(&priv->lock);
439 /* set the PHY register address */
440 nolock_regb_write(priv, MIREGADR, address);
441 /* start the register read operation */
442 nolock_regb_write(priv, MICMD, MICMD_MIIRD);
443 /* wait until the PHY read completes */
444 wait_phy_ready(priv);
446 nolock_regb_write(priv, MICMD, 0x00);
447 /* return the data */
448 ret = nolock_regw_read(priv, MIRDL);
449 mutex_unlock(&priv->lock);
454 static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
458 mutex_lock(&priv->lock);
459 /* set the PHY register address */
460 nolock_regb_write(priv, MIREGADR, address);
461 /* write the PHY data */
462 nolock_regw_write(priv, MIWRL, data);
463 /* wait until the PHY write completes and return */
464 ret = wait_phy_ready(priv);
465 mutex_unlock(&priv->lock);
471 * Program the hardware MAC address from dev->dev_addr.
473 static int enc28j60_set_hw_macaddr(struct net_device *ndev)
476 struct enc28j60_net *priv = netdev_priv(ndev);
478 mutex_lock(&priv->lock);
479 if (!priv->hw_enable) {
480 if (netif_msg_drv(priv)) {
481 DECLARE_MAC_BUF(mac);
482 printk(KERN_INFO DRV_NAME
483 ": %s: Setting MAC address to %s\n",
484 ndev->name, print_mac(mac, ndev->dev_addr));
486 /* NOTE: MAC address in ENC28J60 is byte-backward */
487 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
488 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
489 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
490 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
491 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
492 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
495 if (netif_msg_drv(priv))
496 printk(KERN_DEBUG DRV_NAME
497 ": %s() Hardware must be disabled to set "
498 "Mac address\n", __FUNCTION__);
501 mutex_unlock(&priv->lock);
506 * Store the new hardware address in dev->dev_addr, and update the MAC.
508 static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
510 struct sockaddr *address = addr;
512 if (netif_running(dev))
514 if (!is_valid_ether_addr(address->sa_data))
515 return -EADDRNOTAVAIL;
517 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
518 return enc28j60_set_hw_macaddr(dev);
522 * Debug routine to dump useful register contents
524 static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
526 mutex_lock(&priv->lock);
527 printk(KERN_DEBUG DRV_NAME " %s\n"
529 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
530 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
531 "MAC : MACON1 MACON3 MACON4\n"
532 " 0x%02x 0x%02x 0x%02x\n"
533 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
534 " 0x%04x 0x%04x 0x%04x 0x%04x "
535 "0x%02x 0x%02x 0x%04x\n"
536 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
537 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
538 msg, nolock_regb_read(priv, EREVID),
539 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
540 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
541 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
542 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
543 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
544 nolock_regw_read(priv, ERXWRPTL),
545 nolock_regw_read(priv, ERXRDPTL),
546 nolock_regb_read(priv, ERXFCON),
547 nolock_regb_read(priv, EPKTCNT),
548 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
549 nolock_regw_read(priv, ETXNDL),
550 nolock_regb_read(priv, MACLCON1),
551 nolock_regb_read(priv, MACLCON2),
552 nolock_regb_read(priv, MAPHSUP));
553 mutex_unlock(&priv->lock);
557 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
559 static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
563 if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
566 erxrdpt = next_packet_ptr - 1;
571 static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
575 if (start > 0x1FFF || end > 0x1FFF || start > end) {
576 if (netif_msg_drv(priv))
577 printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
578 "bad parameters!\n", __FUNCTION__, start, end);
581 /* set receive buffer start + end */
582 priv->next_pk_ptr = start;
583 nolock_regw_write(priv, ERXSTL, start);
584 erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
585 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
586 nolock_regw_write(priv, ERXNDL, end);
589 static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
591 if (start > 0x1FFF || end > 0x1FFF || start > end) {
592 if (netif_msg_drv(priv))
593 printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
594 "bad parameters!\n", __FUNCTION__, start, end);
597 /* set transmit buffer start + end */
598 nolock_regw_write(priv, ETXSTL, start);
599 nolock_regw_write(priv, ETXNDL, end);
603 * Low power mode shrinks power consumption about 100x, so we'd like
604 * the chip to be in that mode whenever it's inactive. (However, we
605 * can't stay in lowpower mode during suspend with WOL active.)
607 static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
609 if (netif_msg_drv(priv))
610 dev_dbg(&priv->spi->dev, "%s power...\n",
611 is_low ? "low" : "high");
613 mutex_lock(&priv->lock);
615 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
616 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
617 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
618 /* ECON2_VRPS was set during initialization */
619 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
621 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
622 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
623 /* caller sets ECON1_RXEN */
625 mutex_unlock(&priv->lock);
628 static int enc28j60_hw_init(struct enc28j60_net *priv)
632 if (netif_msg_drv(priv))
633 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __FUNCTION__,
634 priv->full_duplex ? "FullDuplex" : "HalfDuplex");
636 mutex_lock(&priv->lock);
637 /* first reset the chip */
638 enc28j60_soft_reset(priv);
640 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
642 priv->hw_enable = false;
643 priv->tx_retry_count = 0;
644 priv->max_pk_counter = 0;
645 priv->rxfilter = RXFILTER_NORMAL;
646 /* enable address auto increment and voltage regulator powersave */
647 nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
649 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
650 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
651 mutex_unlock(&priv->lock);
655 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
658 reg = locked_regb_read(priv, EREVID);
659 if (netif_msg_drv(priv))
660 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
661 if (reg == 0x00 || reg == 0xff) {
662 if (netif_msg_drv(priv))
663 printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
668 /* default filter mode: (unicast OR broadcast) AND crc valid */
669 locked_regb_write(priv, ERXFCON,
670 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
672 /* enable MAC receive */
673 locked_regb_write(priv, MACON1,
674 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
675 /* enable automatic padding and CRC operations */
676 if (priv->full_duplex) {
677 locked_regb_write(priv, MACON3,
678 MACON3_PADCFG0 | MACON3_TXCRCEN |
679 MACON3_FRMLNEN | MACON3_FULDPX);
680 /* set inter-frame gap (non-back-to-back) */
681 locked_regb_write(priv, MAIPGL, 0x12);
682 /* set inter-frame gap (back-to-back) */
683 locked_regb_write(priv, MABBIPG, 0x15);
685 locked_regb_write(priv, MACON3,
686 MACON3_PADCFG0 | MACON3_TXCRCEN |
688 locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */
689 /* set inter-frame gap (non-back-to-back) */
690 locked_regw_write(priv, MAIPGL, 0x0C12);
691 /* set inter-frame gap (back-to-back) */
692 locked_regb_write(priv, MABBIPG, 0x12);
697 * Set the maximum packet size which the controller will accept
699 locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
702 if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
705 if (priv->full_duplex) {
706 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
708 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
711 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
713 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
716 if (netif_msg_hw(priv))
717 enc28j60_dump_regs(priv, "Hw initialized.");
722 static void enc28j60_hw_enable(struct enc28j60_net *priv)
724 /* enable interrupts */
725 if (netif_msg_hw(priv))
726 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
729 enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
731 mutex_lock(&priv->lock);
732 nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
733 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
734 nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
735 EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
737 /* enable receive logic */
738 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
739 priv->hw_enable = true;
740 mutex_unlock(&priv->lock);
743 static void enc28j60_hw_disable(struct enc28j60_net *priv)
745 mutex_lock(&priv->lock);
746 /* disable interrutps and packet reception */
747 nolock_regb_write(priv, EIE, 0x00);
748 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
749 priv->hw_enable = false;
750 mutex_unlock(&priv->lock);
754 enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
756 struct enc28j60_net *priv = netdev_priv(ndev);
759 if (!priv->hw_enable) {
760 /* link is in low power mode now; duplex setting
761 * will take effect on next enc28j60_hw_init().
763 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
764 priv->full_duplex = (duplex == DUPLEX_FULL);
766 if (netif_msg_link(priv))
768 "unsupported link setting\n");
772 if (netif_msg_link(priv))
773 dev_warn(&ndev->dev, "Warning: hw must be disabled "
774 "to set link mode\n");
781 * Read the Transmit Status Vector
783 static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
787 endptr = locked_regw_read(priv, ETXNDL);
788 if (netif_msg_hw(priv))
789 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
791 enc28j60_mem_read(priv, endptr + 1, sizeof(tsv), tsv);
794 static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
799 printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
808 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
809 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
810 printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
811 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
812 TSV_GETBIT(tsv, TSV_TXCRCERROR),
813 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
814 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
815 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
816 "PacketDefer: %d, ExDefer: %d\n",
817 TSV_GETBIT(tsv, TSV_TXMULTICAST),
818 TSV_GETBIT(tsv, TSV_TXBROADCAST),
819 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
820 TSV_GETBIT(tsv, TSV_TXEXDEFER));
821 printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
822 "Giant: %d, Underrun: %d\n",
823 TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
824 TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
825 TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
826 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
827 "BackPressApp: %d, VLanTagFrame: %d\n",
828 TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
829 TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
830 TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
831 TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
835 * Receive Status vector
837 static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
838 u16 pk_ptr, int len, u16 sts)
840 printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
842 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
843 RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
844 printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
845 " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
846 RSV_GETBIT(sts, RSV_CRCERROR),
847 RSV_GETBIT(sts, RSV_LENCHECKERR),
848 RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
849 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
850 "LongDropEvent: %d, CarrierEvent: %d\n",
851 RSV_GETBIT(sts, RSV_RXMULTICAST),
852 RSV_GETBIT(sts, RSV_RXBROADCAST),
853 RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
854 RSV_GETBIT(sts, RSV_CARRIEREV));
855 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
856 " UnknownOp: %d, VLanTagFrame: %d\n",
857 RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
858 RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
859 RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
860 RSV_GETBIT(sts, RSV_RXTYPEVLAN));
863 static void dump_packet(const char *msg, int len, const char *data)
865 printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
866 print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
871 * Hardware receive function.
872 * Read the buffer memory, update the FIFO pointer to free the buffer,
873 * check the status vector and decrement the packet counter.
875 static void enc28j60_hw_rx(struct net_device *ndev)
877 struct enc28j60_net *priv = netdev_priv(ndev);
878 struct sk_buff *skb = NULL;
879 u16 erxrdpt, next_packet, rxstat;
883 if (netif_msg_rx_status(priv))
884 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
887 if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
888 if (netif_msg_rx_err(priv))
890 "%s() Invalid packet address!! 0x%04x\n",
891 __FUNCTION__, priv->next_pk_ptr);
892 /* packet address corrupted: reset RX logic */
893 mutex_lock(&priv->lock);
894 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
895 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
896 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
897 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
898 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
899 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
900 mutex_unlock(&priv->lock);
901 ndev->stats.rx_errors++;
904 /* Read next packet pointer and rx status vector */
905 enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
907 next_packet = rsv[1];
909 next_packet |= rsv[0];
919 if (netif_msg_rx_status(priv))
920 enc28j60_dump_rsv(priv, __FUNCTION__, next_packet, len, rxstat);
922 if (!RSV_GETBIT(rxstat, RSV_RXOK)) {
923 if (netif_msg_rx_err(priv))
924 dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
925 ndev->stats.rx_errors++;
926 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
927 ndev->stats.rx_crc_errors++;
928 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
929 ndev->stats.rx_frame_errors++;
931 skb = dev_alloc_skb(len + NET_IP_ALIGN);
933 if (netif_msg_rx_err(priv))
935 "out of memory for Rx'd frame\n");
936 ndev->stats.rx_dropped++;
939 skb_reserve(skb, NET_IP_ALIGN);
940 /* copy the packet from the receive buffer */
941 enc28j60_mem_read(priv, priv->next_pk_ptr + sizeof(rsv),
942 len, skb_put(skb, len));
943 if (netif_msg_pktdata(priv))
944 dump_packet(__FUNCTION__, skb->len, skb->data);
945 skb->protocol = eth_type_trans(skb, ndev);
946 /* update statistics */
947 ndev->stats.rx_packets++;
948 ndev->stats.rx_bytes += len;
949 ndev->last_rx = jiffies;
954 * Move the RX read pointer to the start of the next
956 * This frees the memory we just read out
958 erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
959 if (netif_msg_hw(priv))
960 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
961 __FUNCTION__, erxrdpt);
963 mutex_lock(&priv->lock);
964 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
965 #ifdef CONFIG_ENC28J60_WRITEVERIFY
966 if (netif_msg_drv(priv)) {
968 reg = nolock_regw_read(priv, ERXRDPTL);
970 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
971 "error (0x%04x - 0x%04x)\n", __FUNCTION__,
975 priv->next_pk_ptr = next_packet;
976 /* we are done with this packet, decrement the packet counter */
977 nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
978 mutex_unlock(&priv->lock);
982 * Calculate free space in RxFIFO
984 static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
986 int epkcnt, erxst, erxnd, erxwr, erxrd;
989 mutex_lock(&priv->lock);
990 epkcnt = nolock_regb_read(priv, EPKTCNT);
994 erxst = nolock_regw_read(priv, ERXSTL);
995 erxnd = nolock_regw_read(priv, ERXNDL);
996 erxwr = nolock_regw_read(priv, ERXWRPTL);
997 erxrd = nolock_regw_read(priv, ERXRDPTL);
1000 free_space = (erxnd - erxst) - (erxwr - erxrd);
1001 else if (erxwr == erxrd)
1002 free_space = (erxnd - erxst);
1004 free_space = erxrd - erxwr - 1;
1006 mutex_unlock(&priv->lock);
1007 if (netif_msg_rx_status(priv))
1008 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
1009 __FUNCTION__, free_space);
1014 * Access the PHY to determine link status
1016 static void enc28j60_check_link_status(struct net_device *ndev)
1018 struct enc28j60_net *priv = netdev_priv(ndev);
1022 reg = enc28j60_phy_read(priv, PHSTAT2);
1023 if (netif_msg_hw(priv))
1024 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
1025 "PHSTAT2: %04x\n", __FUNCTION__,
1026 enc28j60_phy_read(priv, PHSTAT1), reg);
1027 duplex = reg & PHSTAT2_DPXSTAT;
1029 if (reg & PHSTAT2_LSTAT) {
1030 netif_carrier_on(ndev);
1031 if (netif_msg_ifup(priv))
1032 dev_info(&ndev->dev, "link up - %s\n",
1033 duplex ? "Full duplex" : "Half duplex");
1035 if (netif_msg_ifdown(priv))
1036 dev_info(&ndev->dev, "link down\n");
1037 netif_carrier_off(ndev);
1041 static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1043 struct enc28j60_net *priv = netdev_priv(ndev);
1046 ndev->stats.tx_errors++;
1048 ndev->stats.tx_packets++;
1052 ndev->stats.tx_bytes += priv->tx_skb->len;
1053 dev_kfree_skb(priv->tx_skb);
1054 priv->tx_skb = NULL;
1056 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1057 netif_wake_queue(ndev);
1062 * ignore PKTIF because is unreliable! (look at the errata datasheet)
1063 * check EPKTCNT is the suggested workaround.
1064 * We don't need to clear interrupt flag, automatically done when
1065 * enc28j60_hw_rx() decrements the packet counter.
1066 * Returns how many packet processed.
1068 static int enc28j60_rx_interrupt(struct net_device *ndev)
1070 struct enc28j60_net *priv = netdev_priv(ndev);
1071 int pk_counter, ret;
1073 pk_counter = locked_regb_read(priv, EPKTCNT);
1074 if (pk_counter && netif_msg_intr(priv))
1075 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1076 if (pk_counter > priv->max_pk_counter) {
1077 /* update statistics */
1078 priv->max_pk_counter = pk_counter;
1079 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1080 printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1081 priv->max_pk_counter);
1084 while (pk_counter-- > 0)
1085 enc28j60_hw_rx(ndev);
1090 static void enc28j60_irq_work_handler(struct work_struct *work)
1092 struct enc28j60_net *priv =
1093 container_of(work, struct enc28j60_net, irq_work);
1094 struct net_device *ndev = priv->netdev;
1097 if (netif_msg_intr(priv))
1098 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1099 /* disable further interrupts */
1100 locked_reg_bfclr(priv, EIE, EIE_INTIE);
1104 intflags = locked_regb_read(priv, EIR);
1105 /* DMA interrupt handler (not currently used) */
1106 if ((intflags & EIR_DMAIF) != 0) {
1108 if (netif_msg_intr(priv))
1109 printk(KERN_DEBUG DRV_NAME
1110 ": intDMA(%d)\n", loop);
1111 locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1113 /* LINK changed handler */
1114 if ((intflags & EIR_LINKIF) != 0) {
1116 if (netif_msg_intr(priv))
1117 printk(KERN_DEBUG DRV_NAME
1118 ": intLINK(%d)\n", loop);
1119 enc28j60_check_link_status(ndev);
1120 /* read PHIR to clear the flag */
1121 enc28j60_phy_read(priv, PHIR);
1123 /* TX complete handler */
1124 if ((intflags & EIR_TXIF) != 0) {
1127 if (netif_msg_intr(priv))
1128 printk(KERN_DEBUG DRV_NAME
1129 ": intTX(%d)\n", loop);
1130 priv->tx_retry_count = 0;
1131 if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1132 if (netif_msg_tx_err(priv))
1134 "Tx Error (aborted)\n");
1137 if (netif_msg_tx_done(priv)) {
1139 enc28j60_read_tsv(priv, tsv);
1140 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1142 enc28j60_tx_clear(ndev, err);
1143 locked_reg_bfclr(priv, EIR, EIR_TXIF);
1145 /* TX Error handler */
1146 if ((intflags & EIR_TXERIF) != 0) {
1150 if (netif_msg_intr(priv))
1151 printk(KERN_DEBUG DRV_NAME
1152 ": intTXErr(%d)\n", loop);
1153 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1154 enc28j60_read_tsv(priv, tsv);
1155 if (netif_msg_tx_err(priv))
1156 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1157 /* Reset TX logic */
1158 mutex_lock(&priv->lock);
1159 nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1160 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1161 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1162 mutex_unlock(&priv->lock);
1163 /* Transmit Late collision check for retransmit */
1164 if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1165 if (netif_msg_tx_err(priv))
1166 printk(KERN_DEBUG DRV_NAME
1167 ": LateCollision TXErr (%d)\n",
1168 priv->tx_retry_count);
1169 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1170 locked_reg_bfset(priv, ECON1,
1173 enc28j60_tx_clear(ndev, true);
1175 enc28j60_tx_clear(ndev, true);
1176 locked_reg_bfclr(priv, EIR, EIR_TXERIF);
1178 /* RX Error handler */
1179 if ((intflags & EIR_RXERIF) != 0) {
1181 if (netif_msg_intr(priv))
1182 printk(KERN_DEBUG DRV_NAME
1183 ": intRXErr(%d)\n", loop);
1184 /* Check free FIFO space to flag RX overrun */
1185 if (enc28j60_get_free_rxfifo(priv) <= 0) {
1186 if (netif_msg_rx_err(priv))
1187 printk(KERN_DEBUG DRV_NAME
1189 ndev->stats.rx_dropped++;
1191 locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1194 if (enc28j60_rx_interrupt(ndev))
1198 /* re-enable interrupts */
1199 locked_reg_bfset(priv, EIE, EIE_INTIE);
1200 if (netif_msg_intr(priv))
1201 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __FUNCTION__);
1205 * Hardware transmit function.
1206 * Fill the buffer memory and send the contents of the transmit buffer
1209 static void enc28j60_hw_tx(struct enc28j60_net *priv)
1211 if (netif_msg_tx_queued(priv))
1212 printk(KERN_DEBUG DRV_NAME
1213 ": Tx Packet Len:%d\n", priv->tx_skb->len);
1215 if (netif_msg_pktdata(priv))
1216 dump_packet(__FUNCTION__,
1217 priv->tx_skb->len, priv->tx_skb->data);
1218 enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1220 #ifdef CONFIG_ENC28J60_WRITEVERIFY
1221 /* readback and verify written data */
1222 if (netif_msg_drv(priv)) {
1224 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1227 test_len = priv->tx_skb->len;
1228 if (test_len > sizeof(test_buf))
1229 test_len = sizeof(test_buf);
1231 /* + 1 to skip control byte */
1232 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1234 for (k = 0; k < test_len; k++) {
1235 if (priv->tx_skb->data[k] != test_buf[k]) {
1236 printk(KERN_DEBUG DRV_NAME
1237 ": Error, %d location differ: "
1238 "0x%02x-0x%02x\n", k,
1239 priv->tx_skb->data[k], test_buf[k]);
1244 printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1248 /* set TX request flag */
1249 locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1252 static int enc28j60_send_packet(struct sk_buff *skb, struct net_device *dev)
1254 struct enc28j60_net *priv = netdev_priv(dev);
1256 if (netif_msg_tx_queued(priv))
1257 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1259 /* If some error occurs while trying to transmit this
1260 * packet, you should return '1' from this function.
1261 * In such a case you _may not_ do anything to the
1262 * SKB, it is still owned by the network queueing
1263 * layer when an error is returned. This means you
1264 * may not modify any SKB fields, you may not free
1267 netif_stop_queue(dev);
1269 /* save the timestamp */
1270 priv->netdev->trans_start = jiffies;
1271 /* Remember the skb for deferred processing */
1273 schedule_work(&priv->tx_work);
1278 static void enc28j60_tx_work_handler(struct work_struct *work)
1280 struct enc28j60_net *priv =
1281 container_of(work, struct enc28j60_net, tx_work);
1283 /* actual delivery of data */
1284 enc28j60_hw_tx(priv);
1287 static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1289 struct enc28j60_net *priv = dev_id;
1292 * Can't do anything in interrupt context because we need to
1293 * block (spi_sync() is blocking) so fire of the interrupt
1294 * handling workqueue.
1295 * Remember that we access enc28j60 registers through SPI bus
1296 * via spi_sync() call.
1298 schedule_work(&priv->irq_work);
1303 static void enc28j60_tx_timeout(struct net_device *ndev)
1305 struct enc28j60_net *priv = netdev_priv(ndev);
1307 if (netif_msg_timer(priv))
1308 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1310 ndev->stats.tx_errors++;
1311 /* can't restart safely under softirq */
1312 schedule_work(&priv->restart_work);
1316 * Open/initialize the board. This is called (in the current kernel)
1317 * sometime after booting when the 'ifconfig' program is run.
1319 * This routine should set everything up anew at each open, even
1320 * registers that "should" only need to be set once at boot, so that
1321 * there is non-reboot way to recover if something goes wrong.
1323 static int enc28j60_net_open(struct net_device *dev)
1325 struct enc28j60_net *priv = netdev_priv(dev);
1327 if (netif_msg_drv(priv))
1328 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1330 if (!is_valid_ether_addr(dev->dev_addr)) {
1331 if (netif_msg_ifup(priv)) {
1332 DECLARE_MAC_BUF(mac);
1333 dev_err(&dev->dev, "invalid MAC address %s\n",
1334 print_mac(mac, dev->dev_addr));
1336 return -EADDRNOTAVAIL;
1338 /* Reset the hardware here (and take it out of low power mode) */
1339 enc28j60_lowpower(priv, false);
1340 enc28j60_hw_disable(priv);
1341 if (!enc28j60_hw_init(priv)) {
1342 if (netif_msg_ifup(priv))
1343 dev_err(&dev->dev, "hw_reset() failed\n");
1346 /* Update the MAC address (in case user has changed it) */
1347 enc28j60_set_hw_macaddr(dev);
1348 /* Enable interrupts */
1349 enc28j60_hw_enable(priv);
1350 /* check link status */
1351 enc28j60_check_link_status(dev);
1352 /* We are now ready to accept transmit requests from
1353 * the queueing layer of the networking.
1355 netif_start_queue(dev);
1360 /* The inverse routine to net_open(). */
1361 static int enc28j60_net_close(struct net_device *dev)
1363 struct enc28j60_net *priv = netdev_priv(dev);
1365 if (netif_msg_drv(priv))
1366 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1368 enc28j60_hw_disable(priv);
1369 enc28j60_lowpower(priv, true);
1370 netif_stop_queue(dev);
1376 * Set or clear the multicast filter for this adapter
1377 * num_addrs == -1 Promiscuous mode, receive all packets
1378 * num_addrs == 0 Normal mode, filter out multicast packets
1379 * num_addrs > 0 Multicast mode, receive normal and MC packets
1381 static void enc28j60_set_multicast_list(struct net_device *dev)
1383 struct enc28j60_net *priv = netdev_priv(dev);
1384 int oldfilter = priv->rxfilter;
1386 if (dev->flags & IFF_PROMISC) {
1387 if (netif_msg_link(priv))
1388 dev_info(&dev->dev, "promiscuous mode\n");
1389 priv->rxfilter = RXFILTER_PROMISC;
1390 } else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count) {
1391 if (netif_msg_link(priv))
1392 dev_info(&dev->dev, "%smulticast mode\n",
1393 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1394 priv->rxfilter = RXFILTER_MULTI;
1396 if (netif_msg_link(priv))
1397 dev_info(&dev->dev, "normal mode\n");
1398 priv->rxfilter = RXFILTER_NORMAL;
1401 if (oldfilter != priv->rxfilter)
1402 schedule_work(&priv->setrx_work);
1405 static void enc28j60_setrx_work_handler(struct work_struct *work)
1407 struct enc28j60_net *priv =
1408 container_of(work, struct enc28j60_net, setrx_work);
1410 if (priv->rxfilter == RXFILTER_PROMISC) {
1411 if (netif_msg_drv(priv))
1412 printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1413 locked_regb_write(priv, ERXFCON, 0x00);
1414 } else if (priv->rxfilter == RXFILTER_MULTI) {
1415 if (netif_msg_drv(priv))
1416 printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1417 locked_regb_write(priv, ERXFCON,
1418 ERXFCON_UCEN | ERXFCON_CRCEN |
1419 ERXFCON_BCEN | ERXFCON_MCEN);
1421 if (netif_msg_drv(priv))
1422 printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1423 locked_regb_write(priv, ERXFCON,
1424 ERXFCON_UCEN | ERXFCON_CRCEN |
1429 static void enc28j60_restart_work_handler(struct work_struct *work)
1431 struct enc28j60_net *priv =
1432 container_of(work, struct enc28j60_net, restart_work);
1433 struct net_device *ndev = priv->netdev;
1437 if (netif_running(ndev)) {
1438 enc28j60_net_close(ndev);
1439 ret = enc28j60_net_open(ndev);
1440 if (unlikely(ret)) {
1441 dev_info(&ndev->dev, " could not restart %d\n", ret);
1448 /* ......................... ETHTOOL SUPPORT ........................... */
1451 enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1453 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1454 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1455 strlcpy(info->bus_info,
1456 dev->dev.parent->bus_id, sizeof(info->bus_info));
1460 enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1462 struct enc28j60_net *priv = netdev_priv(dev);
1464 cmd->transceiver = XCVR_INTERNAL;
1465 cmd->supported = SUPPORTED_10baseT_Half
1466 | SUPPORTED_10baseT_Full
1468 cmd->speed = SPEED_10;
1469 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1470 cmd->port = PORT_TP;
1471 cmd->autoneg = AUTONEG_DISABLE;
1477 enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1479 return enc28j60_setlink(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1482 static u32 enc28j60_get_msglevel(struct net_device *dev)
1484 struct enc28j60_net *priv = netdev_priv(dev);
1485 return priv->msg_enable;
1488 static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1490 struct enc28j60_net *priv = netdev_priv(dev);
1491 priv->msg_enable = val;
1494 static const struct ethtool_ops enc28j60_ethtool_ops = {
1495 .get_settings = enc28j60_get_settings,
1496 .set_settings = enc28j60_set_settings,
1497 .get_drvinfo = enc28j60_get_drvinfo,
1498 .get_msglevel = enc28j60_get_msglevel,
1499 .set_msglevel = enc28j60_set_msglevel,
1502 static int enc28j60_chipset_init(struct net_device *dev)
1504 struct enc28j60_net *priv = netdev_priv(dev);
1506 return enc28j60_hw_init(priv);
1509 static int __devinit enc28j60_probe(struct spi_device *spi)
1511 struct net_device *dev;
1512 struct enc28j60_net *priv;
1515 if (netif_msg_drv(&debug))
1516 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1519 dev = alloc_etherdev(sizeof(struct enc28j60_net));
1521 if (netif_msg_drv(&debug))
1522 dev_err(&spi->dev, DRV_NAME
1523 ": unable to alloc new ethernet\n");
1527 priv = netdev_priv(dev);
1529 priv->netdev = dev; /* priv to netdev reference */
1530 priv->spi = spi; /* priv to spi reference */
1531 priv->msg_enable = netif_msg_init(debug.msg_enable,
1532 ENC28J60_MSG_DEFAULT);
1533 mutex_init(&priv->lock);
1534 INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1535 INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1536 INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1537 INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1538 dev_set_drvdata(&spi->dev, priv); /* spi to priv reference */
1539 SET_NETDEV_DEV(dev, &spi->dev);
1541 if (!enc28j60_chipset_init(dev)) {
1542 if (netif_msg_probe(priv))
1543 dev_info(&spi->dev, DRV_NAME " chip not found\n");
1547 random_ether_addr(dev->dev_addr);
1548 enc28j60_set_hw_macaddr(dev);
1550 /* Board setup must set the relevant edge trigger type;
1551 * level triggers won't currently work.
1553 ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
1555 if (netif_msg_probe(priv))
1556 dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1557 "(ret = %d)\n", spi->irq, ret);
1561 dev->if_port = IF_PORT_10BASET;
1562 dev->irq = spi->irq;
1563 dev->open = enc28j60_net_open;
1564 dev->stop = enc28j60_net_close;
1565 dev->hard_start_xmit = enc28j60_send_packet;
1566 dev->set_multicast_list = &enc28j60_set_multicast_list;
1567 dev->set_mac_address = enc28j60_set_mac_address;
1568 dev->tx_timeout = &enc28j60_tx_timeout;
1569 dev->watchdog_timeo = TX_TIMEOUT;
1570 SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops);
1572 enc28j60_lowpower(priv, true);
1574 ret = register_netdev(dev);
1576 if (netif_msg_probe(priv))
1577 dev_err(&spi->dev, "register netdev " DRV_NAME
1578 " failed (ret = %d)\n", ret);
1579 goto error_register;
1581 dev_info(&dev->dev, DRV_NAME " driver registered\n");
1586 free_irq(spi->irq, priv);
1593 static int __devexit enc28j60_remove(struct spi_device *spi)
1595 struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
1597 if (netif_msg_drv(priv))
1598 printk(KERN_DEBUG DRV_NAME ": remove\n");
1600 unregister_netdev(priv->netdev);
1601 free_irq(spi->irq, priv);
1602 free_netdev(priv->netdev);
1607 static struct spi_driver enc28j60_driver = {
1610 .owner = THIS_MODULE,
1612 .probe = enc28j60_probe,
1613 .remove = __devexit_p(enc28j60_remove),
1616 static int __init enc28j60_init(void)
1618 msec20_to_jiffies = msecs_to_jiffies(20);
1620 return spi_register_driver(&enc28j60_driver);
1623 module_init(enc28j60_init);
1625 static void __exit enc28j60_exit(void)
1627 spi_unregister_driver(&enc28j60_driver);
1630 module_exit(enc28j60_exit);
1632 MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1633 MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1634 MODULE_LICENSE("GPL");
1635 module_param_named(debug, debug.msg_enable, int, 0);
1636 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");