git.oblomov.eu Git - linux-2.6/blob - arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/string.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ctype.h>
  17 #include <linux/init.h>
  18 #include <linux/sched.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/module.h>
  21 #include <linux/hardirq.h>
  22 #include <asm/smp.h>
  23 #include <asm/ipi.h>
  24 #include <asm/genapic.h>
  25 #include <asm/pgtable.h>
  26 #include <asm/uv/uv_mmrs.h>
  27 #include <asm/uv/uv_hub.h>
  28 #include <asm/uv/bios.h>
  29
  30 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  31 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  32
  33 struct uv_blade_info *uv_blade_info;
  34 EXPORT_SYMBOL_GPL(uv_blade_info);
  35
  36 short *uv_node_to_blade;
  37 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  38
  39 short *uv_cpu_to_blade;
  40 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  41
  42 short uv_possible_blades;
  43 EXPORT_SYMBOL_GPL(uv_possible_blades);
  44
  45 unsigned long sn_rtc_cycles_per_second;
  46 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  47
  48 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  49
  50 static cpumask_t uv_target_cpus(void)
  51 {
  52         return cpumask_of_cpu(0);
  53 }
  54
  55 static cpumask_t uv_vector_allocation_domain(int cpu)
  56 {
  57         cpumask_t domain = CPU_MASK_NONE;
  58         cpu_set(cpu, domain);
  59         return domain;
  60 }
  61
  62 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  63 {
  64         unsigned long val;
  65         int pnode;
  66
  67         pnode = uv_apicid_to_pnode(phys_apicid);
  68         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  69             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  70             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
  71             APIC_DM_INIT;
  72         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  73         mdelay(10);
  74
  75         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  76             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  77             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
  78             APIC_DM_STARTUP;
  79         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  80         return 0;
  81 }
  82
  83 static void uv_send_IPI_one(int cpu, int vector)
  84 {
  85         unsigned long val, apicid, lapicid;
  86         int pnode;
  87
  88         apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
  89         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
  90         pnode = uv_apicid_to_pnode(apicid);
  91         val =
  92             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
  93                                               UVH_IPI_INT_APIC_ID_SHFT) |
  94             (vector << UVH_IPI_INT_VECTOR_SHFT);
  95         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  96 }
  97
  98 static void uv_send_IPI_mask(cpumask_t mask, int vector)
  99 {
 100         unsigned int cpu;
 101
 102         for (cpu = 0; cpu < NR_CPUS; ++cpu)
 103                 if (cpu_isset(cpu, mask))
 104                         uv_send_IPI_one(cpu, vector);
 105 }
 106
 107 static void uv_send_IPI_allbutself(int vector)
 108 {
 109         cpumask_t mask = cpu_online_map;
 110
 111         cpu_clear(smp_processor_id(), mask);
 112
 113         if (!cpus_empty(mask))
 114                 uv_send_IPI_mask(mask, vector);
 115 }
 116
 117 static void uv_send_IPI_all(int vector)
 118 {
 119         uv_send_IPI_mask(cpu_online_map, vector);
 120 }
 121
 122 static int uv_apic_id_registered(void)
 123 {
 124         return 1;
 125 }
 126
 127 static void uv_init_apic_ldr(void)
 128 {
 129 }
 130
 131 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
 132 {
 133         int cpu;
 134
 135         /*
 136          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 137          * May as well be the first.
 138          */
 139         cpu = first_cpu(cpumask);
 140         if ((unsigned)cpu < NR_CPUS)
 141                 return per_cpu(x86_cpu_to_apicid, cpu);
 142         else
 143                 return BAD_APICID;
 144 }
 145
 146 static unsigned int get_apic_id(unsigned long x)
 147 {
 148         unsigned int id;
 149
 150         WARN_ON(preemptible() && num_online_cpus() > 1);
 151         id = x | __get_cpu_var(x2apic_extra_bits);
 152
 153         return id;
 154 }
 155
 156 static long set_apic_id(unsigned int id)
 157 {
 158         unsigned long x;
 159
 160         /* maskout x2apic_extra_bits ? */
 161         x = id;
 162         return x;
 163 }
 164
 165 static unsigned int uv_read_apic_id(void)
 166 {
 167
 168         return get_apic_id(apic_read(APIC_ID));
 169 }
 170
 171 static unsigned int phys_pkg_id(int index_msb)
 172 {
 173         return uv_read_apic_id() >> index_msb;
 174 }
 175
 176 #ifdef ZZZ              /* Needs x2apic patch */
 177 static void uv_send_IPI_self(int vector)
 178 {
 179         apic_write(APIC_SELF_IPI, vector);
 180 }
 181 #endif
 182
 183 struct genapic apic_x2apic_uv_x = {
 184         .name = "UV large system",
 185         .int_delivery_mode = dest_Fixed,
 186         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 187         .target_cpus = uv_target_cpus,
 188         .vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
 189         .apic_id_registered = uv_apic_id_registered,
 190         .init_apic_ldr = uv_init_apic_ldr,
 191         .send_IPI_all = uv_send_IPI_all,
 192         .send_IPI_allbutself = uv_send_IPI_allbutself,
 193         .send_IPI_mask = uv_send_IPI_mask,
 194         /* ZZZ.send_IPI_self = uv_send_IPI_self, */
 195         .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
 196         .phys_pkg_id = phys_pkg_id,     /* Fixme ZZZ */
 197         .get_apic_id = get_apic_id,
 198         .set_apic_id = set_apic_id,
 199         .apic_id_mask = (0xFFFFFFFFu),
 200 };
 201
 202 static __cpuinit void set_x2apic_extra_bits(int pnode)
 203 {
 204         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 205 }
 206
 207 /*
 208  * Called on boot cpu.
 209  */
 210 static __init int boot_pnode_to_blade(int pnode)
 211 {
 212         int blade;
 213
 214         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 215                 if (pnode == uv_blade_info[blade].pnode)
 216                         return blade;
 217         BUG();
 218 }
 219
 220 struct redir_addr {
 221         unsigned long redirect;
 222         unsigned long alias;
 223 };
 224
 225 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 226
 227 static __initdata struct redir_addr redir_addrs[] = {
 228         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 229         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 230         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 231 };
 232
 233 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 234 {
 235         union uvh_si_alias0_overlay_config_u alias;
 236         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 237         int i;
 238
 239         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 240                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 241                 if (alias.s.base == 0) {
 242                         *size = (1UL << alias.s.m_alias);
 243                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 244                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 245                         return;
 246                 }
 247         }
 248         BUG();
 249 }
 250
 251 static __init void map_low_mmrs(void)
 252 {
 253         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 254         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 255 }
 256
 257 enum map_type {map_wb, map_uc};
 258
 259 static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
 260 {
 261         unsigned long bytes, paddr;
 262
 263         paddr = base << shift;
 264         bytes = (1UL << shift);
 265         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 266                                                 paddr + bytes);
 267         if (map_type == map_uc)
 268                 init_extra_mapping_uc(paddr, bytes);
 269         else
 270                 init_extra_mapping_wb(paddr, bytes);
 271
 272 }
 273 static __init void map_gru_high(int max_pnode)
 274 {
 275         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 276         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 277
 278         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 279         if (gru.s.enable)
 280                 map_high("GRU", gru.s.base, shift, map_wb);
 281 }
 282
 283 static __init void map_config_high(int max_pnode)
 284 {
 285         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 286         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 287
 288         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 289         if (cfg.s.enable)
 290                 map_high("CONFIG", cfg.s.base, shift, map_uc);
 291 }
 292
 293 static __init void map_mmr_high(int max_pnode)
 294 {
 295         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 296         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 297
 298         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 299         if (mmr.s.enable)
 300                 map_high("MMR", mmr.s.base, shift, map_uc);
 301 }
 302
 303 static __init void map_mmioh_high(int max_pnode)
 304 {
 305         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 306         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 307
 308         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 309         if (mmioh.s.enable)
 310                 map_high("MMIOH", mmioh.s.base, shift, map_uc);
 311 }
 312
 313 static __init void uv_rtc_init(void)
 314 {
 315         long status, ticks_per_sec, drift;
 316
 317         status =
 318             x86_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
 319                                         &drift);
 320         if (status != 0 || ticks_per_sec < 100000) {
 321                 printk(KERN_WARNING
 322                         "unable to determine platform RTC clock frequency, "
 323                         "guessing.\n");
 324                 /* BIOS gives wrong value for clock freq. so guess */
 325                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 326         } else
 327                 sn_rtc_cycles_per_second = ticks_per_sec;
 328 }
 329
 330 static __init void uv_system_init(void)
 331 {
 332         union uvh_si_addr_map_config_u m_n_config;
 333         union uvh_node_id_u node_id;
 334         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 335         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 336         int max_pnode = 0;
 337         unsigned long mmr_base, present;
 338
 339         map_low_mmrs();
 340
 341         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 342         m_val = m_n_config.s.m_skt;
 343         n_val = m_n_config.s.n_skt;
 344         mmr_base =
 345             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 346             ~UV_MMR_ENABLE;
 347         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 348
 349         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 350                 uv_possible_blades +=
 351                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 352         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 353
 354         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 355         uv_blade_info = alloc_bootmem_pages(bytes);
 356
 357         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 358
 359         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 360         uv_node_to_blade = alloc_bootmem_pages(bytes);
 361         memset(uv_node_to_blade, 255, bytes);
 362
 363         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 364         uv_cpu_to_blade = alloc_bootmem_pages(bytes);
 365         memset(uv_cpu_to_blade, 255, bytes);
 366
 367         blade = 0;
 368         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 369                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 370                 for (j = 0; j < 64; j++) {
 371                         if (!test_bit(j, &present))
 372                                 continue;
 373                         uv_blade_info[blade].pnode = (i * 64 + j);
 374                         uv_blade_info[blade].nr_possible_cpus = 0;
 375                         uv_blade_info[blade].nr_online_cpus = 0;
 376                         blade++;
 377                 }
 378         }
 379
 380         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 381         gnode_upper = (((unsigned long)node_id.s.node_id) &
 382                        ~((1 << n_val) - 1)) << m_val;
 383
 384         uv_rtc_init();
 385
 386         for_each_present_cpu(cpu) {
 387                 nid = cpu_to_node(cpu);
 388                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 389                 blade = boot_pnode_to_blade(pnode);
 390                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 391                 uv_blade_info[blade].nr_possible_cpus++;
 392
 393                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 394                 uv_cpu_hub_info(cpu)->lowmem_remap_top =
 395                                         lowmem_redir_base + lowmem_redir_size;
 396                 uv_cpu_hub_info(cpu)->m_val = m_val;
 397                 uv_cpu_hub_info(cpu)->n_val = m_val;
 398                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 399                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 400                 uv_cpu_hub_info(cpu)->pnode = pnode;
 401                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 402                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 403                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 404                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 405                 uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
 406                 uv_node_to_blade[nid] = blade;
 407                 uv_cpu_to_blade[cpu] = blade;
 408                 max_pnode = max(pnode, max_pnode);
 409
 410                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 411                         "lcpu %d, blade %d\n",
 412                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 413                         lcpu, blade);
 414         }
 415
 416         map_gru_high(max_pnode);
 417         map_mmr_high(max_pnode);
 418         map_config_high(max_pnode);
 419         map_mmioh_high(max_pnode);
 420 }
 421
 422 /*
 423  * Called on each cpu to initialize the per_cpu UV data area.
 424  *      ZZZ hotplug not supported yet
 425  */
 426 void __cpuinit uv_cpu_init(void)
 427 {
 428         if (!uv_node_to_blade)
 429                 uv_system_init();
 430
 431         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 432
 433         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 434                 set_x2apic_extra_bits(uv_hub_info->pnode);
 435 }